]> Git Repo - qemu.git/blame - hw/net/rtl8139.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
migration: Move the VMStateDescription typedef to typedefs.h
[qemu.git] / hw / net / rtl8139.c
CommitLineData
a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
b6af0975 46 * when strictly needed (required for
05447803 47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f 51/* For crc32 */
0b8fa32f 52
e8d40465 53#include "qemu/osdep.h"
2c406b8f
BP		 54#include <zlib.h>
55
83c9f4ca
PB		 56#include "hw/hw.h"
57#include "hw/pci/pci.h"
9c17d615 58#include "sysemu/dma.h"
0b8fa32f 59#include "qemu/module.h"
1de7afc9 60#include "qemu/timer.h"
1422e32d 61#include "net/net.h"
5d61721a 62#include "net/eth.h"
9c17d615 63#include "sysemu/sysemu.h"
a41b2ff2 64
a41b2ff2
PB		 65/* debug RTL8139 card */
66//#define DEBUG_RTL8139 1
67
37b9ab92 68#define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */
6cadb320 69
a41b2ff2
PB		 70#define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73/* arg % size for size which is a power of 2 */
74#define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
18dabfd1 77#define ETHER_TYPE_LEN 2
18dabfd1
BP		 78#define ETH_MTU 1500
79
80#define VLAN_TCI_LEN 2
81#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
82
6cadb320 83#if defined (DEBUG_RTL8139)
7cdeb319
BP		 84# define DPRINTF(fmt, ...) \
85 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 86#else
c6a0487b 87static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 88{
89 return 0;
90}
6cadb320
FB		 91#endif
92
39257515
PC		 93#define TYPE_RTL8139 "rtl8139"
94
95#define RTL8139(obj) \
96 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139)
97
a41b2ff2
PB		 98/* Symbolic offsets to registers. */
99enum RTL8139_registers {
100 MAC0 = 0, /* Ethernet hardware address. */
101 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 102 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
103 /* Dump Tally Conter control register(64bit). C+ mode only */
104 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 105 RxBuf = 0x30,
106 ChipCmd = 0x37,
107 RxBufPtr = 0x38,
108 RxBufAddr = 0x3A,
109 IntrMask = 0x3C,
110 IntrStatus = 0x3E,
111 TxConfig = 0x40,
112 RxConfig = 0x44,
113 Timer = 0x48, /* A general-purpose counter. */
114 RxMissed = 0x4C, /* 24 bits valid, write clears. */
115 Cfg9346 = 0x50,
116 Config0 = 0x51,
117 Config1 = 0x52,
118 FlashReg = 0x54,
119 MediaStatus = 0x58,
120 Config3 = 0x59,
121 Config4 = 0x5A, /* absent on RTL-8139A */
122 HltClk = 0x5B,
123 MultiIntr = 0x5C,
124 PCIRevisionID = 0x5E,
125 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
126 BasicModeCtrl = 0x62,
127 BasicModeStatus = 0x64,
128 NWayAdvert = 0x66,
129 NWayLPAR = 0x68,
130 NWayExpansion = 0x6A,
131 /* Undocumented registers, but required for proper operation. */
132 FIFOTMS = 0x70, /* FIFO Control and test. */
133 CSCR = 0x74, /* Chip Status and Configuration Register. */
134 PARA78 = 0x78,
135 PARA7c = 0x7c, /* Magic transceiver parameter register. */
136 Config5 = 0xD8, /* absent on RTL-8139A */
137 /* C+ mode */
138 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
139 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
140 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
141 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
142 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
143 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
144 TxThresh = 0xEC, /* Early Tx threshold */
145};
146
147enum ClearBitMasks {
148 MultiIntrClear = 0xF000,
149 ChipCmdClear = 0xE2,
150 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
151};
152
153enum ChipCmdBits {
154 CmdReset = 0x10,
155 CmdRxEnb = 0x08,
156 CmdTxEnb = 0x04,
157 RxBufEmpty = 0x01,
158};
159
160/* C+ mode */
161enum CplusCmdBits {
6cadb320
FB		 162 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
163 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
164 CPlusRxEnb = 0x0002,
165 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 166};
167
168/* Interrupt register bits, using my own meaningful names. */
169enum IntrStatusBits {
170 PCIErr = 0x8000,
171 PCSTimeout = 0x4000,
172 RxFIFOOver = 0x40,
9e12c5af 173 RxUnderrun = 0x20, /* Packet Underrun / Link Change */
a41b2ff2
PB		 174 RxOverflow = 0x10,
175 TxErr = 0x08,
176 TxOK = 0x04,
177 RxErr = 0x02,
178 RxOK = 0x01,
179
180 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
181};
182
183enum TxStatusBits {
184 TxHostOwns = 0x2000,
185 TxUnderrun = 0x4000,
186 TxStatOK = 0x8000,
187 TxOutOfWindow = 0x20000000,
188 TxAborted = 0x40000000,
189 TxCarrierLost = 0x80000000,
190};
191enum RxStatusBits {
192 RxMulticast = 0x8000,
193 RxPhysical = 0x4000,
194 RxBroadcast = 0x2000,
195 RxBadSymbol = 0x0020,
196 RxRunt = 0x0010,
197 RxTooLong = 0x0008,
198 RxCRCErr = 0x0004,
199 RxBadAlign = 0x0002,
200 RxStatusOK = 0x0001,
201};
202
203/* Bits in RxConfig. */
204enum rx_mode_bits {
205 AcceptErr = 0x20,
206 AcceptRunt = 0x10,
207 AcceptBroadcast = 0x08,
208 AcceptMulticast = 0x04,
209 AcceptMyPhys = 0x02,
210 AcceptAllPhys = 0x01,
211};
212
213/* Bits in TxConfig. */
214enum tx_config_bits {
215
216 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
217 TxIFGShift = 24,
218 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
219 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
220 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
221 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
222
223 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
224 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
225 TxClearAbt = (1 << 0), /* Clear abort (WO) */
226 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
227 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
228
229 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
230};
231
232
233/* Transmit Status of All Descriptors (TSAD) Register */
234enum TSAD_bits {
235 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
236 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
237 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
238 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
239 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
240 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
241 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
242 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
243 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
244 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
245 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
246 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
247 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
248 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
249 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
250 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
251};
252
253
254/* Bits in Config1 */
255enum Config1Bits {
256 Cfg1_PM_Enable = 0x01,
257 Cfg1_VPD_Enable = 0x02,
258 Cfg1_PIO = 0x04,
259 Cfg1_MMIO = 0x08,
260 LWAKE = 0x10, /* not on 8139, 8139A */
261 Cfg1_Driver_Load = 0x20,
262 Cfg1_LED0 = 0x40,
263 Cfg1_LED1 = 0x80,
264 SLEEP = (1 << 1), /* only on 8139, 8139A */
265 PWRDN = (1 << 0), /* only on 8139, 8139A */
266};
267
268/* Bits in Config3 */
269enum Config3Bits {
270 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
271 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
272 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
273 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
274 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
275 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
276 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
277 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
278};
279
280/* Bits in Config4 */
281enum Config4Bits {
282 LWPTN = (1 << 2), /* not on 8139, 8139A */
283};
284
285/* Bits in Config5 */
286enum Config5Bits {
287 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
288 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
289 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
290 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
291 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
292 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
293 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
294};
295
296enum RxConfigBits {
297 /* rx fifo threshold */
298 RxCfgFIFOShift = 13,
299 RxCfgFIFONone = (7 << RxCfgFIFOShift),
300
301 /* Max DMA burst */
302 RxCfgDMAShift = 8,
303 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
304
305 /* rx ring buffer length */
306 RxCfgRcv8K = 0,
307 RxCfgRcv16K = (1 << 11),
308 RxCfgRcv32K = (1 << 12),
309 RxCfgRcv64K = (1 << 11) | (1 << 12),
310
311 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
312 RxNoWrap = (1 << 7),
313};
314
315/* Twister tuning parameters from RealTek.
316 Completely undocumented, but required to tune bad links on some boards. */
317/*
318enum CSCRBits {
319 CSCR_LinkOKBit = 0x0400,
320 CSCR_LinkChangeBit = 0x0800,
321 CSCR_LinkStatusBits = 0x0f000,
322 CSCR_LinkDownOffCmd = 0x003c0,
323 CSCR_LinkDownCmd = 0x0f3c0,
324*/
325enum CSCRBits {
5fafdf24 326 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 327 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
328 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
329 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 330 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 331 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
332 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
333 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
334 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
335};
336
337enum Cfg9346Bits {
eb46c5ed
JW		 338 Cfg9346_Normal = 0x00,
339 Cfg9346_Autoload = 0x40,
340 Cfg9346_Programming = 0x80,
341 Cfg9346_ConfigWrite = 0xC0,
a41b2ff2
PB		 342};
343
344typedef enum {
345 CH_8139 = 0,
346 CH_8139_K,
347 CH_8139A,
348 CH_8139A_G,
349 CH_8139B,
350 CH_8130,
351 CH_8139C,
352 CH_8100,
353 CH_8100B_8139D,
354 CH_8101,
c227f099 355} chip_t;
a41b2ff2
PB		 356
357enum chip_flags {
358 HasHltClk = (1 << 0),
359 HasLWake = (1 << 1),
360};
361
362#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
363 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
364#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
365
6cadb320
FB		 366#define RTL8139_PCI_REVID_8139 0x10
367#define RTL8139_PCI_REVID_8139CPLUS 0x20
368
369#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
370
a41b2ff2
PB		 371/* Size is 64 * 16bit words */
372#define EEPROM_9346_ADDR_BITS 6
373#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
374#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
375
376enum Chip9346Operation
377{
378 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
379 Chip9346_op_read = 0x80, /* 10 AAAAAA */
380 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
381 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
382 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
383 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
384 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
385};
386
387enum Chip9346Mode
388{
389 Chip9346_none = 0,
390 Chip9346_enter_command_mode,
391 Chip9346_read_command,
392 Chip9346_data_read, /* from output register */
393 Chip9346_data_write, /* to input register, then to contents at specified address */
394 Chip9346_data_write_all, /* to input register, then filling contents */
395};
396
397typedef struct EEprom9346
398{
399 uint16_t contents[EEPROM_9346_SIZE];
400 int mode;
401 uint32_t tick;
402 uint8_t address;
403 uint16_t input;
404 uint16_t output;
405
406 uint8_t eecs;
407 uint8_t eesk;
408 uint8_t eedi;
409 uint8_t eedo;
410} EEprom9346;
411
6cadb320
FB		 412typedef struct RTL8139TallyCounters
413{
414 /* Tally counters */
415 uint64_t TxOk;
416 uint64_t RxOk;
417 uint64_t TxERR;
418 uint32_t RxERR;
419 uint16_t MissPkt;
420 uint16_t FAE;
421 uint32_t Tx1Col;
422 uint32_t TxMCol;
423 uint64_t RxOkPhy;
424 uint64_t RxOkBrd;
425 uint32_t RxOkMul;
426 uint16_t TxAbt;
427 uint16_t TxUndrn;
428} RTL8139TallyCounters;
429
430/* Clears all tally counters */
431static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
432
a41b2ff2 433typedef struct RTL8139State {
88a411a8
AF		 434 /*< private >*/
435 PCIDevice parent_obj;
436 /*< public >*/
437
a41b2ff2
PB		 438 uint8_t phys[8]; /* mac address */
439 uint8_t mult[8]; /* multicast mask array */
440
6cadb320 441 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 442 uint32_t TxAddr[4]; /* TxAddr0 */
443 uint32_t RxBuf; /* Receive buffer */
444 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
445 uint32_t RxBufPtr;
446 uint32_t RxBufAddr;
447
448 uint16_t IntrStatus;
449 uint16_t IntrMask;
450
451 uint32_t TxConfig;
452 uint32_t RxConfig;
453 uint32_t RxMissed;
454
455 uint16_t CSCR;
456
457 uint8_t Cfg9346;
458 uint8_t Config0;
459 uint8_t Config1;
460 uint8_t Config3;
461 uint8_t Config4;
462 uint8_t Config5;
463
464 uint8_t clock_enabled;
465 uint8_t bChipCmdState;
466
467 uint16_t MultiIntr;
468
469 uint16_t BasicModeCtrl;
470 uint16_t BasicModeStatus;
471 uint16_t NWayAdvert;
472 uint16_t NWayLPAR;
473 uint16_t NWayExpansion;
474
475 uint16_t CpCmd;
476 uint8_t TxThresh;
477
1673ad51 478 NICState *nic;
254111ec 479 NICConf conf;
a41b2ff2
PB		 480
481 /* C ring mode */
482 uint32_t currTxDesc;
483
484 /* C+ mode */
2c3891ab
AL		 485 uint32_t cplus_enabled;
486
a41b2ff2
PB		 487 uint32_t currCPlusRxDesc;
488 uint32_t currCPlusTxDesc;
489
490 uint32_t RxRingAddrLO;
491 uint32_t RxRingAddrHI;
492
493 EEprom9346 eeprom;
6cadb320
FB		 494
495 uint32_t TCTR;
496 uint32_t TimerInt;
497 int64_t TCTR_base;
498
499 /* Tally counters */
500 RTL8139TallyCounters tally_counters;
501
502 /* Non-persistent data */
503 uint8_t *cplus_txbuffer;
504 int cplus_txbuffer_len;
505 int cplus_txbuffer_offset;
506
507 /* PCI interrupt timer */
508 QEMUTimer *timer;
509
bd80f3fc
AK		 510 MemoryRegion bar_io;
511 MemoryRegion bar_mem;
512
c574ba5a
AW		 513 /* Support migration to/from old versions */
514 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 515} RTL8139State;
516
3ada003a
EGM		 517/* Writes tally counters to memory via DMA */
518static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
519
237c255c 520static void rtl8139_set_next_tctr_time(RTL8139State *s);
05447803 521
9596ebb7 522static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 523{
7cdeb319 524 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 525
526 switch (command & Chip9346_op_mask)
527 {
528 case Chip9346_op_read:
529 {
530 eeprom->address = command & EEPROM_9346_ADDR_MASK;
531 eeprom->output = eeprom->contents[eeprom->address];
532 eeprom->eedo = 0;
533 eeprom->tick = 0;
534 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 535 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
536 eeprom->address, eeprom->output);
a41b2ff2
PB		 537 }
538 break;
539
540 case Chip9346_op_write:
541 {
542 eeprom->address = command & EEPROM_9346_ADDR_MASK;
543 eeprom->input = 0;
544 eeprom->tick = 0;
545 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 546 DPRINTF("eeprom begin write to address 0x%02x\n",
547 eeprom->address);
a41b2ff2
PB		 548 }
549 break;
550 default:
551 eeprom->mode = Chip9346_none;
552 switch (command & Chip9346_op_ext_mask)
553 {
554 case Chip9346_op_write_enable:
7cdeb319 555 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 556 break;
557 case Chip9346_op_write_all:
7cdeb319 558 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 559 break;
560 case Chip9346_op_write_disable:
7cdeb319 561 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 562 break;
563 }
564 break;
565 }
566}
567
9596ebb7 568static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 569{
570 int bit = eeprom->eedi?1:0;
571
572 ++ eeprom->tick;
573
7cdeb319
BP		 574 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
575 eeprom->eedo);
a41b2ff2
PB		 576
577 switch (eeprom->mode)
578 {
579 case Chip9346_enter_command_mode:
580 if (bit)
581 {
582 eeprom->mode = Chip9346_read_command;
583 eeprom->tick = 0;
584 eeprom->input = 0;
7cdeb319 585 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 586 }
587 break;
588
589 case Chip9346_read_command:
590 eeprom->input = (eeprom->input << 1) | (bit & 1);
591 if (eeprom->tick == 8)
592 {
593 prom9346_decode_command(eeprom, eeprom->input & 0xff);
594 }
595 break;
596
597 case Chip9346_data_read:
598 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
599 eeprom->output <<= 1;
600 if (eeprom->tick == 16)
601 {
6cadb320
FB		 602#if 1
603 // the FreeBSD drivers (rl and re) don't explicitly toggle
604 // CS between reads (or does setting Cfg9346 to 0 count too?),
605 // so we need to enter wait-for-command state here
606 eeprom->mode = Chip9346_enter_command_mode;
607 eeprom->input = 0;
608 eeprom->tick = 0;
609
7cdeb319 610 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 611#else
612 // original behaviour
a41b2ff2
PB		 613 ++eeprom->address;
614 eeprom->address &= EEPROM_9346_ADDR_MASK;
615 eeprom->output = eeprom->contents[eeprom->address];
616 eeprom->tick = 0;
617
7cdeb319
BP		 618 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
619 eeprom->address, eeprom->output);
a41b2ff2
PB		 620#endif
621 }
622 break;
623
624 case Chip9346_data_write:
625 eeprom->input = (eeprom->input << 1) | (bit & 1);
626 if (eeprom->tick == 16)
627 {
7cdeb319
BP		 628 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
629 eeprom->address, eeprom->input);
6cadb320 630
a41b2ff2
PB		 631 eeprom->contents[eeprom->address] = eeprom->input;
632 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
633 eeprom->tick = 0;
634 eeprom->input = 0;
635 }
636 break;
637
638 case Chip9346_data_write_all:
639 eeprom->input = (eeprom->input << 1) | (bit & 1);
640 if (eeprom->tick == 16)
641 {
642 int i;
643 for (i = 0; i < EEPROM_9346_SIZE; i++)
644 {
645 eeprom->contents[i] = eeprom->input;
646 }
7cdeb319 647 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 648
a41b2ff2
PB		 649 eeprom->mode = Chip9346_enter_command_mode;
650 eeprom->tick = 0;
651 eeprom->input = 0;
652 }
653 break;
654
655 default:
656 break;
657 }
658}
659
9596ebb7 660static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 661{
662 EEprom9346 *eeprom = &s->eeprom;
663 if (!eeprom->eecs)
664 return 0;
665
666 return eeprom->eedo;
667}
668
9596ebb7
PB		 669/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
670static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 671{
672 EEprom9346 *eeprom = &s->eeprom;
673 uint8_t old_eecs = eeprom->eecs;
674 uint8_t old_eesk = eeprom->eesk;
675
676 eeprom->eecs = eecs;
677 eeprom->eesk = eesk;
678 eeprom->eedi = eedi;
679
7cdeb319
BP		 680 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
681 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 682
683 if (!old_eecs && eecs)
684 {
685 /* Synchronize start */
686 eeprom->tick = 0;
687 eeprom->input = 0;
688 eeprom->output = 0;
689 eeprom->mode = Chip9346_enter_command_mode;
690
7cdeb319 691 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 692 }
693
694 if (!eecs)
695 {
7cdeb319 696 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 697 return;
698 }
699
700 if (!old_eesk && eesk)
701 {
702 /* SK front rules */
703 prom9346_shift_clock(eeprom);
704 }
705}
706
707static void rtl8139_update_irq(RTL8139State *s)
708{
88a411a8 709 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 710 int isr;
711 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 712
7cdeb319
BP		 713 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
714 s->IntrMask);
6cadb320 715
9e64f8a3 716 pci_set_irq(d, (isr != 0));
a41b2ff2
PB		 717}
718
a41b2ff2
PB		 719static int rtl8139_RxWrap(RTL8139State *s)
720{
721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
722 return (s->RxConfig & (1 << 7));
723}
724
725static int rtl8139_receiver_enabled(RTL8139State *s)
726{
727 return s->bChipCmdState & CmdRxEnb;
728}
729
730static int rtl8139_transmitter_enabled(RTL8139State *s)
731{
732 return s->bChipCmdState & CmdTxEnb;
733}
734
735static int rtl8139_cp_receiver_enabled(RTL8139State *s)
736{
737 return s->CpCmd & CPlusRxEnb;
738}
739
740static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
741{
742 return s->CpCmd & CPlusTxEnb;
743}
744
745static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
746{
88a411a8
AF		 747 PCIDevice *d = PCI_DEVICE(s);
748
a41b2ff2
PB		 749 if (s->RxBufAddr + size > s->RxBufferSize)
750 {
751 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
752
753 /* write packet data */
ccf1d14a 754 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 755 {
7cdeb319 756 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 757
758 if (size > wrapped)
759 {
88a411a8 760 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
3ada003a 761 buf, size-wrapped);
a41b2ff2
PB		 762 }
763
764 /* reset buffer pointer */
765 s->RxBufAddr = 0;
766
88a411a8 767 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
3ada003a 768 buf + (size-wrapped), wrapped);
a41b2ff2
PB		 769
770 s->RxBufAddr = wrapped;
771
772 return;
773 }
774 }
775
776 /* non-wrapping path or overwrapping enabled */
88a411a8 777 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
a41b2ff2
PB		 778
779 s->RxBufAddr += size;
780}
781
782#define MIN_BUF_SIZE 60
3ada003a 783static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2 784{
4be403c8 785 return low | ((uint64_t)high << 32);
a41b2ff2
PB		 786}
787
fcce6fd2
JW		 788/* Workaround for buggy guest driver such as linux who allocates rx
789 * rings after the receiver were enabled. */
790static bool rtl8139_cp_rx_valid(RTL8139State *s)
791{
792 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
793}
794
4e68f7a0 795static int rtl8139_can_receive(NetClientState *nc)
a41b2ff2 796{
cc1f0f45 797 RTL8139State *s = qemu_get_nic_opaque(nc);
a41b2ff2
PB		 798 int avail;
799
aa1f17c1 800 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 801 if (!s->clock_enabled)
802 return 1;
803 if (!rtl8139_receiver_enabled(s))
804 return 1;
805
fcce6fd2 806 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
a41b2ff2
PB		 807 /* ??? Flow control not implemented in c+ mode.
808 This is a hack to work around slirp deficiencies anyway. */
809 return 1;
810 } else {
811 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
812 s->RxBufferSize);
fee9d348 813 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow));
a41b2ff2
PB		 814 }
815}
816
4e68f7a0 817static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 818{
cc1f0f45 819 RTL8139State *s = qemu_get_nic_opaque(nc);
88a411a8 820 PCIDevice *d = PCI_DEVICE(s);
18dabfd1 821 /* size is the length of the buffer passed to the driver */
1a326646 822 size_t size = size_;
18dabfd1 823 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 824
825 uint32_t packet_header = 0;
826
18dabfd1 827 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 828 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 829 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
830
1a326646 831 DPRINTF(">>> received len=%zu\n", size);
a41b2ff2
PB		 832
833 /* test if board clock is stopped */
834 if (!s->clock_enabled)
835 {
7cdeb319 836 DPRINTF("stopped ==========================\n");
4f1c942b 837 return -1;
a41b2ff2
PB		 838 }
839
840 /* first check if receiver is enabled */
841
842 if (!rtl8139_receiver_enabled(s))
843 {
7cdeb319 844 DPRINTF("receiver disabled ================\n");
4f1c942b 845 return -1;
a41b2ff2
PB		 846 }
847
848 /* XXX: check this */
849 if (s->RxConfig & AcceptAllPhys) {
850 /* promiscuous: receive all */
7cdeb319 851 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 852
853 } else {
854 if (!memcmp(buf, broadcast_macaddr, 6)) {
855 /* broadcast address */
856 if (!(s->RxConfig & AcceptBroadcast))
857 {
7cdeb319 858 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 859
860 /* update tally counter */
861 ++s->tally_counters.RxERR;
862
4f1c942b 863 return size;
a41b2ff2
PB		 864 }
865
866 packet_header |= RxBroadcast;
867
7cdeb319 868 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 869
870 /* update tally counter */
871 ++s->tally_counters.RxOkBrd;
872
a41b2ff2
PB		 873 } else if (buf[0] & 0x01) {
874 /* multicast */
875 if (!(s->RxConfig & AcceptMulticast))
876 {
7cdeb319 877 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 878
879 /* update tally counter */
880 ++s->tally_counters.RxERR;
881
4f1c942b 882 return size;
a41b2ff2
PB		 883 }
884
e7a58fc7 885 int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
a41b2ff2
PB		 886
887 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
888 {
7cdeb319 889 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 890
891 /* update tally counter */
892 ++s->tally_counters.RxERR;
893
4f1c942b 894 return size;
a41b2ff2
PB		 895 }
896
897 packet_header |= RxMulticast;
898
7cdeb319 899 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 900
901 /* update tally counter */
902 ++s->tally_counters.RxOkMul;
903
a41b2ff2 904 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 905 s->phys[1] == buf[1] &&
906 s->phys[2] == buf[2] &&
907 s->phys[3] == buf[3] &&
908 s->phys[4] == buf[4] &&
a41b2ff2
PB		 909 s->phys[5] == buf[5]) {
910 /* match */
911 if (!(s->RxConfig & AcceptMyPhys))
912 {
7cdeb319 913 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 914
915 /* update tally counter */
916 ++s->tally_counters.RxERR;
917
4f1c942b 918 return size;
a41b2ff2
PB		 919 }
920
921 packet_header |= RxPhysical;
922
7cdeb319 923 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 924
925 /* update tally counter */
926 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 927
928 } else {
929
7cdeb319 930 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 931
932 /* update tally counter */
933 ++s->tally_counters.RxERR;
934
4f1c942b 935 return size;
a41b2ff2
PB		 936 }
937 }
938
18dabfd1
BP		 939 /* if too small buffer, then expand it
940 * Include some tailroom in case a vlan tag is later removed. */
941 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 942 memcpy(buf1, buf, size);
18dabfd1 943 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 944 buf = buf1;
18dabfd1
BP		 945 if (size < MIN_BUF_SIZE) {
946 size = MIN_BUF_SIZE;
947 }
a41b2ff2
PB		 948 }
949
950 if (rtl8139_cp_receiver_enabled(s))
951 {
fcce6fd2
JW		 952 if (!rtl8139_cp_rx_valid(s)) {
953 return size;
954 }
955
7cdeb319 956 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 957
958 /* begin C+ receiver mode */
959
960/* w0 ownership flag */
961#define CP_RX_OWN (1<<31)
962/* w0 end of ring flag */
963#define CP_RX_EOR (1<<30)
964/* w0 bits 0...12 : buffer size */
965#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
966/* w1 tag available flag */
967#define CP_RX_TAVA (1<<16)
968/* w1 bits 0...15 : VLAN tag */
969#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
970/* w2 low 32bit of Rx buffer ptr */
971/* w3 high 32bit of Rx buffer ptr */
972
973 int descriptor = s->currCPlusRxDesc;
3ada003a 974 dma_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 975
976 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
977 cplus_rx_ring_desc += 16 * descriptor;
978
7cdeb319 979 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
3ada003a 980 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
7cdeb319 981 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 982
983 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
984
88a411a8 985 pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
a41b2ff2 986 rxdw0 = le32_to_cpu(val);
88a411a8 987 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
a41b2ff2 988 rxdw1 = le32_to_cpu(val);
88a411a8 989 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
a41b2ff2 990 rxbufLO = le32_to_cpu(val);
88a411a8 991 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
a41b2ff2
PB		 992 rxbufHI = le32_to_cpu(val);
993
7cdeb319
BP		 994 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
995 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 996
997 if (!(rxdw0 & CP_RX_OWN))
998 {
7cdeb319
BP		 999 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1000 descriptor);
6cadb320 1001
a41b2ff2
PB		 1002 s->IntrStatus |= RxOverflow;
1003 ++s->RxMissed;
6cadb320
FB		 1004
1005 /* update tally counter */
1006 ++s->tally_counters.RxERR;
1007 ++s->tally_counters.MissPkt;
1008
a41b2ff2 1009 rtl8139_update_irq(s);
4f1c942b 1010 return size_;
a41b2ff2
PB		 1011 }
1012
1013 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1014
18dabfd1 1015 /* write VLAN info to descriptor variables. */
6960bfca
PM		 1016 if (s->CpCmd & CPlusRxVLAN &&
1017 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) {
1bf11332 1018 dot1q_buf = &buf[ETH_ALEN * 2];
18dabfd1
BP		 1019 size -= VLAN_HLEN;
1020 /* if too small buffer, use the tailroom added duing expansion */
1021 if (size < MIN_BUF_SIZE) {
1022 size = MIN_BUF_SIZE;
1023 }
1024
1025 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1026 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
6960bfca 1027 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]);
18dabfd1 1028
7cdeb319 1029 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
6960bfca 1030 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1031 } else {
1032 /* reset VLAN tag flag */
1033 rxdw1 &= ~CP_RX_TAVA;
1034 }
1035
6cadb320
FB		 1036 /* TODO: scatter the packet over available receive ring descriptors space */
1037
a41b2ff2
PB		 1038 if (size+4 > rx_space)
1039 {
1a326646 1040 DPRINTF("C+ Rx mode : descriptor %d size %d received %zu + 4\n",
7cdeb319 1041 descriptor, rx_space, size);
6cadb320 1042
a41b2ff2
PB		 1043 s->IntrStatus |= RxOverflow;
1044 ++s->RxMissed;
6cadb320
FB		 1045
1046 /* update tally counter */
1047 ++s->tally_counters.RxERR;
1048 ++s->tally_counters.MissPkt;
1049
a41b2ff2 1050 rtl8139_update_irq(s);
4f1c942b 1051 return size_;
a41b2ff2
PB		 1052 }
1053
3ada003a 1054 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1055
1056 /* receive/copy to target memory */
18dabfd1 1057 if (dot1q_buf) {
1bf11332
SH		 1058 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN);
1059 pci_dma_write(d, rx_addr + 2 * ETH_ALEN,
1060 buf + 2 * ETH_ALEN + VLAN_HLEN,
1061 size - 2 * ETH_ALEN);
18dabfd1 1062 } else {
88a411a8 1063 pci_dma_write(d, rx_addr, buf, size);
18dabfd1 1064 }
a41b2ff2 1065
6cadb320
FB		 1066 if (s->CpCmd & CPlusRxChkSum)
1067 {
1068 /* do some packet checksumming */
1069 }
1070
a41b2ff2 1071 /* write checksum */
18dabfd1 1072 val = cpu_to_le32(crc32(0, buf, size_));
88a411a8 1073 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
a41b2ff2
PB		 1074
1075/* first segment of received packet flag */
1076#define CP_RX_STATUS_FS (1<<29)
1077/* last segment of received packet flag */
1078#define CP_RX_STATUS_LS (1<<28)
1079/* multicast packet flag */
1080#define CP_RX_STATUS_MAR (1<<26)
1081/* physical-matching packet flag */
1082#define CP_RX_STATUS_PAM (1<<25)
1083/* broadcast packet flag */
1084#define CP_RX_STATUS_BAR (1<<24)
1085/* runt packet flag */
1086#define CP_RX_STATUS_RUNT (1<<19)
1087/* crc error flag */
1088#define CP_RX_STATUS_CRC (1<<18)
1089/* IP checksum error flag */
1090#define CP_RX_STATUS_IPF (1<<15)
1091/* UDP checksum error flag */
1092#define CP_RX_STATUS_UDPF (1<<14)
1093/* TCP checksum error flag */
1094#define CP_RX_STATUS_TCPF (1<<13)
1095
1096 /* transfer ownership to target */
1097 rxdw0 &= ~CP_RX_OWN;
1098
1099 /* set first segment bit */
1100 rxdw0 |= CP_RX_STATUS_FS;
1101
1102 /* set last segment bit */
1103 rxdw0 |= CP_RX_STATUS_LS;
1104
1105 /* set received packet type flags */
1106 if (packet_header & RxBroadcast)
1107 rxdw0 |= CP_RX_STATUS_BAR;
1108 if (packet_header & RxMulticast)
1109 rxdw0 |= CP_RX_STATUS_MAR;
1110 if (packet_header & RxPhysical)
1111 rxdw0 |= CP_RX_STATUS_PAM;
1112
1113 /* set received size */
1114 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1115 rxdw0 |= (size+4);
1116
a41b2ff2
PB		 1117 /* update ring data */
1118 val = cpu_to_le32(rxdw0);
88a411a8 1119 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1120 val = cpu_to_le32(rxdw1);
88a411a8 1121 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1122
6cadb320
FB		 1123 /* update tally counter */
1124 ++s->tally_counters.RxOk;
1125
a41b2ff2
PB		 1126 /* seek to next Rx descriptor */
1127 if (rxdw0 & CP_RX_EOR)
1128 {
1129 s->currCPlusRxDesc = 0;
1130 }
1131 else
1132 {
1133 ++s->currCPlusRxDesc;
1134 }
1135
7cdeb319 1136 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1137
1138 }
1139 else
1140 {
7cdeb319 1141 DPRINTF("in ring Rx mode ================\n");
6cadb320 1142
a41b2ff2
PB		 1143 /* begin ring receiver mode */
1144 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1145
1146 /* if receiver buffer is empty then avail == 0 */
1147
fabdcd33
VY		 1148#define RX_ALIGN(x) (((x) + 3) & ~0x3)
1149
1150 if (avail != 0 && RX_ALIGN(size + 8) >= avail)
a41b2ff2 1151 {
7cdeb319 1152 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1a326646 1153 "read 0x%04x === available 0x%04x need 0x%04zx\n",
7cdeb319 1154 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1155
a41b2ff2
PB		 1156 s->IntrStatus |= RxOverflow;
1157 ++s->RxMissed;
1158 rtl8139_update_irq(s);
26c4e7ca 1159 return 0;
a41b2ff2
PB		 1160 }
1161
1162 packet_header |= RxStatusOK;
1163
1164 packet_header |= (((size+4) << 16) & 0xffff0000);
1165
1166 /* write header */
1167 uint32_t val = cpu_to_le32(packet_header);
1168
1169 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1170
1171 rtl8139_write_buffer(s, buf, size);
1172
1173 /* write checksum */
ccf1d14a 1174 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1175 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1176
1177 /* correct buffer write pointer */
fabdcd33 1178 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize);
a41b2ff2
PB		 1179
1180 /* now we can signal we have received something */
1181
7cdeb319
BP		 1182 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1183 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1184 }
1185
1186 s->IntrStatus |= RxOK;
6cadb320
FB		 1187
1188 if (do_interrupt)
1189 {
1190 rtl8139_update_irq(s);
1191 }
4f1c942b
MM		 1192
1193 return size_;
6cadb320
FB		 1194}
1195
4e68f7a0 1196static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1197{
1673ad51 1198 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1199}
1200
1201static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1202{
1203 s->RxBufferSize = bufferSize;
1204 s->RxBufPtr = 0;
1205 s->RxBufAddr = 0;
1206}
1207
30a3e701
HP		 1208static void rtl8139_reset_phy(RTL8139State *s)
1209{
1210 s->BasicModeStatus = 0x7809;
1211 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1212 /* preserve link state */
1213 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04;
1214
1215 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1216 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1217 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1218
1219 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1220}
1221
7f23f812 1222static void rtl8139_reset(DeviceState *d)
a41b2ff2 1223{
39257515 1224 RTL8139State *s = RTL8139(d);
a41b2ff2
PB		 1225 int i;
1226
1227 /* restore MAC address */
254111ec 1228 memcpy(s->phys, s->conf.macaddr.a, 6);
655d3b63 1229 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
a41b2ff2
PB		 1230
1231 /* reset interrupt mask */
1232 s->IntrStatus = 0;
1233 s->IntrMask = 0;
1234
1235 rtl8139_update_irq(s);
1236
a41b2ff2
PB		 1237 /* mark all status registers as owned by host */
1238 for (i = 0; i < 4; ++i)
1239 {
1240 s->TxStatus[i] = TxHostOwns;
1241 }
1242
1243 s->currTxDesc = 0;
1244 s->currCPlusRxDesc = 0;
1245 s->currCPlusTxDesc = 0;
1246
1247 s->RxRingAddrLO = 0;
1248 s->RxRingAddrHI = 0;
1249
1250 s->RxBuf = 0;
1251
1252 rtl8139_reset_rxring(s, 8192);
1253
1254 /* ACK the reset */
1255 s->TxConfig = 0;
1256
1257#if 0
1258// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1259 s->clock_enabled = 0;
1260#else
6cadb320 1261 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1262 s->clock_enabled = 1;
1263#endif
1264
1265 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1266
1267 /* set initial state data */
1268 s->Config0 = 0x0; /* No boot ROM */
1269 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1270 s->Config3 = 0x1; /* fast back-to-back compatible */
1271 s->Config5 = 0x0;
1272
a41b2ff2 1273 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1274 s->cplus_enabled = 0;
1275
a41b2ff2
PB		 1276// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1277// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1278 s->BasicModeCtrl = 0x1000; // autonegotiation
1279
30a3e701 1280 rtl8139_reset_phy(s);
6cadb320
FB		 1281
1282 /* also reset timer and disable timer interrupt */
1283 s->TCTR = 0;
1284 s->TimerInt = 0;
1285 s->TCTR_base = 0;
237c255c 1286 rtl8139_set_next_tctr_time(s);
6cadb320
FB		 1287
1288 /* reset tally counters */
1289 RTL8139TallyCounters_clear(&s->tally_counters);
1290}
1291
b1d8e52e 1292static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1293{
1294 counters->TxOk = 0;
1295 counters->RxOk = 0;
1296 counters->TxERR = 0;
1297 counters->RxERR = 0;
1298 counters->MissPkt = 0;
1299 counters->FAE = 0;
1300 counters->Tx1Col = 0;
1301 counters->TxMCol = 0;
1302 counters->RxOkPhy = 0;
1303 counters->RxOkBrd = 0;
1304 counters->RxOkMul = 0;
1305 counters->TxAbt = 0;
1306 counters->TxUndrn = 0;
1307}
1308
3ada003a 1309static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
6cadb320 1310{
88a411a8 1311 PCIDevice *d = PCI_DEVICE(s);
3ada003a 1312 RTL8139TallyCounters *tally_counters = &s->tally_counters;
6cadb320
FB		 1313 uint16_t val16;
1314 uint32_t val32;
1315 uint64_t val64;
1316
1317 val64 = cpu_to_le64(tally_counters->TxOk);
88a411a8 1318 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
6cadb320
FB		 1319
1320 val64 = cpu_to_le64(tally_counters->RxOk);
88a411a8 1321 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
6cadb320
FB		 1322
1323 val64 = cpu_to_le64(tally_counters->TxERR);
88a411a8 1324 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
6cadb320
FB		 1325
1326 val32 = cpu_to_le32(tally_counters->RxERR);
88a411a8 1327 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
6cadb320
FB		 1328
1329 val16 = cpu_to_le16(tally_counters->MissPkt);
88a411a8 1330 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
6cadb320
FB		 1331
1332 val16 = cpu_to_le16(tally_counters->FAE);
88a411a8 1333 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
6cadb320
FB		 1334
1335 val32 = cpu_to_le32(tally_counters->Tx1Col);
88a411a8 1336 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
6cadb320
FB		 1337
1338 val32 = cpu_to_le32(tally_counters->TxMCol);
88a411a8 1339 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
6cadb320
FB		 1340
1341 val64 = cpu_to_le64(tally_counters->RxOkPhy);
88a411a8 1342 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
6cadb320
FB		 1343
1344 val64 = cpu_to_le64(tally_counters->RxOkBrd);
88a411a8 1345 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
6cadb320
FB		 1346
1347 val32 = cpu_to_le32(tally_counters->RxOkMul);
88a411a8 1348 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
6cadb320
FB		 1349
1350 val16 = cpu_to_le16(tally_counters->TxAbt);
88a411a8 1351 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
6cadb320
FB		 1352
1353 val16 = cpu_to_le16(tally_counters->TxUndrn);
88a411a8 1354 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
6cadb320
FB		 1355}
1356
a41b2ff2
PB		 1357static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1358{
39257515
PC		 1359 DeviceState *d = DEVICE(s);
1360
a41b2ff2
PB		 1361 val &= 0xff;
1362
7cdeb319 1363 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1364
1365 if (val & CmdReset)
1366 {
7cdeb319 1367 DPRINTF("ChipCmd reset\n");
39257515 1368 rtl8139_reset(d);
a41b2ff2
PB		 1369 }
1370 if (val & CmdRxEnb)
1371 {
7cdeb319 1372 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1373
1374 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1375 }
1376 if (val & CmdTxEnb)
1377 {
7cdeb319 1378 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1379
1380 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1381 }
1382
ebabb67a 1383 /* mask unwritable bits */
a41b2ff2
PB		 1384 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1385
1386 /* Deassert reset pin before next read */
1387 val &= ~CmdReset;
1388
1389 s->bChipCmdState = val;
1390}
1391
1392static int rtl8139_RxBufferEmpty(RTL8139State *s)
1393{
1394 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1395
1396 if (unread != 0)
1397 {
7cdeb319 1398 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1399 return 0;
1400 }
1401
7cdeb319 1402 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1403
1404 return 1;
1405}
1406
1407static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1408{
1409 uint32_t ret = s->bChipCmdState;
1410
1411 if (rtl8139_RxBufferEmpty(s))
1412 ret |= RxBufEmpty;
1413
7cdeb319 1414 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1415
1416 return ret;
1417}
1418
1419static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1420{
1421 val &= 0xffff;
1422
7cdeb319 1423 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1424
2c3891ab
AL		 1425 s->cplus_enabled = 1;
1426
ebabb67a 1427 /* mask unwritable bits */
a41b2ff2
PB		 1428 val = SET_MASKED(val, 0xff84, s->CpCmd);
1429
1430 s->CpCmd = val;
1431}
1432
1433static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1434{
1435 uint32_t ret = s->CpCmd;
1436
7cdeb319 1437 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1438
1439 return ret;
1440}
1441
1442static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1443{
7cdeb319 1444 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1445}
1446
1447static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1448{
1449 uint32_t ret = 0;
1450
7cdeb319 1451 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1452
1453 return ret;
1454}
1455
ebabb67a 1456static int rtl8139_config_writable(RTL8139State *s)
a41b2ff2 1457{
eb46c5ed 1458 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
a41b2ff2
PB		 1459 {
1460 return 1;
1461 }
1462
7cdeb319 1463 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1464
1465 return 0;
1466}
1467
1468static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1469{
1470 val &= 0xffff;
1471
7cdeb319 1472 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2 1473
ebabb67a 1474 /* mask unwritable bits */
30a3e701 1475 uint32_t mask = 0xccff;
a41b2ff2 1476
ebabb67a 1477 if (1 || !rtl8139_config_writable(s))
a41b2ff2
PB		 1478 {
1479 /* Speed setting and autonegotiation enable bits are read-only */
1480 mask |= 0x3000;
1481 /* Duplex mode setting is read-only */
1482 mask |= 0x0100;
1483 }
1484
30a3e701
HP		 1485 if (val & 0x8000) {
1486 /* Reset PHY */
1487 rtl8139_reset_phy(s);
1488 }
1489
a41b2ff2
PB		 1490 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1491
1492 s->BasicModeCtrl = val;
1493}
1494
1495static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1496{
1497 uint32_t ret = s->BasicModeCtrl;
1498
7cdeb319 1499 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1500
1501 return ret;
1502}
1503
1504static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1505{
1506 val &= 0xffff;
1507
7cdeb319 1508 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2 1509
ebabb67a 1510 /* mask unwritable bits */
a41b2ff2
PB		 1511 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1512
1513 s->BasicModeStatus = val;
1514}
1515
1516static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1517{
1518 uint32_t ret = s->BasicModeStatus;
1519
7cdeb319 1520 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1521
1522 return ret;
1523}
1524
1525static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1526{
39257515
PC		 1527 DeviceState *d = DEVICE(s);
1528
a41b2ff2
PB		 1529 val &= 0xff;
1530
7cdeb319 1531 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2 1532
ebabb67a 1533 /* mask unwritable bits */
a41b2ff2
PB		 1534 val = SET_MASKED(val, 0x31, s->Cfg9346);
1535
1536 uint32_t opmode = val & 0xc0;
1537 uint32_t eeprom_val = val & 0xf;
1538
1539 if (opmode == 0x80) {
1540 /* eeprom access */
1541 int eecs = (eeprom_val & 0x08)?1:0;
1542 int eesk = (eeprom_val & 0x04)?1:0;
1543 int eedi = (eeprom_val & 0x02)?1:0;
1544 prom9346_set_wire(s, eecs, eesk, eedi);
1545 } else if (opmode == 0x40) {
1546 /* Reset. */
1547 val = 0;
39257515 1548 rtl8139_reset(d);
a41b2ff2
PB		 1549 }
1550
1551 s->Cfg9346 = val;
1552}
1553
1554static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1555{
1556 uint32_t ret = s->Cfg9346;
1557
1558 uint32_t opmode = ret & 0xc0;
1559
1560 if (opmode == 0x80)
1561 {
1562 /* eeprom access */
1563 int eedo = prom9346_get_wire(s);
1564 if (eedo)
1565 {
1566 ret |= 0x01;
1567 }
1568 else
1569 {
1570 ret &= ~0x01;
1571 }
1572 }
1573
7cdeb319 1574 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1575
1576 return ret;
1577}
1578
1579static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1580{
1581 val &= 0xff;
1582
7cdeb319 1583 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2 1584
ebabb67a 1585 if (!rtl8139_config_writable(s)) {
a41b2ff2 1586 return;
ebabb67a 1587 }
a41b2ff2 1588
ebabb67a 1589 /* mask unwritable bits */
a41b2ff2
PB		 1590 val = SET_MASKED(val, 0xf8, s->Config0);
1591
1592 s->Config0 = val;
1593}
1594
1595static uint32_t rtl8139_Config0_read(RTL8139State *s)
1596{
1597 uint32_t ret = s->Config0;
1598
7cdeb319 1599 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1600
1601 return ret;
1602}
1603
1604static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1605{
1606 val &= 0xff;
1607
7cdeb319 1608 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2 1609
ebabb67a 1610 if (!rtl8139_config_writable(s)) {
a41b2ff2 1611 return;
ebabb67a 1612 }
a41b2ff2 1613
ebabb67a 1614 /* mask unwritable bits */
a41b2ff2
PB		 1615 val = SET_MASKED(val, 0xC, s->Config1);
1616
1617 s->Config1 = val;
1618}
1619
1620static uint32_t rtl8139_Config1_read(RTL8139State *s)
1621{
1622 uint32_t ret = s->Config1;
1623
7cdeb319 1624 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1625
1626 return ret;
1627}
1628
1629static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1630{
1631 val &= 0xff;
1632
7cdeb319 1633 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2 1634
ebabb67a 1635 if (!rtl8139_config_writable(s)) {
a41b2ff2 1636 return;
ebabb67a 1637 }
a41b2ff2 1638
ebabb67a 1639 /* mask unwritable bits */
a41b2ff2
PB		 1640 val = SET_MASKED(val, 0x8F, s->Config3);
1641
1642 s->Config3 = val;
1643}
1644
1645static uint32_t rtl8139_Config3_read(RTL8139State *s)
1646{
1647 uint32_t ret = s->Config3;
1648
7cdeb319 1649 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1650
1651 return ret;
1652}
1653
1654static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1655{
1656 val &= 0xff;
1657
7cdeb319 1658 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2 1659
ebabb67a 1660 if (!rtl8139_config_writable(s)) {
a41b2ff2 1661 return;
ebabb67a 1662 }
a41b2ff2 1663
ebabb67a 1664 /* mask unwritable bits */
a41b2ff2
PB		 1665 val = SET_MASKED(val, 0x0a, s->Config4);
1666
1667 s->Config4 = val;
1668}
1669
1670static uint32_t rtl8139_Config4_read(RTL8139State *s)
1671{
1672 uint32_t ret = s->Config4;
1673
7cdeb319 1674 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1675
1676 return ret;
1677}
1678
1679static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1680{
1681 val &= 0xff;
1682
7cdeb319 1683 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2 1684
ebabb67a 1685 /* mask unwritable bits */
a41b2ff2
PB		 1686 val = SET_MASKED(val, 0x80, s->Config5);
1687
1688 s->Config5 = val;
1689}
1690
1691static uint32_t rtl8139_Config5_read(RTL8139State *s)
1692{
1693 uint32_t ret = s->Config5;
1694
7cdeb319 1695 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1696
1697 return ret;
1698}
1699
1700static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1701{
1702 if (!rtl8139_transmitter_enabled(s))
1703 {
7cdeb319 1704 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1705 return;
1706 }
1707
7cdeb319 1708 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1709
1710 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1711
1712 s->TxConfig = val;
1713}
1714
1715static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1716{
7cdeb319 1717 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1718
1719 uint32_t tc = s->TxConfig;
1720 tc &= 0xFFFFFF00;
1721 tc |= (val & 0x000000FF);
1722 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1723}
1724
1725static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1726{
1727 uint32_t ret = s->TxConfig;
1728
7cdeb319 1729 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1730
1731 return ret;
1732}
1733
1734static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1735{
7cdeb319 1736 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2 1737
ebabb67a 1738 /* mask unwritable bits */
a41b2ff2
PB		 1739 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1740
1741 s->RxConfig = val;
1742
1743 /* reset buffer size and read/write pointers */
1744 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1745
7cdeb319 1746 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1747}
1748
1749static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1750{
1751 uint32_t ret = s->RxConfig;
1752
7cdeb319 1753 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1754
1755 return ret;
1756}
1757
bf6b87a8
BP		 1758static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1759 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1760{
bf6b87a8 1761 struct iovec *iov = NULL;
b0af8440 1762 struct iovec vlan_iov[3];
bf6b87a8 1763
718da2b9
FB		 1764 if (!size)
1765 {
7cdeb319 1766 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1767 return;
1768 }
1769
1bf11332 1770 if (dot1q_buf && size >= ETH_ALEN * 2) {
bf6b87a8 1771 iov = (struct iovec[3]) {
1bf11332 1772 { .iov_base = buf, .iov_len = ETH_ALEN * 2 },
bf6b87a8 1773 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1bf11332
SH		 1774 { .iov_base = buf + ETH_ALEN * 2,
1775 .iov_len = size - ETH_ALEN * 2 },
bf6b87a8 1776 };
b0af8440
GA		 1777
1778 memcpy(vlan_iov, iov, sizeof(vlan_iov));
1779 iov = vlan_iov;
bf6b87a8
BP		 1780 }
1781
718da2b9
FB		 1782 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1783 {
bf6b87a8
BP		 1784 size_t buf2_size;
1785 uint8_t *buf2;
1786
1787 if (iov) {
1788 buf2_size = iov_size(iov, 3);
7267c094 1789 buf2 = g_malloc(buf2_size);
dcf6f5e1 1790 iov_to_buf(iov, 3, 0, buf2, buf2_size);
bf6b87a8
BP		 1791 buf = buf2;
1792 }
1793
7cdeb319 1794 DPRINTF("+++ transmit loopback mode\n");
b356f76d 1795 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt);
bf6b87a8
BP		 1796
1797 if (iov) {
7267c094 1798 g_free(buf2);
bf6b87a8 1799 }
718da2b9
FB		 1800 }
1801 else
1802 {
bf6b87a8 1803 if (iov) {
b356f76d 1804 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3);
bf6b87a8 1805 } else {
b356f76d 1806 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
bf6b87a8 1807 }
718da2b9
FB		 1808 }
1809}
1810
a41b2ff2
PB		 1811static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1812{
1813 if (!rtl8139_transmitter_enabled(s))
1814 {
7cdeb319
BP		 1815 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1816 "disabled\n", descriptor);
a41b2ff2
PB		 1817 return 0;
1818 }
1819
1820 if (s->TxStatus[descriptor] & TxHostOwns)
1821 {
7cdeb319
BP		 1822 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1823 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1824 return 0;
1825 }
1826
7cdeb319 1827 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2 1828
88a411a8 1829 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 1830 int txsize = s->TxStatus[descriptor] & 0x1fff;
1831 uint8_t txbuffer[0x2000];
1832
7cdeb319
BP		 1833 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1834 txsize, s->TxAddr[descriptor]);
a41b2ff2 1835
88a411a8 1836 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1837
1838 /* Mark descriptor as transferred */
1839 s->TxStatus[descriptor] |= TxHostOwns;
1840 s->TxStatus[descriptor] |= TxStatOK;
1841
bf6b87a8 1842 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1843
7cdeb319
BP		 1844 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1845 descriptor);
a41b2ff2
PB		 1846
1847 /* update interrupt */
1848 s->IntrStatus |= TxOK;
1849 rtl8139_update_irq(s);
1850
1851 return 1;
1852}
1853
718da2b9
FB		 1854#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1855
718da2b9
FB		 1856/* produces ones' complement sum of data */
1857static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1858{
1859 uint32_t result = 0;
1860
1861 for (; len > 1; data+=2, len-=2)
1862 {
1863 result += *(uint16_t*)data;
1864 }
1865
1866 /* add the remainder byte */
1867 if (len)
1868 {
1869 uint8_t odd[2] = {*data, 0};
1870 result += *(uint16_t*)odd;
1871 }
1872
1873 while (result>>16)
1874 result = (result & 0xffff) + (result >> 16);
1875
1876 return result;
1877}
1878
1879static uint16_t ip_checksum(void *data, size_t len)
1880{
1881 return ~ones_complement_sum((uint8_t*)data, len);
1882}
1883
a41b2ff2
PB		 1884static int rtl8139_cplus_transmit_one(RTL8139State *s)
1885{
1886 if (!rtl8139_transmitter_enabled(s))
1887 {
7cdeb319 1888 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1889 return 0;
1890 }
1891
1892 if (!rtl8139_cp_transmitter_enabled(s))
1893 {
7cdeb319 1894 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1895 return 0 ;
1896 }
1897
88a411a8 1898 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 1899 int descriptor = s->currCPlusTxDesc;
1900
3ada003a 1901 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
a41b2ff2
PB		 1902
1903 /* Normal priority ring */
1904 cplus_tx_ring_desc += 16 * descriptor;
1905
7cdeb319 1906 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
4abf12f4 1907 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
7cdeb319 1908 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1909
1910 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1911
88a411a8 1912 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1913 txdw0 = le32_to_cpu(val);
88a411a8 1914 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1915 txdw1 = le32_to_cpu(val);
88a411a8 1916 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
a41b2ff2 1917 txbufLO = le32_to_cpu(val);
88a411a8 1918 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
a41b2ff2
PB		 1919 txbufHI = le32_to_cpu(val);
1920
7cdeb319
BP		 1921 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1922 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1923
1924/* w0 ownership flag */
1925#define CP_TX_OWN (1<<31)
1926/* w0 end of ring flag */
1927#define CP_TX_EOR (1<<30)
1928/* first segment of received packet flag */
1929#define CP_TX_FS (1<<29)
1930/* last segment of received packet flag */
1931#define CP_TX_LS (1<<28)
1932/* large send packet flag */
1933#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1934/* large send MSS mask, bits 16...25 */
1935#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1936
a41b2ff2
PB		 1937/* IP checksum offload flag */
1938#define CP_TX_IPCS (1<<18)
1939/* UDP checksum offload flag */
1940#define CP_TX_UDPCS (1<<17)
1941/* TCP checksum offload flag */
1942#define CP_TX_TCPCS (1<<16)
1943
1944/* w0 bits 0...15 : buffer size */
1945#define CP_TX_BUFFER_SIZE (1<<16)
1946#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 1947/* w1 add tag flag */
1948#define CP_TX_TAGC (1<<17)
1949/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 1950#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1951/* w2 low 32bit of Rx buffer ptr */
1952/* w3 high 32bit of Rx buffer ptr */
1953
1954/* set after transmission */
1955/* FIFO underrun flag */
1956#define CP_TX_STATUS_UNF (1<<25)
1957/* transmit error summary flag, valid if set any of three below */
1958#define CP_TX_STATUS_TES (1<<23)
1959/* out-of-window collision flag */
1960#define CP_TX_STATUS_OWC (1<<22)
1961/* link failure flag */
1962#define CP_TX_STATUS_LNKF (1<<21)
1963/* excessive collisions flag */
1964#define CP_TX_STATUS_EXC (1<<20)
1965
1966 if (!(txdw0 & CP_TX_OWN))
1967 {
7cdeb319 1968 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 1969 return 0 ;
1970 }
1971
7cdeb319 1972 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 1973
1974 if (txdw0 & CP_TX_FS)
1975 {
7cdeb319
BP		 1976 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
1977 "descriptor\n", descriptor);
6cadb320
FB		 1978
1979 /* reset internal buffer offset */
1980 s->cplus_txbuffer_offset = 0;
1981 }
a41b2ff2
PB		 1982
1983 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
3ada003a 1984 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 1985
6cadb320
FB		 1986 /* make sure we have enough space to assemble the packet */
1987 if (!s->cplus_txbuffer)
1988 {
1989 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
7267c094 1990 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
6cadb320 1991 s->cplus_txbuffer_offset = 0;
718da2b9 1992
7cdeb319
BP		 1993 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
1994 s->cplus_txbuffer_len);
6cadb320
FB		 1995 }
1996
cde31a0e 1997 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
6cadb320 1998 {
cde31a0e
JW		 1999 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2000 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2001 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2002 "length to %d\n", txsize);
6cadb320
FB		 2003 }
2004
6cadb320
FB		 2005 /* append more data to the packet */
2006
7cdeb319 2007 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
3ada003a
EGM		 2008 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2009 s->cplus_txbuffer_offset);
6cadb320 2010
88a411a8 2011 pci_dma_read(d, tx_addr,
3ada003a 2012 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
6cadb320
FB		 2013 s->cplus_txbuffer_offset += txsize;
2014
2015 /* seek to next Rx descriptor */
2016 if (txdw0 & CP_TX_EOR)
2017 {
2018 s->currCPlusTxDesc = 0;
2019 }
2020 else
2021 {
2022 ++s->currCPlusTxDesc;
2023 if (s->currCPlusTxDesc >= 64)
2024 s->currCPlusTxDesc = 0;
2025 }
a41b2ff2
PB		 2026
2027 /* transfer ownership to target */
91731d5f 2028 txdw0 &= ~CP_TX_OWN;
a41b2ff2
PB		 2029
2030 /* reset error indicator bits */
2031 txdw0 &= ~CP_TX_STATUS_UNF;
2032 txdw0 &= ~CP_TX_STATUS_TES;
2033 txdw0 &= ~CP_TX_STATUS_OWC;
2034 txdw0 &= ~CP_TX_STATUS_LNKF;
2035 txdw0 &= ~CP_TX_STATUS_EXC;
2036
2037 /* update ring data */
2038 val = cpu_to_le32(txdw0);
88a411a8 2039 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2040
6cadb320
FB		 2041 /* Now decide if descriptor being processed is holding the last segment of packet */
2042 if (txdw0 & CP_TX_LS)
a41b2ff2 2043 {
bf6b87a8
BP		 2044 uint8_t dot1q_buffer_space[VLAN_HLEN];
2045 uint16_t *dot1q_buffer;
2046
7cdeb319
BP		 2047 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2048 descriptor);
6cadb320
FB		 2049
2050 /* can transfer fully assembled packet */
2051
2052 uint8_t *saved_buffer = s->cplus_txbuffer;
2053 int saved_size = s->cplus_txbuffer_offset;
2054 int saved_buffer_len = s->cplus_txbuffer_len;
2055
bf6b87a8
BP		 2056 /* create vlan tag */
2057 if (txdw1 & CP_TX_TAGC) {
2058 /* the vlan tag is in BE byte order in the descriptor
2059 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2060 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2061 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2062
2063 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
1bf11332 2064 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN);
bf6b87a8
BP		 2065 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2066 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2067 } else {
2068 dot1q_buffer = NULL;
2069 }
2070
6cadb320
FB		 2071 /* reset the card space to protect from recursive call */
2072 s->cplus_txbuffer = NULL;
2073 s->cplus_txbuffer_offset = 0;
2074 s->cplus_txbuffer_len = 0;
2075
718da2b9 2076 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2077 {
7cdeb319 2078 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2079
e1c120a9 2080 /* Large enough for Ethernet and IP headers? */
5d61721a 2081 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) {
e1c120a9
SH		 2082 goto skip_offload;
2083 }
2084
6cadb320 2085 /* ip packet header */
5d61721a 2086 struct ip_header *ip = NULL;
6cadb320 2087 int hlen = 0;
718da2b9
FB		 2088 uint8_t ip_protocol = 0;
2089 uint16_t ip_data_len = 0;
6cadb320 2090
660f11be 2091 uint8_t *eth_payload_data = NULL;
718da2b9 2092 size_t eth_payload_len = 0;
6cadb320 2093
718da2b9 2094 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
39b8e7dc 2095 if (proto != ETH_P_IP)
6cadb320 2096 {
39b8e7dc 2097 goto skip_offload;
6cadb320
FB		 2098 }
2099
39b8e7dc
SH		 2100 DPRINTF("+++ C+ mode has IP packet\n");
2101
26c0114d
SH		 2102 /* Note on memory alignment: eth_payload_data is 16-bit aligned
2103 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is
2104 * even. 32-bit accesses must use ldl/stl wrappers to avoid
2105 * unaligned accesses.
2106 */
39b8e7dc
SH		 2107 eth_payload_data = saved_buffer + ETH_HLEN;
2108 eth_payload_len = saved_size - ETH_HLEN;
2109
5d61721a 2110 ip = (struct ip_header*)eth_payload_data;
39b8e7dc
SH		 2111
2112 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2113 DPRINTF("+++ C+ mode packet has bad IP version %d "
2114 "expected %d\n", IP_HEADER_VERSION(ip),
2115 IP_HEADER_VERSION_4);
2116 goto skip_offload;
2117 }
2118
1bf11332 2119 hlen = IP_HDR_GET_LEN(ip);
5d61721a 2120 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) {
03247d43
SH		 2121 goto skip_offload;
2122 }
2123
39b8e7dc 2124 ip_protocol = ip->ip_p;
c6296ea8
SH		 2125
2126 ip_data_len = be16_to_cpu(ip->ip_len);
2127 if (ip_data_len < hlen || ip_data_len > eth_payload_len) {
2128 goto skip_offload;
2129 }
2130 ip_data_len -= hlen;
39b8e7dc 2131
d6812d60 2132 if (txdw0 & CP_TX_IPCS)
6cadb320 2133 {
d6812d60 2134 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2135
03247d43
SH		 2136 ip->ip_sum = 0;
2137 ip->ip_sum = ip_checksum(ip, hlen);
2138 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2139 hlen, ip->ip_sum);
d6812d60 2140 }
ec48c774 2141
d6812d60
SH		 2142 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2143 {
4240be45
SH		 2144 /* Large enough for the TCP header? */
2145 if (ip_data_len < sizeof(tcp_header)) {
2146 goto skip_offload;
2147 }
2148
d6812d60 2149 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
6cadb320 2150
d6812d60
SH		 2151 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2152 "frame data %d specified MSS=%d\n", ETH_MTU,
2153 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2154
d6812d60
SH		 2155 int tcp_send_offset = 0;
2156 int send_count = 0;
6cadb320 2157
d6812d60
SH		 2158 /* maximum IP header length is 60 bytes */
2159 uint8_t saved_ip_header[60];
718da2b9 2160
d6812d60
SH		 2161 /* save IP header template; data area is used in tcp checksum calculation */
2162 memcpy(saved_ip_header, eth_payload_data, hlen);
718da2b9 2163
d6812d60
SH		 2164 /* a placeholder for checksum calculation routine in tcp case */
2165 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2166 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
718da2b9 2167
d6812d60
SH		 2168 /* pointer to TCP header */
2169 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
718da2b9 2170
d6812d60 2171 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
718da2b9 2172
8357946b
SH		 2173 /* Invalid TCP data offset? */
2174 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) {
2175 goto skip_offload;
2176 }
2177
d6812d60
SH		 2178 /* ETH_MTU = ip header len + tcp header len + payload */
2179 int tcp_data_len = ip_data_len - tcp_hlen;
2180 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
718da2b9 2181
d6812d60
SH		 2182 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2183 "data len %d TCP chunk size %d\n", ip_data_len,
2184 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9 2185
d6812d60
SH		 2186 /* note the cycle below overwrites IP header data,
2187 but restores it from saved_ip_header before sending packet */
718da2b9 2188
d6812d60 2189 int is_last_frame = 0;
718da2b9 2190
d6812d60 2191 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
718da2b9 2192 {
d6812d60 2193 uint16_t chunk_size = tcp_chunk_size;
718da2b9 2194
d6812d60
SH		 2195 /* check if this is the last frame */
2196 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2197 {
2198 is_last_frame = 1;
2199 chunk_size = tcp_data_len - tcp_send_offset;
2200 }
718da2b9 2201
d6812d60 2202 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
26c0114d 2203 ldl_be_p(&p_tcp_hdr->th_seq));
6cadb320
FB		 2204
2205 /* add 4 TCP pseudoheader fields */
2206 /* copy IP source and destination fields */
718da2b9 2207 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2208
d6812d60
SH		 2209 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2210 "packet with %d bytes data\n", tcp_hlen +
2211 chunk_size);
2212
2213 if (tcp_send_offset)
6cadb320 2214 {
d6812d60
SH		 2215 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2216 }
6cadb320 2217
d6812d60
SH		 2218 /* keep PUSH and FIN flags only for the last frame */
2219 if (!is_last_frame)
2220 {
1bf11332 2221 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN);
d6812d60 2222 }
6cadb320 2223
d6812d60
SH		 2224 /* recalculate TCP checksum */
2225 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2226 p_tcpip_hdr->zeros = 0;
2227 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2228 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
6cadb320 2229
d6812d60 2230 p_tcp_hdr->th_sum = 0;
6cadb320 2231
d6812d60
SH		 2232 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2233 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2234 tcp_checksum);
6cadb320 2235
d6812d60 2236 p_tcp_hdr->th_sum = tcp_checksum;
6cadb320 2237
d6812d60
SH		 2238 /* restore IP header */
2239 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320 2240
d6812d60
SH		 2241 /* set IP data length and recalculate IP checksum */
2242 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
6cadb320 2243
d6812d60
SH		 2244 /* increment IP id for subsequent frames */
2245 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
6cadb320 2246
d6812d60
SH		 2247 ip->ip_sum = 0;
2248 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2249 DPRINTF("+++ C+ mode TSO IP header len=%d "
2250 "checksum=%04x\n", hlen, ip->ip_sum);
6cadb320 2251
d6812d60
SH		 2252 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2253 DPRINTF("+++ C+ mode TSO transferring packet size "
2254 "%d\n", tso_send_size);
2255 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2256 0, (uint8_t *) dot1q_buffer);
6cadb320 2257
d6812d60 2258 /* add transferred count to TCP sequence number */
26c0114d
SH		 2259 stl_be_p(&p_tcp_hdr->th_seq,
2260 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq));
d6812d60 2261 ++send_count;
6cadb320 2262 }
d6812d60
SH		 2263
2264 /* Stop sending this frame */
2265 saved_size = 0;
2266 }
2267 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2268 {
2269 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2270
2271 /* maximum IP header length is 60 bytes */
2272 uint8_t saved_ip_header[60];
2273 memcpy(saved_ip_header, eth_payload_data, hlen);
2274
2275 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2276 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2277
2278 /* add 4 TCP pseudoheader fields */
2279 /* copy IP source and destination fields */
2280 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2281
2282 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2283 {
2284 DPRINTF("+++ C+ mode calculating TCP checksum for "
2285 "packet with %d bytes data\n", ip_data_len);
2286
2287 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2288 p_tcpip_hdr->zeros = 0;
2289 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2290 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2291
2292 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2293
2294 p_tcp_hdr->th_sum = 0;
2295
2296 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2297 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2298 tcp_checksum);
2299
2300 p_tcp_hdr->th_sum = tcp_checksum;
2301 }
2302 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2303 {
2304 DPRINTF("+++ C+ mode calculating UDP checksum for "
2305 "packet with %d bytes data\n", ip_data_len);
2306
2307 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2308 p_udpip_hdr->zeros = 0;
2309 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2310 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2311
2312 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2313
2314 p_udp_hdr->uh_sum = 0;
2315
2316 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2317 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2318 udp_checksum);
2319
2320 p_udp_hdr->uh_sum = udp_checksum;
2321 }
2322
2323 /* restore IP header */
2324 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2325 }
2326 }
2327
39b8e7dc 2328skip_offload:
6cadb320
FB		 2329 /* update tally counter */
2330 ++s->tally_counters.TxOk;
2331
7cdeb319 2332 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2333
bf6b87a8
BP		 2334 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2335 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2336
2337 /* restore card space if there was no recursion and reset offset */
2338 if (!s->cplus_txbuffer)
2339 {
2340 s->cplus_txbuffer = saved_buffer;
2341 s->cplus_txbuffer_len = saved_buffer_len;
2342 s->cplus_txbuffer_offset = 0;
2343 }
2344 else
2345 {
7267c094 2346 g_free(saved_buffer);
6cadb320 2347 }
a41b2ff2
PB		 2348 }
2349 else
2350 {
7cdeb319 2351 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2352 }
2353
a41b2ff2
PB		 2354 return 1;
2355}
2356
2357static void rtl8139_cplus_transmit(RTL8139State *s)
2358{
2359 int txcount = 0;
2360
c7c35916 2361 while (txcount < 64 && rtl8139_cplus_transmit_one(s))
a41b2ff2
PB		 2362 {
2363 ++txcount;
2364 }
2365
2366 /* Mark transfer completed */
2367 if (!txcount)
2368 {
7cdeb319
BP		 2369 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2370 s->currCPlusTxDesc);
a41b2ff2
PB		 2371 }
2372 else
2373 {
2374 /* update interrupt status */
2375 s->IntrStatus |= TxOK;
2376 rtl8139_update_irq(s);
2377 }
2378}
2379
2380static void rtl8139_transmit(RTL8139State *s)
2381{
2382 int descriptor = s->currTxDesc, txcount = 0;
2383
2384 /*while*/
2385 if (rtl8139_transmit_one(s, descriptor))
2386 {
2387 ++s->currTxDesc;
2388 s->currTxDesc %= 4;
2389 ++txcount;
2390 }
2391
2392 /* Mark transfer completed */
2393 if (!txcount)
2394 {
7cdeb319
BP		 2395 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2396 s->currTxDesc);
a41b2ff2
PB		 2397 }
2398}
2399
2400static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2401{
2402
2403 int descriptor = txRegOffset/4;
6cadb320
FB		 2404
2405 /* handle C+ transmit mode register configuration */
2406
2c3891ab 2407 if (s->cplus_enabled)
6cadb320 2408 {
7cdeb319
BP		 2409 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2410 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2411
2412 /* handle Dump Tally Counters command */
2413 s->TxStatus[descriptor] = val;
2414
2415 if (descriptor == 0 && (val & 0x8))
2416 {
a8170e5e 2417 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2418
2419 /* dump tally counters to specified memory location */
3ada003a 2420 RTL8139TallyCounters_dma_write(s, tc_addr);
6cadb320
FB		 2421
2422 /* mark dump completed */
2423 s->TxStatus[0] &= ~0x8;
2424 }
2425
2426 return;
2427 }
2428
7cdeb319
BP		 2429 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2430 txRegOffset, val, descriptor);
a41b2ff2
PB		 2431
2432 /* mask only reserved bits */
2433 val &= ~0xff00c000; /* these bits are reset on write */
2434 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2435
2436 s->TxStatus[descriptor] = val;
2437
2438 /* attempt to start transmission */
2439 rtl8139_transmit(s);
2440}
2441
3e48dd4a
SH		 2442static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2443 uint32_t base, uint8_t addr,
2444 int size)
a41b2ff2 2445{
3e48dd4a 2446 uint32_t reg = (addr - base) / 4;
afe0a595
JW		 2447 uint32_t offset = addr & 0x3;
2448 uint32_t ret = 0;
2449
2450 if (addr & (size - 1)) {
3e48dd4a
SH		 2451 DPRINTF("not implemented read for TxStatus/TxAddr "
2452 "addr=0x%x size=0x%x\n", addr, size);
afe0a595
JW		 2453 return ret;
2454 }
a41b2ff2 2455
afe0a595
JW		 2456 switch (size) {
2457 case 1: /* fall through */
2458 case 2: /* fall through */
2459 case 4:
bdc62e62 2460 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
3e48dd4a
SH		 2461 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2462 reg, addr, size, ret);
afe0a595
JW		 2463 break;
2464 default:
3e48dd4a 2465 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
afe0a595
JW		 2466 break;
2467 }
a41b2ff2
PB		 2468
2469 return ret;
2470}
2471
2472static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2473{
2474 uint16_t ret = 0;
2475
2476 /* Simulate TSAD, it is read only anyway */
2477
2478 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2479 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2480 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2481 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2482
2483 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2484 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2485 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2486 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2487
a41b2ff2
PB		 2488 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2489 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2490 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2491 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2492
a41b2ff2
PB		 2493 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2494 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2495 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2496 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2497
a41b2ff2 2498
7cdeb319 2499 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2500
2501 return ret;
2502}
2503
2504static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2505{
2506 uint16_t ret = s->CSCR;
2507
7cdeb319 2508 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2509
2510 return ret;
2511}
2512
2513static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2514{
7cdeb319 2515 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2516
290a0933 2517 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2518}
2519
2520static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2521{
290a0933 2522 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2523
7cdeb319 2524 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2525
2526 return ret;
2527}
2528
2529static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2530{
7cdeb319 2531 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2532
2533 /* this value is off by 16 */
2534 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2535
00b7ade8
SH		 2536 /* more buffer space may be available so try to receive */
2537 qemu_flush_queued_packets(qemu_get_queue(s->nic));
2538
7cdeb319
BP		 2539 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2540 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2541}
2542
2543static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2544{
2545 /* this value is off by 16 */
2546 uint32_t ret = s->RxBufPtr - 0x10;
2547
7cdeb319 2548 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2549
2550 return ret;
2551}
2552
2553static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2554{
2555 /* this value is NOT off by 16 */
2556 uint32_t ret = s->RxBufAddr;
2557
7cdeb319 2558 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2559
2560 return ret;
2561}
2562
2563static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2564{
7cdeb319 2565 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2566
2567 s->RxBuf = val;
2568
2569 /* may need to reset rxring here */
2570}
2571
2572static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2573{
2574 uint32_t ret = s->RxBuf;
2575
7cdeb319 2576 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2577
2578 return ret;
2579}
2580
2581static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2582{
7cdeb319 2583 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2 2584
ebabb67a 2585 /* mask unwritable bits */
a41b2ff2
PB		 2586 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2587
2588 s->IntrMask = val;
2589
2590 rtl8139_update_irq(s);
05447803 2591
a41b2ff2
PB		 2592}
2593
2594static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2595{
2596 uint32_t ret = s->IntrMask;
2597
7cdeb319 2598 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2599
2600 return ret;
2601}
2602
2603static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2604{
7cdeb319 2605 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2606
2607#if 0
2608
2609 /* writing to ISR has no effect */
2610
2611 return;
2612
2613#else
2614 uint16_t newStatus = s->IntrStatus & ~val;
2615
ebabb67a 2616 /* mask unwritable bits */
a41b2ff2
PB		 2617 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2618
2619 /* writing 1 to interrupt status register bit clears it */
2620 s->IntrStatus = 0;
2621 rtl8139_update_irq(s);
2622
2623 s->IntrStatus = newStatus;
237c255c 2624 rtl8139_set_next_tctr_time(s);
a41b2ff2 2625 rtl8139_update_irq(s);
05447803 2626
a41b2ff2
PB		 2627#endif
2628}
2629
2630static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2631{
2632 uint32_t ret = s->IntrStatus;
2633
7cdeb319 2634 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2635
2636#if 0
2637
2638 /* reading ISR clears all interrupts */
2639 s->IntrStatus = 0;
2640
2641 rtl8139_update_irq(s);
2642
2643#endif
2644
2645 return ret;
2646}
2647
2648static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2649{
7cdeb319 2650 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2 2651
ebabb67a 2652 /* mask unwritable bits */
a41b2ff2
PB		 2653 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2654
2655 s->MultiIntr = val;
2656}
2657
2658static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2659{
2660 uint32_t ret = s->MultiIntr;
2661
7cdeb319 2662 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2663
2664 return ret;
2665}
2666
2667static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2668{
2669 RTL8139State *s = opaque;
2670
a41b2ff2
PB		 2671 switch (addr)
2672 {
90d131fb
MT		 2673 case MAC0 ... MAC0+4:
2674 s->phys[addr - MAC0] = val;
2675 break;
2676 case MAC0+5:
23c37c37
AK		 2677 s->phys[addr - MAC0] = val;
2678 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
2679 break;
a41b2ff2
PB		 2680 case MAC0+6 ... MAC0+7:
2681 /* reserved */
2682 break;
2683 case MAR0 ... MAR0+7:
2684 s->mult[addr - MAR0] = val;
2685 break;
2686 case ChipCmd:
2687 rtl8139_ChipCmd_write(s, val);
2688 break;
2689 case Cfg9346:
2690 rtl8139_Cfg9346_write(s, val);
2691 break;
2692 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2693 rtl8139_TxConfig_writeb(s, val);
2694 break;
2695 case Config0:
2696 rtl8139_Config0_write(s, val);
2697 break;
2698 case Config1:
2699 rtl8139_Config1_write(s, val);
2700 break;
2701 case Config3:
2702 rtl8139_Config3_write(s, val);
2703 break;
2704 case Config4:
2705 rtl8139_Config4_write(s, val);
2706 break;
2707 case Config5:
2708 rtl8139_Config5_write(s, val);
2709 break;
2710 case MediaStatus:
2711 /* ignore */
7cdeb319
BP		 2712 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2713 val);
a41b2ff2
PB		 2714 break;
2715
2716 case HltClk:
7cdeb319 2717 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2718 if (val == 'R')
2719 {
2720 s->clock_enabled = 1;
2721 }
2722 else if (val == 'H')
2723 {
2724 s->clock_enabled = 0;
2725 }
2726 break;
2727
2728 case TxThresh:
7cdeb319 2729 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2730 s->TxThresh = val;
2731 break;
2732
2733 case TxPoll:
7cdeb319 2734 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2735 if (val & (1 << 7))
2736 {
7cdeb319
BP		 2737 DPRINTF("C+ TxPoll high priority transmission (not "
2738 "implemented)\n");
a41b2ff2
PB		 2739 //rtl8139_cplus_transmit(s);
2740 }
2741 if (val & (1 << 6))
2742 {
7cdeb319 2743 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2744 rtl8139_cplus_transmit(s);
2745 }
2746
2747 break;
2748
2749 default:
7cdeb319
BP		 2750 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2751 val);
a41b2ff2
PB		 2752 break;
2753 }
2754}
2755
2756static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2757{
2758 RTL8139State *s = opaque;
2759
a41b2ff2
PB		 2760 switch (addr)
2761 {
2762 case IntrMask:
2763 rtl8139_IntrMask_write(s, val);
2764 break;
2765
2766 case IntrStatus:
2767 rtl8139_IntrStatus_write(s, val);
2768 break;
2769
2770 case MultiIntr:
2771 rtl8139_MultiIntr_write(s, val);
2772 break;
2773
2774 case RxBufPtr:
2775 rtl8139_RxBufPtr_write(s, val);
2776 break;
2777
2778 case BasicModeCtrl:
2779 rtl8139_BasicModeCtrl_write(s, val);
2780 break;
2781 case BasicModeStatus:
2782 rtl8139_BasicModeStatus_write(s, val);
2783 break;
2784 case NWayAdvert:
7cdeb319 2785 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2786 s->NWayAdvert = val;
2787 break;
2788 case NWayLPAR:
7cdeb319 2789 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2790 break;
2791 case NWayExpansion:
7cdeb319 2792 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2793 s->NWayExpansion = val;
2794 break;
2795
2796 case CpCmd:
2797 rtl8139_CpCmd_write(s, val);
2798 break;
2799
6cadb320
FB		 2800 case IntrMitigate:
2801 rtl8139_IntrMitigate_write(s, val);
2802 break;
2803
a41b2ff2 2804 default:
7cdeb319
BP		 2805 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2806 addr, val);
a41b2ff2 2807
a41b2ff2
PB		 2808 rtl8139_io_writeb(opaque, addr, val & 0xff);
2809 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2810 break;
2811 }
2812}
2813
237c255c 2814static void rtl8139_set_next_tctr_time(RTL8139State *s)
05447803 2815{
37b9ab92 2816 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32;
05447803 2817
7cdeb319 2818 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803 2819
237c255c
PB		 2820 /* This function is called at least once per period, so it is a good
2821 * place to update the timer base.
2822 *
2823 * After one iteration of this loop the value in the Timer register does
2824 * not change, but the device model is counting up by 2^32 ticks (approx.
2825 * 130 seconds).
05447803 2826 */
237c255c
PB		 2827 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2828 s->TCTR_base += ns_per_period;
05447803 2829 }
05447803 2830
237c255c
PB		 2831 if (!s->TimerInt) {
2832 timer_del(s->timer);
2833 } else {
37b9ab92 2834 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD;
237c255c
PB		 2835 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2836 delta += ns_per_period;
2837 }
2838 timer_mod(s->timer, s->TCTR_base + delta);
05447803
FZ		 2839 }
2840}
2841
a41b2ff2
PB		 2842static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2843{
2844 RTL8139State *s = opaque;
2845
a41b2ff2
PB		 2846 switch (addr)
2847 {
2848 case RxMissed:
7cdeb319 2849 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2850 s->RxMissed = 0;
2851 break;
2852
2853 case TxConfig:
2854 rtl8139_TxConfig_write(s, val);
2855 break;
2856
2857 case RxConfig:
2858 rtl8139_RxConfig_write(s, val);
2859 break;
2860
2861 case TxStatus0 ... TxStatus0+4*4-1:
2862 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2863 break;
2864
2865 case TxAddr0 ... TxAddr0+4*4-1:
2866 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2867 break;
2868
2869 case RxBuf:
2870 rtl8139_RxBuf_write(s, val);
2871 break;
2872
2873 case RxRingAddrLO:
7cdeb319 2874 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2875 s->RxRingAddrLO = val;
2876 break;
2877
2878 case RxRingAddrHI:
7cdeb319 2879 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2880 s->RxRingAddrHI = val;
2881 break;
2882
6cadb320 2883 case Timer:
7cdeb319 2884 DPRINTF("TCTR Timer reset on write\n");
bc72ad67 2885 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
237c255c 2886 rtl8139_set_next_tctr_time(s);
6cadb320
FB		 2887 break;
2888
2889 case FlashReg:
7cdeb319 2890 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2891 if (s->TimerInt != val) {
2892 s->TimerInt = val;
237c255c 2893 rtl8139_set_next_tctr_time(s);
05447803 2894 }
6cadb320
FB		 2895 break;
2896
a41b2ff2 2897 default:
7cdeb319
BP		 2898 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2899 addr, val);
a41b2ff2
PB		 2900 rtl8139_io_writeb(opaque, addr, val & 0xff);
2901 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2902 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2903 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2904 break;
2905 }
2906}
2907
2908static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2909{
2910 RTL8139State *s = opaque;
2911 int ret;
2912
a41b2ff2
PB		 2913 switch (addr)
2914 {
2915 case MAC0 ... MAC0+5:
2916 ret = s->phys[addr - MAC0];
2917 break;
2918 case MAC0+6 ... MAC0+7:
2919 ret = 0;
2920 break;
2921 case MAR0 ... MAR0+7:
2922 ret = s->mult[addr - MAR0];
2923 break;
afe0a595 2924 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 2925 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2926 addr, 1);
afe0a595 2927 break;
a41b2ff2
PB		 2928 case ChipCmd:
2929 ret = rtl8139_ChipCmd_read(s);
2930 break;
2931 case Cfg9346:
2932 ret = rtl8139_Cfg9346_read(s);
2933 break;
2934 case Config0:
2935 ret = rtl8139_Config0_read(s);
2936 break;
2937 case Config1:
2938 ret = rtl8139_Config1_read(s);
2939 break;
2940 case Config3:
2941 ret = rtl8139_Config3_read(s);
2942 break;
2943 case Config4:
2944 ret = rtl8139_Config4_read(s);
2945 break;
2946 case Config5:
2947 ret = rtl8139_Config5_read(s);
2948 break;
2949
2950 case MediaStatus:
9e12c5af
JW		 2951 /* The LinkDown bit of MediaStatus is inverse with link status */
2952 ret = 0xd0 | (~s->BasicModeStatus & 0x04);
7cdeb319 2953 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 2954 break;
2955
2956 case HltClk:
2957 ret = s->clock_enabled;
7cdeb319 2958 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 2959 break;
2960
2961 case PCIRevisionID:
6cadb320 2962 ret = RTL8139_PCI_REVID;
7cdeb319 2963 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 2964 break;
2965
2966 case TxThresh:
2967 ret = s->TxThresh;
7cdeb319 2968 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 2969 break;
2970
2971 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2972 ret = s->TxConfig >> 24;
7cdeb319 2973 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 2974 break;
2975
2976 default:
7cdeb319 2977 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 2978 ret = 0;
2979 break;
2980 }
2981
2982 return ret;
2983}
2984
2985static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2986{
2987 RTL8139State *s = opaque;
2988 uint32_t ret;
2989
a41b2ff2
PB		 2990 switch (addr)
2991 {
afe0a595 2992 case TxAddr0 ... TxAddr0+4*4-1:
3e48dd4a 2993 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
afe0a595 2994 break;
a41b2ff2
PB		 2995 case IntrMask:
2996 ret = rtl8139_IntrMask_read(s);
2997 break;
2998
2999 case IntrStatus:
3000 ret = rtl8139_IntrStatus_read(s);
3001 break;
3002
3003 case MultiIntr:
3004 ret = rtl8139_MultiIntr_read(s);
3005 break;
3006
3007 case RxBufPtr:
3008 ret = rtl8139_RxBufPtr_read(s);
3009 break;
3010
6cadb320
FB		 3011 case RxBufAddr:
3012 ret = rtl8139_RxBufAddr_read(s);
3013 break;
3014
a41b2ff2
PB		 3015 case BasicModeCtrl:
3016 ret = rtl8139_BasicModeCtrl_read(s);
3017 break;
3018 case BasicModeStatus:
3019 ret = rtl8139_BasicModeStatus_read(s);
3020 break;
3021 case NWayAdvert:
3022 ret = s->NWayAdvert;
7cdeb319 3023 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3024 break;
3025 case NWayLPAR:
3026 ret = s->NWayLPAR;
7cdeb319 3027 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3028 break;
3029 case NWayExpansion:
3030 ret = s->NWayExpansion;
7cdeb319 3031 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3032 break;
3033
3034 case CpCmd:
3035 ret = rtl8139_CpCmd_read(s);
3036 break;
3037
6cadb320
FB		 3038 case IntrMitigate:
3039 ret = rtl8139_IntrMitigate_read(s);
3040 break;
3041
a41b2ff2
PB		 3042 case TxSummary:
3043 ret = rtl8139_TSAD_read(s);
3044 break;
3045
3046 case CSCR:
3047 ret = rtl8139_CSCR_read(s);
3048 break;
3049
3050 default:
7cdeb319 3051 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3052
a41b2ff2
PB		 3053 ret = rtl8139_io_readb(opaque, addr);
3054 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3055
7cdeb319 3056 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3057 break;
3058 }
3059
3060 return ret;
3061}
3062
3063static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3064{
3065 RTL8139State *s = opaque;
3066 uint32_t ret;
3067
a41b2ff2
PB		 3068 switch (addr)
3069 {
3070 case RxMissed:
3071 ret = s->RxMissed;
3072
7cdeb319 3073 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3074 break;
3075
3076 case TxConfig:
3077 ret = rtl8139_TxConfig_read(s);
3078 break;
3079
3080 case RxConfig:
3081 ret = rtl8139_RxConfig_read(s);
3082 break;
3083
3084 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 3085 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3086 addr, 4);
a41b2ff2
PB		 3087 break;
3088
3089 case TxAddr0 ... TxAddr0+4*4-1:
3090 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3091 break;
3092
3093 case RxBuf:
3094 ret = rtl8139_RxBuf_read(s);
3095 break;
3096
3097 case RxRingAddrLO:
3098 ret = s->RxRingAddrLO;
7cdeb319 3099 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3100 break;
3101
3102 case RxRingAddrHI:
3103 ret = s->RxRingAddrHI;
7cdeb319 3104 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3105 break;
3106
3107 case Timer:
37b9ab92
LV		 3108 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) /
3109 PCI_PERIOD;
7cdeb319 3110 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3111 break;
3112
3113 case FlashReg:
3114 ret = s->TimerInt;
7cdeb319 3115 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3116 break;
3117
3118 default:
7cdeb319 3119 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3120
a41b2ff2
PB		 3121 ret = rtl8139_io_readb(opaque, addr);
3122 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3123 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3124 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3125
7cdeb319 3126 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3127 break;
3128 }
3129
3130 return ret;
3131}
3132
3133/* */
3134
060110c3 3135static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3136{
6597ebbb 3137 RTL8139State* s = opaque;
237c255c 3138 rtl8139_set_next_tctr_time(s);
060110c3 3139 if (version_id < 4) {
2c3891ab
AL		 3140 s->cplus_enabled = s->CpCmd != 0;
3141 }
3142
9e12c5af
JW		 3143 /* nc.link_down can't be migrated, so infer link_down according
3144 * to link status bit in BasicModeStatus */
b356f76d 3145 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0;
9e12c5af 3146
a41b2ff2
PB		 3147 return 0;
3148}
3149
c574ba5a
AW		 3150static bool rtl8139_hotplug_ready_needed(void *opaque)
3151{
3152 return qdev_machine_modified();
3153}
3154
3155static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3156 .name = "rtl8139/hotplug_ready",
3157 .version_id = 1,
3158 .minimum_version_id = 1,
5cd8cada 3159 .needed = rtl8139_hotplug_ready_needed,
d49805ae 3160 .fields = (VMStateField[]) {
c574ba5a
AW		 3161 VMSTATE_END_OF_LIST()
3162 }
3163};
3164
44b1ff31 3165static int rtl8139_pre_save(void *opaque)
05447803
FZ		 3166{
3167 RTL8139State* s = opaque;
bc72ad67 3168 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
05447803 3169
237c255c 3170 /* for migration to older versions */
37b9ab92 3171 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD;
bd80f3fc 3172 s->rtl8139_mmio_io_addr_dummy = 0;
44b1ff31
DDAG		 3173
3174 return 0;
05447803
FZ		 3175}
3176
060110c3
JQ		 3177static const VMStateDescription vmstate_rtl8139 = {
3178 .name = "rtl8139",
46fe8bef 3179 .version_id = 5,
060110c3 3180 .minimum_version_id = 3,
060110c3 3181 .post_load = rtl8139_post_load,
05447803 3182 .pre_save = rtl8139_pre_save,
d49805ae 3183 .fields = (VMStateField[]) {
88a411a8 3184 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
060110c3
JQ		 3185 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3186 VMSTATE_BUFFER(mult, RTL8139State),
3187 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3188 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3189
3190 VMSTATE_UINT32(RxBuf, RTL8139State),
3191 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3192 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3193 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3194
3195 VMSTATE_UINT16(IntrStatus, RTL8139State),
3196 VMSTATE_UINT16(IntrMask, RTL8139State),
3197
3198 VMSTATE_UINT32(TxConfig, RTL8139State),
3199 VMSTATE_UINT32(RxConfig, RTL8139State),
3200 VMSTATE_UINT32(RxMissed, RTL8139State),
3201 VMSTATE_UINT16(CSCR, RTL8139State),
3202
3203 VMSTATE_UINT8(Cfg9346, RTL8139State),
3204 VMSTATE_UINT8(Config0, RTL8139State),
3205 VMSTATE_UINT8(Config1, RTL8139State),
3206 VMSTATE_UINT8(Config3, RTL8139State),
3207 VMSTATE_UINT8(Config4, RTL8139State),
3208 VMSTATE_UINT8(Config5, RTL8139State),
3209
3210 VMSTATE_UINT8(clock_enabled, RTL8139State),
3211 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3212
3213 VMSTATE_UINT16(MultiIntr, RTL8139State),
3214
3215 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3216 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3217 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3218 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3219 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3220
3221 VMSTATE_UINT16(CpCmd, RTL8139State),
3222 VMSTATE_UINT8(TxThresh, RTL8139State),
3223
3224 VMSTATE_UNUSED(4),
3225 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3226 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3227
3228 VMSTATE_UINT32(currTxDesc, RTL8139State),
3229 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3230 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3231 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3232 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3233
3234 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3235 VMSTATE_INT32(eeprom.mode, RTL8139State),
3236 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3237 VMSTATE_UINT8(eeprom.address, RTL8139State),
3238 VMSTATE_UINT16(eeprom.input, RTL8139State),
3239 VMSTATE_UINT16(eeprom.output, RTL8139State),
3240
3241 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3242 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3243 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3244 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3245
3246 VMSTATE_UINT32(TCTR, RTL8139State),
3247 VMSTATE_UINT32(TimerInt, RTL8139State),
3248 VMSTATE_INT64(TCTR_base, RTL8139State),
3249
46fe8bef
DV		 3250 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State),
3251 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State),
3252 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State),
3253 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State),
3254 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State),
3255 VMSTATE_UINT16(tally_counters.FAE, RTL8139State),
3256 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State),
3257 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State),
3258 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State),
3259 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State),
3260 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5),
3261 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State),
3262 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State),
060110c3
JQ		 3263
3264 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3265 VMSTATE_END_OF_LIST()
c574ba5a 3266 },
5cd8cada
JQ		 3267 .subsections = (const VMStateDescription*[]) {
3268 &vmstate_rtl8139_hotplug_ready,
3269 NULL
060110c3
JQ		 3270 }
3271};
3272
a41b2ff2
PB		 3273/***********************************************************/
3274/* PCI RTL8139 definitions */
3275
1bebb0ad
AG		 3276static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3277 uint64_t val, unsigned size)
3278{
3279 switch (size) {
3280 case 1:
3281 rtl8139_io_writeb(opaque, addr, val);
3282 break;
3283 case 2:
3284 rtl8139_io_writew(opaque, addr, val);
3285 break;
3286 case 4:
3287 rtl8139_io_writel(opaque, addr, val);
3288 break;
3289 }
3290}
3291
3292static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3293 unsigned size)
3294{
3295 switch (size) {
3296 case 1:
3297 return rtl8139_io_readb(opaque, addr);
3298 case 2:
3299 return rtl8139_io_readw(opaque, addr);
3300 case 4:
3301 return rtl8139_io_readl(opaque, addr);
3302 }
3303
3304 return -1;
3305}
a41b2ff2 3306
bd80f3fc 3307static const MemoryRegionOps rtl8139_io_ops = {
1bebb0ad
AG		 3308 .read = rtl8139_ioport_read,
3309 .write = rtl8139_ioport_write,
3310 .impl = {
3311 .min_access_size = 1,
3312 .max_access_size = 4,
3313 },
bd80f3fc 3314 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3315};
3316
6cadb320
FB		 3317static void rtl8139_timer(void *opaque)
3318{
3319 RTL8139State *s = opaque;
3320
6cadb320
FB		 3321 if (!s->clock_enabled)
3322 {
7cdeb319 3323 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3324 return;
3325 }
3326
05447803
FZ		 3327 s->IntrStatus |= PCSTimeout;
3328 rtl8139_update_irq(s);
237c255c 3329 rtl8139_set_next_tctr_time(s);
6cadb320 3330}
6cadb320 3331
f90c2bcd 3332static void pci_rtl8139_uninit(PCIDevice *dev)
254111ec 3333{
39257515 3334 RTL8139State *s = RTL8139(dev);
254111ec 3335
012aef07
MA		 3336 g_free(s->cplus_txbuffer);
3337 s->cplus_txbuffer = NULL;
bc72ad67
AB		 3338 timer_del(s->timer);
3339 timer_free(s->timer);
948ecf21 3340 qemu_del_nic(s->nic);
b946a153
AL		 3341}
3342
9e12c5af
JW		 3343static void rtl8139_set_link_status(NetClientState *nc)
3344{
cc1f0f45 3345 RTL8139State *s = qemu_get_nic_opaque(nc);
9e12c5af
JW		 3346
3347 if (nc->link_down) {
3348 s->BasicModeStatus &= ~0x04;
3349 } else {
3350 s->BasicModeStatus |= 0x04;
3351 }
3352
3353 s->IntrStatus |= RxUnderrun;
3354 rtl8139_update_irq(s);
3355}
3356
1673ad51 3357static NetClientInfo net_rtl8139_info = {
f394b2e2 3358 .type = NET_CLIENT_DRIVER_NIC,
1673ad51
MM		 3359 .size = sizeof(NICState),
3360 .can_receive = rtl8139_can_receive,
3361 .receive = rtl8139_receive,
9e12c5af 3362 .link_status_changed = rtl8139_set_link_status,
1673ad51
MM		 3363};
3364
9af21dbe 3365static void pci_rtl8139_realize(PCIDevice *dev, Error **errp)
a41b2ff2 3366{
39257515
PC		 3367 RTL8139State *s = RTL8139(dev);
3368 DeviceState *d = DEVICE(dev);
a41b2ff2 3369 uint8_t *pci_conf;
3b46e624 3370
88a411a8 3371 pci_conf = dev->config;
817e0b6f 3372 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
0b5b3547
MT		 3373 /* TODO: start of capability list, but no capability
3374 * list bit in status register, and offset 0xdc seems unused. */
3375 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3376
eedfac6f
PB		 3377 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s,
3378 "rtl8139", 0x100);
726ec828
MP		 3379 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io,
3380 0, 0x100);
3381
88a411a8
AF		 3382 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3383 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
a41b2ff2 3384
254111ec 3385 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3386
7165448a
WD		 3387 /* prepare eeprom */
3388 s->eeprom.contents[0] = 0x8129;
3389#if 1
3390 /* PCI vendor and device ID should be mirrored here */
3391 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3392 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3393#endif
3394 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3395 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3396 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3397
1673ad51 3398 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
39257515 3399 object_get_typename(OBJECT(dev)), d->id, s);
b356f76d 3400 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
6cadb320
FB		 3401
3402 s->cplus_txbuffer = NULL;
3403 s->cplus_txbuffer_len = 0;
3404 s->cplus_txbuffer_offset = 0;
3b46e624 3405
bc72ad67 3406 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
a41b2ff2 3407}
9d07d757 3408
afd7c850
GA		 3409static void rtl8139_instance_init(Object *obj)
3410{
3411 RTL8139State *s = RTL8139(obj);
3412
3413 device_add_bootindex_property(obj, &s->conf.bootindex,
3414 "bootindex", "/ethernet-phy@0",
3415 DEVICE(obj), NULL);
3416}
3417
40021f08
AL		 3418static Property rtl8139_properties[] = {
3419 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3420 DEFINE_PROP_END_OF_LIST(),
3421};
3422
3423static void rtl8139_class_init(ObjectClass *klass, void *data)
3424{
39bffca2 3425 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3426 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3427
9af21dbe 3428 k->realize = pci_rtl8139_realize;
40021f08 3429 k->exit = pci_rtl8139_uninit;
c45e5b5b 3430 k->romfile = "efi-rtl8139.rom";
40021f08
AL		 3431 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3432 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3433 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3434 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 3435 dc->reset = rtl8139_reset;
3436 dc->vmsd = &vmstate_rtl8139;
3437 dc->props = rtl8139_properties;
125ee0ed 3438 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
40021f08
AL		 3439}
3440
8c43a6f0 3441static const TypeInfo rtl8139_info = {
39257515 3442 .name = TYPE_RTL8139,
39bffca2
AL		 3443 .parent = TYPE_PCI_DEVICE,
3444 .instance_size = sizeof(RTL8139State),
3445 .class_init = rtl8139_class_init,
afd7c850 3446 .instance_init = rtl8139_instance_init,
fd3b02c8
EH		 3447 .interfaces = (InterfaceInfo[]) {
3448 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3449 { },
3450 },
0aab0d3a
GH		 3451};
3452
83f7d43a 3453static void rtl8139_register_types(void)
9d07d757 3454{
39bffca2 3455 type_register_static(&rtl8139_info);
9d07d757
PB		 3456}
3457
83f7d43a 3458type_init(rtl8139_register_types)
Empty description
This page took 1.604277 seconds and 4 git commands to generate.