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pc: move port 92 stuff back to pc.c from pckbd.c
[qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80 33#include "vga_int.h"
2bec46dc 34#include "kvm.h"
5245d57a 35#include "loader.h"
e6e5ad80 36
a5082316
FB		 37/*
38 * TODO:
ad81218e 39 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 40 * - optimize linear mappings
41 * - optimize bitblt functions
42 */
43
e36f36e1 44//#define DEBUG_CIRRUS
a21ae81d 45//#define DEBUG_BITBLT
e36f36e1 46
e6e5ad80
FB		 47/***************************************
48 *
49 * definitions
50 *
51 ***************************************/
52
e6e5ad80
FB		 53// ID
54#define CIRRUS_ID_CLGD5422 (0x23<<2)
55#define CIRRUS_ID_CLGD5426 (0x24<<2)
56#define CIRRUS_ID_CLGD5424 (0x25<<2)
57#define CIRRUS_ID_CLGD5428 (0x26<<2)
58#define CIRRUS_ID_CLGD5430 (0x28<<2)
59#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 60#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 61#define CIRRUS_ID_CLGD5446 (0x2E<<2)
62
63// sequencer 0x07
64#define CIRRUS_SR7_BPP_VGA 0x00
65#define CIRRUS_SR7_BPP_SVGA 0x01
66#define CIRRUS_SR7_BPP_MASK 0x0e
67#define CIRRUS_SR7_BPP_8 0x00
68#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69#define CIRRUS_SR7_BPP_24 0x04
70#define CIRRUS_SR7_BPP_16 0x06
71#define CIRRUS_SR7_BPP_32 0x08
72#define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74// sequencer 0x0f
75#define CIRRUS_MEMSIZE_512k 0x08
76#define CIRRUS_MEMSIZE_1M 0x10
77#define CIRRUS_MEMSIZE_2M 0x18
78#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80// sequencer 0x12
81#define CIRRUS_CURSOR_SHOW 0x01
82#define CIRRUS_CURSOR_HIDDENPEL 0x02
83#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85// sequencer 0x17
86#define CIRRUS_BUSTYPE_VLBFAST 0x10
87#define CIRRUS_BUSTYPE_PCI 0x20
88#define CIRRUS_BUSTYPE_VLBSLOW 0x30
89#define CIRRUS_BUSTYPE_ISA 0x38
90#define CIRRUS_MMIO_ENABLE 0x04
91#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94// control 0x0b
95#define CIRRUS_BANKING_DUAL 0x01
96#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98// control 0x30
99#define CIRRUS_BLTMODE_BACKWARDS 0x01
100#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104#define CIRRUS_BLTMODE_COLOREXPAND 0x80
105#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111// control 0x31
112#define CIRRUS_BLT_BUSY 0x01
113#define CIRRUS_BLT_START 0x02
114#define CIRRUS_BLT_RESET 0x04
115#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 116#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 117
118// control 0x32
119#define CIRRUS_ROP_0 0x00
120#define CIRRUS_ROP_SRC_AND_DST 0x05
121#define CIRRUS_ROP_NOP 0x06
122#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123#define CIRRUS_ROP_NOTDST 0x0b
124#define CIRRUS_ROP_SRC 0x0d
125#define CIRRUS_ROP_1 0x0e
126#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127#define CIRRUS_ROP_SRC_XOR_DST 0x59
128#define CIRRUS_ROP_SRC_OR_DST 0x6d
129#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132#define CIRRUS_ROP_NOTSRC 0xd0
133#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
a5082316
FB		 136#define CIRRUS_ROP_NOP_INDEX 2
137#define CIRRUS_ROP_SRC_INDEX 5
138
a21ae81d 139// control 0x33
a5082316 140#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 141#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 142#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 143
e6e5ad80
FB		 144// memory-mapped IO
145#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154#define CIRRUS_MMIO_BLTMODE 0x18 // byte
155#define CIRRUS_MMIO_BLTROP 0x1a // byte
156#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
a21ae81d 175#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 176
b2b183c2
AL		 177#define ABS(a) ((signed)(a) > 0 ? a : -a)
178
b2eb849d
AJ		 179#define BLTUNSAFE(s) \
180 ( \
181 ( /* check dst is within bounds */ \
b2b183c2 182 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 183 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 184 (s)->vga.vram_size \
b2eb849d
AJ		 185 ) || \
186 ( /* check src is within bounds */ \
b2b183c2 187 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 188 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 189 (s)->vga.vram_size \
b2eb849d
AJ		 190 ) \
191 )
192
a5082316
FB		 193struct CirrusVGAState;
194typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
195 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 196 int dstpitch, int srcpitch,
197 int bltwidth, int bltheight);
a5082316
FB		 198typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
199 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 200
201typedef struct CirrusVGAState {
4e12cd94 202 VGACommonState vga;
e6e5ad80
FB		 203
204 int cirrus_linear_io_addr;
a5082316 205 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 206 int cirrus_mmio_io_addr;
207 uint32_t cirrus_addr_mask;
78e127ef 208 uint32_t linear_mmio_mask;
e6e5ad80
FB		 209 uint8_t cirrus_shadow_gr0;
210 uint8_t cirrus_shadow_gr1;
211 uint8_t cirrus_hidden_dac_lockindex;
212 uint8_t cirrus_hidden_dac_data;
213 uint32_t cirrus_bank_base[2];
214 uint32_t cirrus_bank_limit[2];
215 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 216 uint32_t hw_cursor_x;
217 uint32_t hw_cursor_y;
e6e5ad80
FB		 218 int cirrus_blt_pixelwidth;
219 int cirrus_blt_width;
220 int cirrus_blt_height;
221 int cirrus_blt_dstpitch;
222 int cirrus_blt_srcpitch;
a5082316
FB		 223 uint32_t cirrus_blt_fgcol;
224 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 225 uint32_t cirrus_blt_dstaddr;
226 uint32_t cirrus_blt_srcaddr;
227 uint8_t cirrus_blt_mode;
a5082316 228 uint8_t cirrus_blt_modeext;
e6e5ad80 229 cirrus_bitblt_rop_t cirrus_rop;
a5082316 230#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 231 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
232 uint8_t *cirrus_srcptr;
233 uint8_t *cirrus_srcptr_end;
234 uint32_t cirrus_srccounter;
a5082316
FB		 235 /* hwcursor display state */
236 int last_hw_cursor_size;
237 int last_hw_cursor_x;
238 int last_hw_cursor_y;
239 int last_hw_cursor_y_start;
240 int last_hw_cursor_y_end;
78e127ef 241 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 242 int device_id;
243 int bustype;
e6e5ad80
FB		 244} CirrusVGAState;
245
246typedef struct PCICirrusVGAState {
247 PCIDevice dev;
248 CirrusVGAState cirrus_vga;
249} PCICirrusVGAState;
250
a5082316 251static uint8_t rop_to_index[256];
3b46e624 252
e6e5ad80
FB		 253/***************************************
254 *
255 * prototypes.
256 *
257 ***************************************/
258
259
8926b517
FB		 260static void cirrus_bitblt_reset(CirrusVGAState *s);
261static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 262
263/***************************************
264 *
265 * raster operations
266 *
267 ***************************************/
268
a5082316
FB		 269static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
270 uint8_t *dst,const uint8_t *src,
271 int dstpitch,int srcpitch,
272 int bltwidth,int bltheight)
273{
e6e5ad80
FB		 274}
275
a5082316
FB		 276static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
277 uint8_t *dst,
278 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 279{
a5082316 280}
e6e5ad80 281
a5082316 282#define ROP_NAME 0
8c78881f 283#define ROP_FN(d, s) 0
a5082316 284#include "cirrus_vga_rop.h"
e6e5ad80 285
a5082316 286#define ROP_NAME src_and_dst
8c78881f 287#define ROP_FN(d, s) (s) & (d)
a5082316 288#include "cirrus_vga_rop.h"
e6e5ad80 289
a5082316 290#define ROP_NAME src_and_notdst
8c78881f 291#define ROP_FN(d, s) (s) & (~(d))
a5082316 292#include "cirrus_vga_rop.h"
e6e5ad80 293
a5082316 294#define ROP_NAME notdst
8c78881f 295#define ROP_FN(d, s) ~(d)
a5082316 296#include "cirrus_vga_rop.h"
e6e5ad80 297
a5082316 298#define ROP_NAME src
8c78881f 299#define ROP_FN(d, s) s
a5082316 300#include "cirrus_vga_rop.h"
e6e5ad80 301
a5082316 302#define ROP_NAME 1
8c78881f 303#define ROP_FN(d, s) ~0
a5082316
FB		 304#include "cirrus_vga_rop.h"
305
306#define ROP_NAME notsrc_and_dst
8c78881f 307#define ROP_FN(d, s) (~(s)) & (d)
a5082316
FB		 308#include "cirrus_vga_rop.h"
309
310#define ROP_NAME src_xor_dst
8c78881f 311#define ROP_FN(d, s) (s) ^ (d)
a5082316
FB		 312#include "cirrus_vga_rop.h"
313
314#define ROP_NAME src_or_dst
8c78881f 315#define ROP_FN(d, s) (s) | (d)
a5082316
FB		 316#include "cirrus_vga_rop.h"
317
318#define ROP_NAME notsrc_or_notdst
8c78881f 319#define ROP_FN(d, s) (~(s)) | (~(d))
a5082316
FB		 320#include "cirrus_vga_rop.h"
321
322#define ROP_NAME src_notxor_dst
8c78881f 323#define ROP_FN(d, s) ~((s) ^ (d))
a5082316 324#include "cirrus_vga_rop.h"
e6e5ad80 325
a5082316 326#define ROP_NAME src_or_notdst
8c78881f 327#define ROP_FN(d, s) (s) | (~(d))
a5082316
FB		 328#include "cirrus_vga_rop.h"
329
330#define ROP_NAME notsrc
8c78881f 331#define ROP_FN(d, s) (~(s))
a5082316
FB		 332#include "cirrus_vga_rop.h"
333
334#define ROP_NAME notsrc_or_dst
8c78881f 335#define ROP_FN(d, s) (~(s)) | (d)
a5082316
FB		 336#include "cirrus_vga_rop.h"
337
338#define ROP_NAME notsrc_and_notdst
8c78881f 339#define ROP_FN(d, s) (~(s)) & (~(d))
a5082316
FB		 340#include "cirrus_vga_rop.h"
341
342static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
343 cirrus_bitblt_rop_fwd_0,
344 cirrus_bitblt_rop_fwd_src_and_dst,
345 cirrus_bitblt_rop_nop,
346 cirrus_bitblt_rop_fwd_src_and_notdst,
347 cirrus_bitblt_rop_fwd_notdst,
348 cirrus_bitblt_rop_fwd_src,
349 cirrus_bitblt_rop_fwd_1,
350 cirrus_bitblt_rop_fwd_notsrc_and_dst,
351 cirrus_bitblt_rop_fwd_src_xor_dst,
352 cirrus_bitblt_rop_fwd_src_or_dst,
353 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
354 cirrus_bitblt_rop_fwd_src_notxor_dst,
355 cirrus_bitblt_rop_fwd_src_or_notdst,
356 cirrus_bitblt_rop_fwd_notsrc,
357 cirrus_bitblt_rop_fwd_notsrc_or_dst,
358 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
359};
360
361static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
362 cirrus_bitblt_rop_bkwd_0,
363 cirrus_bitblt_rop_bkwd_src_and_dst,
364 cirrus_bitblt_rop_nop,
365 cirrus_bitblt_rop_bkwd_src_and_notdst,
366 cirrus_bitblt_rop_bkwd_notdst,
367 cirrus_bitblt_rop_bkwd_src,
368 cirrus_bitblt_rop_bkwd_1,
369 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
370 cirrus_bitblt_rop_bkwd_src_xor_dst,
371 cirrus_bitblt_rop_bkwd_src_or_dst,
372 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
373 cirrus_bitblt_rop_bkwd_src_notxor_dst,
374 cirrus_bitblt_rop_bkwd_src_or_notdst,
375 cirrus_bitblt_rop_bkwd_notsrc,
376 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
377 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
378};
96cf2df8
TS		 379
380#define TRANSP_ROP(name) {\
381 name ## _8,\
382 name ## _16,\
383 }
384#define TRANSP_NOP(func) {\
385 func,\
386 func,\
387 }
388
389static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
390 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
391 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
392 TRANSP_NOP(cirrus_bitblt_rop_nop),
393 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
394 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
395 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
396 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
406};
407
408static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
409 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
410 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
411 TRANSP_NOP(cirrus_bitblt_rop_nop),
412 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
413 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
414 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
415 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
425};
426
a5082316
FB		 427#define ROP2(name) {\
428 name ## _8,\
429 name ## _16,\
430 name ## _24,\
431 name ## _32,\
432 }
433
434#define ROP_NOP2(func) {\
435 func,\
436 func,\
437 func,\
438 func,\
439 }
440
e69390ce
FB		 441static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
442 ROP2(cirrus_patternfill_0),
443 ROP2(cirrus_patternfill_src_and_dst),
444 ROP_NOP2(cirrus_bitblt_rop_nop),
445 ROP2(cirrus_patternfill_src_and_notdst),
446 ROP2(cirrus_patternfill_notdst),
447 ROP2(cirrus_patternfill_src),
448 ROP2(cirrus_patternfill_1),
449 ROP2(cirrus_patternfill_notsrc_and_dst),
450 ROP2(cirrus_patternfill_src_xor_dst),
451 ROP2(cirrus_patternfill_src_or_dst),
452 ROP2(cirrus_patternfill_notsrc_or_notdst),
453 ROP2(cirrus_patternfill_src_notxor_dst),
454 ROP2(cirrus_patternfill_src_or_notdst),
455 ROP2(cirrus_patternfill_notsrc),
456 ROP2(cirrus_patternfill_notsrc_or_dst),
457 ROP2(cirrus_patternfill_notsrc_and_notdst),
458};
459
a5082316
FB		 460static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
461 ROP2(cirrus_colorexpand_transp_0),
462 ROP2(cirrus_colorexpand_transp_src_and_dst),
463 ROP_NOP2(cirrus_bitblt_rop_nop),
464 ROP2(cirrus_colorexpand_transp_src_and_notdst),
465 ROP2(cirrus_colorexpand_transp_notdst),
466 ROP2(cirrus_colorexpand_transp_src),
467 ROP2(cirrus_colorexpand_transp_1),
468 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
469 ROP2(cirrus_colorexpand_transp_src_xor_dst),
470 ROP2(cirrus_colorexpand_transp_src_or_dst),
471 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
472 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
473 ROP2(cirrus_colorexpand_transp_src_or_notdst),
474 ROP2(cirrus_colorexpand_transp_notsrc),
475 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
476 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
477};
478
479static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
480 ROP2(cirrus_colorexpand_0),
481 ROP2(cirrus_colorexpand_src_and_dst),
482 ROP_NOP2(cirrus_bitblt_rop_nop),
483 ROP2(cirrus_colorexpand_src_and_notdst),
484 ROP2(cirrus_colorexpand_notdst),
485 ROP2(cirrus_colorexpand_src),
486 ROP2(cirrus_colorexpand_1),
487 ROP2(cirrus_colorexpand_notsrc_and_dst),
488 ROP2(cirrus_colorexpand_src_xor_dst),
489 ROP2(cirrus_colorexpand_src_or_dst),
490 ROP2(cirrus_colorexpand_notsrc_or_notdst),
491 ROP2(cirrus_colorexpand_src_notxor_dst),
492 ROP2(cirrus_colorexpand_src_or_notdst),
493 ROP2(cirrus_colorexpand_notsrc),
494 ROP2(cirrus_colorexpand_notsrc_or_dst),
495 ROP2(cirrus_colorexpand_notsrc_and_notdst),
496};
497
b30d4608
FB		 498static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
499 ROP2(cirrus_colorexpand_pattern_transp_0),
500 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
501 ROP_NOP2(cirrus_bitblt_rop_nop),
502 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
503 ROP2(cirrus_colorexpand_pattern_transp_notdst),
504 ROP2(cirrus_colorexpand_pattern_transp_src),
505 ROP2(cirrus_colorexpand_pattern_transp_1),
506 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
507 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
508 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
509 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
510 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
511 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
512 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
513 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
514 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
515};
516
517static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
518 ROP2(cirrus_colorexpand_pattern_0),
519 ROP2(cirrus_colorexpand_pattern_src_and_dst),
520 ROP_NOP2(cirrus_bitblt_rop_nop),
521 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
522 ROP2(cirrus_colorexpand_pattern_notdst),
523 ROP2(cirrus_colorexpand_pattern_src),
524 ROP2(cirrus_colorexpand_pattern_1),
525 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
526 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
527 ROP2(cirrus_colorexpand_pattern_src_or_dst),
528 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
529 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
530 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
531 ROP2(cirrus_colorexpand_pattern_notsrc),
532 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
533 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
534};
535
a5082316
FB		 536static const cirrus_fill_t cirrus_fill[16][4] = {
537 ROP2(cirrus_fill_0),
538 ROP2(cirrus_fill_src_and_dst),
539 ROP_NOP2(cirrus_bitblt_fill_nop),
540 ROP2(cirrus_fill_src_and_notdst),
541 ROP2(cirrus_fill_notdst),
542 ROP2(cirrus_fill_src),
543 ROP2(cirrus_fill_1),
544 ROP2(cirrus_fill_notsrc_and_dst),
545 ROP2(cirrus_fill_src_xor_dst),
546 ROP2(cirrus_fill_src_or_dst),
547 ROP2(cirrus_fill_notsrc_or_notdst),
548 ROP2(cirrus_fill_src_notxor_dst),
549 ROP2(cirrus_fill_src_or_notdst),
550 ROP2(cirrus_fill_notsrc),
551 ROP2(cirrus_fill_notsrc_or_dst),
552 ROP2(cirrus_fill_notsrc_and_notdst),
553};
554
555static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 556{
a5082316
FB		 557 unsigned int color;
558 switch (s->cirrus_blt_pixelwidth) {
559 case 1:
560 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
561 break;
562 case 2:
4e12cd94 563 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 564 s->cirrus_blt_fgcol = le16_to_cpu(color);
565 break;
566 case 3:
5fafdf24 567 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 568 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 569 break;
570 default:
571 case 4:
4e12cd94
AK		 572 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
573 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 574 s->cirrus_blt_fgcol = le32_to_cpu(color);
575 break;
e6e5ad80
FB		 576 }
577}
578
a5082316 579static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 580{
a5082316 581 unsigned int color;
e6e5ad80
FB		 582 switch (s->cirrus_blt_pixelwidth) {
583 case 1:
a5082316
FB		 584 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
585 break;
e6e5ad80 586 case 2:
4e12cd94 587 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 588 s->cirrus_blt_bgcol = le16_to_cpu(color);
589 break;
e6e5ad80 590 case 3:
5fafdf24 591 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 592 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 593 break;
e6e5ad80 594 default:
a5082316 595 case 4:
4e12cd94
AK		 596 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
597 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 598 s->cirrus_blt_bgcol = le32_to_cpu(color);
599 break;
e6e5ad80
FB		 600 }
601}
602
603static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
604 int off_pitch, int bytesperline,
605 int lines)
606{
607 int y;
608 int off_cur;
609 int off_cur_end;
610
611 for (y = 0; y < lines; y++) {
612 off_cur = off_begin;
b2eb849d 613 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 614 off_cur &= TARGET_PAGE_MASK;
615 while (off_cur < off_cur_end) {
4e12cd94 616 cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
e6e5ad80
FB		 617 off_cur += TARGET_PAGE_SIZE;
618 }
619 off_begin += off_pitch;
620 }
621}
622
e6e5ad80
FB		 623static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
624 const uint8_t * src)
625{
e6e5ad80 626 uint8_t *dst;
e6e5ad80 627
4e12cd94 628 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 629
630 if (BLTUNSAFE(s))
631 return 0;
632
e69390ce 633 (*s->cirrus_rop) (s, dst, src,
5fafdf24 634 s->cirrus_blt_dstpitch, 0,
e69390ce 635 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 636 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 637 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
638 s->cirrus_blt_height);
e6e5ad80
FB		 639 return 1;
640}
641
a21ae81d
FB		 642/* fill */
643
a5082316 644static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 645{
a5082316 646 cirrus_fill_t rop_func;
a21ae81d 647
b2eb849d
AJ		 648 if (BLTUNSAFE(s))
649 return 0;
a5082316 650 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 651 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 652 s->cirrus_blt_dstpitch,
653 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 654 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
655 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
656 s->cirrus_blt_height);
657 cirrus_bitblt_reset(s);
658 return 1;
659}
660
e6e5ad80
FB		 661/***************************************
662 *
663 * bitblt (video-to-video)
664 *
665 ***************************************/
666
667static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
668{
669 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 670 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 671 s->cirrus_addr_mask));
e6e5ad80
FB		 672}
673
24236869 674static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 675{
24236869
FB		 676 int sx, sy;
677 int dx, dy;
24236869
FB		 678 int depth;
679 int notify = 0;
680
92d675d1
AJ		 681 /* make sure to only copy if it's a plain copy ROP */
682 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
683 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 684
92d675d1
AJ		 685 int width, height;
686
687 depth = s->vga.get_bpp(&s->vga) / 8;
688 s->vga.get_resolution(&s->vga, &width, &height);
689
690 /* extra x, y */
691 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
692 sy = (src / ABS(s->cirrus_blt_srcpitch));
693 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
694 dy = (dst / ABS(s->cirrus_blt_dstpitch));
695
696 /* normalize width */
697 w /= depth;
24236869 698
92d675d1
AJ		 699 /* if we're doing a backward copy, we have to adjust
700 our x/y to be the upper left corner (instead of the lower
701 right corner) */
702 if (s->cirrus_blt_dstpitch < 0) {
703 sx -= (s->cirrus_blt_width / depth) - 1;
704 dx -= (s->cirrus_blt_width / depth) - 1;
705 sy -= s->cirrus_blt_height - 1;
706 dy -= s->cirrus_blt_height - 1;
707 }
708
709 /* are we in the visible portion of memory? */
710 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
711 (sx + w) <= width && (sy + h) <= height &&
712 (dx + w) <= width && (dy + h) <= height) {
713 notify = 1;
714 }
715 }
24236869
FB		 716
717 /* we have to flush all pending changes so that the copy
718 is generated at the appropriate moment in time */
719 if (notify)
720 vga_hw_update();
721
4e12cd94 722 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 723 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 724 s->vga.vram_ptr +
b2eb849d 725 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 726 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
727 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 728
729 if (notify)
4e12cd94 730 qemu_console_copy(s->vga.ds,
38334f76
AZ		 731 sx, sy, dx, dy,
732 s->cirrus_blt_width / depth,
733 s->cirrus_blt_height);
24236869
FB		 734
735 /* we don't have to notify the display that this portion has
38334f76 736 changed since qemu_console_copy implies this */
24236869 737
31c05501
AL		 738 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
739 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
740 s->cirrus_blt_height);
24236869
FB		 741}
742
743static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
744{
65d35a09
AJ		 745 if (BLTUNSAFE(s))
746 return 0;
747
4e12cd94
AK		 748 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
749 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 750 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 751
e6e5ad80
FB		 752 return 1;
753}
754
755/***************************************
756 *
757 * bitblt (cpu-to-video)
758 *
759 ***************************************/
760
e6e5ad80
FB		 761static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
762{
763 int copy_count;
a5082316 764 uint8_t *end_ptr;
3b46e624 765
e6e5ad80 766 if (s->cirrus_srccounter > 0) {
a5082316
FB		 767 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
768 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
769 the_end:
770 s->cirrus_srccounter = 0;
771 cirrus_bitblt_reset(s);
772 } else {
773 /* at least one scan line */
774 do {
4e12cd94 775 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 776 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
777 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 778 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
779 s->cirrus_blt_width, 1);
780 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
781 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
782 if (s->cirrus_srccounter <= 0)
783 goto the_end;
784 /* more bytes than needed can be transfered because of
785 word alignment, so we keep them for the next line */
786 /* XXX: keep alignment to speed up transfer */
787 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
788 copy_count = s->cirrus_srcptr_end - end_ptr;
789 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
790 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
791 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
792 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
793 }
e6e5ad80
FB		 794 }
795}
796
797/***************************************
798 *
799 * bitblt wrapper
800 *
801 ***************************************/
802
803static void cirrus_bitblt_reset(CirrusVGAState * s)
804{
f8b237af
AL		 805 int need_update;
806
4e12cd94 807 s->vga.gr[0x31] &=
e6e5ad80 808 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 809 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
810 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 811 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
812 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
813 s->cirrus_srccounter = 0;
f8b237af
AL		 814 if (!need_update)
815 return;
8926b517 816 cirrus_update_memory_access(s);
e6e5ad80
FB		 817}
818
819static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
820{
a5082316
FB		 821 int w;
822
e6e5ad80
FB		 823 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
824 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
825 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
826
827 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
828 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 829 s->cirrus_blt_srcpitch = 8;
e6e5ad80 830 } else {
b30d4608 831 /* XXX: check for 24 bpp */
a5082316 832 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 833 }
a5082316 834 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 835 } else {
836 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 837 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 838 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 839 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
840 else
841 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 842 } else {
c9c0eae8
FB		 843 /* always align input size to 32 bits */
844 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 845 }
a5082316 846 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 847 }
a5082316
FB		 848 s->cirrus_srcptr = s->cirrus_bltbuf;
849 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 850 cirrus_update_memory_access(s);
e6e5ad80
FB		 851 return 1;
852}
853
854static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
855{
856 /* XXX */
a5082316 857#ifdef DEBUG_BITBLT
e6e5ad80
FB		 858 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
859#endif
860 return 0;
861}
862
863static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
864{
865 int ret;
866
867 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
868 ret = cirrus_bitblt_videotovideo_patterncopy(s);
869 } else {
870 ret = cirrus_bitblt_videotovideo_copy(s);
871 }
e6e5ad80
FB		 872 if (ret)
873 cirrus_bitblt_reset(s);
874 return ret;
875}
876
877static void cirrus_bitblt_start(CirrusVGAState * s)
878{
879 uint8_t blt_rop;
880
4e12cd94 881 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 882
4e12cd94
AK		 883 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
884 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
885 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
886 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 887 s->cirrus_blt_dstaddr =
4e12cd94 888 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 889 s->cirrus_blt_srcaddr =
4e12cd94
AK		 890 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
891 s->cirrus_blt_mode = s->vga.gr[0x30];
892 s->cirrus_blt_modeext = s->vga.gr[0x33];
893 blt_rop = s->vga.gr[0x32];
e6e5ad80 894
a21ae81d 895#ifdef DEBUG_BITBLT
0b74ed78 896 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 897 blt_rop,
a21ae81d 898 s->cirrus_blt_mode,
a5082316 899 s->cirrus_blt_modeext,
a21ae81d
FB		 900 s->cirrus_blt_width,
901 s->cirrus_blt_height,
902 s->cirrus_blt_dstpitch,
903 s->cirrus_blt_srcpitch,
904 s->cirrus_blt_dstaddr,
a5082316 905 s->cirrus_blt_srcaddr,
4e12cd94 906 s->vga.gr[0x2f]);
a21ae81d
FB		 907#endif
908
e6e5ad80
FB		 909 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
910 case CIRRUS_BLTMODE_PIXELWIDTH8:
911 s->cirrus_blt_pixelwidth = 1;
912 break;
913 case CIRRUS_BLTMODE_PIXELWIDTH16:
914 s->cirrus_blt_pixelwidth = 2;
915 break;
916 case CIRRUS_BLTMODE_PIXELWIDTH24:
917 s->cirrus_blt_pixelwidth = 3;
918 break;
919 case CIRRUS_BLTMODE_PIXELWIDTH32:
920 s->cirrus_blt_pixelwidth = 4;
921 break;
922 default:
a5082316 923#ifdef DEBUG_BITBLT
e6e5ad80
FB		 924 printf("cirrus: bitblt - pixel width is unknown\n");
925#endif
926 goto bitblt_ignore;
927 }
928 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
929
930 if ((s->
931 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
932 CIRRUS_BLTMODE_MEMSYSDEST))
933 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 934#ifdef DEBUG_BITBLT
e6e5ad80
FB		 935 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
936#endif
937 goto bitblt_ignore;
938 }
939
a5082316 940 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 941 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 942 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 943 CIRRUS_BLTMODE_PATTERNCOPY |
944 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 945 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 946 cirrus_bitblt_fgcol(s);
947 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 948 } else {
5fafdf24
TS		 949 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
950 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 951 CIRRUS_BLTMODE_COLOREXPAND) {
952
953 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 954 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 955 cirrus_bitblt_bgcol(s);
b30d4608 956 else
4c8732d7 957 cirrus_bitblt_fgcol(s);
b30d4608 958 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 959 } else {
960 cirrus_bitblt_fgcol(s);
961 cirrus_bitblt_bgcol(s);
962 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
963 }
e69390ce 964 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 965 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
966 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
967 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
968 cirrus_bitblt_bgcol(s);
969 else
970 cirrus_bitblt_fgcol(s);
971 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
972 } else {
973 cirrus_bitblt_fgcol(s);
974 cirrus_bitblt_bgcol(s);
975 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
976 }
977 } else {
978 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
979 }
a21ae81d 980 } else {
96cf2df8
TS		 981 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
982 if (s->cirrus_blt_pixelwidth > 2) {
983 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
984 goto bitblt_ignore;
985 }
986 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
987 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
988 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
989 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
990 } else {
991 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
992 }
993 } else {
994 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
995 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
996 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
997 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
998 } else {
999 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1000 }
1001 }
1002 }
a21ae81d
FB		 1003 // setup bitblt engine.
1004 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1005 if (!cirrus_bitblt_cputovideo(s))
1006 goto bitblt_ignore;
1007 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1008 if (!cirrus_bitblt_videotocpu(s))
1009 goto bitblt_ignore;
1010 } else {
1011 if (!cirrus_bitblt_videotovideo(s))
1012 goto bitblt_ignore;
1013 }
e6e5ad80 1014 }
e6e5ad80
FB		 1015 return;
1016 bitblt_ignore:;
1017 cirrus_bitblt_reset(s);
1018}
1019
1020static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1021{
1022 unsigned old_value;
1023
4e12cd94
AK		 1024 old_value = s->vga.gr[0x31];
1025 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1026
1027 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1028 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1029 cirrus_bitblt_reset(s);
1030 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1031 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1032 cirrus_bitblt_start(s);
1033 }
1034}
1035
1036
1037/***************************************
1038 *
1039 * basic parameters
1040 *
1041 ***************************************/
1042
a4a2f59c 1043static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1044 uint32_t *pline_offset,
1045 uint32_t *pstart_addr,
1046 uint32_t *pline_compare)
e6e5ad80 1047{
4e12cd94 1048 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1049 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1050
4e12cd94
AK		 1051 line_offset = s->vga.cr[0x13]
1052 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1053 line_offset <<= 3;
1054 *pline_offset = line_offset;
1055
4e12cd94
AK		 1056 start_addr = (s->vga.cr[0x0c] << 8)
1057 | s->vga.cr[0x0d]
1058 | ((s->vga.cr[0x1b] & 0x01) << 16)
1059 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1060 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1061 *pstart_addr = start_addr;
83acc96b 1062
4e12cd94
AK		 1063 line_compare = s->vga.cr[0x18] |
1064 ((s->vga.cr[0x07] & 0x10) << 4) |
1065 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1066 *pline_compare = line_compare;
e6e5ad80
FB		 1067}
1068
1069static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1070{
1071 uint32_t ret = 16;
1072
1073 switch (s->cirrus_hidden_dac_data & 0xf) {
1074 case 0:
1075 ret = 15;
1076 break; /* Sierra HiColor */
1077 case 1:
1078 ret = 16;
1079 break; /* XGA HiColor */
1080 default:
1081#ifdef DEBUG_CIRRUS
1082 printf("cirrus: invalid DAC value %x in 16bpp\n",
1083 (s->cirrus_hidden_dac_data & 0xf));
1084#endif
1085 ret = 15; /* XXX */
1086 break;
1087 }
1088 return ret;
1089}
1090
a4a2f59c 1091static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1092{
4e12cd94 1093 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1094 uint32_t ret = 8;
1095
4e12cd94 1096 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1097 /* Cirrus SVGA */
4e12cd94 1098 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1099 case CIRRUS_SR7_BPP_8:
1100 ret = 8;
1101 break;
1102 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1103 ret = cirrus_get_bpp16_depth(s);
1104 break;
1105 case CIRRUS_SR7_BPP_24:
1106 ret = 24;
1107 break;
1108 case CIRRUS_SR7_BPP_16:
1109 ret = cirrus_get_bpp16_depth(s);
1110 break;
1111 case CIRRUS_SR7_BPP_32:
1112 ret = 32;
1113 break;
1114 default:
1115#ifdef DEBUG_CIRRUS
4e12cd94 1116 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1117#endif
1118 ret = 8;
1119 break;
1120 }
1121 } else {
1122 /* VGA */
aeb3c85f 1123 ret = 0;
e6e5ad80
FB		 1124 }
1125
1126 return ret;
1127}
1128
a4a2f59c 1129static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1130{
1131 int width, height;
3b46e624 1132
78e127ef 1133 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1134 height = s->cr[0x12] |
1135 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1136 ((s->cr[0x07] & 0x40) << 3);
1137 height = (height + 1);
1138 /* interlace support */
1139 if (s->cr[0x1a] & 0x01)
1140 height = height * 2;
1141 *pwidth = width;
1142 *pheight = height;
1143}
1144
e6e5ad80
FB		 1145/***************************************
1146 *
1147 * bank memory
1148 *
1149 ***************************************/
1150
1151static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1152{
1153 unsigned offset;
1154 unsigned limit;
1155
4e12cd94
AK		 1156 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1157 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1158 else /* single bank */
4e12cd94 1159 offset = s->vga.gr[0x09];
e6e5ad80 1160
4e12cd94 1161 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1162 offset <<= 14;
1163 else
1164 offset <<= 12;
1165
e3a4e4b6 1166 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1167 limit = 0;
1168 else
e3a4e4b6 1169 limit = s->real_vram_size - offset;
e6e5ad80 1170
4e12cd94 1171 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1172 if (limit > 0x8000) {
1173 offset += 0x8000;
1174 limit -= 0x8000;
1175 } else {
1176 limit = 0;
1177 }
1178 }
1179
1180 if (limit > 0) {
2bec46dc
AL		 1181 /* Thinking about changing bank base? First, drop the dirty bitmap information
1182 * on the current location, otherwise we lose this pointer forever */
4e12cd94 1183 if (s->vga.lfb_vram_mapped) {
c227f099 1184 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
2bec46dc
AL		 1185 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1186 }
e6e5ad80
FB		 1187 s->cirrus_bank_base[bank_index] = offset;
1188 s->cirrus_bank_limit[bank_index] = limit;
1189 } else {
1190 s->cirrus_bank_base[bank_index] = 0;
1191 s->cirrus_bank_limit[bank_index] = 0;
1192 }
1193}
1194
1195/***************************************
1196 *
1197 * I/O access between 0x3c4-0x3c5
1198 *
1199 ***************************************/
1200
8a82c322 1201static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1202{
8a82c322 1203 switch (s->vga.sr_index) {
e6e5ad80
FB		 1204 case 0x00: // Standard VGA
1205 case 0x01: // Standard VGA
1206 case 0x02: // Standard VGA
1207 case 0x03: // Standard VGA
1208 case 0x04: // Standard VGA
8a82c322 1209 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1210 case 0x06: // Unlock Cirrus extensions
8a82c322 1211 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1212 case 0x10:
1213 case 0x30:
1214 case 0x50:
1215 case 0x70: // Graphics Cursor X
1216 case 0x90:
1217 case 0xb0:
1218 case 0xd0:
1219 case 0xf0: // Graphics Cursor X
8a82c322 1220 return s->vga.sr[0x10];
e6e5ad80
FB		 1221 case 0x11:
1222 case 0x31:
1223 case 0x51:
1224 case 0x71: // Graphics Cursor Y
1225 case 0x91:
1226 case 0xb1:
1227 case 0xd1:
a5082316 1228 case 0xf1: // Graphics Cursor Y
8a82c322 1229 return s->vga.sr[0x11];
aeb3c85f
FB		 1230 case 0x05: // ???
1231 case 0x07: // Extended Sequencer Mode
1232 case 0x08: // EEPROM Control
1233 case 0x09: // Scratch Register 0
1234 case 0x0a: // Scratch Register 1
1235 case 0x0b: // VCLK 0
1236 case 0x0c: // VCLK 1
1237 case 0x0d: // VCLK 2
1238 case 0x0e: // VCLK 3
1239 case 0x0f: // DRAM Control
e6e5ad80
FB		 1240 case 0x12: // Graphics Cursor Attribute
1241 case 0x13: // Graphics Cursor Pattern Address
1242 case 0x14: // Scratch Register 2
1243 case 0x15: // Scratch Register 3
1244 case 0x16: // Performance Tuning Register
1245 case 0x17: // Configuration Readback and Extended Control
1246 case 0x18: // Signature Generator Control
1247 case 0x19: // Signal Generator Result
1248 case 0x1a: // Signal Generator Result
1249 case 0x1b: // VCLK 0 Denominator & Post
1250 case 0x1c: // VCLK 1 Denominator & Post
1251 case 0x1d: // VCLK 2 Denominator & Post
1252 case 0x1e: // VCLK 3 Denominator & Post
1253 case 0x1f: // BIOS Write Enable and MCLK select
1254#ifdef DEBUG_CIRRUS
8a82c322 1255 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1256#endif
8a82c322 1257 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1258 default:
1259#ifdef DEBUG_CIRRUS
8a82c322 1260 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1261#endif
8a82c322 1262 return 0xff;
e6e5ad80
FB		 1263 break;
1264 }
e6e5ad80
FB		 1265}
1266
31c63201 1267static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1268{
31c63201 1269 switch (s->vga.sr_index) {
e6e5ad80
FB		 1270 case 0x00: // Standard VGA
1271 case 0x01: // Standard VGA
1272 case 0x02: // Standard VGA
1273 case 0x03: // Standard VGA
1274 case 0x04: // Standard VGA
31c63201
JQ		 1275 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1276 if (s->vga.sr_index == 1)
1277 s->vga.update_retrace_info(&s->vga);
1278 break;
e6e5ad80 1279 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1280 val &= 0x17;
1281 if (val == 0x12) {
1282 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1283 } else {
31c63201 1284 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1285 }
1286 break;
1287 case 0x10:
1288 case 0x30:
1289 case 0x50:
1290 case 0x70: // Graphics Cursor X
1291 case 0x90:
1292 case 0xb0:
1293 case 0xd0:
1294 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1295 s->vga.sr[0x10] = val;
1296 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1297 break;
1298 case 0x11:
1299 case 0x31:
1300 case 0x51:
1301 case 0x71: // Graphics Cursor Y
1302 case 0x91:
1303 case 0xb1:
1304 case 0xd1:
1305 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1306 s->vga.sr[0x11] = val;
1307 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1308 break;
1309 case 0x07: // Extended Sequencer Mode
2bec46dc 1310 cirrus_update_memory_access(s);
e6e5ad80
FB		 1311 case 0x08: // EEPROM Control
1312 case 0x09: // Scratch Register 0
1313 case 0x0a: // Scratch Register 1
1314 case 0x0b: // VCLK 0
1315 case 0x0c: // VCLK 1
1316 case 0x0d: // VCLK 2
1317 case 0x0e: // VCLK 3
1318 case 0x0f: // DRAM Control
1319 case 0x12: // Graphics Cursor Attribute
1320 case 0x13: // Graphics Cursor Pattern Address
1321 case 0x14: // Scratch Register 2
1322 case 0x15: // Scratch Register 3
1323 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1324 case 0x18: // Signature Generator Control
1325 case 0x19: // Signature Generator Result
1326 case 0x1a: // Signature Generator Result
1327 case 0x1b: // VCLK 0 Denominator & Post
1328 case 0x1c: // VCLK 1 Denominator & Post
1329 case 0x1d: // VCLK 2 Denominator & Post
1330 case 0x1e: // VCLK 3 Denominator & Post
1331 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1332 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1333#ifdef DEBUG_CIRRUS
1334 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1335 s->vga.sr_index, val);
e6e5ad80
FB		 1336#endif
1337 break;
8926b517 1338 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1339 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1340 | (val & 0xc7);
8926b517
FB		 1341 cirrus_update_memory_access(s);
1342 break;
e6e5ad80
FB		 1343 default:
1344#ifdef DEBUG_CIRRUS
31c63201
JQ		 1345 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1346 s->vga.sr_index, val);
e6e5ad80
FB		 1347#endif
1348 break;
1349 }
e6e5ad80
FB		 1350}
1351
1352/***************************************
1353 *
1354 * I/O access at 0x3c6
1355 *
1356 ***************************************/
1357
957c9db5 1358static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1359{
a21ae81d 1360 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1361 s->cirrus_hidden_dac_lockindex = 0;
1362 return s->cirrus_hidden_dac_data;
e6e5ad80 1363 }
957c9db5 1364 return 0xff;
e6e5ad80
FB		 1365}
1366
1367static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1368{
1369 if (s->cirrus_hidden_dac_lockindex == 4) {
1370 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1371#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1372 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1373#endif
1374 }
1375 s->cirrus_hidden_dac_lockindex = 0;
1376}
1377
1378/***************************************
1379 *
1380 * I/O access at 0x3c9
1381 *
1382 ***************************************/
1383
5deaeee3 1384static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1385{
5deaeee3
JQ		 1386 int val;
1387
1388 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1389 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1390 s->vga.dac_sub_index];
1391 } else {
1392 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1393 }
4e12cd94
AK		 1394 if (++s->vga.dac_sub_index == 3) {
1395 s->vga.dac_sub_index = 0;
1396 s->vga.dac_read_index++;
e6e5ad80 1397 }
5deaeee3 1398 return val;
e6e5ad80
FB		 1399}
1400
86948bb1 1401static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1402{
4e12cd94
AK		 1403 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1404 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1405 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1406 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1407 s->vga.dac_cache, 3);
1408 } else {
1409 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1410 }
a5082316 1411 /* XXX update cursor */
4e12cd94
AK		 1412 s->vga.dac_sub_index = 0;
1413 s->vga.dac_write_index++;
e6e5ad80 1414 }
e6e5ad80
FB		 1415}
1416
1417/***************************************
1418 *
1419 * I/O access between 0x3ce-0x3cf
1420 *
1421 ***************************************/
1422
f705db9d 1423static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1424{
1425 switch (reg_index) {
aeb3c85f 1426 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1427 return s->cirrus_shadow_gr0;
aeb3c85f 1428 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1429 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1430 case 0x02: // Standard VGA
1431 case 0x03: // Standard VGA
1432 case 0x04: // Standard VGA
1433 case 0x06: // Standard VGA
1434 case 0x07: // Standard VGA
1435 case 0x08: // Standard VGA
f705db9d 1436 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1437 case 0x05: // Standard VGA, Cirrus extended mode
1438 default:
1439 break;
1440 }
1441
1442 if (reg_index < 0x3a) {
f705db9d 1443 return s->vga.gr[reg_index];
e6e5ad80
FB		 1444 } else {
1445#ifdef DEBUG_CIRRUS
1446 printf("cirrus: inport gr_index %02x\n", reg_index);
1447#endif
f705db9d 1448 return 0xff;
e6e5ad80 1449 }
e6e5ad80
FB		 1450}
1451
22286bc6
JQ		 1452static void
1453cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1454{
a5082316
FB		 1455#if defined(DEBUG_BITBLT) && 0
1456 printf("gr%02x: %02x\n", reg_index, reg_value);
1457#endif
e6e5ad80
FB		 1458 switch (reg_index) {
1459 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1460 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1461 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1462 break;
e6e5ad80 1463 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1464 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1465 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1466 break;
e6e5ad80
FB		 1467 case 0x02: // Standard VGA
1468 case 0x03: // Standard VGA
1469 case 0x04: // Standard VGA
1470 case 0x06: // Standard VGA
1471 case 0x07: // Standard VGA
1472 case 0x08: // Standard VGA
22286bc6
JQ		 1473 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1474 break;
e6e5ad80 1475 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1476 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1477 cirrus_update_memory_access(s);
e6e5ad80
FB		 1478 break;
1479 case 0x09: // bank offset #0
1480 case 0x0A: // bank offset #1
4e12cd94 1481 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1482 cirrus_update_bank_ptr(s, 0);
1483 cirrus_update_bank_ptr(s, 1);
2bec46dc 1484 cirrus_update_memory_access(s);
8926b517 1485 break;
e6e5ad80 1486 case 0x0B:
4e12cd94 1487 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1488 cirrus_update_bank_ptr(s, 0);
1489 cirrus_update_bank_ptr(s, 1);
8926b517 1490 cirrus_update_memory_access(s);
e6e5ad80
FB		 1491 break;
1492 case 0x10: // BGCOLOR 0x0000ff00
1493 case 0x11: // FGCOLOR 0x0000ff00
1494 case 0x12: // BGCOLOR 0x00ff0000
1495 case 0x13: // FGCOLOR 0x00ff0000
1496 case 0x14: // BGCOLOR 0xff000000
1497 case 0x15: // FGCOLOR 0xff000000
1498 case 0x20: // BLT WIDTH 0x0000ff
1499 case 0x22: // BLT HEIGHT 0x0000ff
1500 case 0x24: // BLT DEST PITCH 0x0000ff
1501 case 0x26: // BLT SRC PITCH 0x0000ff
1502 case 0x28: // BLT DEST ADDR 0x0000ff
1503 case 0x29: // BLT DEST ADDR 0x00ff00
1504 case 0x2c: // BLT SRC ADDR 0x0000ff
1505 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1506 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1507 case 0x30: // BLT MODE
1508 case 0x32: // RASTER OP
a21ae81d 1509 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1510 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1511 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1512 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1513 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1514 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1515 break;
1516 case 0x21: // BLT WIDTH 0x001f00
1517 case 0x23: // BLT HEIGHT 0x001f00
1518 case 0x25: // BLT DEST PITCH 0x001f00
1519 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1520 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1521 break;
1522 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1523 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1524 /* if auto start mode, starts bit blt now */
4e12cd94 1525 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1526 cirrus_bitblt_start(s);
1527 }
1528 break;
e6e5ad80 1529 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1530 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1531 break;
1532 case 0x31: // BLT STATUS/START
1533 cirrus_write_bitblt(s, reg_value);
1534 break;
1535 default:
1536#ifdef DEBUG_CIRRUS
1537 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1538 reg_value);
1539#endif
1540 break;
1541 }
e6e5ad80
FB		 1542}
1543
1544/***************************************
1545 *
1546 * I/O access between 0x3d4-0x3d5
1547 *
1548 ***************************************/
1549
b863d514 1550static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1551{
1552 switch (reg_index) {
1553 case 0x00: // Standard VGA
1554 case 0x01: // Standard VGA
1555 case 0x02: // Standard VGA
1556 case 0x03: // Standard VGA
1557 case 0x04: // Standard VGA
1558 case 0x05: // Standard VGA
1559 case 0x06: // Standard VGA
1560 case 0x07: // Standard VGA
1561 case 0x08: // Standard VGA
1562 case 0x09: // Standard VGA
1563 case 0x0a: // Standard VGA
1564 case 0x0b: // Standard VGA
1565 case 0x0c: // Standard VGA
1566 case 0x0d: // Standard VGA
1567 case 0x0e: // Standard VGA
1568 case 0x0f: // Standard VGA
1569 case 0x10: // Standard VGA
1570 case 0x11: // Standard VGA
1571 case 0x12: // Standard VGA
1572 case 0x13: // Standard VGA
1573 case 0x14: // Standard VGA
1574 case 0x15: // Standard VGA
1575 case 0x16: // Standard VGA
1576 case 0x17: // Standard VGA
1577 case 0x18: // Standard VGA
b863d514 1578 return s->vga.cr[s->vga.cr_index];
ca896ef3 1579 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1580 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1581 case 0x19: // Interlace End
1582 case 0x1a: // Miscellaneous Control
1583 case 0x1b: // Extended Display Control
1584 case 0x1c: // Sync Adjust and Genlock
1585 case 0x1d: // Overlay Extended Control
1586 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1587 case 0x25: // Part Status
1588 case 0x27: // Part ID (R)
b863d514 1589 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1590 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1591 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1592 break;
1593 default:
1594#ifdef DEBUG_CIRRUS
1595 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1596#endif
b863d514 1597 return 0xff;
e6e5ad80 1598 }
e6e5ad80
FB		 1599}
1600
4ec1ce04 1601static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1602{
4ec1ce04 1603 switch (s->vga.cr_index) {
e6e5ad80
FB		 1604 case 0x00: // Standard VGA
1605 case 0x01: // Standard VGA
1606 case 0x02: // Standard VGA
1607 case 0x03: // Standard VGA
1608 case 0x04: // Standard VGA
1609 case 0x05: // Standard VGA
1610 case 0x06: // Standard VGA
1611 case 0x07: // Standard VGA
1612 case 0x08: // Standard VGA
1613 case 0x09: // Standard VGA
1614 case 0x0a: // Standard VGA
1615 case 0x0b: // Standard VGA
1616 case 0x0c: // Standard VGA
1617 case 0x0d: // Standard VGA
1618 case 0x0e: // Standard VGA
1619 case 0x0f: // Standard VGA
1620 case 0x10: // Standard VGA
1621 case 0x11: // Standard VGA
1622 case 0x12: // Standard VGA
1623 case 0x13: // Standard VGA
1624 case 0x14: // Standard VGA
1625 case 0x15: // Standard VGA
1626 case 0x16: // Standard VGA
1627 case 0x17: // Standard VGA
1628 case 0x18: // Standard VGA
4ec1ce04
JQ		 1629 /* handle CR0-7 protection */
1630 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1631 /* can always write bit 4 of CR7 */
1632 if (s->vga.cr_index == 7)
1633 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1634 return;
1635 }
1636 s->vga.cr[s->vga.cr_index] = reg_value;
1637 switch(s->vga.cr_index) {
1638 case 0x00:
1639 case 0x04:
1640 case 0x05:
1641 case 0x06:
1642 case 0x07:
1643 case 0x11:
1644 case 0x17:
1645 s->vga.update_retrace_info(&s->vga);
1646 break;
1647 }
1648 break;
e6e5ad80
FB		 1649 case 0x19: // Interlace End
1650 case 0x1a: // Miscellaneous Control
1651 case 0x1b: // Extended Display Control
1652 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1653 case 0x1d: // Overlay Extended Control
4ec1ce04 1654 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1655#ifdef DEBUG_CIRRUS
1656 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1657 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1658#endif
1659 break;
1660 case 0x22: // Graphics Data Latches Readback (R)
1661 case 0x24: // Attribute Controller Toggle Readback (R)
1662 case 0x26: // Attribute Controller Index Readback (R)
1663 case 0x27: // Part ID (R)
1664 break;
e6e5ad80
FB		 1665 case 0x25: // Part Status
1666 default:
1667#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1668 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1669 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1670#endif
1671 break;
1672 }
e6e5ad80
FB		 1673}
1674
1675/***************************************
1676 *
1677 * memory-mapped I/O (bitblt)
1678 *
1679 ***************************************/
1680
1681static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1682{
1683 int value = 0xff;
1684
1685 switch (address) {
1686 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1687 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1688 break;
1689 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1690 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1691 break;
1692 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1693 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1694 break;
1695 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1696 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1697 break;
1698 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1699 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1700 break;
1701 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1702 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1703 break;
1704 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1705 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1706 break;
1707 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1708 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1709 break;
1710 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1711 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1712 break;
1713 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1714 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1715 break;
1716 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1717 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1718 break;
1719 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1720 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1721 break;
1722 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1723 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1724 break;
1725 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1726 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1727 break;
1728 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1729 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1730 break;
1731 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1732 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1733 break;
1734 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1735 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1736 break;
1737 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1738 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1739 break;
1740 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1741 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1742 break;
1743 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1744 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1745 break;
1746 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1747 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1748 break;
1749 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1750 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1751 break;
1752 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1753 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1754 break;
1755 case CIRRUS_MMIO_BLTMODE:
f705db9d 1756 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1757 break;
1758 case CIRRUS_MMIO_BLTROP:
f705db9d 1759 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1760 break;
a21ae81d 1761 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1762 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1763 break;
e6e5ad80 1764 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1765 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1766 break;
1767 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1768 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1769 break;
1770 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1771 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1772 break;
1773 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1774 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1775 break;
1776 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1777 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1778 break;
1779 default:
1780#ifdef DEBUG_CIRRUS
1781 printf("cirrus: mmio read - address 0x%04x\n", address);
1782#endif
1783 break;
1784 }
1785
1786 return (uint8_t) value;
1787}
1788
1789static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1790 uint8_t value)
1791{
1792 switch (address) {
1793 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1794 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1795 break;
1796 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1797 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1798 break;
1799 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1800 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1801 break;
1802 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1803 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1804 break;
1805 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1806 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1807 break;
1808 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1809 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1810 break;
1811 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1812 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1813 break;
1814 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1815 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1816 break;
1817 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1818 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1819 break;
1820 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1821 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1822 break;
1823 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1824 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1825 break;
1826 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1827 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1828 break;
1829 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1830 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1831 break;
1832 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1833 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1834 break;
1835 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1836 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1837 break;
1838 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1839 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1840 break;
1841 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1842 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1843 break;
1844 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1845 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1846 break;
1847 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1848 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1849 break;
1850 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1851 /* ignored */
1852 break;
1853 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1854 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1855 break;
1856 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1857 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1858 break;
1859 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1860 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1861 break;
1862 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1863 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1864 break;
1865 case CIRRUS_MMIO_BLTMODE:
22286bc6 1866 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1867 break;
1868 case CIRRUS_MMIO_BLTROP:
22286bc6 1869 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1870 break;
a21ae81d 1871 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1872 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1873 break;
e6e5ad80 1874 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1875 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1876 break;
1877 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1878 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1879 break;
1880 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1881 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1882 break;
1883 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1884 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1885 break;
1886 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1887 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1888 break;
1889 default:
1890#ifdef DEBUG_CIRRUS
1891 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1892 address, value);
1893#endif
1894 break;
1895 }
1896}
1897
e6e5ad80
FB		 1898/***************************************
1899 *
1900 * write mode 4/5
1901 *
1902 * assume TARGET_PAGE_SIZE >= 16
1903 *
1904 ***************************************/
1905
1906static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1907 unsigned mode,
1908 unsigned offset,
1909 uint32_t mem_value)
1910{
1911 int x;
1912 unsigned val = mem_value;
1913 uint8_t *dst;
1914
4e12cd94 1915 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1916 for (x = 0; x < 8; x++) {
1917 if (val & 0x80) {
0b74ed78 1918 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1919 } else if (mode == 5) {
0b74ed78 1920 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1921 }
1922 val <<= 1;
0b74ed78 1923 dst++;
e6e5ad80 1924 }
4e12cd94
AK		 1925 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1926 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
e6e5ad80
FB		 1927}
1928
1929static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1930 unsigned mode,
1931 unsigned offset,
1932 uint32_t mem_value)
1933{
1934 int x;
1935 unsigned val = mem_value;
1936 uint8_t *dst;
1937
4e12cd94 1938 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1939 for (x = 0; x < 8; x++) {
1940 if (val & 0x80) {
0b74ed78 1941 *dst = s->cirrus_shadow_gr1;
4e12cd94 1942 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1943 } else if (mode == 5) {
0b74ed78 1944 *dst = s->cirrus_shadow_gr0;
4e12cd94 1945 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1946 }
1947 val <<= 1;
0b74ed78 1948 dst += 2;
e6e5ad80 1949 }
4e12cd94
AK		 1950 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1951 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
e6e5ad80
FB		 1952}
1953
1954/***************************************
1955 *
1956 * memory access between 0xa0000-0xbffff
1957 *
1958 ***************************************/
1959
c227f099 1960static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 1961{
1962 CirrusVGAState *s = opaque;
1963 unsigned bank_index;
1964 unsigned bank_offset;
1965 uint32_t val;
1966
4e12cd94 1967 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 1968 return vga_mem_readb(s, addr);
1969 }
1970
aeb3c85f
FB		 1971 addr &= 0x1ffff;
1972
e6e5ad80
FB		 1973 if (addr < 0x10000) {
1974 /* XXX handle bitblt */
1975 /* video memory */
1976 bank_index = addr >> 15;
1977 bank_offset = addr & 0x7fff;
1978 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1979 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1980 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1981 bank_offset <<= 4;
4e12cd94 1982 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1983 bank_offset <<= 3;
1984 }
1985 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1986 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1987 } else
1988 val = 0xff;
1989 } else if (addr >= 0x18000 && addr < 0x18100) {
1990 /* memory-mapped I/O */
1991 val = 0xff;
4e12cd94 1992 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1993 val = cirrus_mmio_blt_read(s, addr & 0xff);
1994 }
1995 } else {
1996 val = 0xff;
1997#ifdef DEBUG_CIRRUS
0bf9e31a 1998 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1999#endif
2000 }
2001 return val;
2002}
2003
c227f099 2004static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2005{
2006 uint32_t v;
2007#ifdef TARGET_WORDS_BIGENDIAN
2008 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2009 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2010#else
2011 v = cirrus_vga_mem_readb(opaque, addr);
2012 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2013#endif
2014 return v;
2015}
2016
c227f099 2017static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2018{
2019 uint32_t v;
2020#ifdef TARGET_WORDS_BIGENDIAN
2021 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2022 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2023 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2024 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2025#else
2026 v = cirrus_vga_mem_readb(opaque, addr);
2027 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2028 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2029 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2030#endif
2031 return v;
2032}
2033
c227f099 2034static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2035 uint32_t mem_value)
2036{
2037 CirrusVGAState *s = opaque;
2038 unsigned bank_index;
2039 unsigned bank_offset;
2040 unsigned mode;
2041
4e12cd94 2042 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 2043 vga_mem_writeb(s, addr, mem_value);
2044 return;
2045 }
2046
aeb3c85f
FB		 2047 addr &= 0x1ffff;
2048
e6e5ad80
FB		 2049 if (addr < 0x10000) {
2050 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2051 /* bitblt */
2052 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2053 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2054 cirrus_bitblt_cputovideo_next(s);
2055 }
2056 } else {
2057 /* video memory */
2058 bank_index = addr >> 15;
2059 bank_offset = addr & 0x7fff;
2060 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2061 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2062 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2063 bank_offset <<= 4;
4e12cd94 2064 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2065 bank_offset <<= 3;
2066 }
2067 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2068 mode = s->vga.gr[0x05] & 0x7;
2069 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2070 *(s->vga.vram_ptr + bank_offset) = mem_value;
2071 cpu_physical_memory_set_dirty(s->vga.vram_offset +
e6e5ad80
FB		 2072 bank_offset);
2073 } else {
4e12cd94 2074 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2075 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2076 bank_offset,
2077 mem_value);
2078 } else {
2079 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2080 bank_offset,
2081 mem_value);
2082 }
2083 }
2084 }
2085 }
2086 } else if (addr >= 0x18000 && addr < 0x18100) {
2087 /* memory-mapped I/O */
4e12cd94 2088 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2089 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2090 }
2091 } else {
2092#ifdef DEBUG_CIRRUS
0bf9e31a
BS		 2093 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2094 mem_value);
e6e5ad80
FB		 2095#endif
2096 }
2097}
2098
c227f099 2099static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
e6e5ad80
FB		 2100{
2101#ifdef TARGET_WORDS_BIGENDIAN
2102 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2103 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2104#else
2105 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2106 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2107#endif
2108}
2109
c227f099 2110static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
e6e5ad80
FB		 2111{
2112#ifdef TARGET_WORDS_BIGENDIAN
2113 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2114 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2115 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2116 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2117#else
2118 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2119 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2120 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2121 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2122#endif
2123}
2124
d60efc6b 2125static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
e6e5ad80
FB		 2126 cirrus_vga_mem_readb,
2127 cirrus_vga_mem_readw,
2128 cirrus_vga_mem_readl,
2129};
2130
d60efc6b 2131static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = {
e6e5ad80
FB		 2132 cirrus_vga_mem_writeb,
2133 cirrus_vga_mem_writew,
2134 cirrus_vga_mem_writel,
2135};
2136
a5082316
FB		 2137/***************************************
2138 *
2139 * hardware cursor
2140 *
2141 ***************************************/
2142
2143static inline void invalidate_cursor1(CirrusVGAState *s)
2144{
2145 if (s->last_hw_cursor_size) {
4e12cd94 2146 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2147 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2148 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2149 }
2150}
2151
2152static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2153{
2154 const uint8_t *src;
2155 uint32_t content;
2156 int y, y_min, y_max;
2157
4e12cd94
AK		 2158 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2159 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2160 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2161 y_min = 64;
2162 y_max = -1;
2163 for(y = 0; y < 64; y++) {
2164 content = ((uint32_t *)src)[0] |
2165 ((uint32_t *)src)[1] |
2166 ((uint32_t *)src)[2] |
2167 ((uint32_t *)src)[3];
2168 if (content) {
2169 if (y < y_min)
2170 y_min = y;
2171 if (y > y_max)
2172 y_max = y;
2173 }
2174 src += 16;
2175 }
2176 } else {
4e12cd94 2177 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2178 y_min = 32;
2179 y_max = -1;
2180 for(y = 0; y < 32; y++) {
2181 content = ((uint32_t *)src)[0] |
2182 ((uint32_t *)(src + 128))[0];
2183 if (content) {
2184 if (y < y_min)
2185 y_min = y;
2186 if (y > y_max)
2187 y_max = y;
2188 }
2189 src += 4;
2190 }
2191 }
2192 if (y_min > y_max) {
2193 s->last_hw_cursor_y_start = 0;
2194 s->last_hw_cursor_y_end = 0;
2195 } else {
2196 s->last_hw_cursor_y_start = y_min;
2197 s->last_hw_cursor_y_end = y_max + 1;
2198 }
2199}
2200
2201/* NOTE: we do not currently handle the cursor bitmap change, so we
2202 update the cursor only if it moves. */
a4a2f59c 2203static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2204{
4e12cd94 2205 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2206 int size;
2207
4e12cd94 2208 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2209 size = 0;
2210 } else {
4e12cd94 2211 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2212 size = 64;
2213 else
2214 size = 32;
2215 }
2216 /* invalidate last cursor and new cursor if any change */
2217 if (s->last_hw_cursor_size != size ||
2218 s->last_hw_cursor_x != s->hw_cursor_x ||
2219 s->last_hw_cursor_y != s->hw_cursor_y) {
2220
2221 invalidate_cursor1(s);
3b46e624 2222
a5082316
FB		 2223 s->last_hw_cursor_size = size;
2224 s->last_hw_cursor_x = s->hw_cursor_x;
2225 s->last_hw_cursor_y = s->hw_cursor_y;
2226 /* compute the real cursor min and max y */
2227 cirrus_cursor_compute_yrange(s);
2228 invalidate_cursor1(s);
2229 }
2230}
2231
a4a2f59c 2232static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2233{
4e12cd94 2234 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2235 int w, h, bpp, x1, x2, poffset;
2236 unsigned int color0, color1;
2237 const uint8_t *palette, *src;
2238 uint32_t content;
3b46e624 2239
4e12cd94 2240 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2241 return;
2242 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2243 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2244 h = 64;
2245 } else {
2246 h = 32;
2247 }
2248 if (scr_y < s->hw_cursor_y ||
2249 scr_y >= (s->hw_cursor_y + h))
2250 return;
3b46e624 2251
4e12cd94
AK		 2252 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2253 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2254 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2255 src += (scr_y - s->hw_cursor_y) * 16;
2256 poffset = 8;
2257 content = ((uint32_t *)src)[0] |
2258 ((uint32_t *)src)[1] |
2259 ((uint32_t *)src)[2] |
2260 ((uint32_t *)src)[3];
2261 } else {
4e12cd94 2262 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2263 src += (scr_y - s->hw_cursor_y) * 4;
2264 poffset = 128;
2265 content = ((uint32_t *)src)[0] |
2266 ((uint32_t *)(src + 128))[0];
2267 }
2268 /* if nothing to draw, no need to continue */
2269 if (!content)
2270 return;
2271 w = h;
2272
2273 x1 = s->hw_cursor_x;
4e12cd94 2274 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2275 return;
2276 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2277 if (x2 > s->vga.last_scr_width)
2278 x2 = s->vga.last_scr_width;
a5082316
FB		 2279 w = x2 - x1;
2280 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2281 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2282 c6_to_8(palette[0x0 * 3 + 1]),
2283 c6_to_8(palette[0x0 * 3 + 2]));
2284 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2285 c6_to_8(palette[0xf * 3 + 1]),
2286 c6_to_8(palette[0xf * 3 + 2]));
2287 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2288 d1 += x1 * bpp;
4e12cd94 2289 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2290 default:
2291 break;
2292 case 8:
2293 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2294 break;
2295 case 15:
2296 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2297 break;
2298 case 16:
2299 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2300 break;
2301 case 32:
2302 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2303 break;
2304 }
2305}
2306
e6e5ad80
FB		 2307/***************************************
2308 *
2309 * LFB memory access
2310 *
2311 ***************************************/
2312
c227f099 2313static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
e6e5ad80 2314{
e05587e8 2315 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2316 uint32_t ret;
2317
e6e5ad80
FB		 2318 addr &= s->cirrus_addr_mask;
2319
4e12cd94 2320 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2321 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2322 /* memory-mapped I/O */
2323 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2324 } else if (0) {
2325 /* XXX handle bitblt */
2326 ret = 0xff;
2327 } else {
2328 /* video memory */
4e12cd94 2329 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2330 addr <<= 4;
4e12cd94 2331 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2332 addr <<= 3;
2333 }
2334 addr &= s->cirrus_addr_mask;
4e12cd94 2335 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2336 }
2337
2338 return ret;
2339}
2340
c227f099 2341static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2342{
2343 uint32_t v;
2344#ifdef TARGET_WORDS_BIGENDIAN
2345 v = cirrus_linear_readb(opaque, addr) << 8;
2346 v |= cirrus_linear_readb(opaque, addr + 1);
2347#else
2348 v = cirrus_linear_readb(opaque, addr);
2349 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2350#endif
2351 return v;
2352}
2353
c227f099 2354static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2355{
2356 uint32_t v;
2357#ifdef TARGET_WORDS_BIGENDIAN
2358 v = cirrus_linear_readb(opaque, addr) << 24;
2359 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2360 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2361 v |= cirrus_linear_readb(opaque, addr + 3);
2362#else
2363 v = cirrus_linear_readb(opaque, addr);
2364 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2365 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2366 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2367#endif
2368 return v;
2369}
2370
c227f099 2371static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2372 uint32_t val)
2373{
e05587e8 2374 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2375 unsigned mode;
2376
2377 addr &= s->cirrus_addr_mask;
3b46e624 2378
4e12cd94 2379 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2380 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2381 /* memory-mapped I/O */
2382 cirrus_mmio_blt_write(s, addr & 0xff, val);
2383 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2384 /* bitblt */
2385 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2386 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2387 cirrus_bitblt_cputovideo_next(s);
2388 }
2389 } else {
2390 /* video memory */
4e12cd94 2391 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2392 addr <<= 4;
4e12cd94 2393 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2394 addr <<= 3;
2395 }
2396 addr &= s->cirrus_addr_mask;
2397
4e12cd94
AK		 2398 mode = s->vga.gr[0x05] & 0x7;
2399 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2400 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2401 cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
e6e5ad80 2402 } else {
4e12cd94 2403 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2404 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2405 } else {
2406 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2407 }
2408 }
2409 }
2410}
2411
c227f099 2412static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2413 uint32_t val)
2414{
2415#ifdef TARGET_WORDS_BIGENDIAN
2416 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2417 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2418#else
2419 cirrus_linear_writeb(opaque, addr, val & 0xff);
2420 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2421#endif
2422}
2423
c227f099 2424static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2425 uint32_t val)
2426{
2427#ifdef TARGET_WORDS_BIGENDIAN
2428 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2429 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2430 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2431 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2432#else
2433 cirrus_linear_writeb(opaque, addr, val & 0xff);
2434 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2435 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2436 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2437#endif
2438}
2439
2440
d60efc6b 2441static CPUReadMemoryFunc * const cirrus_linear_read[3] = {
e6e5ad80
FB		 2442 cirrus_linear_readb,
2443 cirrus_linear_readw,
2444 cirrus_linear_readl,
2445};
2446
d60efc6b 2447static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
e6e5ad80
FB		 2448 cirrus_linear_writeb,
2449 cirrus_linear_writew,
2450 cirrus_linear_writel,
2451};
2452
a5082316
FB		 2453/***************************************
2454 *
2455 * system to screen memory access
2456 *
2457 ***************************************/
2458
2459
c227f099 2460static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2461{
2462 uint32_t ret;
2463
2464 /* XXX handle bitblt */
2465 ret = 0xff;
2466 return ret;
2467}
2468
c227f099 2469static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2470{
2471 uint32_t v;
2472#ifdef TARGET_WORDS_BIGENDIAN
2473 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2474 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2475#else
2476 v = cirrus_linear_bitblt_readb(opaque, addr);
2477 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2478#endif
2479 return v;
2480}
2481
c227f099 2482static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2483{
2484 uint32_t v;
2485#ifdef TARGET_WORDS_BIGENDIAN
2486 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2487 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2488 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2489 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2490#else
2491 v = cirrus_linear_bitblt_readb(opaque, addr);
2492 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2493 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2494 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2495#endif
2496 return v;
2497}
2498
c227f099 2499static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2500 uint32_t val)
2501{
e05587e8 2502 CirrusVGAState *s = opaque;
a5082316
FB		 2503
2504 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2505 /* bitblt */
2506 *s->cirrus_srcptr++ = (uint8_t) val;
2507 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2508 cirrus_bitblt_cputovideo_next(s);
2509 }
2510 }
2511}
2512
c227f099 2513static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2514 uint32_t val)
2515{
2516#ifdef TARGET_WORDS_BIGENDIAN
2517 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2518 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2519#else
2520 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2521 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2522#endif
2523}
2524
c227f099 2525static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2526 uint32_t val)
2527{
2528#ifdef TARGET_WORDS_BIGENDIAN
2529 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2530 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2531 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2532 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2533#else
2534 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2535 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2536 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2537 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2538#endif
2539}
2540
2541
d60efc6b 2542static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = {
a5082316
FB		 2543 cirrus_linear_bitblt_readb,
2544 cirrus_linear_bitblt_readw,
2545 cirrus_linear_bitblt_readl,
2546};
2547
d60efc6b 2548static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = {
a5082316
FB		 2549 cirrus_linear_bitblt_writeb,
2550 cirrus_linear_bitblt_writew,
2551 cirrus_linear_bitblt_writel,
2552};
2553
2bec46dc
AL		 2554static void map_linear_vram(CirrusVGAState *s)
2555{
4e12cd94
AK		 2556 if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2557 s->vga.map_addr = s->vga.lfb_addr;
2558 s->vga.map_end = s->vga.lfb_end;
2559 cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2bec46dc
AL		 2560 }
2561
4e12cd94 2562 if (!s->vga.map_addr)
2bec46dc
AL		 2563 return;
2564
4e12cd94 2565 s->vga.lfb_vram_mapped = 0;
2bec46dc
AL		 2566
2567 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2568 && !((s->vga.sr[0x07] & 0x01) == 0)
2569 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2570 && !(s->vga.gr[0x0B] & 0x02)) {
2bec46dc
AL		 2571
2572 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
4e12cd94 2573 (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2bec46dc 2574 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
4e12cd94 2575 (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2bec46dc 2576
4e12cd94 2577 s->vga.lfb_vram_mapped = 1;
2bec46dc
AL		 2578 }
2579 else {
7cff316e 2580 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
4e12cd94 2581 s->vga.vga_io_memory);
2bec46dc
AL		 2582 }
2583
4e12cd94 2584 vga_dirty_log_start(&s->vga);
2bec46dc
AL		 2585}
2586
2587static void unmap_linear_vram(CirrusVGAState *s)
2588{
4516e45f 2589 if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
4e12cd94 2590 s->vga.map_addr = s->vga.map_end = 0;
4516e45f
JK		 2591 cpu_register_physical_memory(s->vga.lfb_addr, s->vga.vram_size,
2592 s->cirrus_linear_io_addr);
2593 }
2bec46dc 2594 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
4e12cd94 2595 s->vga.vga_io_memory);
2bec46dc
AL		 2596}
2597
8926b517
FB		 2598/* Compute the memory access functions */
2599static void cirrus_update_memory_access(CirrusVGAState *s)
2600{
2601 unsigned mode;
2602
4e12cd94 2603 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2604 goto generic_io;
2605 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2606 goto generic_io;
2607 } else {
4e12cd94 2608 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2609 goto generic_io;
4e12cd94 2610 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2611 goto generic_io;
2612 }
3b46e624 2613
4e12cd94
AK		 2614 mode = s->vga.gr[0x05] & 0x7;
2615 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2616 map_linear_vram(s);
8926b517
FB		 2617 } else {
2618 generic_io:
2bec46dc 2619 unmap_linear_vram(s);
8926b517
FB		 2620 }
2621 }
2622}
2623
2624
e6e5ad80
FB		 2625/* I/O ports */
2626
0ceac75b 2627static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
e6e5ad80 2628{
b6343073
JQ		 2629 CirrusVGAState *c = opaque;
2630 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2631 int val, index;
2632
b6343073 2633 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2634 val = 0xff;
2635 } else {
2636 switch (addr) {
2637 case 0x3c0:
b6343073
JQ		 2638 if (s->ar_flip_flop == 0) {
2639 val = s->ar_index;
e6e5ad80
FB		 2640 } else {
2641 val = 0;
2642 }
2643 break;
2644 case 0x3c1:
b6343073 2645 index = s->ar_index & 0x1f;
e6e5ad80 2646 if (index < 21)
b6343073 2647 val = s->ar[index];
e6e5ad80
FB		 2648 else
2649 val = 0;
2650 break;
2651 case 0x3c2:
b6343073 2652 val = s->st00;
e6e5ad80
FB		 2653 break;
2654 case 0x3c4:
b6343073 2655 val = s->sr_index;
e6e5ad80
FB		 2656 break;
2657 case 0x3c5:
8a82c322
JQ		 2658 val = cirrus_vga_read_sr(c);
2659 break;
e6e5ad80 2660#ifdef DEBUG_VGA_REG
b6343073 2661 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2662#endif
2663 break;
2664 case 0x3c6:
957c9db5 2665 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2666 break;
2667 case 0x3c7:
b6343073 2668 val = s->dac_state;
e6e5ad80 2669 break;
ae184e4a 2670 case 0x3c8:
b6343073
JQ		 2671 val = s->dac_write_index;
2672 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2673 break;
2674 case 0x3c9:
5deaeee3
JQ		 2675 val = cirrus_vga_read_palette(c);
2676 break;
e6e5ad80 2677 case 0x3ca:
b6343073 2678 val = s->fcr;
e6e5ad80
FB		 2679 break;
2680 case 0x3cc:
b6343073 2681 val = s->msr;
e6e5ad80
FB		 2682 break;
2683 case 0x3ce:
b6343073 2684 val = s->gr_index;
e6e5ad80
FB		 2685 break;
2686 case 0x3cf:
f705db9d 2687 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2688#ifdef DEBUG_VGA_REG
b6343073 2689 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2690#endif
2691 break;
2692 case 0x3b4:
2693 case 0x3d4:
b6343073 2694 val = s->cr_index;
e6e5ad80
FB		 2695 break;
2696 case 0x3b5:
2697 case 0x3d5:
b863d514 2698 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2699#ifdef DEBUG_VGA_REG
b6343073 2700 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2701#endif
2702 break;
2703 case 0x3ba:
2704 case 0x3da:
2705 /* just toggle to fool polling */
b6343073
JQ		 2706 val = s->st01 = s->retrace(s);
2707 s->ar_flip_flop = 0;
e6e5ad80
FB		 2708 break;
2709 default:
2710 val = 0x00;
2711 break;
2712 }
2713 }
2714#if defined(DEBUG_VGA)
2715 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2716#endif
2717 return val;
2718}
2719
0ceac75b 2720static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e6e5ad80 2721{
b6343073
JQ		 2722 CirrusVGAState *c = opaque;
2723 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2724 int index;
2725
2726 /* check port range access depending on color/monochrome mode */
b6343073 2727 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2728 return;
25a18cbd 2729 }
e6e5ad80
FB		 2730#ifdef DEBUG_VGA
2731 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2732#endif
2733
2734 switch (addr) {
2735 case 0x3c0:
b6343073 2736 if (s->ar_flip_flop == 0) {
e6e5ad80 2737 val &= 0x3f;
b6343073 2738 s->ar_index = val;
e6e5ad80 2739 } else {
b6343073 2740 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2741 switch (index) {
2742 case 0x00 ... 0x0f:
b6343073 2743 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2744 break;
2745 case 0x10:
b6343073 2746 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2747 break;
2748 case 0x11:
b6343073 2749 s->ar[index] = val;
e6e5ad80
FB		 2750 break;
2751 case 0x12:
b6343073 2752 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2753 break;
2754 case 0x13:
b6343073 2755 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2756 break;
2757 case 0x14:
b6343073 2758 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2759 break;
2760 default:
2761 break;
2762 }
2763 }
b6343073 2764 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2765 break;
2766 case 0x3c2:
b6343073
JQ		 2767 s->msr = val & ~0x10;
2768 s->update_retrace_info(s);
e6e5ad80
FB		 2769 break;
2770 case 0x3c4:
b6343073 2771 s->sr_index = val;
e6e5ad80
FB		 2772 break;
2773 case 0x3c5:
e6e5ad80 2774#ifdef DEBUG_VGA_REG
b6343073 2775 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2776#endif
31c63201
JQ		 2777 cirrus_vga_write_sr(c, val);
2778 break;
e6e5ad80
FB		 2779 break;
2780 case 0x3c6:
b6343073 2781 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2782 break;
2783 case 0x3c7:
b6343073
JQ		 2784 s->dac_read_index = val;
2785 s->dac_sub_index = 0;
2786 s->dac_state = 3;
e6e5ad80
FB		 2787 break;
2788 case 0x3c8:
b6343073
JQ		 2789 s->dac_write_index = val;
2790 s->dac_sub_index = 0;
2791 s->dac_state = 0;
e6e5ad80
FB		 2792 break;
2793 case 0x3c9:
86948bb1
JQ		 2794 cirrus_vga_write_palette(c, val);
2795 break;
e6e5ad80 2796 case 0x3ce:
b6343073 2797 s->gr_index = val;
e6e5ad80
FB		 2798 break;
2799 case 0x3cf:
e6e5ad80 2800#ifdef DEBUG_VGA_REG
b6343073 2801 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2802#endif
22286bc6 2803 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2804 break;
2805 case 0x3b4:
2806 case 0x3d4:
b6343073 2807 s->cr_index = val;
e6e5ad80
FB		 2808 break;
2809 case 0x3b5:
2810 case 0x3d5:
e6e5ad80 2811#ifdef DEBUG_VGA_REG
b6343073 2812 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2813#endif
4ec1ce04 2814 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2815 break;
2816 case 0x3ba:
2817 case 0x3da:
b6343073 2818 s->fcr = val & 0x10;
e6e5ad80
FB		 2819 break;
2820 }
2821}
2822
e36f36e1
FB		 2823/***************************************
2824 *
2825 * memory-mapped I/O access
2826 *
2827 ***************************************/
2828
c227f099 2829static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
e36f36e1 2830{
e05587e8 2831 CirrusVGAState *s = opaque;
e36f36e1
FB		 2832
2833 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2834
2835 if (addr >= 0x100) {
2836 return cirrus_mmio_blt_read(s, addr - 0x100);
2837 } else {
0ceac75b 2838 return cirrus_vga_ioport_read(s, addr + 0x3c0);
e36f36e1
FB		 2839 }
2840}
2841
c227f099 2842static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
e36f36e1
FB		 2843{
2844 uint32_t v;
2845#ifdef TARGET_WORDS_BIGENDIAN
2846 v = cirrus_mmio_readb(opaque, addr) << 8;
2847 v |= cirrus_mmio_readb(opaque, addr + 1);
2848#else
2849 v = cirrus_mmio_readb(opaque, addr);
2850 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2851#endif
2852 return v;
2853}
2854
c227f099 2855static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
e36f36e1
FB		 2856{
2857 uint32_t v;
2858#ifdef TARGET_WORDS_BIGENDIAN
2859 v = cirrus_mmio_readb(opaque, addr) << 24;
2860 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2861 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2862 v |= cirrus_mmio_readb(opaque, addr + 3);
2863#else
2864 v = cirrus_mmio_readb(opaque, addr);
2865 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2866 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2867 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2868#endif
2869 return v;
2870}
2871
c227f099 2872static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2873 uint32_t val)
2874{
e05587e8 2875 CirrusVGAState *s = opaque;
e36f36e1
FB		 2876
2877 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2878
2879 if (addr >= 0x100) {
2880 cirrus_mmio_blt_write(s, addr - 0x100, val);
2881 } else {
0ceac75b 2882 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
e36f36e1
FB		 2883 }
2884}
2885
c227f099 2886static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2887 uint32_t val)
2888{
2889#ifdef TARGET_WORDS_BIGENDIAN
2890 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2891 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2892#else
2893 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2894 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2895#endif
2896}
2897
c227f099 2898static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2899 uint32_t val)
2900{
2901#ifdef TARGET_WORDS_BIGENDIAN
2902 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2903 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2904 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2905 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2906#else
2907 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2908 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2909 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2910 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2911#endif
2912}
2913
2914
d60efc6b 2915static CPUReadMemoryFunc * const cirrus_mmio_read[3] = {
e36f36e1
FB		 2916 cirrus_mmio_readb,
2917 cirrus_mmio_readw,
2918 cirrus_mmio_readl,
2919};
2920
d60efc6b 2921static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
e36f36e1
FB		 2922 cirrus_mmio_writeb,
2923 cirrus_mmio_writew,
2924 cirrus_mmio_writel,
2925};
2926
2c6ab832
FB		 2927/* load/save state */
2928
e59fb374 2929static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2930{
2931 CirrusVGAState *s = opaque;
2932
4e12cd94
AK		 2933 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2934 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2935
2bec46dc 2936 cirrus_update_memory_access(s);
2c6ab832 2937 /* force refresh */
4e12cd94 2938 s->vga.graphic_mode = -1;
2c6ab832
FB		 2939 cirrus_update_bank_ptr(s, 0);
2940 cirrus_update_bank_ptr(s, 1);
2941 return 0;
2942}
2943
7e72abc3
JQ		 2944static const VMStateDescription vmstate_cirrus_vga = {
2945 .name = "cirrus_vga",
2946 .version_id = 2,
2947 .minimum_version_id = 1,
2948 .minimum_version_id_old = 1,
2949 .post_load = cirrus_post_load,
2950 .fields = (VMStateField []) {
2951 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2952 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2953 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2954 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2955 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2956 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2957 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2958 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2959 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2960 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2961 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2962 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2963 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2964 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2965 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2966 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2967 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2968 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2969 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2970 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2971 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2972 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2973 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2974 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2975 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2976 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2977 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2978 /* XXX: we do not save the bitblt state - we assume we do not save
2979 the state when the blitter is active */
2980 VMSTATE_END_OF_LIST()
4f335feb 2981 }
7e72abc3 2982};
4f335feb 2983
7e72abc3
JQ		 2984static const VMStateDescription vmstate_pci_cirrus_vga = {
2985 .name = "cirrus_vga",
2986 .version_id = 2,
2987 .minimum_version_id = 2,
2988 .minimum_version_id_old = 2,
7e72abc3
JQ		 2989 .fields = (VMStateField []) {
2990 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2991 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2992 vmstate_cirrus_vga, CirrusVGAState),
2993 VMSTATE_END_OF_LIST()
2994 }
2995};
4f335feb 2996
e6e5ad80
FB		 2997/***************************************
2998 *
2999 * initialize
3000 *
3001 ***************************************/
3002
4abc796d 3003static void cirrus_reset(void *opaque)
e6e5ad80 3004{
4abc796d 3005 CirrusVGAState *s = opaque;
e6e5ad80 3006
03a3e7ba 3007 vga_common_reset(&s->vga);
ee50c6bc 3008 unmap_linear_vram(s);
4e12cd94 3009 s->vga.sr[0x06] = 0x0f;
4abc796d 3010 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 3011 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 3012 s->vga.sr[0x1F] = 0x2d; // MemClock
3013 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
3014 s->vga.sr[0x0f] = 0x98;
3015 s->vga.sr[0x17] = 0x20;
3016 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 3017 } else {
4e12cd94
AK		 3018 s->vga.sr[0x1F] = 0x22; // MemClock
3019 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
3020 s->vga.sr[0x17] = s->bustype;
3021 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 3022 }
4e12cd94 3023 s->vga.cr[0x27] = s->device_id;
e6e5ad80 3024
78e127ef
FB		 3025 /* Win2K seems to assume that the pattern buffer is at 0xff
3026 initially ! */
4e12cd94 3027 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
78e127ef 3028
e6e5ad80
FB		 3029 s->cirrus_hidden_dac_lockindex = 5;
3030 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 3031}
3032
3033static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3034{
3035 int i;
3036 static int inited;
3037
3038 if (!inited) {
3039 inited = 1;
3040 for(i = 0;i < 256; i++)
3041 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3042 rop_to_index[CIRRUS_ROP_0] = 0;
3043 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3044 rop_to_index[CIRRUS_ROP_NOP] = 2;
3045 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3046 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3047 rop_to_index[CIRRUS_ROP_SRC] = 5;
3048 rop_to_index[CIRRUS_ROP_1] = 6;
3049 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3050 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3051 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3052 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3053 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3054 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3055 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3056 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3057 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3058 s->device_id = device_id;
3059 if (is_pci)
3060 s->bustype = CIRRUS_BUSTYPE_PCI;
3061 else
3062 s->bustype = CIRRUS_BUSTYPE_ISA;
3063 }
3064
0ceac75b 3065 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
4abc796d 3066
0ceac75b
JQ		 3067 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
3068 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
3069 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
3070 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
4abc796d 3071
0ceac75b 3072 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
4abc796d 3073
0ceac75b
JQ		 3074 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
3075 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
3076 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
3077 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
4abc796d 3078
1eed09cb 3079 s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
2507c12a
AG		 3080 cirrus_vga_mem_write, s,
3081 DEVICE_NATIVE_ENDIAN);
4abc796d 3082 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
4e12cd94 3083 s->vga.vga_io_memory);
4abc796d 3084 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2c6ab832 3085
fefe54e3
AL		 3086 /* I/O handler for LFB */
3087 s->cirrus_linear_io_addr =
2507c12a
AG		 3088 cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s,
3089 DEVICE_NATIVE_ENDIAN);
fefe54e3
AL		 3090
3091 /* I/O handler for LFB */
3092 s->cirrus_linear_bitblt_io_addr =
1eed09cb 3093 cpu_register_io_memory(cirrus_linear_bitblt_read,
2507c12a
AG		 3094 cirrus_linear_bitblt_write, s,
3095 DEVICE_NATIVE_ENDIAN);
fefe54e3
AL		 3096
3097 /* I/O handler for memory-mapped I/O */
3098 s->cirrus_mmio_io_addr =
2507c12a
AG		 3099 cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s,
3100 DEVICE_NATIVE_ENDIAN);
fefe54e3
AL		 3101
3102 s->real_vram_size =
3103 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3104
4e12cd94 3105 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 3106 s->cirrus_addr_mask = s->real_vram_size - 1;
3107 s->linear_mmio_mask = s->real_vram_size - 256;
3108
4e12cd94
AK		 3109 s->vga.get_bpp = cirrus_get_bpp;
3110 s->vga.get_offsets = cirrus_get_offsets;
3111 s->vga.get_resolution = cirrus_get_resolution;
3112 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3113 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 3114
a08d4367 3115 qemu_register_reset(cirrus_reset, s);
4abc796d 3116 cirrus_reset(s);
e6e5ad80
FB		 3117}
3118
3119/***************************************
3120 *
3121 * ISA bus support
3122 *
3123 ***************************************/
3124
fbe1b595 3125void isa_cirrus_vga_init(void)
e6e5ad80
FB		 3126{
3127 CirrusVGAState *s;
3128
3129 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 3130
fbe1b595 3131 vga_common_init(&s->vga, VGA_RAM_SIZE);
78e127ef 3132 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
4e12cd94
AK		 3133 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3134 s->vga.screen_dump, s->vga.text_update,
3135 &s->vga);
0be71e32 3136 vmstate_register(NULL, 0, &vmstate_cirrus_vga, s);
5245d57a 3137 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80
FB		 3138 /* XXX ISA-LFB support */
3139}
3140
3141/***************************************
3142 *
3143 * PCI bus support
3144 *
3145 ***************************************/
3146
3147static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
6e355d90 3148 pcibus_t addr, pcibus_t size, int type)
e6e5ad80 3149{
f3566bf9 3150 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
e6e5ad80 3151
a5082316 3152 /* XXX: add byte swapping apertures */
4e12cd94 3153 cpu_register_physical_memory(addr, s->vga.vram_size,
e6e5ad80 3154 s->cirrus_linear_io_addr);
a5082316
FB		 3155 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3156 s->cirrus_linear_bitblt_io_addr);
2bec46dc 3157
4e12cd94
AK		 3158 s->vga.map_addr = s->vga.map_end = 0;
3159 s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3160 s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
2bec46dc 3161 /* account for overflow */
4e12cd94
AK		 3162 if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
3163 s->vga.lfb_end = addr + VGA_RAM_SIZE;
ba7349cd 3164
4e12cd94 3165 vga_dirty_log_start(&s->vga);
e6e5ad80
FB		 3166}
3167
3168static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
6e355d90 3169 pcibus_t addr, pcibus_t size, int type)
e6e5ad80 3170{
f3566bf9 3171 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
e6e5ad80
FB		 3172
3173 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3174 s->cirrus_mmio_io_addr);
3175}
3176
ba7349cd
AL		 3177static void pci_cirrus_write_config(PCIDevice *d,
3178 uint32_t address, uint32_t val, int len)
3179{
f3566bf9 3180 PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d);
ba7349cd
AL		 3181 CirrusVGAState *s = &pvs->cirrus_vga;
3182
ba7349cd 3183 pci_default_write_config(d, address, val, len);
182f9c8a 3184 if (s->vga.map_addr && d->io_regions[0].addr == PCI_BAR_UNMAPPED)
4e12cd94 3185 s->vga.map_addr = 0;
ba7349cd 3186 cirrus_update_memory_access(s);
ba7349cd
AL		 3187}
3188
81a322d4 3189static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 3190{
3191 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
3192 CirrusVGAState *s = &d->cirrus_vga;
3193 uint8_t *pci_conf = d->dev.config;
3194 int device_id = CIRRUS_ID_CLGD5446;
3195
3196 /* setup VGA */
3197 vga_common_init(&s->vga, VGA_RAM_SIZE);
3198 cirrus_init_common(s, device_id, 1);
a414c306
GH		 3199 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3200 s->vga.screen_dump, s->vga.text_update,
3201 &s->vga);
3202
3203 /* setup PCI */
3204 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3205 pci_config_set_device_id(pci_conf, device_id);
a414c306 3206 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
a414c306
GH		 3207
3208 /* setup memory space */
3209 /* memory #0 LFB */
3210 /* memory #1 memory-mapped I/O */
3211 /* XXX: s->vga.vram_size must be a power of two */
b90c73cf 3212 pci_register_bar(&d->dev, 0, 0x2000000,
0392a017 3213 PCI_BASE_ADDRESS_MEM_PREFETCH, cirrus_pci_lfb_map);
a414c306 3214 if (device_id == CIRRUS_ID_CLGD5446) {
b90c73cf 3215 pci_register_bar(&d->dev, 1, CIRRUS_PNPMMIO_SIZE,
0392a017 3216 PCI_BASE_ADDRESS_SPACE_MEMORY, cirrus_pci_mmio_map);
a414c306 3217 }
81a322d4 3218 return 0;
a414c306
GH		 3219}
3220
fbe1b595 3221void pci_cirrus_vga_init(PCIBus *bus)
e6e5ad80 3222{
556cd098 3223 pci_create_simple(bus, -1, "cirrus-vga");
a414c306 3224}
d34cab9f 3225
a414c306 3226static PCIDeviceInfo cirrus_vga_info = {
556cd098
MA		 3227 .qdev.name = "cirrus-vga",
3228 .qdev.desc = "Cirrus CLGD 54xx VGA",
a414c306 3229 .qdev.size = sizeof(PCICirrusVGAState),
be73cfe2 3230 .qdev.vmsd = &vmstate_pci_cirrus_vga,
a414c306 3231 .init = pci_cirrus_vga_initfn,
8c52c8f3 3232 .romfile = VGABIOS_CIRRUS_FILENAME,
a414c306
GH		 3233 .config_write = pci_cirrus_write_config,
3234};
e6e5ad80 3235
a414c306
GH		 3236static void cirrus_vga_register(void)
3237{
3238 pci_qdev_register(&cirrus_vga_info);
e6e5ad80 3239}
a414c306 3240device_init(cirrus_vga_register);
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