]> Git Repo - qemu.git/blame - hw/sparc/sun4m.c
fw_cfg: factor out initialization of FW_CFG_ID (rev. number)
[qemu.git] / hw / sparc / sun4m.c
CommitLineData
420557e8 1/*
ee76f82e 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
5fafdf24 3 *
b81b3b10 4 * Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24 5 *
420557e8
FB
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
83c9f4ca 24#include "hw/sysbus.h"
af87bf29 25#include "qemu/error-report.h"
1de7afc9 26#include "qemu/timer.h"
0d09e41a
PB
27#include "hw/sparc/sun4m.h"
28#include "hw/timer/m48t59.h"
29#include "hw/sparc/sparc32_dma.h"
30#include "hw/block/fdc.h"
9c17d615 31#include "sysemu/sysemu.h"
1422e32d 32#include "net/net.h"
83c9f4ca 33#include "hw/boards.h"
ec0503b4 34#include "hw/nvram/openbios_firmware_abi.h"
0d09e41a
PB
35#include "hw/scsi/esp.h"
36#include "hw/i386/pc.h"
37#include "hw/isa/isa.h"
38#include "hw/nvram/fw_cfg.h"
39#include "hw/char/escc.h"
83c9f4ca 40#include "hw/empty_slot.h"
83c9f4ca 41#include "hw/loader.h"
ca20cf32 42#include "elf.h"
4be74634 43#include "sysemu/block-backend.h"
97bf4851 44#include "trace.h"
420557e8 45
36cd9210
BS
46/*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
77f193da
BS
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
36cd9210
BS
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * See for example: http://www.sunhelp.org/faq/sunref1.html
60 */
61
420557e8 62#define KERNEL_LOAD_ADDR 0x00004000
b6f479d3 63#define CMDLINE_ADDR 0x007ff000
713c45fa 64#define INITRD_LOAD_ADDR 0x00800000
a7227727 65#define PROM_SIZE_MAX (1024 * 1024)
40ce0a9a 66#define PROM_VADDR 0xffd00000
f930d07e 67#define PROM_FILENAME "openbios-sparc32"
3cce6243 68#define CFG_ADDR 0xd00000510ULL
fbfcf955 69#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
b96919e0
MCA
70#define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
71#define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
b8174937 72
ba3c64fb 73#define MAX_CPUS 16
b3a23197 74#define MAX_PILS 16
9a62fb24 75#define MAX_VSIMMS 4
420557e8 76
b4ed08e0
BS
77#define ESCC_CLOCK 4915200
78
8137cde8 79struct sun4m_hwdef {
a8170e5e
AK
80 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
81 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
82 hwaddr serial_base, fd_base;
83 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
84 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
85 hwaddr bpp_base, dbri_base, sx_base;
9a62fb24 86 struct {
a8170e5e 87 hwaddr reg_base, vram_base;
9a62fb24 88 } vsimm[MAX_VSIMMS];
a8170e5e 89 hwaddr ecc_base;
3ebf5aaf
BS
90 uint64_t max_mem;
91 const char * const default_cpu_model;
61999750
BS
92 uint32_t ecc_version;
93 uint32_t iommu_version;
94 uint16_t machine_id;
95 uint8_t nvram_machine_id;
36cd9210
BS
96};
97
6f7e9aec
FB
98int DMA_get_channel_mode (int nchan)
99{
100 return 0;
101}
102int DMA_read_memory (int nchan, void *buf, int pos, int size)
103{
104 return 0;
105}
106int DMA_write_memory (int nchan, void *buf, int pos, int size)
107{
108 return 0;
109}
110void DMA_hold_DREQ (int nchan) {}
111void DMA_release_DREQ (int nchan) {}
112void DMA_schedule(int nchan) {}
4556bd8b
BS
113
114void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
115{
116}
117
6f7e9aec
FB
118void DMA_register_channel (int nchan,
119 DMA_transfer_handler transfer_handler,
120 void *opaque)
121{
122}
123
ddcd5531
GA
124static void fw_cfg_boot_set(void *opaque, const char *boot_device,
125 Error **errp)
81864572 126{
513f789f 127 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
81864572
BS
128}
129
31688246 130static void nvram_init(Nvram *nvram, uint8_t *macaddr,
43a34704
BS
131 const char *cmdline, const char *boot_devices,
132 ram_addr_t RAM_size, uint32_t kernel_size,
f930d07e 133 int width, int height, int depth,
905fdcb5 134 int nvram_machine_id, const char *arch)
e80cfcfc 135{
d2c63fc1 136 unsigned int i;
66508601 137 uint32_t start, end;
d2c63fc1 138 uint8_t image[0x1ff0];
d2c63fc1 139 struct OpenBIOS_nvpart_v1 *part_header;
31688246 140 NvramClass *k = NVRAM_GET_CLASS(nvram);
d2c63fc1
BS
141
142 memset(image, '\0', sizeof(image));
e80cfcfc 143
513f789f 144 start = 0;
b6f479d3 145
66508601
BS
146 // OpenBIOS nvram variables
147 // Variable partition
d2c63fc1
BS
148 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
149 part_header->signature = OPENBIOS_PART_SYSTEM;
363a37d5 150 pstrcpy(part_header->name, sizeof(part_header->name), "system");
66508601 151
d2c63fc1 152 end = start + sizeof(struct OpenBIOS_nvpart_v1);
66508601 153 for (i = 0; i < nb_prom_envs; i++)
d2c63fc1
BS
154 end = OpenBIOS_set_var(image, end, prom_envs[i]);
155
156 // End marker
157 image[end++] = '\0';
66508601 158
66508601 159 end = start + ((end - start + 15) & ~15);
d2c63fc1 160 OpenBIOS_finish_partition(part_header, end - start);
66508601
BS
161
162 // free partition
163 start = end;
d2c63fc1
BS
164 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
165 part_header->signature = OPENBIOS_PART_FREE;
363a37d5 166 pstrcpy(part_header->name, sizeof(part_header->name), "free");
66508601
BS
167
168 end = 0x1fd0;
d2c63fc1
BS
169 OpenBIOS_finish_partition(part_header, end - start);
170
905fdcb5
BS
171 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
172 nvram_machine_id);
d2c63fc1 173
31688246
HP
174 for (i = 0; i < sizeof(image); i++) {
175 (k->write)(nvram, i, image[i]);
176 }
e80cfcfc
FB
177}
178
d453c2c3 179static DeviceState *slavio_intctl;
e80cfcfc 180
1ce6be24 181void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict)
e80cfcfc 182{
7d85892b 183 if (slavio_intctl)
376253ec 184 slavio_pic_info(mon, slavio_intctl);
e80cfcfc
FB
185}
186
1ce6be24 187void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict)
e80cfcfc 188{
7d85892b 189 if (slavio_intctl)
376253ec 190 slavio_irq_info(mon, slavio_intctl);
e80cfcfc
FB
191}
192
98cec4a2 193void cpu_check_irqs(CPUSPARCState *env)
327ac2e7 194{
d8ed887b
AF
195 CPUState *cs;
196
327ac2e7
BS
197 if (env->pil_in && (env->interrupt_index == 0 ||
198 (env->interrupt_index & ~15) == TT_EXTINT)) {
199 unsigned int i;
200
201 for (i = 15; i > 0; i--) {
202 if (env->pil_in & (1 << i)) {
203 int old_interrupt = env->interrupt_index;
204
205 env->interrupt_index = TT_EXTINT | i;
f32d7ec5 206 if (old_interrupt != env->interrupt_index) {
c3affe56 207 cs = CPU(sparc_env_get_cpu(env));
97bf4851 208 trace_sun4m_cpu_interrupt(i);
c3affe56 209 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
f32d7ec5 210 }
327ac2e7
BS
211 break;
212 }
213 }
214 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
d8ed887b 215 cs = CPU(sparc_env_get_cpu(env));
97bf4851 216 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
327ac2e7 217 env->interrupt_index = 0;
d8ed887b 218 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
327ac2e7
BS
219 }
220}
221
38c66cf2 222static void cpu_kick_irq(SPARCCPU *cpu)
94ad5b00 223{
38c66cf2 224 CPUSPARCState *env = &cpu->env;
259186a7 225 CPUState *cs = CPU(cpu);
38c66cf2 226
259186a7 227 cs->halted = 0;
94ad5b00 228 cpu_check_irqs(env);
259186a7 229 qemu_cpu_kick(cs);
94ad5b00
PB
230}
231
b3a23197
BS
232static void cpu_set_irq(void *opaque, int irq, int level)
233{
e0bbf9b5
AF
234 SPARCCPU *cpu = opaque;
235 CPUSPARCState *env = &cpu->env;
b3a23197
BS
236
237 if (level) {
97bf4851 238 trace_sun4m_cpu_set_irq_raise(irq);
327ac2e7 239 env->pil_in |= 1 << irq;
38c66cf2 240 cpu_kick_irq(cpu);
b3a23197 241 } else {
97bf4851 242 trace_sun4m_cpu_set_irq_lower(irq);
327ac2e7
BS
243 env->pil_in &= ~(1 << irq);
244 cpu_check_irqs(env);
b3a23197
BS
245 }
246}
247
248static void dummy_cpu_set_irq(void *opaque, int irq, int level)
249{
250}
251
c68ea704
FB
252static void main_cpu_reset(void *opaque)
253{
5414dec6 254 SPARCCPU *cpu = opaque;
259186a7 255 CPUState *cs = CPU(cpu);
3d29fbef 256
259186a7
AF
257 cpu_reset(cs);
258 cs->halted = 0;
3d29fbef
BS
259}
260
261static void secondary_cpu_reset(void *opaque)
262{
5414dec6 263 SPARCCPU *cpu = opaque;
259186a7 264 CPUState *cs = CPU(cpu);
3d29fbef 265
259186a7
AF
266 cpu_reset(cs);
267 cs->halted = 1;
c68ea704
FB
268}
269
6d0c293d
BS
270static void cpu_halt_signal(void *opaque, int irq, int level)
271{
4917cf44
AF
272 if (level && current_cpu) {
273 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
c3affe56 274 }
6d0c293d
BS
275}
276
409dbce5
AJ
277static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
278{
279 return addr - 0xf0000000ULL;
280}
281
3ebf5aaf 282static unsigned long sun4m_load_kernel(const char *kernel_filename,
293f78bc 283 const char *initrd_filename,
c227f099 284 ram_addr_t RAM_size)
3ebf5aaf
BS
285{
286 int linux_boot;
287 unsigned int i;
288 long initrd_size, kernel_size;
3c178e72 289 uint8_t *ptr;
3ebf5aaf
BS
290
291 linux_boot = (kernel_filename != NULL);
292
293 kernel_size = 0;
294 if (linux_boot) {
ca20cf32
BS
295 int bswap_needed;
296
297#ifdef BSWAP_NEEDED
298 bswap_needed = 1;
299#else
300 bswap_needed = 0;
301#endif
409dbce5
AJ
302 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
303 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
3ebf5aaf 304 if (kernel_size < 0)
293f78bc 305 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
ca20cf32
BS
306 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
307 TARGET_PAGE_SIZE);
3ebf5aaf 308 if (kernel_size < 0)
293f78bc
BS
309 kernel_size = load_image_targphys(kernel_filename,
310 KERNEL_LOAD_ADDR,
311 RAM_size - KERNEL_LOAD_ADDR);
3ebf5aaf
BS
312 if (kernel_size < 0) {
313 fprintf(stderr, "qemu: could not load kernel '%s'\n",
314 kernel_filename);
315 exit(1);
316 }
317
318 /* load initrd */
319 initrd_size = 0;
320 if (initrd_filename) {
293f78bc
BS
321 initrd_size = load_image_targphys(initrd_filename,
322 INITRD_LOAD_ADDR,
323 RAM_size - INITRD_LOAD_ADDR);
3ebf5aaf
BS
324 if (initrd_size < 0) {
325 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
326 initrd_filename);
327 exit(1);
328 }
329 }
330 if (initrd_size > 0) {
331 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
3c178e72
GH
332 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
333 if (ldl_p(ptr) == 0x48647253) { // HdrS
334 stl_p(ptr + 16, INITRD_LOAD_ADDR);
335 stl_p(ptr + 20, initrd_size);
3ebf5aaf
BS
336 break;
337 }
338 }
339 }
340 }
341 return kernel_size;
342}
343
a8170e5e 344static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
4b48bf05
BS
345{
346 DeviceState *dev;
347 SysBusDevice *s;
348
349 dev = qdev_create(NULL, "iommu");
350 qdev_prop_set_uint32(dev, "version", version);
e23a1b33 351 qdev_init_nofail(dev);
1356b98d 352 s = SYS_BUS_DEVICE(dev);
4b48bf05
BS
353 sysbus_connect_irq(s, 0, irq);
354 sysbus_mmio_map(s, 0, addr);
355
356 return s;
357}
358
a8170e5e 359static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
86d1c388 360 void *iommu, qemu_irq *dev_irq, int is_ledma)
74ff8d90
BS
361{
362 DeviceState *dev;
363 SysBusDevice *s;
364
365 dev = qdev_create(NULL, "sparc32_dma");
366 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
86d1c388 367 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
e23a1b33 368 qdev_init_nofail(dev);
1356b98d 369 s = SYS_BUS_DEVICE(dev);
74ff8d90
BS
370 sysbus_connect_irq(s, 0, parent_irq);
371 *dev_irq = qdev_get_gpio_in(dev, 0);
372 sysbus_mmio_map(s, 0, daddr);
373
374 return s;
375}
376
a8170e5e 377static void lance_init(NICInfo *nd, hwaddr leaddr,
74ff8d90 378 void *dma_opaque, qemu_irq irq)
9d07d757
PB
379{
380 DeviceState *dev;
381 SysBusDevice *s;
74ff8d90 382 qemu_irq reset;
9d07d757
PB
383
384 qemu_check_nic_model(&nd_table[0], "lance");
385
386 dev = qdev_create(NULL, "lance");
76224833 387 qdev_set_nic_properties(dev, nd);
daa65491 388 qdev_prop_set_ptr(dev, "dma", dma_opaque);
e23a1b33 389 qdev_init_nofail(dev);
1356b98d 390 s = SYS_BUS_DEVICE(dev);
9d07d757
PB
391 sysbus_mmio_map(s, 0, leaddr);
392 sysbus_connect_irq(s, 0, irq);
74ff8d90
BS
393 reset = qdev_get_gpio_in(dev, 0);
394 qdev_connect_gpio_out(dma_opaque, 0, reset);
9d07d757
PB
395}
396
a8170e5e
AK
397static DeviceState *slavio_intctl_init(hwaddr addr,
398 hwaddr addrg,
462eda24 399 qemu_irq **parent_irq)
4b48bf05
BS
400{
401 DeviceState *dev;
402 SysBusDevice *s;
403 unsigned int i, j;
404
405 dev = qdev_create(NULL, "slavio_intctl");
e23a1b33 406 qdev_init_nofail(dev);
4b48bf05 407
1356b98d 408 s = SYS_BUS_DEVICE(dev);
4b48bf05
BS
409
410 for (i = 0; i < MAX_CPUS; i++) {
411 for (j = 0; j < MAX_PILS; j++) {
412 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
413 }
414 }
415 sysbus_mmio_map(s, 0, addrg);
416 for (i = 0; i < MAX_CPUS; i++) {
417 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
418 }
419
420 return dev;
421}
422
423#define SYS_TIMER_OFFSET 0x10000ULL
424#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
425
a8170e5e 426static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
4b48bf05
BS
427 qemu_irq *cpu_irqs, unsigned int num_cpus)
428{
429 DeviceState *dev;
430 SysBusDevice *s;
431 unsigned int i;
432
433 dev = qdev_create(NULL, "slavio_timer");
434 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
e23a1b33 435 qdev_init_nofail(dev);
1356b98d 436 s = SYS_BUS_DEVICE(dev);
4b48bf05
BS
437 sysbus_connect_irq(s, 0, master_irq);
438 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
439
440 for (i = 0; i < MAX_CPUS; i++) {
a8170e5e 441 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
4b48bf05
BS
442 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
443 }
444}
445
bea42280
IM
446static qemu_irq slavio_system_powerdown;
447
448static void slavio_powerdown_req(Notifier *n, void *opaque)
449{
450 qemu_irq_raise(slavio_system_powerdown);
451}
452
453static Notifier slavio_system_powerdown_notifier = {
454 .notify = slavio_powerdown_req
455};
456
4b48bf05
BS
457#define MISC_LEDS 0x01600000
458#define MISC_CFG 0x01800000
459#define MISC_DIAG 0x01a00000
460#define MISC_MDM 0x01b00000
461#define MISC_SYS 0x01f00000
462
a8170e5e
AK
463static void slavio_misc_init(hwaddr base,
464 hwaddr aux1_base,
465 hwaddr aux2_base, qemu_irq irq,
b2b6f6ec 466 qemu_irq fdc_tc)
4b48bf05
BS
467{
468 DeviceState *dev;
469 SysBusDevice *s;
470
471 dev = qdev_create(NULL, "slavio_misc");
e23a1b33 472 qdev_init_nofail(dev);
1356b98d 473 s = SYS_BUS_DEVICE(dev);
4b48bf05
BS
474 if (base) {
475 /* 8 bit registers */
476 /* Slavio control */
477 sysbus_mmio_map(s, 0, base + MISC_CFG);
478 /* Diagnostics */
479 sysbus_mmio_map(s, 1, base + MISC_DIAG);
480 /* Modem control */
481 sysbus_mmio_map(s, 2, base + MISC_MDM);
482 /* 16 bit registers */
483 /* ss600mp diag LEDs */
484 sysbus_mmio_map(s, 3, base + MISC_LEDS);
485 /* 32 bit registers */
486 /* System control */
487 sysbus_mmio_map(s, 4, base + MISC_SYS);
488 }
489 if (aux1_base) {
490 /* AUX 1 (Misc System Functions) */
491 sysbus_mmio_map(s, 5, aux1_base);
492 }
493 if (aux2_base) {
494 /* AUX 2 (Software Powerdown Control) */
495 sysbus_mmio_map(s, 6, aux2_base);
496 }
497 sysbus_connect_irq(s, 0, irq);
498 sysbus_connect_irq(s, 1, fdc_tc);
bea42280
IM
499 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
500 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
4b48bf05
BS
501}
502
a8170e5e 503static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
4b48bf05
BS
504{
505 DeviceState *dev;
506 SysBusDevice *s;
507
508 dev = qdev_create(NULL, "eccmemctl");
509 qdev_prop_set_uint32(dev, "version", version);
e23a1b33 510 qdev_init_nofail(dev);
1356b98d 511 s = SYS_BUS_DEVICE(dev);
4b48bf05
BS
512 sysbus_connect_irq(s, 0, irq);
513 sysbus_mmio_map(s, 0, base);
514 if (version == 0) { // SS-600MP only
515 sysbus_mmio_map(s, 1, base + 0x1000);
516 }
517}
518
a8170e5e 519static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
4b48bf05
BS
520{
521 DeviceState *dev;
522 SysBusDevice *s;
523
524 dev = qdev_create(NULL, "apc");
e23a1b33 525 qdev_init_nofail(dev);
1356b98d 526 s = SYS_BUS_DEVICE(dev);
4b48bf05
BS
527 /* Power management (APC) XXX: not a Slavio device */
528 sysbus_mmio_map(s, 0, power_base);
529 sysbus_connect_irq(s, 0, cpu_halt);
530}
531
55d7bfe2 532static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
4b48bf05
BS
533 int height, int depth)
534{
535 DeviceState *dev;
536 SysBusDevice *s;
537
538 dev = qdev_create(NULL, "SUNW,tcx");
4b48bf05
BS
539 qdev_prop_set_uint32(dev, "vram_size", vram_size);
540 qdev_prop_set_uint16(dev, "width", width);
541 qdev_prop_set_uint16(dev, "height", height);
542 qdev_prop_set_uint16(dev, "depth", depth);
da87dd7b 543 qdev_prop_set_uint64(dev, "prom_addr", addr);
e23a1b33 544 qdev_init_nofail(dev);
1356b98d 545 s = SYS_BUS_DEVICE(dev);
55d7bfe2
MCA
546
547 /* 10/ROM : FCode ROM */
da87dd7b 548 sysbus_mmio_map(s, 0, addr);
55d7bfe2
MCA
549 /* 2/STIP : Stipple */
550 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
551 /* 3/BLIT : Blitter */
552 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
553 /* 5/RSTIP : Raw Stipple */
554 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
555 /* 6/RBLIT : Raw Blitter */
556 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
557 /* 7/TEC : Transform Engine */
558 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
559 /* 8/CMAP : DAC */
560 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
561 /* 9/THC : */
562 if (depth == 8) {
563 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
4b48bf05 564 } else {
55d7bfe2 565 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
4b48bf05 566 }
55d7bfe2
MCA
567 /* 11/DHC : */
568 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
569 /* 12/ALT : */
570 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
571 /* 0/DFB8 : 8-bit plane */
572 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
573 /* 1/DFB24 : 24bit plane */
574 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
575 /* 4/RDFB32: Raw framebuffer. Control plane */
576 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
577 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
578 if (depth == 8) {
579 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
580 }
581
582 sysbus_connect_irq(s, 0, irq);
4b48bf05
BS
583}
584
af87bf29
MCA
585static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
586 int height, int depth)
587{
588 DeviceState *dev;
589 SysBusDevice *s;
590
591 dev = qdev_create(NULL, "cgthree");
592 qdev_prop_set_uint32(dev, "vram-size", vram_size);
593 qdev_prop_set_uint16(dev, "width", width);
594 qdev_prop_set_uint16(dev, "height", height);
595 qdev_prop_set_uint16(dev, "depth", depth);
596 qdev_prop_set_uint64(dev, "prom-addr", addr);
597 qdev_init_nofail(dev);
598 s = SYS_BUS_DEVICE(dev);
599
600 /* FCode ROM */
601 sysbus_mmio_map(s, 0, addr);
602 /* DAC */
603 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
604 /* 8-bit plane */
605 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
606
607 sysbus_connect_irq(s, 0, irq);
608}
609
325f2747 610/* NCR89C100/MACIO Internal ID register */
ef9dfa4c
AF
611
612#define TYPE_MACIO_ID_REGISTER "macio_idreg"
613
325f2747
BS
614static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
615
a8170e5e 616static void idreg_init(hwaddr addr)
325f2747
BS
617{
618 DeviceState *dev;
619 SysBusDevice *s;
620
ef9dfa4c 621 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
e23a1b33 622 qdev_init_nofail(dev);
1356b98d 623 s = SYS_BUS_DEVICE(dev);
325f2747
BS
624
625 sysbus_mmio_map(s, 0, addr);
2a221651
EI
626 cpu_physical_memory_write_rom(&address_space_memory,
627 addr, idreg_data, sizeof(idreg_data));
325f2747
BS
628}
629
ef9dfa4c
AF
630#define MACIO_ID_REGISTER(obj) \
631 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
632
3150fa50 633typedef struct IDRegState {
ef9dfa4c
AF
634 SysBusDevice parent_obj;
635
3150fa50
AK
636 MemoryRegion mem;
637} IDRegState;
638
81a322d4 639static int idreg_init1(SysBusDevice *dev)
325f2747 640{
ef9dfa4c 641 IDRegState *s = MACIO_ID_REGISTER(dev);
325f2747 642
29776739 643 memory_region_init_ram(&s->mem, OBJECT(s),
49946538 644 "sun4m.idreg", sizeof(idreg_data), &error_abort);
c5705a77 645 vmstate_register_ram_global(&s->mem);
3150fa50 646 memory_region_set_readonly(&s->mem, true);
750ecd44 647 sysbus_init_mmio(dev, &s->mem);
81a322d4 648 return 0;
325f2747
BS
649}
650
999e12bb
AL
651static void idreg_class_init(ObjectClass *klass, void *data)
652{
653 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
654
655 k->init = idreg_init1;
656}
657
8c43a6f0 658static const TypeInfo idreg_info = {
ef9dfa4c 659 .name = TYPE_MACIO_ID_REGISTER,
39bffca2
AL
660 .parent = TYPE_SYS_BUS_DEVICE,
661 .instance_size = sizeof(IDRegState),
662 .class_init = idreg_class_init,
325f2747
BS
663};
664
b3a49965
AF
665#define TYPE_TCX_AFX "tcx_afx"
666#define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
667
3150fa50 668typedef struct AFXState {
b3a49965
AF
669 SysBusDevice parent_obj;
670
3150fa50
AK
671 MemoryRegion mem;
672} AFXState;
673
c5de386a 674/* SS-5 TCX AFX register */
a8170e5e 675static void afx_init(hwaddr addr)
c5de386a
AT
676{
677 DeviceState *dev;
678 SysBusDevice *s;
679
b3a49965 680 dev = qdev_create(NULL, TYPE_TCX_AFX);
c5de386a 681 qdev_init_nofail(dev);
1356b98d 682 s = SYS_BUS_DEVICE(dev);
c5de386a
AT
683
684 sysbus_mmio_map(s, 0, addr);
685}
686
687static int afx_init1(SysBusDevice *dev)
688{
b3a49965 689 AFXState *s = TCX_AFX(dev);
c5de386a 690
49946538 691 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_abort);
c5705a77 692 vmstate_register_ram_global(&s->mem);
750ecd44 693 sysbus_init_mmio(dev, &s->mem);
c5de386a
AT
694 return 0;
695}
696
999e12bb
AL
697static void afx_class_init(ObjectClass *klass, void *data)
698{
699 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
700
701 k->init = afx_init1;
702}
703
8c43a6f0 704static const TypeInfo afx_info = {
b3a49965 705 .name = TYPE_TCX_AFX,
39bffca2
AL
706 .parent = TYPE_SYS_BUS_DEVICE,
707 .instance_size = sizeof(AFXState),
708 .class_init = afx_class_init,
c5de386a
AT
709};
710
e6f54c91
AF
711#define TYPE_OPENPROM "openprom"
712#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
713
3150fa50 714typedef struct PROMState {
e6f54c91
AF
715 SysBusDevice parent_obj;
716
3150fa50
AK
717 MemoryRegion prom;
718} PROMState;
719
f48f6569 720/* Boot PROM (OpenBIOS) */
409dbce5
AJ
721static uint64_t translate_prom_address(void *opaque, uint64_t addr)
722{
a8170e5e 723 hwaddr *base_addr = (hwaddr *)opaque;
409dbce5
AJ
724 return addr + *base_addr - PROM_VADDR;
725}
726
a8170e5e 727static void prom_init(hwaddr addr, const char *bios_name)
f48f6569
BS
728{
729 DeviceState *dev;
730 SysBusDevice *s;
731 char *filename;
732 int ret;
733
e6f54c91 734 dev = qdev_create(NULL, TYPE_OPENPROM);
e23a1b33 735 qdev_init_nofail(dev);
1356b98d 736 s = SYS_BUS_DEVICE(dev);
f48f6569
BS
737
738 sysbus_mmio_map(s, 0, addr);
739
740 /* load boot prom */
741 if (bios_name == NULL) {
742 bios_name = PROM_FILENAME;
743 }
744 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
745 if (filename) {
409dbce5
AJ
746 ret = load_elf(filename, translate_prom_address, &addr, NULL,
747 NULL, NULL, 1, ELF_MACHINE, 0);
f48f6569
BS
748 if (ret < 0 || ret > PROM_SIZE_MAX) {
749 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
750 }
7267c094 751 g_free(filename);
f48f6569
BS
752 } else {
753 ret = -1;
754 }
755 if (ret < 0 || ret > PROM_SIZE_MAX) {
756 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
757 exit(1);
758 }
759}
760
81a322d4 761static int prom_init1(SysBusDevice *dev)
f48f6569 762{
e6f54c91 763 PROMState *s = OPENPROM(dev);
f48f6569 764
49946538
HT
765 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
766 &error_abort);
c5705a77 767 vmstate_register_ram_global(&s->prom);
3150fa50 768 memory_region_set_readonly(&s->prom, true);
750ecd44 769 sysbus_init_mmio(dev, &s->prom);
81a322d4 770 return 0;
f48f6569
BS
771}
772
999e12bb
AL
773static Property prom_properties[] = {
774 {/* end of property list */},
775};
776
777static void prom_class_init(ObjectClass *klass, void *data)
778{
39bffca2 779 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb
AL
780 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
781
782 k->init = prom_init1;
39bffca2 783 dc->props = prom_properties;
999e12bb
AL
784}
785
8c43a6f0 786static const TypeInfo prom_info = {
e6f54c91 787 .name = TYPE_OPENPROM,
39bffca2
AL
788 .parent = TYPE_SYS_BUS_DEVICE,
789 .instance_size = sizeof(PROMState),
790 .class_init = prom_class_init,
f48f6569
BS
791};
792
5ab6b4c6
AF
793#define TYPE_SUN4M_MEMORY "memory"
794#define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
795
796typedef struct RamDevice {
797 SysBusDevice parent_obj;
798
3150fa50 799 MemoryRegion ram;
04843626 800 uint64_t size;
ee6847d1
GH
801} RamDevice;
802
a350db85 803/* System RAM */
81a322d4 804static int ram_init1(SysBusDevice *dev)
a350db85 805{
5ab6b4c6 806 RamDevice *d = SUN4M_RAM(dev);
a350db85 807
49946538
HT
808 memory_region_init_ram(&d->ram, OBJECT(d), "sun4m.ram", d->size,
809 &error_abort);
c5705a77 810 vmstate_register_ram_global(&d->ram);
750ecd44 811 sysbus_init_mmio(dev, &d->ram);
81a322d4 812 return 0;
a350db85
BS
813}
814
a8170e5e 815static void ram_init(hwaddr addr, ram_addr_t RAM_size,
a350db85
BS
816 uint64_t max_mem)
817{
818 DeviceState *dev;
819 SysBusDevice *s;
ee6847d1 820 RamDevice *d;
a350db85
BS
821
822 /* allocate RAM */
823 if ((uint64_t)RAM_size > max_mem) {
824 fprintf(stderr,
825 "qemu: Too much memory for this machine: %d, maximum %d\n",
826 (unsigned int)(RAM_size / (1024 * 1024)),
827 (unsigned int)(max_mem / (1024 * 1024)));
828 exit(1);
829 }
830 dev = qdev_create(NULL, "memory");
1356b98d 831 s = SYS_BUS_DEVICE(dev);
a350db85 832
5ab6b4c6 833 d = SUN4M_RAM(dev);
ee6847d1 834 d->size = RAM_size;
e23a1b33 835 qdev_init_nofail(dev);
ee6847d1 836
a350db85
BS
837 sysbus_mmio_map(s, 0, addr);
838}
839
999e12bb
AL
840static Property ram_properties[] = {
841 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
842 DEFINE_PROP_END_OF_LIST(),
843};
844
845static void ram_class_init(ObjectClass *klass, void *data)
846{
39bffca2 847 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb
AL
848 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
849
850 k->init = ram_init1;
39bffca2 851 dc->props = ram_properties;
999e12bb
AL
852}
853
8c43a6f0 854static const TypeInfo ram_info = {
5ab6b4c6 855 .name = TYPE_SUN4M_MEMORY,
39bffca2
AL
856 .parent = TYPE_SYS_BUS_DEVICE,
857 .instance_size = sizeof(RamDevice),
858 .class_init = ram_class_init,
a350db85
BS
859};
860
89835363
BS
861static void cpu_devinit(const char *cpu_model, unsigned int id,
862 uint64_t prom_addr, qemu_irq **cpu_irqs)
666713c0 863{
259186a7 864 CPUState *cs;
8968f588 865 SPARCCPU *cpu;
98cec4a2 866 CPUSPARCState *env;
666713c0 867
8968f588
AF
868 cpu = cpu_sparc_init(cpu_model);
869 if (cpu == NULL) {
666713c0
BS
870 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
871 exit(1);
872 }
8968f588 873 env = &cpu->env;
666713c0
BS
874
875 cpu_sparc_set_id(env, id);
876 if (id == 0) {
5414dec6 877 qemu_register_reset(main_cpu_reset, cpu);
666713c0 878 } else {
5414dec6 879 qemu_register_reset(secondary_cpu_reset, cpu);
259186a7
AF
880 cs = CPU(cpu);
881 cs->halted = 1;
666713c0 882 }
e0bbf9b5 883 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
666713c0 884 env->prom_addr = prom_addr;
666713c0
BS
885}
886
acfbe712
BS
887static void dummy_fdc_tc(void *opaque, int irq, int level)
888{
889}
890
6b63ef4d 891static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
3ef96221 892 MachineState *machine)
420557e8 893{
3ef96221 894 const char *cpu_model = machine->cpu_model;
713c45fa 895 unsigned int i;
cfb9de9c 896 void *iommu, *espdma, *ledma, *nvram;
a1961a4b 897 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
6f6260c7 898 espdma_irq, ledma_irq;
73d74342 899 qemu_irq esp_reset, dma_enable;
2582cfa0 900 qemu_irq fdc_tc;
6d0c293d 901 qemu_irq *cpu_halt;
5c6602c5 902 unsigned long kernel_size;
fd8014e1 903 DriveInfo *fd[MAX_FD];
a88b362c 904 FWCfgState *fw_cfg;
9a62fb24 905 unsigned int num_vsimms;
420557e8 906
ba3c64fb 907 /* init CPUs */
3ebf5aaf
BS
908 if (!cpu_model)
909 cpu_model = hwdef->default_cpu_model;
b3a23197 910
ba3c64fb 911 for(i = 0; i < smp_cpus; i++) {
89835363 912 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
ba3c64fb 913 }
b3a23197
BS
914
915 for (i = smp_cpus; i < MAX_CPUS; i++)
916 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
917
3ebf5aaf 918
3ebf5aaf 919 /* set up devices */
3ef96221 920 ram_init(0, machine->ram_size, hwdef->max_mem);
676d9b9b
AT
921 /* models without ECC don't trap when missing ram is accessed */
922 if (!hwdef->ecc_base) {
3ef96221 923 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
676d9b9b 924 }
a350db85 925
f48f6569
BS
926 prom_init(hwdef->slavio_base, bios_name);
927
d453c2c3
BS
928 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
929 hwdef->intctl_base + 0x10000ULL,
462eda24 930 cpu_irqs);
a1961a4b
BS
931
932 for (i = 0; i < 32; i++) {
d453c2c3 933 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
a1961a4b
BS
934 }
935 for (i = 0; i < MAX_CPUS; i++) {
d453c2c3 936 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
a1961a4b 937 }
b3a23197 938
fe096129 939 if (hwdef->idreg_base) {
325f2747 940 idreg_init(hwdef->idreg_base);
4c2485de
BS
941 }
942
c5de386a
AT
943 if (hwdef->afx_base) {
944 afx_init(hwdef->afx_base);
945 }
946
ff403da6 947 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
c533e0b3 948 slavio_irq[30]);
ff403da6 949
3386376c
AT
950 if (hwdef->iommu_pad_base) {
951 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
952 Software shouldn't use aliased addresses, neither should it crash
953 when does. Using empty_slot instead of aliasing can help with
954 debugging such accesses */
955 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
956 }
957
c533e0b3 958 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
86d1c388 959 iommu, &espdma_irq, 0);
2d069bab 960
5aca8c3b 961 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
86d1c388 962 slavio_irq[16], iommu, &ledma_irq, 1);
ba3c64fb 963
eee0b836 964 if (graphic_depth != 8 && graphic_depth != 24) {
af87bf29 965 error_report("Unsupported depth: %d", graphic_depth);
eee0b836
BS
966 exit (1);
967 }
9a62fb24
BB
968 num_vsimms = 0;
969 if (num_vsimms == 0) {
af87bf29
MCA
970 if (vga_interface_type == VGA_CG3) {
971 if (graphic_depth != 8) {
972 error_report("Unsupported depth: %d", graphic_depth);
973 exit(1);
974 }
975
976 if (!(graphic_width == 1024 && graphic_height == 768) &&
977 !(graphic_width == 1152 && graphic_height == 900)) {
978 error_report("Unsupported resolution: %d x %d", graphic_width,
979 graphic_height);
980 exit(1);
981 }
982
983 /* sbus irq 5 */
984 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
985 graphic_width, graphic_height, graphic_depth);
986 } else {
987 /* If no display specified, default to TCX */
988 if (graphic_depth != 8 && graphic_depth != 24) {
989 error_report("Unsupported depth: %d", graphic_depth);
990 exit(1);
991 }
992
993 if (!(graphic_width == 1024 && graphic_height == 768)) {
994 error_report("Unsupported resolution: %d x %d",
995 graphic_width, graphic_height);
996 exit(1);
997 }
998
55d7bfe2
MCA
999 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
1000 graphic_width, graphic_height, graphic_depth);
af87bf29 1001 }
9a62fb24
BB
1002 }
1003
1004 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
1005 /* vsimm registers probed by OBP */
1006 if (hwdef->vsimm[i].reg_base) {
1007 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
1008 }
1009 }
1010
1011 if (hwdef->sx_base) {
1012 empty_slot_init(hwdef->sx_base, 0x2000);
1013 }
dbe06e18 1014
74ff8d90 1015 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
dbe06e18 1016
6de04973 1017 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
81732d19 1018
c533e0b3 1019 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
81732d19 1020
c533e0b3 1021 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
993fbfdb 1022 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
5cbdb3a3
SW
1023 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1024 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
c533e0b3 1025 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
aeeb69c7 1026 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
741402f9 1027
6d0c293d 1028 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
2582cfa0
BS
1029 if (hwdef->apc_base) {
1030 apc_init(hwdef->apc_base, cpu_halt[0]);
1031 }
2be17ebd 1032
fe096129 1033 if (hwdef->fd_base) {
e4bcb14c 1034 /* there is zero or one floppy drive */
309e60bd 1035 memset(fd, 0, sizeof(fd));
fd8014e1 1036 fd[0] = drive_get(IF_FLOPPY, 0, 0);
c533e0b3 1037 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
2582cfa0 1038 &fdc_tc);
acfbe712
BS
1039 } else {
1040 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
e4bcb14c
TS
1041 }
1042
acfbe712
BS
1043 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1044 slavio_irq[30], fdc_tc);
1045
e4bcb14c
TS
1046 if (drive_get_max_bus(IF_SCSI) > 0) {
1047 fprintf(stderr, "qemu: too many SCSI bus\n");
1048 exit(1);
1049 }
1050
cfb9de9c
PB
1051 esp_init(hwdef->esp_base, 2,
1052 espdma_memory_read, espdma_memory_write,
73d74342 1053 espdma, espdma_irq, &esp_reset, &dma_enable);
74ff8d90 1054
73d74342
BS
1055 qdev_connect_gpio_out(espdma, 0, esp_reset);
1056 qdev_connect_gpio_out(espdma, 1, dma_enable);
f1587550 1057
fa28ec52
BS
1058 if (hwdef->cs_base) {
1059 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
c533e0b3 1060 slavio_irq[5]);
fa28ec52 1061 }
b3ceef24 1062
9a62fb24
BB
1063 if (hwdef->dbri_base) {
1064 /* ISDN chip with attached CS4215 audio codec */
1065 /* prom space */
1066 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1067 /* reg space */
1068 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1069 }
1070
1071 if (hwdef->bpp_base) {
1072 /* parallel port */
1073 empty_slot_init(hwdef->bpp_base, 0x20);
1074 }
1075
3ef96221
MA
1076 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1077 machine->initrd_filename,
1078 machine->ram_size);
36cd9210 1079
3ef96221
MA
1080 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1081 machine->boot_order, machine->ram_size, kernel_size,
1082 graphic_width, graphic_height, graphic_depth,
1083 hwdef->nvram_machine_id, "Sun4m");
7eb0c8e8 1084
fe096129 1085 if (hwdef->ecc_base)
c533e0b3 1086 ecc_init(hwdef->ecc_base, slavio_irq[28],
e42c20b4 1087 hwdef->ecc_version);
3cce6243 1088
66708822 1089 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
70db9222 1090 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
905fdcb5
BS
1091 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1092 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fbfcf955 1093 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
b96919e0
MCA
1094 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1095 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
513f789f
BS
1096 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1097 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
3ef96221 1098 if (machine->kernel_cmdline) {
513f789f 1099 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
6b63ef4d 1100 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
3ef96221
MA
1101 machine->kernel_cmdline);
1102 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
748a4ee3 1103 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
3ef96221 1104 strlen(machine->kernel_cmdline) + 1);
513f789f
BS
1105 } else {
1106 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
748a4ee3 1107 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
513f789f
BS
1108 }
1109 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1110 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
3ef96221 1111 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
513f789f 1112 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
36cd9210
BS
1113}
1114
905fdcb5 1115enum {
905fdcb5
BS
1116 ss5_id = 32,
1117 vger_id,
1118 lx_id,
1119 ss4_id,
1120 scls_id,
1121 sbook_id,
1122 ss10_id = 64,
1123 ss20_id,
1124 ss600mp_id,
905fdcb5
BS
1125};
1126
8137cde8 1127static const struct sun4m_hwdef sun4m_hwdefs[] = {
36cd9210
BS
1128 /* SS-5 */
1129 {
1130 .iommu_base = 0x10000000,
3386376c
AT
1131 .iommu_pad_base = 0x10004000,
1132 .iommu_pad_len = 0x0fffb000,
36cd9210
BS
1133 .tcx_base = 0x50000000,
1134 .cs_base = 0x6c000000,
384ccb5d 1135 .slavio_base = 0x70000000,
36cd9210
BS
1136 .ms_kb_base = 0x71000000,
1137 .serial_base = 0x71100000,
1138 .nvram_base = 0x71200000,
1139 .fd_base = 0x71400000,
1140 .counter_base = 0x71d00000,
1141 .intctl_base = 0x71e00000,
4c2485de 1142 .idreg_base = 0x78000000,
36cd9210
BS
1143 .dma_base = 0x78400000,
1144 .esp_base = 0x78800000,
1145 .le_base = 0x78c00000,
127fc407 1146 .apc_base = 0x6a000000,
c5de386a 1147 .afx_base = 0x6e000000,
0019ad53
BS
1148 .aux1_base = 0x71900000,
1149 .aux2_base = 0x71910000,
905fdcb5
BS
1150 .nvram_machine_id = 0x80,
1151 .machine_id = ss5_id,
cf3102ac 1152 .iommu_version = 0x05000000,
3ebf5aaf
BS
1153 .max_mem = 0x10000000,
1154 .default_cpu_model = "Fujitsu MB86904",
e0353fe2
BS
1155 },
1156 /* SS-10 */
e0353fe2 1157 {
5dcb6b91
BS
1158 .iommu_base = 0xfe0000000ULL,
1159 .tcx_base = 0xe20000000ULL,
5dcb6b91
BS
1160 .slavio_base = 0xff0000000ULL,
1161 .ms_kb_base = 0xff1000000ULL,
1162 .serial_base = 0xff1100000ULL,
1163 .nvram_base = 0xff1200000ULL,
1164 .fd_base = 0xff1700000ULL,
1165 .counter_base = 0xff1300000ULL,
1166 .intctl_base = 0xff1400000ULL,
4c2485de 1167 .idreg_base = 0xef0000000ULL,
5dcb6b91
BS
1168 .dma_base = 0xef0400000ULL,
1169 .esp_base = 0xef0800000ULL,
1170 .le_base = 0xef0c00000ULL,
0019ad53 1171 .apc_base = 0xefa000000ULL, // XXX should not exist
127fc407
BS
1172 .aux1_base = 0xff1800000ULL,
1173 .aux2_base = 0xff1a01000ULL,
7eb0c8e8
BS
1174 .ecc_base = 0xf00000000ULL,
1175 .ecc_version = 0x10000000, // version 0, implementation 1
905fdcb5
BS
1176 .nvram_machine_id = 0x72,
1177 .machine_id = ss10_id,
7fbfb139 1178 .iommu_version = 0x03000000,
6ef05b95 1179 .max_mem = 0xf00000000ULL,
3ebf5aaf 1180 .default_cpu_model = "TI SuperSparc II",
36cd9210 1181 },
6a3b9cc9
BS
1182 /* SS-600MP */
1183 {
1184 .iommu_base = 0xfe0000000ULL,
1185 .tcx_base = 0xe20000000ULL,
6a3b9cc9
BS
1186 .slavio_base = 0xff0000000ULL,
1187 .ms_kb_base = 0xff1000000ULL,
1188 .serial_base = 0xff1100000ULL,
1189 .nvram_base = 0xff1200000ULL,
6a3b9cc9
BS
1190 .counter_base = 0xff1300000ULL,
1191 .intctl_base = 0xff1400000ULL,
1192 .dma_base = 0xef0081000ULL,
1193 .esp_base = 0xef0080000ULL,
1194 .le_base = 0xef0060000ULL,
0019ad53 1195 .apc_base = 0xefa000000ULL, // XXX should not exist
127fc407
BS
1196 .aux1_base = 0xff1800000ULL,
1197 .aux2_base = 0xff1a01000ULL, // XXX should not exist
7eb0c8e8
BS
1198 .ecc_base = 0xf00000000ULL,
1199 .ecc_version = 0x00000000, // version 0, implementation 0
905fdcb5
BS
1200 .nvram_machine_id = 0x71,
1201 .machine_id = ss600mp_id,
7fbfb139 1202 .iommu_version = 0x01000000,
6ef05b95 1203 .max_mem = 0xf00000000ULL,
3ebf5aaf 1204 .default_cpu_model = "TI SuperSparc II",
6a3b9cc9 1205 },
ae40972f
BS
1206 /* SS-20 */
1207 {
1208 .iommu_base = 0xfe0000000ULL,
1209 .tcx_base = 0xe20000000ULL,
ae40972f
BS
1210 .slavio_base = 0xff0000000ULL,
1211 .ms_kb_base = 0xff1000000ULL,
1212 .serial_base = 0xff1100000ULL,
1213 .nvram_base = 0xff1200000ULL,
1214 .fd_base = 0xff1700000ULL,
1215 .counter_base = 0xff1300000ULL,
1216 .intctl_base = 0xff1400000ULL,
4c2485de 1217 .idreg_base = 0xef0000000ULL,
ae40972f
BS
1218 .dma_base = 0xef0400000ULL,
1219 .esp_base = 0xef0800000ULL,
1220 .le_base = 0xef0c00000ULL,
9a62fb24 1221 .bpp_base = 0xef4800000ULL,
0019ad53 1222 .apc_base = 0xefa000000ULL, // XXX should not exist
577d8dd4
BS
1223 .aux1_base = 0xff1800000ULL,
1224 .aux2_base = 0xff1a01000ULL,
9a62fb24
BB
1225 .dbri_base = 0xee0000000ULL,
1226 .sx_base = 0xf80000000ULL,
1227 .vsimm = {
1228 {
1229 .reg_base = 0x9c000000ULL,
1230 .vram_base = 0xfc000000ULL
1231 }, {
1232 .reg_base = 0x90000000ULL,
1233 .vram_base = 0xf0000000ULL
1234 }, {
1235 .reg_base = 0x94000000ULL
1236 }, {
1237 .reg_base = 0x98000000ULL
1238 }
1239 },
ae40972f
BS
1240 .ecc_base = 0xf00000000ULL,
1241 .ecc_version = 0x20000000, // version 0, implementation 2
905fdcb5
BS
1242 .nvram_machine_id = 0x72,
1243 .machine_id = ss20_id,
ae40972f 1244 .iommu_version = 0x13000000,
6ef05b95 1245 .max_mem = 0xf00000000ULL,
ae40972f
BS
1246 .default_cpu_model = "TI SuperSparc II",
1247 },
a526a31c
BS
1248 /* Voyager */
1249 {
1250 .iommu_base = 0x10000000,
1251 .tcx_base = 0x50000000,
a526a31c
BS
1252 .slavio_base = 0x70000000,
1253 .ms_kb_base = 0x71000000,
1254 .serial_base = 0x71100000,
1255 .nvram_base = 0x71200000,
1256 .fd_base = 0x71400000,
1257 .counter_base = 0x71d00000,
1258 .intctl_base = 0x71e00000,
1259 .idreg_base = 0x78000000,
1260 .dma_base = 0x78400000,
1261 .esp_base = 0x78800000,
1262 .le_base = 0x78c00000,
1263 .apc_base = 0x71300000, // pmc
1264 .aux1_base = 0x71900000,
1265 .aux2_base = 0x71910000,
905fdcb5
BS
1266 .nvram_machine_id = 0x80,
1267 .machine_id = vger_id,
a526a31c 1268 .iommu_version = 0x05000000,
a526a31c
BS
1269 .max_mem = 0x10000000,
1270 .default_cpu_model = "Fujitsu MB86904",
1271 },
1272 /* LX */
1273 {
1274 .iommu_base = 0x10000000,
3386376c
AT
1275 .iommu_pad_base = 0x10004000,
1276 .iommu_pad_len = 0x0fffb000,
a526a31c 1277 .tcx_base = 0x50000000,
a526a31c
BS
1278 .slavio_base = 0x70000000,
1279 .ms_kb_base = 0x71000000,
1280 .serial_base = 0x71100000,
1281 .nvram_base = 0x71200000,
1282 .fd_base = 0x71400000,
1283 .counter_base = 0x71d00000,
1284 .intctl_base = 0x71e00000,
1285 .idreg_base = 0x78000000,
1286 .dma_base = 0x78400000,
1287 .esp_base = 0x78800000,
1288 .le_base = 0x78c00000,
a526a31c
BS
1289 .aux1_base = 0x71900000,
1290 .aux2_base = 0x71910000,
905fdcb5
BS
1291 .nvram_machine_id = 0x80,
1292 .machine_id = lx_id,
a526a31c 1293 .iommu_version = 0x04000000,
a526a31c
BS
1294 .max_mem = 0x10000000,
1295 .default_cpu_model = "TI MicroSparc I",
1296 },
1297 /* SS-4 */
1298 {
1299 .iommu_base = 0x10000000,
1300 .tcx_base = 0x50000000,
1301 .cs_base = 0x6c000000,
1302 .slavio_base = 0x70000000,
1303 .ms_kb_base = 0x71000000,
1304 .serial_base = 0x71100000,
1305 .nvram_base = 0x71200000,
1306 .fd_base = 0x71400000,
1307 .counter_base = 0x71d00000,
1308 .intctl_base = 0x71e00000,
1309 .idreg_base = 0x78000000,
1310 .dma_base = 0x78400000,
1311 .esp_base = 0x78800000,
1312 .le_base = 0x78c00000,
1313 .apc_base = 0x6a000000,
1314 .aux1_base = 0x71900000,
1315 .aux2_base = 0x71910000,
905fdcb5
BS
1316 .nvram_machine_id = 0x80,
1317 .machine_id = ss4_id,
a526a31c 1318 .iommu_version = 0x05000000,
a526a31c
BS
1319 .max_mem = 0x10000000,
1320 .default_cpu_model = "Fujitsu MB86904",
1321 },
1322 /* SPARCClassic */
1323 {
1324 .iommu_base = 0x10000000,
1325 .tcx_base = 0x50000000,
a526a31c
BS
1326 .slavio_base = 0x70000000,
1327 .ms_kb_base = 0x71000000,
1328 .serial_base = 0x71100000,
1329 .nvram_base = 0x71200000,
1330 .fd_base = 0x71400000,
1331 .counter_base = 0x71d00000,
1332 .intctl_base = 0x71e00000,
1333 .idreg_base = 0x78000000,
1334 .dma_base = 0x78400000,
1335 .esp_base = 0x78800000,
1336 .le_base = 0x78c00000,
1337 .apc_base = 0x6a000000,
1338 .aux1_base = 0x71900000,
1339 .aux2_base = 0x71910000,
905fdcb5
BS
1340 .nvram_machine_id = 0x80,
1341 .machine_id = scls_id,
a526a31c 1342 .iommu_version = 0x05000000,
a526a31c
BS
1343 .max_mem = 0x10000000,
1344 .default_cpu_model = "TI MicroSparc I",
1345 },
1346 /* SPARCbook */
1347 {
1348 .iommu_base = 0x10000000,
1349 .tcx_base = 0x50000000, // XXX
a526a31c
BS
1350 .slavio_base = 0x70000000,
1351 .ms_kb_base = 0x71000000,
1352 .serial_base = 0x71100000,
1353 .nvram_base = 0x71200000,
1354 .fd_base = 0x71400000,
1355 .counter_base = 0x71d00000,
1356 .intctl_base = 0x71e00000,
1357 .idreg_base = 0x78000000,
1358 .dma_base = 0x78400000,
1359 .esp_base = 0x78800000,
1360 .le_base = 0x78c00000,
1361 .apc_base = 0x6a000000,
1362 .aux1_base = 0x71900000,
1363 .aux2_base = 0x71910000,
905fdcb5
BS
1364 .nvram_machine_id = 0x80,
1365 .machine_id = sbook_id,
a526a31c 1366 .iommu_version = 0x05000000,
a526a31c
BS
1367 .max_mem = 0x10000000,
1368 .default_cpu_model = "TI MicroSparc I",
1369 },
36cd9210
BS
1370};
1371
36cd9210 1372/* SPARCstation 5 hardware initialisation */
3ef96221 1373static void ss5_init(MachineState *machine)
36cd9210 1374{
3ef96221 1375 sun4m_hw_init(&sun4m_hwdefs[0], machine);
420557e8 1376}
c0e564d5 1377
e0353fe2 1378/* SPARCstation 10 hardware initialisation */
3ef96221 1379static void ss10_init(MachineState *machine)
e0353fe2 1380{
3ef96221 1381 sun4m_hw_init(&sun4m_hwdefs[1], machine);
e0353fe2
BS
1382}
1383
6a3b9cc9 1384/* SPARCserver 600MP hardware initialisation */
3ef96221 1385static void ss600mp_init(MachineState *machine)
6a3b9cc9 1386{
3ef96221 1387 sun4m_hw_init(&sun4m_hwdefs[2], machine);
6a3b9cc9
BS
1388}
1389
ae40972f 1390/* SPARCstation 20 hardware initialisation */
3ef96221 1391static void ss20_init(MachineState *machine)
ae40972f 1392{
3ef96221 1393 sun4m_hw_init(&sun4m_hwdefs[3], machine);
ee76f82e
BS
1394}
1395
a526a31c 1396/* SPARCstation Voyager hardware initialisation */
3ef96221 1397static void vger_init(MachineState *machine)
a526a31c 1398{
3ef96221 1399 sun4m_hw_init(&sun4m_hwdefs[4], machine);
a526a31c
BS
1400}
1401
1402/* SPARCstation LX hardware initialisation */
3ef96221 1403static void ss_lx_init(MachineState *machine)
a526a31c 1404{
3ef96221 1405 sun4m_hw_init(&sun4m_hwdefs[5], machine);
a526a31c
BS
1406}
1407
1408/* SPARCstation 4 hardware initialisation */
3ef96221 1409static void ss4_init(MachineState *machine)
a526a31c 1410{
3ef96221 1411 sun4m_hw_init(&sun4m_hwdefs[6], machine);
a526a31c
BS
1412}
1413
1414/* SPARCClassic hardware initialisation */
3ef96221 1415static void scls_init(MachineState *machine)
a526a31c 1416{
3ef96221 1417 sun4m_hw_init(&sun4m_hwdefs[7], machine);
a526a31c
BS
1418}
1419
1420/* SPARCbook hardware initialisation */
3ef96221 1421static void sbook_init(MachineState *machine)
a526a31c 1422{
3ef96221 1423 sun4m_hw_init(&sun4m_hwdefs[8], machine);
a526a31c
BS
1424}
1425
f80f9ec9 1426static QEMUMachine ss5_machine = {
66de733b
BS
1427 .name = "SS-5",
1428 .desc = "Sun4m platform, SPARCstation 5",
1429 .init = ss5_init,
2d0d2837 1430 .block_default_type = IF_SCSI,
0c257437 1431 .is_default = 1,
c1654732 1432 .default_boot_order = "c",
c0e564d5 1433};
e0353fe2 1434
f80f9ec9 1435static QEMUMachine ss10_machine = {
66de733b
BS
1436 .name = "SS-10",
1437 .desc = "Sun4m platform, SPARCstation 10",
1438 .init = ss10_init,
2d0d2837 1439 .block_default_type = IF_SCSI,
1bcee014 1440 .max_cpus = 4,
c1654732 1441 .default_boot_order = "c",
e0353fe2 1442};
6a3b9cc9 1443
f80f9ec9 1444static QEMUMachine ss600mp_machine = {
66de733b
BS
1445 .name = "SS-600MP",
1446 .desc = "Sun4m platform, SPARCserver 600MP",
1447 .init = ss600mp_init,
2d0d2837 1448 .block_default_type = IF_SCSI,
1bcee014 1449 .max_cpus = 4,
c1654732 1450 .default_boot_order = "c",
6a3b9cc9 1451};
ae40972f 1452
f80f9ec9 1453static QEMUMachine ss20_machine = {
66de733b
BS
1454 .name = "SS-20",
1455 .desc = "Sun4m platform, SPARCstation 20",
1456 .init = ss20_init,
2d0d2837 1457 .block_default_type = IF_SCSI,
1bcee014 1458 .max_cpus = 4,
c1654732 1459 .default_boot_order = "c",
ae40972f
BS
1460};
1461
f80f9ec9 1462static QEMUMachine voyager_machine = {
66de733b
BS
1463 .name = "Voyager",
1464 .desc = "Sun4m platform, SPARCstation Voyager",
1465 .init = vger_init,
2d0d2837 1466 .block_default_type = IF_SCSI,
c1654732 1467 .default_boot_order = "c",
a526a31c
BS
1468};
1469
f80f9ec9 1470static QEMUMachine ss_lx_machine = {
66de733b
BS
1471 .name = "LX",
1472 .desc = "Sun4m platform, SPARCstation LX",
1473 .init = ss_lx_init,
2d0d2837 1474 .block_default_type = IF_SCSI,
c1654732 1475 .default_boot_order = "c",
a526a31c
BS
1476};
1477
f80f9ec9 1478static QEMUMachine ss4_machine = {
66de733b
BS
1479 .name = "SS-4",
1480 .desc = "Sun4m platform, SPARCstation 4",
1481 .init = ss4_init,
2d0d2837 1482 .block_default_type = IF_SCSI,
c1654732 1483 .default_boot_order = "c",
a526a31c
BS
1484};
1485
f80f9ec9 1486static QEMUMachine scls_machine = {
66de733b
BS
1487 .name = "SPARCClassic",
1488 .desc = "Sun4m platform, SPARCClassic",
1489 .init = scls_init,
2d0d2837 1490 .block_default_type = IF_SCSI,
c1654732 1491 .default_boot_order = "c",
a526a31c
BS
1492};
1493
f80f9ec9 1494static QEMUMachine sbook_machine = {
66de733b
BS
1495 .name = "SPARCbook",
1496 .desc = "Sun4m platform, SPARCbook",
1497 .init = sbook_init,
2d0d2837 1498 .block_default_type = IF_SCSI,
c1654732 1499 .default_boot_order = "c",
a526a31c
BS
1500};
1501
83f7d43a
AF
1502static void sun4m_register_types(void)
1503{
1504 type_register_static(&idreg_info);
1505 type_register_static(&afx_info);
1506 type_register_static(&prom_info);
1507 type_register_static(&ram_info);
1508}
1509
6a4e1771 1510static void sun4m_machine_init(void)
f80f9ec9
AL
1511{
1512 qemu_register_machine(&ss5_machine);
1513 qemu_register_machine(&ss10_machine);
1514 qemu_register_machine(&ss600mp_machine);
1515 qemu_register_machine(&ss20_machine);
1516 qemu_register_machine(&voyager_machine);
1517 qemu_register_machine(&ss_lx_machine);
1518 qemu_register_machine(&ss4_machine);
1519 qemu_register_machine(&scls_machine);
1520 qemu_register_machine(&sbook_machine);
f80f9ec9
AL
1521}
1522
83f7d43a 1523type_init(sun4m_register_types)
6a4e1771 1524machine_init(sun4m_machine_init);
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