]> Git Repo - qemu.git/blame - hw/scsi/megasas.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
scsi: Improve error reporting for invalid drive property
[qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
9c17d615 23#include "sysemu/dma.h"
4be74634 24#include "sysemu/block-backend.h"
4522b69c 25#include "hw/pci/msi.h"
83c9f4ca 26#include "hw/pci/msix.h"
1de7afc9 27#include "qemu/iov.h"
0d09e41a
PB		 28#include "hw/scsi/scsi.h"
29#include "block/scsi.h"
e8f943c3 30#include "trace.h"
fa617181 31#include "qapi/qmp/qerror.h"
e8f943c3 32
47b43a1f 33#include "mfi.h"
e8f943c3 34
e23d0498
HR		 35#define MEGASAS_VERSION_GEN1 "1.70"
36#define MEGASAS_VERSION_GEN2 "1.80"
e8f943c3
HR		 37#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
38#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
e23d0498 39#define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
e8f943c3
HR		 40#define MEGASAS_MAX_SGE 128 /* Firmware limit */
41#define MEGASAS_DEFAULT_SGE 80
42#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
43#define MEGASAS_MAX_ARRAYS 128
44
fb654157 45#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 46#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
47#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
48
e8f943c3
HR		 49#define MEGASAS_FLAG_USE_JBOD 0
50#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
4522b69c
HR		 51#define MEGASAS_FLAG_USE_MSI 1
52#define MEGASAS_MASK_USE_MSI (1 << MEGASAS_FLAG_USE_MSI)
53#define MEGASAS_FLAG_USE_MSIX 2
e8f943c3 54#define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX)
4522b69c 55#define MEGASAS_FLAG_USE_QUEUE64 3
e8f943c3
HR		 56#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
57
a97ad268 58static const char *mfi_frame_desc[] = {
e8f943c3
HR		 59 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
60 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
61
62typedef struct MegasasCmd {
63 uint32_t index;
64 uint16_t flags;
65 uint16_t count;
66 uint64_t context;
67
a8170e5e
AK		 68 hwaddr pa;
69 hwaddr pa_size;
e8f943c3
HR		 70 union mfi_frame *frame;
71 SCSIRequest *req;
72 QEMUSGList qsg;
73 void *iov_buf;
74 size_t iov_size;
75 size_t iov_offset;
76 struct MegasasState *state;
77} MegasasCmd;
78
79typedef struct MegasasState {
52190c1e
AF		 80 /*< private >*/
81 PCIDevice parent_obj;
82 /*< public >*/
83
e8f943c3
HR		 84 MemoryRegion mmio_io;
85 MemoryRegion port_io;
86 MemoryRegion queue_io;
87 uint32_t frame_hi;
88
89 int fw_state;
90 uint32_t fw_sge;
91 uint32_t fw_cmds;
92 uint32_t flags;
93 int fw_luns;
94 int intr_mask;
95 int doorbell;
96 int busy;
e23d0498
HR		 97 int diag;
98 int adp_reset;
e8f943c3
HR		 99
100 MegasasCmd *event_cmd;
101 int event_locale;
102 int event_class;
103 int event_count;
104 int shutdown_event;
105 int boot_event;
106
76b523db 107 uint64_t sas_addr;
fb654157 108 char *hba_serial;
76b523db 109
e8f943c3
HR		 110 uint64_t reply_queue_pa;
111 void *reply_queue;
112 int reply_queue_len;
113 int reply_queue_head;
114 int reply_queue_tail;
115 uint64_t consumer_pa;
116 uint64_t producer_pa;
117
118 MegasasCmd frames[MEGASAS_MAX_FRAMES];
6df5718b 119 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 120 SCSIBus bus;
121} MegasasState;
122
e23d0498
HR		 123typedef struct MegasasBaseClass {
124 PCIDeviceClass parent_class;
125 const char *product_name;
126 const char *product_version;
127 int mmio_bar;
128 int ioport_bar;
129 int osts;
130} MegasasBaseClass;
131
132#define TYPE_MEGASAS_BASE "megasas-base"
133#define TYPE_MEGASAS_GEN1 "megasas"
134#define TYPE_MEGASAS_GEN2 "megasas-gen2"
c79e16ae
PC		 135
136#define MEGASAS(obj) \
e23d0498
HR		 137 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
138
139#define MEGASAS_DEVICE_CLASS(oc) \
140 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
141#define MEGASAS_DEVICE_GET_CLASS(oc) \
142 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
c79e16ae 143
e8f943c3
HR		 144#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
145
146static bool megasas_intr_enabled(MegasasState *s)
147{
148 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
149 MEGASAS_INTR_DISABLED_MASK) {
150 return true;
151 }
152 return false;
153}
154
155static bool megasas_use_queue64(MegasasState *s)
156{
157 return s->flags & MEGASAS_MASK_USE_QUEUE64;
158}
159
4522b69c
HR		 160static bool megasas_use_msi(MegasasState *s)
161{
162 return s->flags & MEGASAS_MASK_USE_MSI;
163}
164
e8f943c3
HR		 165static bool megasas_use_msix(MegasasState *s)
166{
167 return s->flags & MEGASAS_MASK_USE_MSIX;
168}
169
170static bool megasas_is_jbod(MegasasState *s)
171{
172 return s->flags & MEGASAS_MASK_USE_JBOD;
173}
174
175static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
176{
db3be60d
EI		 177 stb_phys(&address_space_memory,
178 frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 179}
180
181static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
182{
db3be60d
EI		 183 stb_phys(&address_space_memory,
184 frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 185}
186
187/*
188 * Context is considered opaque, but the HBA firmware is running
189 * in little endian mode. So convert it to little endian, too.
190 */
191static uint64_t megasas_frame_get_context(unsigned long frame)
192{
2c17449b
EI		 193 return ldq_le_phys(&address_space_memory,
194 frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 195}
196
197static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
198{
199 return cmd->flags & MFI_FRAME_IEEE_SGL;
200}
201
202static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
203{
204 return cmd->flags & MFI_FRAME_SGL64;
205}
206
207static bool megasas_frame_is_sense64(MegasasCmd *cmd)
208{
209 return cmd->flags & MFI_FRAME_SENSE64;
210}
211
212static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
213 union mfi_sgl *sgl)
214{
215 uint64_t addr;
216
217 if (megasas_frame_is_ieee_sgl(cmd)) {
218 addr = le64_to_cpu(sgl->sg_skinny->addr);
219 } else if (megasas_frame_is_sgl64(cmd)) {
220 addr = le64_to_cpu(sgl->sg64->addr);
221 } else {
222 addr = le32_to_cpu(sgl->sg32->addr);
223 }
224 return addr;
225}
226
227static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
228 union mfi_sgl *sgl)
229{
230 uint32_t len;
231
232 if (megasas_frame_is_ieee_sgl(cmd)) {
233 len = le32_to_cpu(sgl->sg_skinny->len);
234 } else if (megasas_frame_is_sgl64(cmd)) {
235 len = le32_to_cpu(sgl->sg64->len);
236 } else {
237 len = le32_to_cpu(sgl->sg32->len);
238 }
239 return len;
240}
241
242static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
243 union mfi_sgl *sgl)
244{
245 uint8_t *next = (uint8_t *)sgl;
246
247 if (megasas_frame_is_ieee_sgl(cmd)) {
248 next += sizeof(struct mfi_sg_skinny);
249 } else if (megasas_frame_is_sgl64(cmd)) {
250 next += sizeof(struct mfi_sg64);
251 } else {
252 next += sizeof(struct mfi_sg32);
253 }
254
255 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
256 return NULL;
257 }
258 return (union mfi_sgl *)next;
259}
260
261static void megasas_soft_reset(MegasasState *s);
262
263static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
264{
265 int i;
266 int iov_count = 0;
267 size_t iov_size = 0;
268
269 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
270 iov_count = cmd->frame->header.sge_count;
271 if (iov_count > MEGASAS_MAX_SGE) {
272 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
273 MEGASAS_MAX_SGE);
274 return iov_count;
275 }
52190c1e 276 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 277 for (i = 0; i < iov_count; i++) {
278 dma_addr_t iov_pa, iov_size_p;
279
280 if (!sgl) {
281 trace_megasas_iovec_sgl_underflow(cmd->index, i);
282 goto unmap;
283 }
284 iov_pa = megasas_sgl_get_addr(cmd, sgl);
285 iov_size_p = megasas_sgl_get_len(cmd, sgl);
286 if (!iov_pa || !iov_size_p) {
287 trace_megasas_iovec_sgl_invalid(cmd->index, i,
288 iov_pa, iov_size_p);
289 goto unmap;
290 }
291 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
292 sgl = megasas_sgl_next(cmd, sgl);
293 iov_size += (size_t)iov_size_p;
294 }
295 if (cmd->iov_size > iov_size) {
296 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
297 } else if (cmd->iov_size < iov_size) {
298 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
299 }
300 cmd->iov_offset = 0;
301 return 0;
302unmap:
303 qemu_sglist_destroy(&cmd->qsg);
304 return iov_count - i;
305}
306
307static void megasas_unmap_sgl(MegasasCmd *cmd)
308{
309 qemu_sglist_destroy(&cmd->qsg);
310 cmd->iov_offset = 0;
311}
312
313/*
314 * passthrough sense and io sense are at the same offset
315 */
316static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
317 uint8_t sense_len)
318{
1016b239 319 PCIDevice *pcid = PCI_DEVICE(cmd->state);
e8f943c3 320 uint32_t pa_hi = 0, pa_lo;
a8170e5e 321 hwaddr pa;
e8f943c3
HR		 322
323 if (sense_len > cmd->frame->header.sense_len) {
324 sense_len = cmd->frame->header.sense_len;
325 }
326 if (sense_len) {
327 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
328 if (megasas_frame_is_sense64(cmd)) {
329 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
330 }
331 pa = ((uint64_t) pa_hi << 32) | pa_lo;
1016b239 332 pci_dma_write(pcid, pa, sense_ptr, sense_len);
e8f943c3
HR		 333 cmd->frame->header.sense_len = sense_len;
334 }
335 return sense_len;
336}
337
338static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
339{
340 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
341 uint8_t sense_len = 18;
342
343 memset(sense_buf, 0, sense_len);
344 sense_buf[0] = 0xf0;
345 sense_buf[2] = sense.key;
346 sense_buf[7] = 10;
347 sense_buf[12] = sense.asc;
348 sense_buf[13] = sense.ascq;
349 megasas_build_sense(cmd, sense_buf, sense_len);
350}
351
352static void megasas_copy_sense(MegasasCmd *cmd)
353{
354 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
355 uint8_t sense_len;
356
357 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
358 SCSI_SENSE_BUF_SIZE);
359 megasas_build_sense(cmd, sense_buf, sense_len);
360}
361
362/*
363 * Format an INQUIRY CDB
364 */
365static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
366{
367 memset(cdb, 0, 6);
368 cdb[0] = INQUIRY;
369 if (pg > 0) {
370 cdb[1] = 0x1;
371 cdb[2] = pg;
372 }
373 cdb[3] = (len >> 8) & 0xff;
374 cdb[4] = (len & 0xff);
375 return len;
376}
377
378/*
379 * Encode lba and len into a READ_16/WRITE_16 CDB
380 */
381static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
382 uint32_t len, bool is_write)
383{
384 memset(cdb, 0x0, 16);
385 if (is_write) {
386 cdb[0] = WRITE_16;
387 } else {
388 cdb[0] = READ_16;
389 }
390 cdb[2] = (lba >> 56) & 0xff;
391 cdb[3] = (lba >> 48) & 0xff;
392 cdb[4] = (lba >> 40) & 0xff;
393 cdb[5] = (lba >> 32) & 0xff;
394 cdb[6] = (lba >> 24) & 0xff;
395 cdb[7] = (lba >> 16) & 0xff;
396 cdb[8] = (lba >> 8) & 0xff;
397 cdb[9] = (lba) & 0xff;
398 cdb[10] = (len >> 24) & 0xff;
399 cdb[11] = (len >> 16) & 0xff;
400 cdb[12] = (len >> 8) & 0xff;
401 cdb[13] = (len) & 0xff;
402}
403
404/*
405 * Utility functions
406 */
407static uint64_t megasas_fw_time(void)
408{
409 struct tm curtime;
410 uint64_t bcd_time;
411
412 qemu_get_timedate(&curtime, 0);
413 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 |
414 ((uint64_t)curtime.tm_min & 0xff) << 40 |
415 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
416 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
417 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
418 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
419
420 return bcd_time;
421}
422
76b523db
HR		 423/*
424 * Default disk sata address
425 * 0x1221 is the magic number as
426 * present in real hardware,
427 * so use it here, too.
428 */
429static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 430{
76b523db
HR		 431 uint64_t addr = (0x1221ULL << 48);
432 return addr & (id << 24);
e8f943c3
HR		 433}
434
435/*
436 * Frame handling
437 */
438static int megasas_next_index(MegasasState *s, int index, int limit)
439{
440 index++;
441 if (index == limit) {
442 index = 0;
443 }
444 return index;
445}
446
447static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 448 hwaddr frame)
e8f943c3
HR		 449{
450 MegasasCmd *cmd = NULL;
451 int num = 0, index;
452
453 index = s->reply_queue_head;
454
455 while (num < s->fw_cmds) {
456 if (s->frames[index].pa && s->frames[index].pa == frame) {
457 cmd = &s->frames[index];
458 break;
459 }
460 index = megasas_next_index(s, index, s->fw_cmds);
461 num++;
462 }
463
464 return cmd;
465}
466
6df5718b 467static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
e8f943c3 468{
6df5718b 469 PCIDevice *p = PCI_DEVICE(s);
e8f943c3 470
6df5718b
HR		 471 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
472 cmd->frame = NULL;
473 cmd->pa = 0;
474 clear_bit(cmd->index, s->frame_map);
e8f943c3
HR		 475}
476
6df5718b
HR		 477/*
478 * This absolutely needs to be locked if
479 * qemu ever goes multithreaded.
480 */
e8f943c3 481static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 482 hwaddr frame, uint64_t context, int count)
e8f943c3 483{
1016b239 484 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 485 MegasasCmd *cmd = NULL;
486 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 487 hwaddr frame_size_p = frame_size;
6df5718b 488 unsigned long index;
e8f943c3 489
6df5718b
HR		 490 index = 0;
491 while (index < s->fw_cmds) {
492 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
493 if (!s->frames[index].pa)
494 break;
495 /* Busy frame found */
496 trace_megasas_qf_mapped(index);
497 }
498 if (index >= s->fw_cmds) {
499 /* All frames busy */
500 trace_megasas_qf_busy(frame);
e8f943c3
HR		 501 return NULL;
502 }
6df5718b
HR		 503 cmd = &s->frames[index];
504 set_bit(index, s->frame_map);
505 trace_megasas_qf_new(index, frame);
506
507 cmd->pa = frame;
508 /* Map all possible frames */
509 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
510 if (frame_size_p != frame_size) {
511 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
512 if (cmd->frame) {
513 megasas_unmap_frame(s, cmd);
e8f943c3 514 }
6df5718b
HR		 515 s->event_count++;
516 return NULL;
517 }
518 cmd->pa_size = frame_size_p;
519 cmd->context = context;
520 if (!megasas_use_queue64(s)) {
521 cmd->context &= (uint64_t)0xFFFFFFFF;
e8f943c3
HR		 522 }
523 cmd->count = count;
524 s->busy++;
525
aaf2a859
HR		 526 if (s->consumer_pa) {
527 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
528 s->consumer_pa);
529 }
e8f943c3 530 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
aaf2a859 531 s->reply_queue_head, s->reply_queue_tail, s->busy);
e8f943c3
HR		 532
533 return cmd;
534}
535
536static void megasas_complete_frame(MegasasState *s, uint64_t context)
537{
52190c1e 538 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 539 int tail, queue_offset;
540
541 /* Decrement busy count */
542 s->busy--;
e8f943c3
HR		 543 if (s->reply_queue_pa) {
544 /*
545 * Put command on the reply queue.
546 * Context is opaque, but emulation is running in
547 * little endian. So convert it.
548 */
e8f943c3 549 if (megasas_use_queue64(s)) {
7957ee71 550 queue_offset = s->reply_queue_head * sizeof(uint64_t);
f606604f
EI		 551 stq_le_phys(&address_space_memory,
552 s->reply_queue_pa + queue_offset, context);
e8f943c3 553 } else {
7957ee71 554 queue_offset = s->reply_queue_head * sizeof(uint32_t);
ab1da857
EI		 555 stl_le_phys(&address_space_memory,
556 s->reply_queue_pa + queue_offset, context);
e8f943c3 557 }
aaf2a859
HR		 558 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
559 s->consumer_pa);
560 trace_megasas_qf_complete(context, s->reply_queue_head,
7957ee71 561 s->reply_queue_tail, s->busy);
e8f943c3
HR		 562 }
563
564 if (megasas_intr_enabled(s)) {
7957ee71
HR		 565 /* Update reply queue pointer */
566 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
567 s->consumer_pa);
568 tail = s->reply_queue_head;
569 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
570 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
571 s->busy);
572 stl_le_phys(&address_space_memory,
573 s->producer_pa, s->reply_queue_head);
e8f943c3 574 /* Notify HBA */
7957ee71
HR		 575 if (msix_enabled(pci_dev)) {
576 trace_megasas_msix_raise(0);
577 msix_notify(pci_dev, 0);
578 } else if (msi_enabled(pci_dev)) {
579 trace_megasas_msi_raise(0);
580 msi_notify(pci_dev, 0);
581 } else {
582 s->doorbell++;
583 if (s->doorbell == 1) {
e8f943c3 584 trace_megasas_irq_raise();
9e64f8a3 585 pci_irq_assert(pci_dev);
e8f943c3
HR		 586 }
587 }
588 } else {
589 trace_megasas_qf_complete_noirq(context);
590 }
591}
592
593static void megasas_reset_frames(MegasasState *s)
594{
595 int i;
596 MegasasCmd *cmd;
597
598 for (i = 0; i < s->fw_cmds; i++) {
599 cmd = &s->frames[i];
600 if (cmd->pa) {
6df5718b 601 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 602 }
603 }
6df5718b 604 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 605}
606
607static void megasas_abort_command(MegasasCmd *cmd)
608{
609 if (cmd->req) {
e2b06058 610 scsi_req_cancel(cmd->req);
e8f943c3
HR		 611 cmd->req = NULL;
612 }
613}
614
615static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
616{
1016b239 617 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 618 uint32_t pa_hi, pa_lo;
96f8f23a
HR		 619 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
620 struct mfi_init_qinfo *initq = NULL;
e8f943c3
HR		 621 uint32_t flags;
622 int ret = MFI_STAT_OK;
623
96f8f23a
HR		 624 if (s->reply_queue_pa) {
625 trace_megasas_initq_mapped(s->reply_queue_pa);
626 goto out;
627 }
e8f943c3
HR		 628 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
629 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
630 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
631 trace_megasas_init_firmware((uint64_t)iq_pa);
1016b239 632 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
e8f943c3
HR		 633 if (!initq || initq_size != sizeof(*initq)) {
634 trace_megasas_initq_map_failed(cmd->index);
635 s->event_count++;
636 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
637 goto out;
638 }
639 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
640 if (s->reply_queue_len > s->fw_cmds) {
641 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
642 s->event_count++;
643 ret = MFI_STAT_INVALID_PARAMETER;
644 goto out;
645 }
646 pa_lo = le32_to_cpu(initq->rq_addr_lo);
647 pa_hi = le32_to_cpu(initq->rq_addr_hi);
648 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
649 pa_lo = le32_to_cpu(initq->ci_addr_lo);
650 pa_hi = le32_to_cpu(initq->ci_addr_hi);
651 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
652 pa_lo = le32_to_cpu(initq->pi_addr_lo);
653 pa_hi = le32_to_cpu(initq->pi_addr_hi);
654 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
fdfba1a2
EI		 655 s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
656 s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
e8f943c3
HR		 657 flags = le32_to_cpu(initq->flags);
658 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
659 s->flags |= MEGASAS_MASK_USE_QUEUE64;
660 }
661 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
662 s->reply_queue_len, s->reply_queue_head,
663 s->reply_queue_tail, flags);
664 megasas_reset_frames(s);
665 s->fw_state = MFI_FWSTATE_OPERATIONAL;
666out:
667 if (initq) {
1016b239 668 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
e8f943c3
HR		 669 }
670 return ret;
671}
672
673static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
674{
675 dma_addr_t iov_pa, iov_size;
676
677 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
678 if (!cmd->frame->header.sge_count) {
679 trace_megasas_dcmd_zero_sge(cmd->index);
680 cmd->iov_size = 0;
681 return 0;
682 } else if (cmd->frame->header.sge_count > 1) {
683 trace_megasas_dcmd_invalid_sge(cmd->index,
684 cmd->frame->header.sge_count);
685 cmd->iov_size = 0;
686 return -1;
687 }
688 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
689 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 690 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 691 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
692 cmd->iov_size = iov_size;
693 return cmd->iov_size;
694}
695
696static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
697{
698 trace_megasas_finish_dcmd(cmd->index, iov_size);
699
700 if (cmd->frame->header.sge_count) {
701 qemu_sglist_destroy(&cmd->qsg);
702 }
703 if (iov_size > cmd->iov_size) {
704 if (megasas_frame_is_ieee_sgl(cmd)) {
705 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
706 } else if (megasas_frame_is_sgl64(cmd)) {
707 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
708 } else {
709 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
710 }
711 }
712 cmd->iov_size = 0;
e8f943c3
HR		 713}
714
715static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
716{
52190c1e 717 PCIDevice *pci_dev = PCI_DEVICE(s);
e23d0498
HR		 718 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
719 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 720 struct mfi_ctrl_info info;
721 size_t dcmd_size = sizeof(info);
722 BusChild *kid;
3f2cd4dd 723 int num_pd_disks = 0;
e8f943c3
HR		 724
725 memset(&info, 0x0, cmd->iov_size);
726 if (cmd->iov_size < dcmd_size) {
727 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
728 dcmd_size);
729 return MFI_STAT_INVALID_PARAMETER;
730 }
731
e23d0498
HR		 732 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
733 info.pci.device = cpu_to_le16(pci_class->device_id);
734 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
735 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
e8f943c3 736
76b523db
HR		 737 /*
738 * For some reason the firmware supports
739 * only up to 8 device ports.
740 * Despite supporting a far larger number
741 * of devices for the physical devices.
742 * So just display the first 8 devices
743 * in the device port list, independent
744 * of how many logical devices are actually
745 * present.
746 */
747 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 748 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 749 info.device.port_count = 8;
750 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
751 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd 752 uint16_t pd_id;
76b523db 753
3f2cd4dd
HR		 754 if (num_pd_disks < 8) {
755 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
756 info.device.port_addr[num_pd_disks] =
757 cpu_to_le64(megasas_get_sata_addr(pd_id));
76b523db 758 }
3f2cd4dd 759 num_pd_disks++;
76b523db 760 }
e8f943c3 761
e23d0498 762 memcpy(info.product_name, base_class->product_name, 24);
fb654157 763 snprintf(info.serial_number, 32, "%s", s->hba_serial);
e8f943c3
HR		 764 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION);
765 memcpy(info.image_component[0].name, "APP", 3);
e23d0498
HR		 766 snprintf(info.image_component[0].version, 10, "%s-QEMU",
767 base_class->product_version);
5a7733b0
OH		 768 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
769 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 770 info.image_component_count = 1;
52190c1e 771 if (pci_dev->has_rom) {
e8f943c3
HR		 772 uint8_t biosver[32];
773 uint8_t *ptr;
774
52190c1e 775 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 776 memcpy(biosver, ptr + 0x41, 31);
e8f943c3
HR		 777 memcpy(info.image_component[1].name, "BIOS", 4);
778 memcpy(info.image_component[1].version, biosver,
779 strlen((const char *)biosver));
780 info.image_component_count++;
781 }
782 info.current_fw_time = cpu_to_le32(megasas_fw_time());
783 info.max_arms = 32;
784 info.max_spans = 8;
785 info.max_arrays = MEGASAS_MAX_ARRAYS;
3f2cd4dd 786 info.max_lds = MFI_MAX_LD;
e8f943c3
HR		 787 info.max_cmds = cpu_to_le16(s->fw_cmds);
788 info.max_sg_elements = cpu_to_le16(s->fw_sge);
789 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
3f2cd4dd
HR		 790 if (!megasas_is_jbod(s))
791 info.lds_present = cpu_to_le16(num_pd_disks);
792 info.pd_present = cpu_to_le16(num_pd_disks);
793 info.pd_disks_present = cpu_to_le16(num_pd_disks);
e8f943c3
HR		 794 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
795 MFI_INFO_HW_MEM |
796 MFI_INFO_HW_FLASH);
797 info.memory_size = cpu_to_le16(512);
798 info.nvram_size = cpu_to_le16(32);
799 info.flash_size = cpu_to_le16(16);
800 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
801 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
802 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
803 MFI_INFO_AOPS_MIXED_ARRAY);
804 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
805 MFI_INFO_LDOPS_ACCESS_POLICY |
806 MFI_INFO_LDOPS_IO_POLICY |
807 MFI_INFO_LDOPS_WRITE_POLICY |
808 MFI_INFO_LDOPS_READ_POLICY);
809 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
810 info.stripe_sz_ops.min = 3;
811 info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1;
812 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
813 info.properties.intr_throttle_cnt = cpu_to_le16(16);
814 info.properties.intr_throttle_timeout = cpu_to_le16(50);
815 info.properties.rebuild_rate = 30;
816 info.properties.patrol_read_rate = 30;
817 info.properties.bgi_rate = 30;
818 info.properties.cc_rate = 30;
819 info.properties.recon_rate = 30;
820 info.properties.cache_flush_interval = 4;
821 info.properties.spinup_drv_cnt = 2;
822 info.properties.spinup_delay = 6;
823 info.properties.ecc_bucket_size = 15;
824 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
825 info.properties.expose_encl_devices = 1;
826 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
827 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
828 MFI_INFO_PDOPS_FORCE_OFFLINE);
829 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
830 MFI_INFO_PDMIX_SATA |
831 MFI_INFO_PDMIX_LD);
832
833 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
834 return MFI_STAT_OK;
835}
836
837static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
838{
839 struct mfi_defaults info;
840 size_t dcmd_size = sizeof(struct mfi_defaults);
841
842 memset(&info, 0x0, dcmd_size);
843 if (cmd->iov_size < dcmd_size) {
844 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
845 dcmd_size);
846 return MFI_STAT_INVALID_PARAMETER;
847 }
848
76b523db 849 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 850 info.stripe_size = 3;
851 info.flush_time = 4;
852 info.background_rate = 30;
853 info.allow_mix_in_enclosure = 1;
854 info.allow_mix_in_ld = 1;
855 info.direct_pd_mapping = 1;
856 /* Enable for BIOS support */
857 info.bios_enumerate_lds = 1;
858 info.disable_ctrl_r = 1;
859 info.expose_enclosure_devices = 1;
860 info.disable_preboot_cli = 1;
861 info.cluster_disable = 1;
862
863 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
864 return MFI_STAT_OK;
865}
866
867static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
868{
869 struct mfi_bios_data info;
870 size_t dcmd_size = sizeof(info);
871
872 memset(&info, 0x0, dcmd_size);
873 if (cmd->iov_size < dcmd_size) {
874 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
875 dcmd_size);
876 return MFI_STAT_INVALID_PARAMETER;
877 }
878 info.continue_on_error = 1;
879 info.verbose = 1;
880 if (megasas_is_jbod(s)) {
881 info.expose_all_drives = 1;
882 }
883
884 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
885 return MFI_STAT_OK;
886}
887
888static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
889{
890 uint64_t fw_time;
891 size_t dcmd_size = sizeof(fw_time);
892
893 fw_time = cpu_to_le64(megasas_fw_time());
894
895 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
896 return MFI_STAT_OK;
897}
898
899static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
900{
901 uint64_t fw_time;
902
903 /* This is a dummy; setting of firmware time is not allowed */
904 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
905
906 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
907 fw_time = cpu_to_le64(megasas_fw_time());
908 return MFI_STAT_OK;
909}
910
911static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
912{
913 struct mfi_evt_log_state info;
914 size_t dcmd_size = sizeof(info);
915
916 memset(&info, 0, dcmd_size);
917
918 info.newest_seq_num = cpu_to_le32(s->event_count);
919 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
920 info.boot_seq_num = cpu_to_le32(s->boot_event);
921
922 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
923 return MFI_STAT_OK;
924}
925
926static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
927{
928 union mfi_evt event;
929
930 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
931 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
932 sizeof(struct mfi_evt_detail));
933 return MFI_STAT_INVALID_PARAMETER;
934 }
935 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
936 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
937 s->event_locale = event.members.locale;
938 s->event_class = event.members.class;
939 s->event_cmd = cmd;
940 /* Decrease busy count; event frame doesn't count here */
941 s->busy--;
942 cmd->iov_size = sizeof(struct mfi_evt_detail);
943 return MFI_STAT_INVALID_STATUS;
944}
945
946static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
947{
948 struct mfi_pd_list info;
949 size_t dcmd_size = sizeof(info);
950 BusChild *kid;
951 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
e8f943c3
HR		 952
953 memset(&info, 0, dcmd_size);
954 offset = 8;
955 dcmd_limit = offset + sizeof(struct mfi_pd_address);
956 if (cmd->iov_size < dcmd_limit) {
957 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
958 dcmd_limit);
959 return MFI_STAT_INVALID_PARAMETER;
960 }
961
962 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
3f2cd4dd
HR		 963 if (max_pd_disks > MFI_MAX_SYS_PDS) {
964 max_pd_disks = MFI_MAX_SYS_PDS;
e8f943c3 965 }
e8f943c3
HR		 966 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
967 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd
HR		 968 uint16_t pd_id;
969
970 if (num_pd_disks >= max_pd_disks)
971 break;
e8f943c3 972
3f2cd4dd
HR		 973 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
974 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 975 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
976 info.addr[num_pd_disks].encl_index = 0;
3f2cd4dd 977 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
e8f943c3
HR		 978 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
979 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
980 info.addr[num_pd_disks].sas_addr[0] =
3f2cd4dd 981 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 982 num_pd_disks++;
983 offset += sizeof(struct mfi_pd_address);
984 }
985 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
986 max_pd_disks, offset);
987
988 info.size = cpu_to_le32(offset);
989 info.count = cpu_to_le32(num_pd_disks);
990
991 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
992 return MFI_STAT_OK;
993}
994
995static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
996{
997 uint16_t flags;
998
999 /* mbox0 contains flags */
1000 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1001 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1002 if (flags == MR_PD_QUERY_TYPE_ALL ||
1003 megasas_is_jbod(s)) {
1004 return megasas_dcmd_pd_get_list(s, cmd);
1005 }
1006
1007 return MFI_STAT_OK;
1008}
1009
1010static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1011 MegasasCmd *cmd)
1012{
1013 struct mfi_pd_info *info = cmd->iov_buf;
1014 size_t dcmd_size = sizeof(struct mfi_pd_info);
e8f943c3 1015 uint64_t pd_size;
3f2cd4dd 1016 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1017 uint8_t cmdbuf[6];
1018 SCSIRequest *req;
1019 size_t len, resid;
1020
1021 if (!cmd->iov_buf) {
0bd0adbe 1022 cmd->iov_buf = g_malloc0(dcmd_size);
e8f943c3
HR		 1023 info = cmd->iov_buf;
1024 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1025 info->vpd_page83[0] = 0x7f;
1026 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1027 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1028 if (!req) {
1029 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1030 "PD get info std inquiry");
1031 g_free(cmd->iov_buf);
1032 cmd->iov_buf = NULL;
1033 return MFI_STAT_FLASH_ALLOC_FAIL;
1034 }
1035 trace_megasas_dcmd_internal_submit(cmd->index,
1036 "PD get info std inquiry", lun);
1037 len = scsi_req_enqueue(req);
1038 if (len > 0) {
1039 cmd->iov_size = len;
1040 scsi_req_continue(req);
1041 }
1042 return MFI_STAT_INVALID_STATUS;
1043 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1044 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1045 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1046 if (!req) {
1047 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1048 "PD get info vpd inquiry");
1049 return MFI_STAT_FLASH_ALLOC_FAIL;
1050 }
1051 trace_megasas_dcmd_internal_submit(cmd->index,
1052 "PD get info vpd inquiry", lun);
1053 len = scsi_req_enqueue(req);
1054 if (len > 0) {
1055 cmd->iov_size = len;
1056 scsi_req_continue(req);
1057 }
1058 return MFI_STAT_INVALID_STATUS;
1059 }
1060 /* Finished, set FW state */
1061 if ((info->inquiry_data[0] >> 5) == 0) {
1062 if (megasas_is_jbod(cmd->state)) {
1063 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1064 } else {
1065 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1066 }
1067 } else {
1068 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1069 }
1070
3f2cd4dd 1071 info->ref.v.device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 1072 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1073 MFI_PD_DDF_TYPE_INTF_SAS);
4be74634 1074 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1075 info->raw_size = cpu_to_le64(pd_size);
1076 info->non_coerced_size = cpu_to_le64(pd_size);
1077 info->coerced_size = cpu_to_le64(pd_size);
1078 info->encl_device_id = 0xFFFF;
1079 info->slot_number = (sdev->id & 0xFF);
1080 info->path_info.count = 1;
1081 info->path_info.sas_addr[0] =
3f2cd4dd 1082 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 1083 info->connected_port_bitmap = 0x1;
1084 info->device_speed = 1;
1085 info->link_speed = 1;
1086 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1087 g_free(cmd->iov_buf);
1088 cmd->iov_size = dcmd_size - resid;
1089 cmd->iov_buf = NULL;
1090 return MFI_STAT_OK;
1091}
1092
1093static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1094{
1095 size_t dcmd_size = sizeof(struct mfi_pd_info);
1096 uint16_t pd_id;
3f2cd4dd 1097 uint8_t target_id, lun_id;
e8f943c3
HR		 1098 SCSIDevice *sdev = NULL;
1099 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1100
1101 if (cmd->iov_size < dcmd_size) {
1102 return MFI_STAT_INVALID_PARAMETER;
1103 }
1104
1105 /* mbox0 has the ID */
1106 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
3f2cd4dd
HR		 1107 target_id = (pd_id >> 8) & 0xFF;
1108 lun_id = pd_id & 0xFF;
1109 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
e8f943c3
HR		 1110 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1111
1112 if (sdev) {
1113 /* Submit inquiry */
1114 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1115 }
1116
1117 return retval;
1118}
1119
1120static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1121{
1122 struct mfi_ld_list info;
1123 size_t dcmd_size = sizeof(info), resid;
3f2cd4dd 1124 uint32_t num_ld_disks = 0, max_ld_disks;
e8f943c3
HR		 1125 uint64_t ld_size;
1126 BusChild *kid;
1127
1128 memset(&info, 0, dcmd_size);
e74a4315 1129 if (cmd->iov_size > dcmd_size) {
e8f943c3
HR		 1130 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1131 dcmd_size);
1132 return MFI_STAT_INVALID_PARAMETER;
1133 }
1134
3f2cd4dd 1135 max_ld_disks = (cmd->iov_size - 8) / 16;
e8f943c3
HR		 1136 if (megasas_is_jbod(s)) {
1137 max_ld_disks = 0;
1138 }
3f2cd4dd
HR		 1139 if (max_ld_disks > MFI_MAX_LD) {
1140 max_ld_disks = MFI_MAX_LD;
1141 }
e8f943c3
HR		 1142 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1143 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
e8f943c3
HR		 1144
1145 if (num_ld_disks >= max_ld_disks) {
1146 break;
1147 }
1148 /* Logical device size is in blocks */
4be74634 1149 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1150 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1151 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1152 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1153 num_ld_disks++;
1154 }
1155 info.ld_count = cpu_to_le32(num_ld_disks);
1156 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1157
1158 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1159 cmd->iov_size = dcmd_size - resid;
1160 return MFI_STAT_OK;
1161}
1162
34bb4d02
HR		 1163static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1164{
1165 uint16_t flags;
d97ae368
HR		 1166 struct mfi_ld_targetid_list info;
1167 size_t dcmd_size = sizeof(info), resid;
1168 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1169 BusChild *kid;
34bb4d02
HR		 1170
1171 /* mbox0 contains flags */
1172 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1173 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
d97ae368
HR		 1174 if (flags != MR_LD_QUERY_TYPE_ALL &&
1175 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1176 max_ld_disks = 0;
1177 }
1178
1179 memset(&info, 0, dcmd_size);
1180 if (cmd->iov_size < 12) {
1181 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1182 dcmd_size);
1183 return MFI_STAT_INVALID_PARAMETER;
1184 }
1185 dcmd_size = sizeof(uint32_t) * 2 + 3;
3f2cd4dd 1186 max_ld_disks = cmd->iov_size - dcmd_size;
d97ae368
HR		 1187 if (megasas_is_jbod(s)) {
1188 max_ld_disks = 0;
34bb4d02 1189 }
3f2cd4dd
HR		 1190 if (max_ld_disks > MFI_MAX_LD) {
1191 max_ld_disks = MFI_MAX_LD;
1192 }
d97ae368
HR		 1193 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1194 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
34bb4d02 1195
d97ae368
HR		 1196 if (num_ld_disks >= max_ld_disks) {
1197 break;
1198 }
1199 info.targetid[num_ld_disks] = sdev->lun;
1200 num_ld_disks++;
1201 dcmd_size++;
1202 }
1203 info.ld_count = cpu_to_le32(num_ld_disks);
1204 info.size = dcmd_size;
1205 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1206
1207 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1208 cmd->iov_size = dcmd_size - resid;
34bb4d02
HR		 1209 return MFI_STAT_OK;
1210}
1211
e8f943c3
HR		 1212static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1213 MegasasCmd *cmd)
1214{
1215 struct mfi_ld_info *info = cmd->iov_buf;
1216 size_t dcmd_size = sizeof(struct mfi_ld_info);
1217 uint8_t cdb[6];
1218 SCSIRequest *req;
1219 ssize_t len, resid;
3f2cd4dd 1220 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1221 uint64_t ld_size;
1222
1223 if (!cmd->iov_buf) {
0bd0adbe 1224 cmd->iov_buf = g_malloc0(dcmd_size);
e8f943c3
HR		 1225 info = cmd->iov_buf;
1226 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1227 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1228 if (!req) {
1229 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1230 "LD get info vpd inquiry");
1231 g_free(cmd->iov_buf);
1232 cmd->iov_buf = NULL;
1233 return MFI_STAT_FLASH_ALLOC_FAIL;
1234 }
1235 trace_megasas_dcmd_internal_submit(cmd->index,
1236 "LD get info vpd inquiry", lun);
1237 len = scsi_req_enqueue(req);
1238 if (len > 0) {
1239 cmd->iov_size = len;
1240 scsi_req_continue(req);
1241 }
1242 return MFI_STAT_INVALID_STATUS;
1243 }
1244
1245 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1246 info->ld_config.properties.ld.v.target_id = lun;
1247 info->ld_config.params.stripe_size = 3;
1248 info->ld_config.params.num_drives = 1;
1249 info->ld_config.params.is_consistent = 1;
1250 /* Logical device size is in blocks */
4be74634 1251 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1252 info->size = cpu_to_le64(ld_size);
1253 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1254 info->ld_config.span[0].start_block = 0;
1255 info->ld_config.span[0].num_blocks = info->size;
1256 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1257
1258 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1259 g_free(cmd->iov_buf);
1260 cmd->iov_size = dcmd_size - resid;
1261 cmd->iov_buf = NULL;
1262 return MFI_STAT_OK;
1263}
1264
1265static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1266{
1267 struct mfi_ld_info info;
1268 size_t dcmd_size = sizeof(info);
1269 uint16_t ld_id;
1270 uint32_t max_ld_disks = s->fw_luns;
1271 SCSIDevice *sdev = NULL;
1272 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1273
1274 if (cmd->iov_size < dcmd_size) {
1275 return MFI_STAT_INVALID_PARAMETER;
1276 }
1277
1278 /* mbox0 has the ID */
1279 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1280 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1281
1282 if (megasas_is_jbod(s)) {
1283 return MFI_STAT_DEVICE_NOT_FOUND;
1284 }
1285
1286 if (ld_id < max_ld_disks) {
1287 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1288 }
1289
1290 if (sdev) {
1291 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1292 }
1293
1294 return retval;
1295}
1296
1297static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1298{
1299 uint8_t data[4096];
1300 struct mfi_config_data *info;
1301 int num_pd_disks = 0, array_offset, ld_offset;
1302 BusChild *kid;
1303
1304 if (cmd->iov_size > 4096) {
1305 return MFI_STAT_INVALID_PARAMETER;
1306 }
1307
1308 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1309 num_pd_disks++;
1310 }
1311 info = (struct mfi_config_data *)&data;
1312 /*
1313 * Array mapping:
1314 * - One array per SCSI device
1315 * - One logical drive per SCSI device
1316 * spanning the entire device
1317 */
1318 info->array_count = num_pd_disks;
1319 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1320 info->log_drv_count = num_pd_disks;
1321 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1322 info->spares_count = 0;
1323 info->spares_size = sizeof(struct mfi_spare);
1324 info->size = sizeof(struct mfi_config_data) + info->array_size +
1325 info->log_drv_size;
1326 if (info->size > 4096) {
1327 return MFI_STAT_INVALID_PARAMETER;
1328 }
1329
1330 array_offset = sizeof(struct mfi_config_data);
1331 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1332
1333 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1334 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd 1335 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
e8f943c3
HR		 1336 struct mfi_array *array;
1337 struct mfi_ld_config *ld;
1338 uint64_t pd_size;
1339 int i;
1340
1341 array = (struct mfi_array *)(data + array_offset);
4be74634 1342 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1343 array->size = cpu_to_le64(pd_size);
1344 array->num_drives = 1;
1345 array->array_ref = cpu_to_le16(sdev_id);
1346 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1347 array->pd[0].ref.v.seq_num = 0;
1348 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1349 array->pd[0].encl.pd = 0xFF;
1350 array->pd[0].encl.slot = (sdev->id & 0xFF);
1351 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1352 array->pd[i].ref.v.device_id = 0xFFFF;
1353 array->pd[i].ref.v.seq_num = 0;
1354 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1355 array->pd[i].encl.pd = 0xFF;
1356 array->pd[i].encl.slot = 0xFF;
1357 }
1358 array_offset += sizeof(struct mfi_array);
1359 ld = (struct mfi_ld_config *)(data + ld_offset);
1360 memset(ld, 0, sizeof(struct mfi_ld_config));
3f2cd4dd 1361 ld->properties.ld.v.target_id = sdev->id;
e8f943c3
HR		 1362 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1363 MR_LD_CACHE_READ_ADAPTIVE;
1364 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1365 MR_LD_CACHE_READ_ADAPTIVE;
1366 ld->params.state = MFI_LD_STATE_OPTIMAL;
1367 ld->params.stripe_size = 3;
1368 ld->params.num_drives = 1;
1369 ld->params.span_depth = 1;
1370 ld->params.is_consistent = 1;
1371 ld->span[0].start_block = 0;
1372 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1373 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1374 ld_offset += sizeof(struct mfi_ld_config);
1375 }
1376
1377 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1378 return MFI_STAT_OK;
1379}
1380
1381static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1382{
1383 struct mfi_ctrl_props info;
1384 size_t dcmd_size = sizeof(info);
1385
1386 memset(&info, 0x0, dcmd_size);
1387 if (cmd->iov_size < dcmd_size) {
1388 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1389 dcmd_size);
1390 return MFI_STAT_INVALID_PARAMETER;
1391 }
1392 info.pred_fail_poll_interval = cpu_to_le16(300);
1393 info.intr_throttle_cnt = cpu_to_le16(16);
1394 info.intr_throttle_timeout = cpu_to_le16(50);
1395 info.rebuild_rate = 30;
1396 info.patrol_read_rate = 30;
1397 info.bgi_rate = 30;
1398 info.cc_rate = 30;
1399 info.recon_rate = 30;
1400 info.cache_flush_interval = 4;
1401 info.spinup_drv_cnt = 2;
1402 info.spinup_delay = 6;
1403 info.ecc_bucket_size = 15;
1404 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1405 info.expose_encl_devices = 1;
1406
1407 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1408 return MFI_STAT_OK;
1409}
1410
1411static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1412{
4be74634 1413 blk_drain_all();
e8f943c3
HR		 1414 return MFI_STAT_OK;
1415}
1416
1417static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1418{
1419 s->fw_state = MFI_FWSTATE_READY;
1420 return MFI_STAT_OK;
1421}
1422
200b6966 1423/* Some implementations use CLUSTER RESET LD to simulate a device reset */
e8f943c3
HR		 1424static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1425{
200b6966
HR		 1426 uint16_t target_id;
1427 int i;
1428
1429 /* mbox0 contains the device index */
1430 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1431 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1432 for (i = 0; i < s->fw_cmds; i++) {
1433 MegasasCmd *tmp_cmd = &s->frames[i];
1434 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1435 SCSIDevice *d = tmp_cmd->req->dev;
1436 qdev_reset_all(&d->qdev);
1437 }
1438 }
1439 return MFI_STAT_OK;
e8f943c3
HR		 1440}
1441
1442static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1443{
10d6530c
HR		 1444 struct mfi_ctrl_props info;
1445 size_t dcmd_size = sizeof(info);
1446
1447 if (cmd->iov_size < dcmd_size) {
1448 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1449 dcmd_size);
1450 return MFI_STAT_INVALID_PARAMETER;
1451 }
1452 dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg);
1453 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1454 return MFI_STAT_OK;
1455}
1456
1457static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1458{
1459 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1460 return MFI_STAT_OK;
1461}
1462
1463static const struct dcmd_cmd_tbl_t {
1464 int opcode;
1465 const char *desc;
1466 int (*func)(MegasasState *s, MegasasCmd *cmd);
1467} dcmd_cmd_tbl[] = {
1468 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1469 megasas_dcmd_dummy },
1470 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1471 megasas_ctrl_get_info },
1472 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1473 megasas_dcmd_get_properties },
1474 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1475 megasas_dcmd_set_properties },
1476 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1477 megasas_dcmd_dummy },
1478 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1479 megasas_dcmd_dummy },
1480 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1481 megasas_dcmd_dummy },
1482 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1483 megasas_dcmd_dummy },
1484 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1485 megasas_dcmd_dummy },
1486 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1487 megasas_event_info },
1488 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1489 megasas_dcmd_dummy },
1490 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1491 megasas_event_wait },
1492 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1493 megasas_ctrl_shutdown },
1494 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1495 megasas_dcmd_dummy },
1496 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1497 megasas_dcmd_get_fw_time },
1498 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1499 megasas_dcmd_set_fw_time },
1500 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1501 megasas_dcmd_get_bios_info },
1502 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1503 megasas_dcmd_dummy },
1504 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1505 megasas_mfc_get_defaults },
1506 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1507 megasas_dcmd_dummy },
1508 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1509 megasas_cache_flush },
1510 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1511 megasas_dcmd_pd_get_list },
1512 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1513 megasas_dcmd_pd_list_query },
1514 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1515 megasas_dcmd_pd_get_info },
1516 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1517 megasas_dcmd_dummy },
1518 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1519 megasas_dcmd_dummy },
1520 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1521 megasas_dcmd_dummy },
1522 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1523 megasas_dcmd_dummy },
1524 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1525 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1526 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1527 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1528 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1529 megasas_dcmd_ld_get_info },
1530 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1531 megasas_dcmd_dummy },
1532 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1533 megasas_dcmd_dummy },
1534 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1535 megasas_dcmd_dummy },
1536 { MFI_DCMD_CFG_READ, "CFG_READ",
1537 megasas_dcmd_cfg_read },
1538 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1539 megasas_dcmd_dummy },
1540 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1541 megasas_dcmd_dummy },
1542 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1543 megasas_dcmd_dummy },
1544 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1545 megasas_dcmd_dummy },
1546 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1547 megasas_dcmd_dummy },
1548 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1549 megasas_dcmd_dummy },
1550 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1551 megasas_dcmd_dummy },
1552 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1553 megasas_dcmd_dummy },
1554 { MFI_DCMD_CLUSTER, "CLUSTER",
1555 megasas_dcmd_dummy },
1556 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1557 megasas_dcmd_dummy },
1558 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1559 megasas_cluster_reset_ld },
1560 { -1, NULL, NULL }
1561};
1562
1563static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1564{
1565 int opcode, len;
1566 int retval = 0;
1567 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1568
1569 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1570 trace_megasas_handle_dcmd(cmd->index, opcode);
1571 len = megasas_map_dcmd(s, cmd);
1572 if (len < 0) {
1573 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1574 }
1575 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1576 cmdptr++;
1577 }
1578 if (cmdptr->opcode == -1) {
1579 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1580 retval = megasas_dcmd_dummy(s, cmd);
1581 } else {
1582 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1583 retval = cmdptr->func(s, cmd);
1584 }
1585 if (retval != MFI_STAT_INVALID_STATUS) {
1586 megasas_finish_dcmd(cmd, len);
1587 }
1588 return retval;
1589}
1590
1591static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1592 SCSIRequest *req)
1593{
1594 int opcode;
1595 int retval = MFI_STAT_OK;
1596 int lun = req->lun;
1597
1598 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1599 scsi_req_unref(req);
1600 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1601 switch (opcode) {
1602 case MFI_DCMD_PD_GET_INFO:
1603 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1604 break;
1605 case MFI_DCMD_LD_GET_INFO:
1606 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1607 break;
1608 default:
1609 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1610 retval = MFI_STAT_INVALID_DCMD;
1611 break;
1612 }
1613 if (retval != MFI_STAT_INVALID_STATUS) {
1614 megasas_finish_dcmd(cmd, cmd->iov_size);
1615 }
1616 return retval;
1617}
1618
1619static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1620{
1621 int len;
1622
1623 len = scsi_req_enqueue(cmd->req);
1624 if (len < 0) {
1625 len = -len;
1626 }
1627 if (len > 0) {
1628 if (len > cmd->iov_size) {
1629 if (is_write) {
1630 trace_megasas_iov_write_overflow(cmd->index, len,
1631 cmd->iov_size);
1632 } else {
1633 trace_megasas_iov_read_overflow(cmd->index, len,
1634 cmd->iov_size);
1635 }
1636 }
1637 if (len < cmd->iov_size) {
1638 if (is_write) {
1639 trace_megasas_iov_write_underflow(cmd->index, len,
1640 cmd->iov_size);
1641 } else {
1642 trace_megasas_iov_read_underflow(cmd->index, len,
1643 cmd->iov_size);
1644 }
1645 cmd->iov_size = len;
1646 }
1647 scsi_req_continue(cmd->req);
1648 }
1649 return len;
1650}
1651
1652static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1653 bool is_logical)
1654{
1655 uint8_t *cdb;
e8f943c3
HR		 1656 bool is_write;
1657 struct SCSIDevice *sdev = NULL;
1658
1659 cdb = cmd->frame->pass.cdb;
1660
3f2cd4dd
HR		 1661 if (is_logical) {
1662 if (cmd->frame->header.target_id >= MFI_MAX_LD ||
1663 cmd->frame->header.lun_id != 0) {
1664 trace_megasas_scsi_target_not_present(
1665 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1666 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1667 return MFI_STAT_DEVICE_NOT_FOUND;
1668 }
e8f943c3 1669 }
3f2cd4dd
HR		 1670 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1671 cmd->frame->header.lun_id);
1672
e8f943c3
HR		 1673 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1674 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1675 is_logical, cmd->frame->header.target_id,
1676 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1677
1678 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1679 trace_megasas_scsi_target_not_present(
1680 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1681 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1682 return MFI_STAT_DEVICE_NOT_FOUND;
1683 }
1684
1685 if (cmd->frame->header.cdb_len > 16) {
1686 trace_megasas_scsi_invalid_cdb_len(
1687 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1688 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1689 cmd->frame->header.cdb_len);
1690 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1691 cmd->frame->header.scsi_status = CHECK_CONDITION;
1692 s->event_count++;
1693 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1694 }
1695
1696 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1697 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1698 cmd->frame->header.scsi_status = CHECK_CONDITION;
1699 s->event_count++;
1700 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1701 }
1702
1703 cmd->req = scsi_req_new(sdev, cmd->index,
1704 cmd->frame->header.lun_id, cdb, cmd);
1705 if (!cmd->req) {
1706 trace_megasas_scsi_req_alloc_failed(
1707 mfi_frame_desc[cmd->frame->header.frame_cmd],
1708 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1709 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1710 cmd->frame->header.scsi_status = BUSY;
1711 s->event_count++;
1712 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1713 }
1714
1715 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
aaf2a859 1716 if (cmd->iov_size) {
e8f943c3 1717 if (is_write) {
aaf2a859 1718 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
e8f943c3 1719 } else {
aaf2a859 1720 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
e8f943c3
HR		 1721 }
1722 } else {
1723 trace_megasas_scsi_nodata(cmd->index);
1724 }
aaf2a859 1725 megasas_enqueue_req(cmd, is_write);
e8f943c3
HR		 1726 return MFI_STAT_INVALID_STATUS;
1727}
1728
1729static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1730{
1731 uint32_t lba_count, lba_start_hi, lba_start_lo;
1732 uint64_t lba_start;
1733 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1734 uint8_t cdb[16];
1735 int len;
1736 struct SCSIDevice *sdev = NULL;
1737
1738 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1739 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1740 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1741 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1742
3f2cd4dd
HR		 1743 if (cmd->frame->header.target_id < MFI_MAX_LD &&
1744 cmd->frame->header.lun_id == 0) {
e8f943c3
HR		 1745 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1746 cmd->frame->header.lun_id);
1747 }
1748
1749 trace_megasas_handle_io(cmd->index,
1750 mfi_frame_desc[cmd->frame->header.frame_cmd],
1751 cmd->frame->header.target_id,
1752 cmd->frame->header.lun_id,
1753 (unsigned long)lba_start, (unsigned long)lba_count);
1754 if (!sdev) {
1755 trace_megasas_io_target_not_present(cmd->index,
1756 mfi_frame_desc[cmd->frame->header.frame_cmd],
1757 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1758 return MFI_STAT_DEVICE_NOT_FOUND;
1759 }
1760
1761 if (cmd->frame->header.cdb_len > 16) {
1762 trace_megasas_scsi_invalid_cdb_len(
1763 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1764 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1765 cmd->frame->header.cdb_len);
1766 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1767 cmd->frame->header.scsi_status = CHECK_CONDITION;
1768 s->event_count++;
1769 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1770 }
1771
1772 cmd->iov_size = lba_count * sdev->blocksize;
1773 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1774 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1775 cmd->frame->header.scsi_status = CHECK_CONDITION;
1776 s->event_count++;
1777 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1778 }
1779
1780 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1781 cmd->req = scsi_req_new(sdev, cmd->index,
1782 cmd->frame->header.lun_id, cdb, cmd);
1783 if (!cmd->req) {
1784 trace_megasas_scsi_req_alloc_failed(
1785 mfi_frame_desc[cmd->frame->header.frame_cmd],
1786 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1787 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1788 cmd->frame->header.scsi_status = BUSY;
1789 s->event_count++;
1790 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1791 }
1792 len = megasas_enqueue_req(cmd, is_write);
1793 if (len > 0) {
1794 if (is_write) {
1795 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1796 } else {
1797 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1798 }
1799 }
1800 return MFI_STAT_INVALID_STATUS;
1801}
1802
1803static int megasas_finish_internal_command(MegasasCmd *cmd,
1804 SCSIRequest *req, size_t resid)
1805{
1806 int retval = MFI_STAT_INVALID_CMD;
1807
1808 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1809 cmd->iov_size -= resid;
1810 retval = megasas_finish_internal_dcmd(cmd, req);
1811 }
1812 return retval;
1813}
1814
1815static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1816{
1817 MegasasCmd *cmd = req->hba_private;
1818
1819 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1820 return NULL;
1821 } else {
1822 return &cmd->qsg;
1823 }
1824}
1825
1826static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1827{
1828 MegasasCmd *cmd = req->hba_private;
1829 uint8_t *buf;
1830 uint32_t opcode;
1831
1832 trace_megasas_io_complete(cmd->index, len);
1833
1834 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1835 scsi_req_continue(req);
1836 return;
1837 }
1838
1839 buf = scsi_req_get_buf(req);
1840 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1841 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1842 struct mfi_pd_info *info = cmd->iov_buf;
1843
1844 if (info->inquiry_data[0] == 0x7f) {
1845 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1846 memcpy(info->inquiry_data, buf, len);
1847 } else if (info->vpd_page83[0] == 0x7f) {
1848 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1849 memcpy(info->vpd_page83, buf, len);
1850 }
1851 scsi_req_continue(req);
1852 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1853 struct mfi_ld_info *info = cmd->iov_buf;
1854
1855 if (cmd->iov_buf) {
1856 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1857 scsi_req_continue(req);
1858 }
1859 }
1860}
1861
1862static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1863 size_t resid)
1864{
1865 MegasasCmd *cmd = req->hba_private;
1866 uint8_t cmd_status = MFI_STAT_OK;
1867
1868 trace_megasas_command_complete(cmd->index, status, resid);
1869
1870 if (cmd->req != req) {
1871 /*
1872 * Internal command complete
1873 */
1874 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1875 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1876 return;
1877 }
1878 } else {
1879 req->status = status;
1880 trace_megasas_scsi_complete(cmd->index, req->status,
1881 cmd->iov_size, req->cmd.xfer);
1882 if (req->status != GOOD) {
1883 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1884 }
1885 if (req->status == CHECK_CONDITION) {
1886 megasas_copy_sense(cmd);
1887 }
1888
1889 megasas_unmap_sgl(cmd);
1890 cmd->frame->header.scsi_status = req->status;
1891 scsi_req_unref(cmd->req);
1892 cmd->req = NULL;
1893 }
1894 cmd->frame->header.cmd_status = cmd_status;
6df5718b 1895 megasas_unmap_frame(cmd->state, cmd);
e8f943c3
HR		 1896 megasas_complete_frame(cmd->state, cmd->context);
1897}
1898
1899static void megasas_command_cancel(SCSIRequest *req)
1900{
1901 MegasasCmd *cmd = req->hba_private;
1902
1903 if (cmd) {
1904 megasas_abort_command(cmd);
1905 } else {
1906 scsi_req_unref(req);
1907 }
1908}
1909
1910static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1911{
1912 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1913 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1914 MegasasCmd *abort_cmd;
1915
1916 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1917 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1918 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1919
1920 abort_cmd = megasas_lookup_frame(s, abort_addr);
1921 if (!abort_cmd) {
1922 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1923 s->event_count++;
1924 return MFI_STAT_OK;
1925 }
1926 if (!megasas_use_queue64(s)) {
1927 abort_ctx &= (uint64_t)0xFFFFFFFF;
1928 }
1929 if (abort_cmd->context != abort_ctx) {
1930 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1931 abort_cmd->context);
1932 s->event_count++;
1933 return MFI_STAT_ABORT_NOT_POSSIBLE;
1934 }
1935 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1936 megasas_abort_command(abort_cmd);
1937 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1938 s->event_cmd = NULL;
1939 }
1940 s->event_count++;
1941 return MFI_STAT_OK;
1942}
1943
1944static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1945 uint32_t frame_count)
1946{
1947 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1948 uint64_t frame_context;
1949 MegasasCmd *cmd;
1950
1951 /*
1952 * Always read 64bit context, top bits will be
1953 * masked out if required in megasas_enqueue_frame()
1954 */
1955 frame_context = megasas_frame_get_context(frame_addr);
1956
1957 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1958 if (!cmd) {
1959 /* reply queue full */
1960 trace_megasas_frame_busy(frame_addr);
1961 megasas_frame_set_scsi_status(frame_addr, BUSY);
1962 megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1963 megasas_complete_frame(s, frame_context);
1964 s->event_count++;
1965 return;
1966 }
1967 switch (cmd->frame->header.frame_cmd) {
1968 case MFI_CMD_INIT:
1969 frame_status = megasas_init_firmware(s, cmd);
1970 break;
1971 case MFI_CMD_DCMD:
1972 frame_status = megasas_handle_dcmd(s, cmd);
1973 break;
1974 case MFI_CMD_ABORT:
1975 frame_status = megasas_handle_abort(s, cmd);
1976 break;
1977 case MFI_CMD_PD_SCSI_IO:
1978 frame_status = megasas_handle_scsi(s, cmd, 0);
1979 break;
1980 case MFI_CMD_LD_SCSI_IO:
1981 frame_status = megasas_handle_scsi(s, cmd, 1);
1982 break;
1983 case MFI_CMD_LD_READ:
1984 case MFI_CMD_LD_WRITE:
1985 frame_status = megasas_handle_io(s, cmd);
1986 break;
1987 default:
1988 trace_megasas_unhandled_frame_cmd(cmd->index,
1989 cmd->frame->header.frame_cmd);
1990 s->event_count++;
1991 break;
1992 }
1993 if (frame_status != MFI_STAT_INVALID_STATUS) {
1994 if (cmd->frame) {
1995 cmd->frame->header.cmd_status = frame_status;
1996 } else {
1997 megasas_frame_set_cmd_status(frame_addr, frame_status);
1998 }
6df5718b 1999 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 2000 megasas_complete_frame(s, cmd->context);
2001 }
2002}
2003
a8170e5e 2004static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2005 unsigned size)
2006{
2007 MegasasState *s = opaque;
e23d0498
HR		 2008 PCIDevice *pci_dev = PCI_DEVICE(s);
2009 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2010 uint32_t retval = 0;
2011
2012 switch (addr) {
2013 case MFI_IDB:
2014 retval = 0;
77bb6b17 2015 trace_megasas_mmio_readl("MFI_IDB", retval);
e8f943c3
HR		 2016 break;
2017 case MFI_OMSG0:
2018 case MFI_OSP0:
e23d0498 2019 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
e8f943c3
HR		 2020 (s->fw_state & MFI_FWSTATE_MASK) |
2021 ((s->fw_sge & 0xff) << 16) |
2022 (s->fw_cmds & 0xFFFF);
77bb6b17
HR		 2023 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2024 retval);
e8f943c3
HR		 2025 break;
2026 case MFI_OSTS:
2027 if (megasas_intr_enabled(s) && s->doorbell) {
e23d0498 2028 retval = base_class->osts;
e8f943c3 2029 }
77bb6b17 2030 trace_megasas_mmio_readl("MFI_OSTS", retval);
e8f943c3
HR		 2031 break;
2032 case MFI_OMSK:
2033 retval = s->intr_mask;
77bb6b17 2034 trace_megasas_mmio_readl("MFI_OMSK", retval);
e8f943c3
HR		 2035 break;
2036 case MFI_ODCR0:
7957ee71 2037 retval = s->doorbell ? 1 : 0;
77bb6b17 2038 trace_megasas_mmio_readl("MFI_ODCR0", retval);
e8f943c3 2039 break;
e23d0498
HR		 2040 case MFI_DIAG:
2041 retval = s->diag;
77bb6b17 2042 trace_megasas_mmio_readl("MFI_DIAG", retval);
e23d0498
HR		 2043 break;
2044 case MFI_OSP1:
2045 retval = 15;
77bb6b17 2046 trace_megasas_mmio_readl("MFI_OSP1", retval);
e23d0498 2047 break;
e8f943c3
HR		 2048 default:
2049 trace_megasas_mmio_invalid_readl(addr);
2050 break;
2051 }
e8f943c3
HR		 2052 return retval;
2053}
2054
e23d0498
HR		 2055static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2056
a8170e5e 2057static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2058 uint64_t val, unsigned size)
2059{
2060 MegasasState *s = opaque;
52190c1e 2061 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 2062 uint64_t frame_addr;
2063 uint32_t frame_count;
2064 int i;
2065
e8f943c3
HR		 2066 switch (addr) {
2067 case MFI_IDB:
77bb6b17 2068 trace_megasas_mmio_writel("MFI_IDB", val);
e8f943c3
HR		 2069 if (val & MFI_FWINIT_ABORT) {
2070 /* Abort all pending cmds */
2071 for (i = 0; i < s->fw_cmds; i++) {
2072 megasas_abort_command(&s->frames[i]);
2073 }
2074 }
2075 if (val & MFI_FWINIT_READY) {
2076 /* move to FW READY */
2077 megasas_soft_reset(s);
2078 }
2079 if (val & MFI_FWINIT_MFIMODE) {
2080 /* discard MFIs */
2081 }
e23d0498
HR		 2082 if (val & MFI_FWINIT_STOP_ADP) {
2083 /* Terminal error, stop processing */
2084 s->fw_state = MFI_FWSTATE_FAULT;
2085 }
e8f943c3
HR		 2086 break;
2087 case MFI_OMSK:
77bb6b17 2088 trace_megasas_mmio_writel("MFI_OMSK", val);
e8f943c3 2089 s->intr_mask = val;
4522b69c
HR		 2090 if (!megasas_intr_enabled(s) &&
2091 !msi_enabled(pci_dev) &&
2092 !msix_enabled(pci_dev)) {
e8f943c3 2093 trace_megasas_irq_lower();
9e64f8a3 2094 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2095 }
2096 if (megasas_intr_enabled(s)) {
4522b69c
HR		 2097 if (msix_enabled(pci_dev)) {
2098 trace_megasas_msix_enabled(0);
2099 } else if (msi_enabled(pci_dev)) {
2100 trace_megasas_msi_enabled(0);
2101 } else {
2102 trace_megasas_intr_enabled();
2103 }
e8f943c3
HR		 2104 } else {
2105 trace_megasas_intr_disabled();
e23d0498 2106 megasas_soft_reset(s);
e8f943c3
HR		 2107 }
2108 break;
2109 case MFI_ODCR0:
77bb6b17 2110 trace_megasas_mmio_writel("MFI_ODCR0", val);
e8f943c3 2111 s->doorbell = 0;
7957ee71
HR		 2112 if (megasas_intr_enabled(s)) {
2113 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
e8f943c3 2114 trace_megasas_irq_lower();
9e64f8a3 2115 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2116 }
2117 }
2118 break;
2119 case MFI_IQPH:
77bb6b17 2120 trace_megasas_mmio_writel("MFI_IQPH", val);
e8f943c3
HR		 2121 /* Received high 32 bits of a 64 bit MFI frame address */
2122 s->frame_hi = val;
2123 break;
2124 case MFI_IQPL:
77bb6b17 2125 trace_megasas_mmio_writel("MFI_IQPL", val);
e8f943c3 2126 /* Received low 32 bits of a 64 bit MFI frame address */
e23d0498 2127 /* Fallthrough */
e8f943c3 2128 case MFI_IQP:
77bb6b17
HR		 2129 if (addr == MFI_IQP) {
2130 trace_megasas_mmio_writel("MFI_IQP", val);
2131 /* Received 64 bit MFI frame address */
2132 s->frame_hi = 0;
2133 }
e8f943c3
HR		 2134 frame_addr = (val & ~0x1F);
2135 /* Add possible 64 bit offset */
2136 frame_addr |= ((uint64_t)s->frame_hi << 32);
2137 s->frame_hi = 0;
2138 frame_count = (val >> 1) & 0xF;
2139 megasas_handle_frame(s, frame_addr, frame_count);
2140 break;
e23d0498 2141 case MFI_SEQ:
77bb6b17 2142 trace_megasas_mmio_writel("MFI_SEQ", val);
e23d0498
HR		 2143 /* Magic sequence to start ADP reset */
2144 if (adp_reset_seq[s->adp_reset] == val) {
2145 s->adp_reset++;
2146 } else {
2147 s->adp_reset = 0;
2148 s->diag = 0;
2149 }
2150 if (s->adp_reset == 6) {
2151 s->diag = MFI_DIAG_WRITE_ENABLE;
2152 }
2153 break;
2154 case MFI_DIAG:
77bb6b17 2155 trace_megasas_mmio_writel("MFI_DIAG", val);
e23d0498
HR		 2156 /* ADP reset */
2157 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2158 (val & MFI_DIAG_RESET_ADP)) {
2159 s->diag |= MFI_DIAG_RESET_ADP;
2160 megasas_soft_reset(s);
2161 s->adp_reset = 0;
2162 s->diag = 0;
2163 }
2164 break;
e8f943c3
HR		 2165 default:
2166 trace_megasas_mmio_invalid_writel(addr, val);
2167 break;
2168 }
2169}
2170
2171static const MemoryRegionOps megasas_mmio_ops = {
2172 .read = megasas_mmio_read,
2173 .write = megasas_mmio_write,
2174 .endianness = DEVICE_LITTLE_ENDIAN,
2175 .impl = {
2176 .min_access_size = 8,
2177 .max_access_size = 8,
2178 }
2179};
2180
a8170e5e 2181static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2182 unsigned size)
2183{
2184 return megasas_mmio_read(opaque, addr & 0xff, size);
2185}
2186
a8170e5e 2187static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2188 uint64_t val, unsigned size)
2189{
2190 megasas_mmio_write(opaque, addr & 0xff, val, size);
2191}
2192
2193static const MemoryRegionOps megasas_port_ops = {
2194 .read = megasas_port_read,
2195 .write = megasas_port_write,
2196 .endianness = DEVICE_LITTLE_ENDIAN,
2197 .impl = {
2198 .min_access_size = 4,
2199 .max_access_size = 4,
2200 }
2201};
2202
a8170e5e 2203static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2204 unsigned size)
2205{
2206 return 0;
2207}
2208
2209static const MemoryRegionOps megasas_queue_ops = {
2210 .read = megasas_queue_read,
2211 .endianness = DEVICE_LITTLE_ENDIAN,
2212 .impl = {
2213 .min_access_size = 8,
2214 .max_access_size = 8,
2215 }
2216};
2217
2218static void megasas_soft_reset(MegasasState *s)
2219{
2220 int i;
2221 MegasasCmd *cmd;
2222
8d72db68 2223 trace_megasas_reset(s->fw_state);
e8f943c3
HR		 2224 for (i = 0; i < s->fw_cmds; i++) {
2225 cmd = &s->frames[i];
2226 megasas_abort_command(cmd);
2227 }
8d72db68
HR		 2228 if (s->fw_state == MFI_FWSTATE_READY) {
2229 BusChild *kid;
2230
2231 /*
2232 * The EFI firmware doesn't handle UA,
2233 * so we need to clear the Power On/Reset UA
2234 * after the initial reset.
2235 */
2236 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2237 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
2238
2239 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2240 scsi_device_unit_attention_reported(sdev);
2241 }
2242 }
e8f943c3
HR		 2243 megasas_reset_frames(s);
2244 s->reply_queue_len = s->fw_cmds;
2245 s->reply_queue_pa = 0;
2246 s->consumer_pa = 0;
2247 s->producer_pa = 0;
2248 s->fw_state = MFI_FWSTATE_READY;
2249 s->doorbell = 0;
2250 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2251 s->frame_hi = 0;
2252 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2253 s->event_count++;
2254 s->boot_event = s->event_count;
2255}
2256
2257static void megasas_scsi_reset(DeviceState *dev)
2258{
c79e16ae 2259 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2260
2261 megasas_soft_reset(s);
2262}
2263
e23d0498 2264static const VMStateDescription vmstate_megasas_gen1 = {
e8f943c3
HR		 2265 .name = "megasas",
2266 .version_id = 0,
2267 .minimum_version_id = 0,
d49805ae 2268 .fields = (VMStateField[]) {
52190c1e 2269 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2270 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3
HR		 2271
2272 VMSTATE_INT32(fw_state, MegasasState),
2273 VMSTATE_INT32(intr_mask, MegasasState),
2274 VMSTATE_INT32(doorbell, MegasasState),
2275 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2276 VMSTATE_UINT64(consumer_pa, MegasasState),
2277 VMSTATE_UINT64(producer_pa, MegasasState),
2278 VMSTATE_END_OF_LIST()
2279 }
2280};
2281
e23d0498
HR		 2282static const VMStateDescription vmstate_megasas_gen2 = {
2283 .name = "megasas-gen2",
2284 .version_id = 0,
2285 .minimum_version_id = 0,
2286 .minimum_version_id_old = 0,
2287 .fields = (VMStateField[]) {
2288 VMSTATE_PCIE_DEVICE(parent_obj, MegasasState),
2289 VMSTATE_MSIX(parent_obj, MegasasState),
2290
2291 VMSTATE_INT32(fw_state, MegasasState),
2292 VMSTATE_INT32(intr_mask, MegasasState),
2293 VMSTATE_INT32(doorbell, MegasasState),
2294 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2295 VMSTATE_UINT64(consumer_pa, MegasasState),
2296 VMSTATE_UINT64(producer_pa, MegasasState),
2297 VMSTATE_END_OF_LIST()
2298 }
2299};
2300
18fc611b 2301static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2302{
c79e16ae 2303 MegasasState *s = MEGASAS(d);
e8f943c3 2304
4522b69c
HR		 2305 if (megasas_use_msix(s)) {
2306 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2307 }
2308 if (megasas_use_msi(s)) {
2309 msi_uninit(d);
2310 }
e8f943c3
HR		 2311}
2312
2313static const struct SCSIBusInfo megasas_scsi_info = {
2314 .tcq = true,
2315 .max_target = MFI_MAX_LD,
2316 .max_lun = 255,
2317
2318 .transfer_data = megasas_xfer_complete,
2319 .get_sg_list = megasas_get_sg_list,
2320 .complete = megasas_command_complete,
2321 .cancel = megasas_command_cancel,
2322};
2323
2324static int megasas_scsi_init(PCIDevice *dev)
2325{
22d6aa03 2326 DeviceState *d = DEVICE(dev);
c79e16ae 2327 MegasasState *s = MEGASAS(dev);
e23d0498 2328 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2329 uint8_t *pci_conf;
2330 int i, bar_type;
caad4eb3 2331 Error *err = NULL;
e8f943c3 2332
52190c1e 2333 pci_conf = dev->config;
e8f943c3
HR		 2334
2335 /* PCI latency timer = 0 */
2336 pci_conf[PCI_LATENCY_TIMER] = 0;
2337 /* Interrupt pin 1 */
2338 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2339
29776739 2340 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2341 "megasas-mmio", 0x4000);
29776739 2342 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2343 "megasas-io", 256);
29776739 2344 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2345 "megasas-queue", 0x40000);
2346
4522b69c
HR		 2347 if (megasas_use_msi(s) &&
2348 msi_init(dev, 0x50, 1, true, false)) {
2349 s->flags &= ~MEGASAS_MASK_USE_MSI;
2350 }
e8f943c3 2351 if (megasas_use_msix(s) &&
e23d0498
HR		 2352 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2353 &s->mmio_io, b->mmio_bar, 0x3800, 0x68)) {
e8f943c3
HR		 2354 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2355 }
e23d0498
HR		 2356 if (pci_is_express(dev)) {
2357 pcie_endpoint_cap_init(dev, 0xa0);
2358 }
e8f943c3
HR		 2359
2360 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
e23d0498
HR		 2361 pci_register_bar(dev, b->ioport_bar,
2362 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2363 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
52190c1e 2364 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2365
2366 if (megasas_use_msix(s)) {
52190c1e 2367 msix_vector_use(dev, 0);
e8f943c3
HR		 2368 }
2369
8d72db68 2370 s->fw_state = MFI_FWSTATE_READY;
76b523db
HR		 2371 if (!s->sas_addr) {
2372 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2373 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2374 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2375 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2376 s->sas_addr |= PCI_FUNC(dev->devfn);
2377 }
fb654157 2378 if (!s->hba_serial) {
23335f62 2379 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2380 }
e8f943c3
HR		 2381 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2382 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2383 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2384 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2385 } else {
2386 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2387 }
2388 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2389 s->fw_cmds = MEGASAS_MAX_FRAMES;
2390 }
2391 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3 2392 megasas_is_jbod(s) ? "jbod" : "raid");
3f2cd4dd
HR		 2393
2394 if (megasas_is_jbod(s)) {
2395 s->fw_luns = MFI_MAX_SYS_PDS;
2396 } else {
2397 s->fw_luns = MFI_MAX_LD;
2398 }
e8f943c3
HR		 2399 s->producer_pa = 0;
2400 s->consumer_pa = 0;
2401 for (i = 0; i < s->fw_cmds; i++) {
2402 s->frames[i].index = i;
2403 s->frames[i].context = -1;
2404 s->frames[i].pa = 0;
2405 s->frames[i].state = s;
2406 }
2407
b1187b51
AF		 2408 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2409 &megasas_scsi_info, NULL);
22d6aa03 2410 if (!d->hotplugged) {
caad4eb3
AF		 2411 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2412 if (err != NULL) {
fa617181 2413 qerror_report_err(err);
caad4eb3
AF		 2414 error_free(err);
2415 return -1;
2416 }
22d6aa03 2417 }
e8f943c3
HR		 2418 return 0;
2419}
2420
4522b69c
HR		 2421static void
2422megasas_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len)
2423{
2424 pci_default_write_config(pci, addr, val, len);
2425 msi_write_config(pci, addr, val, len);
2426}
2427
e23d0498 2428static Property megasas_properties_gen1[] = {
e8f943c3
HR		 2429 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2430 MEGASAS_DEFAULT_SGE),
2431 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2432 MEGASAS_DEFAULT_FRAMES),
fb654157 2433 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2434 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
4522b69c
HR		 2435 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2436 MEGASAS_FLAG_USE_MSI, false),
e8f943c3
HR		 2437 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2438 MEGASAS_FLAG_USE_MSIX, false),
e8f943c3
HR		 2439 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2440 MEGASAS_FLAG_USE_JBOD, false),
2441 DEFINE_PROP_END_OF_LIST(),
2442};
2443
e23d0498
HR		 2444static Property megasas_properties_gen2[] = {
2445 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2446 MEGASAS_DEFAULT_SGE),
2447 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2448 MEGASAS_GEN2_DEFAULT_FRAMES),
2449 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2450 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2451 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2452 MEGASAS_FLAG_USE_MSI, true),
2453 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2454 MEGASAS_FLAG_USE_MSIX, true),
2455 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2456 MEGASAS_FLAG_USE_JBOD, false),
2457 DEFINE_PROP_END_OF_LIST(),
2458};
2459
2460typedef struct MegasasInfo {
2461 const char *name;
2462 const char *desc;
2463 const char *product_name;
2464 const char *product_version;
2465 uint16_t device_id;
2466 uint16_t subsystem_id;
2467 int ioport_bar;
2468 int mmio_bar;
2469 bool is_express;
2470 int osts;
2471 const VMStateDescription *vmsd;
2472 Property *props;
2473} MegasasInfo;
2474
2475static struct MegasasInfo megasas_devices[] = {
2476 {
2477 .name = TYPE_MEGASAS_GEN1,
2478 .desc = "LSI MegaRAID SAS 1078",
2479 .product_name = "LSI MegaRAID SAS 8708EM2",
2480 .product_version = MEGASAS_VERSION_GEN1,
2481 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2482 .subsystem_id = 0x1013,
2483 .ioport_bar = 2,
2484 .mmio_bar = 0,
2485 .osts = MFI_1078_RM | 1,
2486 .is_express = false,
2487 .vmsd = &vmstate_megasas_gen1,
2488 .props = megasas_properties_gen1,
2489 },{
2490 .name = TYPE_MEGASAS_GEN2,
2491 .desc = "LSI MegaRAID SAS 2108",
2492 .product_name = "LSI MegaRAID SAS 9260-8i",
2493 .product_version = MEGASAS_VERSION_GEN2,
2494 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2495 .subsystem_id = 0x9261,
2496 .ioport_bar = 0,
2497 .mmio_bar = 1,
2498 .osts = MFI_GEN2_RM,
2499 .is_express = true,
2500 .vmsd = &vmstate_megasas_gen2,
2501 .props = megasas_properties_gen2,
2502 }
2503};
2504
e8f943c3
HR		 2505static void megasas_class_init(ObjectClass *oc, void *data)
2506{
2507 DeviceClass *dc = DEVICE_CLASS(oc);
2508 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
e23d0498
HR		 2509 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2510 const MegasasInfo *info = data;
e8f943c3
HR		 2511
2512 pc->init = megasas_scsi_init;
2513 pc->exit = megasas_scsi_uninit;
2514 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2515 pc->device_id = info->device_id;
e8f943c3 2516 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2517 pc->subsystem_id = info->subsystem_id;
e8f943c3 2518 pc->class_id = PCI_CLASS_STORAGE_RAID;
e23d0498
HR		 2519 pc->is_express = info->is_express;
2520 e->mmio_bar = info->mmio_bar;
2521 e->ioport_bar = info->ioport_bar;
2522 e->osts = info->osts;
2523 e->product_name = info->product_name;
2524 e->product_version = info->product_version;
2525 dc->props = info->props;
e8f943c3 2526 dc->reset = megasas_scsi_reset;
e23d0498 2527 dc->vmsd = info->vmsd;
125ee0ed 2528 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e23d0498 2529 dc->desc = info->desc;
4522b69c 2530 pc->config_write = megasas_write_config;
e8f943c3
HR		 2531}
2532
2533static const TypeInfo megasas_info = {
e23d0498 2534 .name = TYPE_MEGASAS_BASE,
e8f943c3
HR		 2535 .parent = TYPE_PCI_DEVICE,
2536 .instance_size = sizeof(MegasasState),
e23d0498
HR		 2537 .class_size = sizeof(MegasasBaseClass),
2538 .abstract = true,
e8f943c3
HR		 2539};
2540
2541static void megasas_register_types(void)
2542{
e23d0498
HR		 2543 int i;
2544
e8f943c3 2545 type_register_static(&megasas_info);
e23d0498
HR		 2546 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2547 const MegasasInfo *info = &megasas_devices[i];
2548 TypeInfo type_info = {};
2549
2550 type_info.name = info->name;
2551 type_info.parent = TYPE_MEGASAS_BASE;
2552 type_info.class_data = (void *)info;
2553 type_info.class_init = megasas_class_init;
2554
2555 type_register(&type_info);
2556 }
e8f943c3
HR		 2557}
2558
2559type_init(megasas_register_types)
Empty description
This page took 0.576995 seconds and 4 git commands to generate.