]> Git Repo - qemu.git/blame - hw/display/qxl.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
console: add GraphicHwOps
[qemu.git] / hw / display / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a639ab04
AL		 21#include <zlib.h>
22
a19cbfb3 23#include "qemu-common.h"
1de7afc9
PB		 24#include "qemu/timer.h"
25#include "qemu/queue.h"
83c9089e 26#include "monitor/monitor.h"
9c17d615 27#include "sysemu/sysemu.h"
c480bb7d 28#include "trace.h"
a19cbfb3 29
47b43a1f 30#include "qxl.h"
a19cbfb3 31
0b81c478
AL		 32/*
33 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
34 * such can be changed by the guest, so to avoid a guest trigerrable
0a530548 35 * abort we just qxl_set_guest_bug and set the return to NULL. Still
0b81c478
AL		 36 * it may happen as a result of emulator bug as well.
37 */
a19cbfb3 38#undef SPICE_RING_PROD_ITEM
0b81c478 39#define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
a19cbfb3 40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 41 if (prod >= ARRAY_SIZE((r)->items)) { \
0a530548 42 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
bc5f92e5 43 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 44 ret = NULL; \
45 } else { \
bc5f92e5 46 ret = &(r)->items[prod].el; \
a19cbfb3 47 } \
a19cbfb3
GH		 48 }
49
50#undef SPICE_RING_CONS_ITEM
0b81c478 51#define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
a19cbfb3 52 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
bc5f92e5 53 if (cons >= ARRAY_SIZE((r)->items)) { \
0a530548 54 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
bc5f92e5 55 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
0b81c478
AL		 56 ret = NULL; \
57 } else { \
bc5f92e5 58 ret = &(r)->items[cons].el; \
a19cbfb3 59 } \
a19cbfb3
GH		 60 }
61
62#undef ALIGN
63#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
64
65#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
66
67#define QXL_MODE(_x, _y, _b, _o) \
68 { .x_res = _x, \
69 .y_res = _y, \
70 .bits = _b, \
71 .stride = (_x) * (_b) / 8, \
72 .x_mili = PIXEL_SIZE * (_x), \
73 .y_mili = PIXEL_SIZE * (_y), \
74 .orientation = _o, \
75 }
76
77#define QXL_MODE_16_32(x_res, y_res, orientation) \
78 QXL_MODE(x_res, y_res, 16, orientation), \
79 QXL_MODE(x_res, y_res, 32, orientation)
80
81#define QXL_MODE_EX(x_res, y_res) \
82 QXL_MODE_16_32(x_res, y_res, 0), \
038c1879 83 QXL_MODE_16_32(x_res, y_res, 1)
a19cbfb3
GH		 84
85static QXLMode qxl_modes[] = {
86 QXL_MODE_EX(640, 480),
87 QXL_MODE_EX(800, 480),
88 QXL_MODE_EX(800, 600),
89 QXL_MODE_EX(832, 624),
90 QXL_MODE_EX(960, 640),
91 QXL_MODE_EX(1024, 600),
92 QXL_MODE_EX(1024, 768),
93 QXL_MODE_EX(1152, 864),
94 QXL_MODE_EX(1152, 870),
95 QXL_MODE_EX(1280, 720),
96 QXL_MODE_EX(1280, 760),
97 QXL_MODE_EX(1280, 768),
98 QXL_MODE_EX(1280, 800),
99 QXL_MODE_EX(1280, 960),
100 QXL_MODE_EX(1280, 1024),
101 QXL_MODE_EX(1360, 768),
102 QXL_MODE_EX(1366, 768),
103 QXL_MODE_EX(1400, 1050),
104 QXL_MODE_EX(1440, 900),
105 QXL_MODE_EX(1600, 900),
106 QXL_MODE_EX(1600, 1200),
107 QXL_MODE_EX(1680, 1050),
108 QXL_MODE_EX(1920, 1080),
a19cbfb3
GH		 109 /* these modes need more than 8 MB video memory */
110 QXL_MODE_EX(1920, 1200),
111 QXL_MODE_EX(1920, 1440),
112 QXL_MODE_EX(2048, 1536),
113 QXL_MODE_EX(2560, 1440),
114 QXL_MODE_EX(2560, 1600),
a19cbfb3
GH		 115 /* these modes need more than 16 MB video memory */
116 QXL_MODE_EX(2560, 2048),
117 QXL_MODE_EX(2800, 2100),
118 QXL_MODE_EX(3200, 2400),
a19cbfb3
GH		 119};
120
a19cbfb3 121static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 122static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 123static void qxl_reset_memslots(PCIQXLDevice *d);
124static void qxl_reset_surfaces(PCIQXLDevice *d);
125static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
126
0a530548 127void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 128{
917ae08c 129 trace_qxl_set_guest_bug(qxl->id);
2bce0400 130 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
087e6a42 131 qxl->guest_bug = 1;
2bce0400 132 if (qxl->guestdebug) {
7635392c
AL		 133 va_list ap;
134 va_start(ap, msg);
135 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
136 vfprintf(stderr, msg, ap);
137 fprintf(stderr, "\n");
138 va_end(ap);
2bce0400
GH		 139 }
140}
141
087e6a42
AL		 142static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
143{
144 qxl->guest_bug = 0;
145}
aee32bf3
GH		 146
147void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
148 struct QXLRect *area, struct QXLRect *dirty_rects,
149 uint32_t num_dirty_rects,
5ff4e36c 150 uint32_t clear_dirty_region,
2e1a98c9 151 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 152{
c480bb7d
AL		 153 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
154 area->top, area->bottom);
155 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
156 clear_dirty_region);
5ff4e36c
AL		 157 if (async == QXL_SYNC) {
158 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
159 dirty_rects, num_dirty_rects, clear_dirty_region);
160 } else {
2e1a98c9 161 assert(cookie != NULL);
5ff4e36c 162 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
5dba0d45 163 clear_dirty_region, (uintptr_t)cookie);
5ff4e36c 164 }
aee32bf3
GH		 165}
166
5ff4e36c
AL		 167static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
168 uint32_t id)
aee32bf3 169{
c480bb7d 170 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
14898cf6 171 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 172 qxl->guest_surfaces.cmds[id] = 0;
173 qxl->guest_surfaces.count--;
174 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 175}
176
5ff4e36c
AL		 177static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
178 qxl_async_io async)
179{
2e1a98c9
AL		 180 QXLCookie *cookie;
181
c480bb7d 182 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
5ff4e36c 183 if (async) {
2e1a98c9
AL		 184 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
185 QXL_IO_DESTROY_SURFACE_ASYNC);
186 cookie->u.surface_id = id;
5dba0d45 187 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
5ff4e36c
AL		 188 } else {
189 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
753b8b0d 190 qxl_spice_destroy_surface_wait_complete(qxl, id);
5ff4e36c
AL		 191 }
192}
193
3e16b9c5
AL		 194static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
195{
c480bb7d
AL		 196 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
197 qxl->num_free_res);
2e1a98c9 198 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 199 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
200 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 201}
3e16b9c5 202
aee32bf3
GH		 203void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
204 uint32_t count)
205{
c480bb7d 206 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
aee32bf3
GH		 207 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
208}
209
210void qxl_spice_oom(PCIQXLDevice *qxl)
211{
c480bb7d 212 trace_qxl_spice_oom(qxl->id);
aee32bf3
GH		 213 qxl->ssd.worker->oom(qxl->ssd.worker);
214}
215
216void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
217{
c480bb7d 218 trace_qxl_spice_reset_memslots(qxl->id);
aee32bf3
GH		 219 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
220}
221
5ff4e36c 222static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 223{
c480bb7d 224 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
14898cf6 225 qemu_mutex_lock(&qxl->track_lock);
ddd8fdc7
GH		 226 memset(qxl->guest_surfaces.cmds, 0,
227 sizeof(qxl->guest_surfaces.cmds) * qxl->ssd.num_surfaces);
14898cf6
GH		 228 qxl->guest_surfaces.count = 0;
229 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 230}
231
5ff4e36c
AL		 232static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
233{
c480bb7d 234 trace_qxl_spice_destroy_surfaces(qxl->id, async);
5ff4e36c 235 if (async) {
2e1a98c9 236 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
5dba0d45
PM		 237 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
238 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c
AL		 239 } else {
240 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
241 qxl_spice_destroy_surfaces_complete(qxl);
242 }
243}
244
020af1c4
AL		 245static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
246{
247 trace_qxl_spice_monitors_config(qxl->id);
020af1c4
AL		 248 if (replay) {
249 /*
250 * don't use QXL_COOKIE_TYPE_IO:
251 * - we are not running yet (post_load), we will assert
252 * in send_events
253 * - this is not a guest io, but a reply, so async_io isn't set.
254 */
255 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
256 qxl->guest_monitors_config,
257 MEMSLOT_GROUP_GUEST,
258 (uintptr_t)qxl_cookie_new(
259 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
260 0));
261 } else {
262 qxl->guest_monitors_config = qxl->ram->monitors_config;
263 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
264 qxl->ram->monitors_config,
265 MEMSLOT_GROUP_GUEST,
266 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
267 QXL_IO_MONITORS_CONFIG_ASYNC));
268 }
020af1c4
AL		 269}
270
aee32bf3
GH		 271void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
272{
c480bb7d 273 trace_qxl_spice_reset_image_cache(qxl->id);
aee32bf3
GH		 274 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
275}
276
277void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
278{
c480bb7d 279 trace_qxl_spice_reset_cursor(qxl->id);
aee32bf3 280 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
30f6da66
YH		 281 qemu_mutex_lock(&qxl->track_lock);
282 qxl->guest_cursor = 0;
283 qemu_mutex_unlock(&qxl->track_lock);
958c2bce
GH		 284 if (qxl->ssd.cursor) {
285 cursor_put(qxl->ssd.cursor);
286 }
287 qxl->ssd.cursor = cursor_builtin_hidden();
aee32bf3
GH		 288}
289
290
a19cbfb3
GH		 291static inline uint32_t msb_mask(uint32_t val)
292{
293 uint32_t mask;
294
295 do {
296 mask = ~(val - 1) & val;
297 val &= ~mask;
298 } while (mask < val);
299
300 return mask;
301}
302
303static ram_addr_t qxl_rom_size(void)
304{
038c1879
AL		 305 uint32_t required_rom_size = sizeof(QXLRom) + sizeof(QXLModes) +
306 sizeof(qxl_modes);
307 uint32_t rom_size = 8192; /* two pages */
13d1fd44 308
038c1879
AL		 309 required_rom_size = MAX(required_rom_size, TARGET_PAGE_SIZE);
310 required_rom_size = msb_mask(required_rom_size * 2 - 1);
311 assert(required_rom_size <= rom_size);
a19cbfb3
GH		 312 return rom_size;
313}
314
315static void init_qxl_rom(PCIQXLDevice *d)
316{
b1950430 317 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 318 QXLModes *modes = (QXLModes *)(rom + 1);
319 uint32_t ram_header_size;
320 uint32_t surface0_area_size;
321 uint32_t num_pages;
13d1fd44
AL		 322 uint32_t fb;
323 int i, n;
a19cbfb3
GH		 324
325 memset(rom, 0, d->rom_size);
326
327 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
328 rom->id = cpu_to_le32(d->id);
329 rom->log_level = cpu_to_le32(d->guestdebug);
330 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
331
332 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
333 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
334 rom->slots_start = 1;
335 rom->slots_end = NUM_MEMSLOTS - 1;
ddd8fdc7 336 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
a19cbfb3 337
13d1fd44 338 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
a19cbfb3 339 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
13d1fd44
AL		 340 if (fb > d->vgamem_size) {
341 continue;
a19cbfb3 342 }
13d1fd44
AL		 343 modes->modes[n].id = cpu_to_le32(i);
344 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
345 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
346 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
347 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
348 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
349 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
350 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
351 n++;
352 }
353 modes->n_modes = cpu_to_le32(n);
a19cbfb3
GH		 354
355 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
13d1fd44 356 surface0_area_size = ALIGN(d->vgamem_size, 4096);
a19cbfb3
GH		 357 num_pages = d->vga.vram_size;
358 num_pages -= ram_header_size;
359 num_pages -= surface0_area_size;
360 num_pages = num_pages / TARGET_PAGE_SIZE;
361
362 rom->draw_area_offset = cpu_to_le32(0);
363 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
364 rom->pages_offset = cpu_to_le32(surface0_area_size);
365 rom->num_pages = cpu_to_le32(num_pages);
366 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
367
368 d->shadow_rom = *rom;
369 d->rom = rom;
370 d->modes = modes;
371}
372
373static void init_qxl_ram(PCIQXLDevice *d)
374{
375 uint8_t *buf;
376 uint64_t *item;
377
378 buf = d->vga.vram_ptr;
379 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
380 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
381 d->ram->int_pending = cpu_to_le32(0);
382 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 383 d->ram->update_surface = 0;
a19cbfb3
GH		 384 SPICE_RING_INIT(&d->ram->cmd_ring);
385 SPICE_RING_INIT(&d->ram->cursor_ring);
386 SPICE_RING_INIT(&d->ram->release_ring);
0b81c478
AL		 387 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
388 assert(item);
a19cbfb3
GH		 389 *item = 0;
390 qxl_ring_set_dirty(d);
391}
392
393/* can be called from spice server thread context */
b1950430 394static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 395{
fd4aa979 396 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 397}
398
399static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
400{
b1950430 401 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 402}
403
404/* called from spice server thread context only */
405static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
406{
a19cbfb3
GH		 407 void *base = qxl->vga.vram_ptr;
408 intptr_t offset;
409
410 offset = ptr - base;
411 offset &= ~(TARGET_PAGE_SIZE-1);
412 assert(offset < qxl->vga.vram_size);
b1950430 413 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
a19cbfb3
GH		 414}
415
416/* can be called from spice server thread context */
417static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
418{
b1950430
AK		 419 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
420 ram_addr_t end = qxl->vga.vram_size;
421 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 422}
423
424/*
425 * keep track of some command state, for savevm/loadvm.
426 * called from spice server thread context only
427 */
fae2afb1 428static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
a19cbfb3
GH		 429{
430 switch (le32_to_cpu(ext->cmd.type)) {
431 case QXL_CMD_SURFACE:
432 {
433 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 434
435 if (!cmd) {
436 return 1;
437 }
a19cbfb3 438 uint32_t id = le32_to_cpu(cmd->surface_id);
47eddfbf 439
ddd8fdc7 440 if (id >= qxl->ssd.num_surfaces) {
0a530548 441 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
ddd8fdc7 442 qxl->ssd.num_surfaces);
47eddfbf
AL		 443 return 1;
444 }
48f4ba67
AL		 445 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
446 (cmd->u.surface_create.stride & 0x03) != 0) {
447 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
448 cmd->u.surface_create.stride);
449 return 1;
450 }
14898cf6 451 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 452 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
453 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
454 qxl->guest_surfaces.count++;
455 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
456 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
457 }
458 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
459 qxl->guest_surfaces.cmds[id] = 0;
460 qxl->guest_surfaces.count--;
461 }
14898cf6 462 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 463 break;
464 }
465 case QXL_CMD_CURSOR:
466 {
467 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
fae2afb1
AL		 468
469 if (!cmd) {
470 return 1;
471 }
a19cbfb3 472 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 473 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 474 qxl->guest_cursor = ext->cmd.data;
30f6da66 475 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 476 }
477 break;
478 }
479 }
fae2afb1 480 return 0;
a19cbfb3
GH		 481}
482
483/* spice display interface callbacks */
484
485static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
486{
487 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
488
c480bb7d 489 trace_qxl_interface_attach_worker(qxl->id);
a19cbfb3
GH		 490 qxl->ssd.worker = qxl_worker;
491}
492
493static void interface_set_compression_level(QXLInstance *sin, int level)
494{
495 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
496
c480bb7d 497 trace_qxl_interface_set_compression_level(qxl->id, level);
a19cbfb3
GH		 498 qxl->shadow_rom.compression_level = cpu_to_le32(level);
499 qxl->rom->compression_level = cpu_to_le32(level);
500 qxl_rom_set_dirty(qxl);
501}
502
503static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
504{
505 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
506
c480bb7d 507 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
a19cbfb3
GH		 508 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
509 qxl->rom->mm_clock = cpu_to_le32(mm_time);
510 qxl_rom_set_dirty(qxl);
511}
512
513static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
514{
515 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
516
c480bb7d 517 trace_qxl_interface_get_init_info(qxl->id);
a19cbfb3
GH		 518 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
519 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
520 info->num_memslots = NUM_MEMSLOTS;
521 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
522 info->internal_groupslot_id = 0;
523 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
ddd8fdc7 524 info->n_surfaces = qxl->ssd.num_surfaces;
a19cbfb3
GH		 525}
526
5b77870c
AL		 527static const char *qxl_mode_to_string(int mode)
528{
529 switch (mode) {
530 case QXL_MODE_COMPAT:
531 return "compat";
532 case QXL_MODE_NATIVE:
533 return "native";
534 case QXL_MODE_UNDEFINED:
535 return "undefined";
536 case QXL_MODE_VGA:
537 return "vga";
538 }
539 return "INVALID";
540}
541
8b92e298
AL		 542static const char *io_port_to_string(uint32_t io_port)
543{
544 if (io_port >= QXL_IO_RANGE_SIZE) {
545 return "out of range";
546 }
547 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
548 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
549 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
550 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
551 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
552 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
553 [QXL_IO_RESET] = "QXL_IO_RESET",
554 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
555 [QXL_IO_LOG] = "QXL_IO_LOG",
556 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
557 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
558 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
559 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
560 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
561 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
562 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
563 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 564 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
565 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
566 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
567 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
568 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
569 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
570 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
571 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
572 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
020af1c4 573 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
8b92e298
AL		 574 };
575 return io_port_to_string[io_port];
576}
577
a19cbfb3
GH		 578/* called from spice server thread context only */
579static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
580{
581 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
582 SimpleSpiceUpdate *update;
583 QXLCommandRing *ring;
584 QXLCommand *cmd;
e0c64d08 585 int notify, ret;
a19cbfb3 586
c480bb7d
AL		 587 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
588
a19cbfb3
GH		 589 switch (qxl->mode) {
590 case QXL_MODE_VGA:
e0c64d08
GH		 591 ret = false;
592 qemu_mutex_lock(&qxl->ssd.lock);
b1af98ba
GH		 593 update = QTAILQ_FIRST(&qxl->ssd.updates);
594 if (update != NULL) {
595 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
e0c64d08
GH		 596 *ext = update->ext;
597 ret = true;
a19cbfb3 598 }
e0c64d08 599 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 600 if (ret) {
c480bb7d 601 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
212496c9
AL		 602 qxl_log_command(qxl, "vga", ext);
603 }
e0c64d08 604 return ret;
a19cbfb3
GH		 605 case QXL_MODE_COMPAT:
606 case QXL_MODE_NATIVE:
607 case QXL_MODE_UNDEFINED:
a19cbfb3 608 ring = &qxl->ram->cmd_ring;
087e6a42 609 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
a19cbfb3
GH		 610 return false;
611 }
0b81c478
AL		 612 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
613 if (!cmd) {
614 return false;
615 }
a19cbfb3
GH		 616 ext->cmd = *cmd;
617 ext->group_id = MEMSLOT_GROUP_GUEST;
618 ext->flags = qxl->cmdflags;
619 SPICE_RING_POP(ring, notify);
620 qxl_ring_set_dirty(qxl);
621 if (notify) {
622 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
623 }
624 qxl->guest_primary.commands++;
625 qxl_track_command(qxl, ext);
626 qxl_log_command(qxl, "cmd", ext);
0b81c478 627 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 628 return true;
629 default:
630 return false;
631 }
632}
633
634/* called from spice server thread context only */
635static int interface_req_cmd_notification(QXLInstance *sin)
636{
637 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
638 int wait = 1;
639
c480bb7d 640 trace_qxl_ring_command_req_notification(qxl->id);
a19cbfb3
GH		 641 switch (qxl->mode) {
642 case QXL_MODE_COMPAT:
643 case QXL_MODE_NATIVE:
644 case QXL_MODE_UNDEFINED:
645 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
646 qxl_ring_set_dirty(qxl);
647 break;
648 default:
649 /* nothing */
650 break;
651 }
652 return wait;
653}
654
655/* called from spice server thread context only */
656static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
657{
658 QXLReleaseRing *ring = &d->ram->release_ring;
659 uint64_t *item;
660 int notify;
661
662#define QXL_FREE_BUNCH_SIZE 32
663
664 if (ring->prod - ring->cons + 1 == ring->num_items) {
665 /* ring full -- can't push */
666 return;
667 }
668 if (!flush && d->oom_running) {
669 /* collect everything from oom handler before pushing */
670 return;
671 }
672 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
673 /* collect a bit more before pushing */
674 return;
675 }
676
677 SPICE_RING_PUSH(ring, notify);
c480bb7d
AL		 678 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
679 d->guest_surfaces.count, d->num_free_res,
680 d->last_release, notify ? "yes" : "no");
681 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
682 ring->num_items, ring->prod, ring->cons);
a19cbfb3
GH		 683 if (notify) {
684 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
685 }
0b81c478
AL		 686 SPICE_RING_PROD_ITEM(d, ring, item);
687 if (!item) {
688 return;
689 }
a19cbfb3
GH		 690 *item = 0;
691 d->num_free_res = 0;
692 d->last_release = NULL;
693 qxl_ring_set_dirty(d);
694}
695
696/* called from spice server thread context only */
697static void interface_release_resource(QXLInstance *sin,
698 struct QXLReleaseInfoExt ext)
699{
700 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
701 QXLReleaseRing *ring;
702 uint64_t *item, id;
703
704 if (ext.group_id == MEMSLOT_GROUP_HOST) {
705 /* host group -> vga mode update request */
f4a8a424 706 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
a19cbfb3
GH		 707 return;
708 }
709
710 /*
711 * ext->info points into guest-visible memory
712 * pci bar 0, $command.release_info
713 */
714 ring = &qxl->ram->release_ring;
0b81c478
AL		 715 SPICE_RING_PROD_ITEM(qxl, ring, item);
716 if (!item) {
717 return;
718 }
a19cbfb3
GH		 719 if (*item == 0) {
720 /* stick head into the ring */
721 id = ext.info->id;
722 ext.info->next = 0;
723 qxl_ram_set_dirty(qxl, &ext.info->next);
724 *item = id;
725 qxl_ring_set_dirty(qxl);
726 } else {
727 /* append item to the list */
728 qxl->last_release->next = ext.info->id;
729 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
730 ext.info->next = 0;
731 qxl_ram_set_dirty(qxl, &ext.info->next);
732 }
733 qxl->last_release = ext.info;
734 qxl->num_free_res++;
c480bb7d 735 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
a19cbfb3
GH		 736 qxl_push_free_res(qxl, 0);
737}
738
739/* called from spice server thread context only */
740static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
741{
742 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
743 QXLCursorRing *ring;
744 QXLCommand *cmd;
745 int notify;
746
c480bb7d
AL		 747 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
748
a19cbfb3
GH		 749 switch (qxl->mode) {
750 case QXL_MODE_COMPAT:
751 case QXL_MODE_NATIVE:
752 case QXL_MODE_UNDEFINED:
753 ring = &qxl->ram->cursor_ring;
754 if (SPICE_RING_IS_EMPTY(ring)) {
755 return false;
756 }
0b81c478
AL		 757 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
758 if (!cmd) {
759 return false;
760 }
a19cbfb3
GH		 761 ext->cmd = *cmd;
762 ext->group_id = MEMSLOT_GROUP_GUEST;
763 ext->flags = qxl->cmdflags;
764 SPICE_RING_POP(ring, notify);
765 qxl_ring_set_dirty(qxl);
766 if (notify) {
767 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
768 }
769 qxl->guest_primary.commands++;
770 qxl_track_command(qxl, ext);
771 qxl_log_command(qxl, "csr", ext);
772 if (qxl->id == 0) {
773 qxl_render_cursor(qxl, ext);
774 }
c480bb7d 775 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 776 return true;
777 default:
778 return false;
779 }
780}
781
782/* called from spice server thread context only */
783static int interface_req_cursor_notification(QXLInstance *sin)
784{
785 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
786 int wait = 1;
787
c480bb7d 788 trace_qxl_ring_cursor_req_notification(qxl->id);
a19cbfb3
GH		 789 switch (qxl->mode) {
790 case QXL_MODE_COMPAT:
791 case QXL_MODE_NATIVE:
792 case QXL_MODE_UNDEFINED:
793 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
794 qxl_ring_set_dirty(qxl);
795 break;
796 default:
797 /* nothing */
798 break;
799 }
800 return wait;
801}
802
803/* called from spice server thread context */
804static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
805{
baeae407
AL		 806 /*
807 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
808 * use by xf86-video-qxl and is defined out in the qxl windows driver.
809 * Probably was at some earlier version that is prior to git start (2009),
810 * and is still guest trigerrable.
811 */
812 fprintf(stderr, "%s: deprecated\n", __func__);
a19cbfb3
GH		 813}
814
815/* called from spice server thread context only */
816static int interface_flush_resources(QXLInstance *sin)
817{
818 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
819 int ret;
820
a19cbfb3
GH		 821 ret = qxl->num_free_res;
822 if (ret) {
823 qxl_push_free_res(qxl, 1);
824 }
825 return ret;
826}
827
5ff4e36c
AL		 828static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
829
5ff4e36c 830/* called from spice server thread context only */
2e1a98c9 831static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 832{
5ff4e36c
AL		 833 uint32_t current_async;
834
835 qemu_mutex_lock(&qxl->async_lock);
836 current_async = qxl->current_async;
837 qxl->current_async = QXL_UNDEFINED_IO;
838 qemu_mutex_unlock(&qxl->async_lock);
839
c480bb7d 840 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
2e1a98c9
AL		 841 if (!cookie) {
842 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
843 return;
844 }
845 if (cookie && current_async != cookie->io) {
846 fprintf(stderr,
2fce7edf
AL		 847 "qxl: %s: error: current_async = %d != %"
848 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
2e1a98c9 849 }
5ff4e36c 850 switch (current_async) {
81fb6f15
AL		 851 case QXL_IO_MEMSLOT_ADD_ASYNC:
852 case QXL_IO_DESTROY_PRIMARY_ASYNC:
853 case QXL_IO_UPDATE_AREA_ASYNC:
854 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 855 case QXL_IO_MONITORS_CONFIG_ASYNC:
81fb6f15 856 break;
5ff4e36c
AL		 857 case QXL_IO_CREATE_PRIMARY_ASYNC:
858 qxl_create_guest_primary_complete(qxl);
859 break;
860 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
861 qxl_spice_destroy_surfaces_complete(qxl);
862 break;
863 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 864 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c 865 break;
81fb6f15
AL		 866 default:
867 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
868 current_async);
5ff4e36c
AL		 869 }
870 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
871}
872
81fb6f15
AL		 873/* called from spice server thread context only */
874static void interface_update_area_complete(QXLInstance *sin,
875 uint32_t surface_id,
876 QXLRect *dirty, uint32_t num_updated_rects)
877{
878 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
879 int i;
880 int qxl_i;
881
882 qemu_mutex_lock(&qxl->ssd.lock);
883 if (surface_id != 0 || !qxl->render_update_cookie_num) {
884 qemu_mutex_unlock(&qxl->ssd.lock);
885 return;
886 }
c480bb7d
AL		 887 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
888 dirty->right, dirty->top, dirty->bottom);
889 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
81fb6f15
AL		 890 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
891 /*
892 * overflow - treat this as a full update. Not expected to be common.
893 */
c480bb7d
AL		 894 trace_qxl_interface_update_area_complete_overflow(qxl->id,
895 QXL_NUM_DIRTY_RECTS);
81fb6f15
AL		 896 qxl->guest_primary.resized = 1;
897 }
898 if (qxl->guest_primary.resized) {
899 /*
900 * Don't bother copying or scheduling the bh since we will flip
901 * the whole area anyway on completion of the update_area async call
902 */
903 qemu_mutex_unlock(&qxl->ssd.lock);
904 return;
905 }
906 qxl_i = qxl->num_dirty_rects;
907 for (i = 0; i < num_updated_rects; i++) {
908 qxl->dirty[qxl_i++] = dirty[i];
909 }
910 qxl->num_dirty_rects += num_updated_rects;
c480bb7d
AL		 911 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
912 qxl->num_dirty_rects);
81fb6f15
AL		 913 qemu_bh_schedule(qxl->update_area_bh);
914 qemu_mutex_unlock(&qxl->ssd.lock);
915}
916
2e1a98c9
AL		 917/* called from spice server thread context only */
918static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
919{
920 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
5dba0d45 921 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
2e1a98c9
AL		 922
923 switch (cookie->type) {
924 case QXL_COOKIE_TYPE_IO:
925 interface_async_complete_io(qxl, cookie);
81fb6f15
AL		 926 g_free(cookie);
927 break;
928 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
929 qxl_render_update_area_done(qxl, cookie);
2e1a98c9 930 break;
020af1c4
AL		 931 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
932 break;
2e1a98c9
AL		 933 default:
934 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
935 __func__, cookie->type);
81fb6f15 936 g_free(cookie);
2e1a98c9 937 }
2e1a98c9
AL		 938}
939
c10018d6
SSP		 940/* called from spice server thread context only */
941static void interface_set_client_capabilities(QXLInstance *sin,
942 uint8_t client_present,
943 uint8_t caps[58])
944{
945 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
946
e0ac6097
AL		 947 if (qxl->revision < 4) {
948 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
949 qxl->revision);
950 return;
951 }
952
ab902981
HG		 953 if (runstate_check(RUN_STATE_INMIGRATE) ||
954 runstate_check(RUN_STATE_POSTMIGRATE)) {
955 return;
956 }
957
c10018d6 958 qxl->shadow_rom.client_present = client_present;
08688af0
MA		 959 memcpy(qxl->shadow_rom.client_capabilities, caps,
960 sizeof(qxl->shadow_rom.client_capabilities));
c10018d6 961 qxl->rom->client_present = client_present;
08688af0
MA		 962 memcpy(qxl->rom->client_capabilities, caps,
963 sizeof(qxl->rom->client_capabilities));
c10018d6
SSP		 964 qxl_rom_set_dirty(qxl);
965
966 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
967}
968
a639ab04
AL		 969static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
970{
971 /*
972 * zlib xors the seed with 0xffffffff, and xors the result
973 * again with 0xffffffff; Both are not done with linux's crc32,
974 * which we want to be compatible with, so undo that.
975 */
976 return crc32(0xffffffff, p, len) ^ 0xffffffff;
977}
978
979/* called from main context only */
980static int interface_client_monitors_config(QXLInstance *sin,
981 VDAgentMonitorsConfig *monitors_config)
982{
983 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
984 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
985 int i;
986
e0ac6097
AL		 987 if (qxl->revision < 4) {
988 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
989 qxl->revision);
990 return 0;
991 }
a639ab04
AL		 992 /*
993 * Older windows drivers set int_mask to 0 when their ISR is called,
994 * then later set it to ~0. So it doesn't relate to the actual interrupts
995 * handled. However, they are old, so clearly they don't support this
996 * interrupt
997 */
998 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
999 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1000 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1001 qxl->ram->int_mask,
1002 monitors_config);
1003 return 0;
1004 }
1005 if (!monitors_config) {
1006 return 1;
1007 }
1008 memset(&rom->client_monitors_config, 0,
1009 sizeof(rom->client_monitors_config));
1010 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1011 /* monitors_config->flags ignored */
1012 if (rom->client_monitors_config.count >=
1013 ARRAY_SIZE(rom->client_monitors_config.heads)) {
1014 trace_qxl_client_monitors_config_capped(qxl->id,
1015 monitors_config->num_of_monitors,
1016 ARRAY_SIZE(rom->client_monitors_config.heads));
1017 rom->client_monitors_config.count =
1018 ARRAY_SIZE(rom->client_monitors_config.heads);
1019 }
1020 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1021 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1022 QXLURect *rect = &rom->client_monitors_config.heads[i];
1023 /* monitor->depth ignored */
1024 rect->left = monitor->x;
1025 rect->top = monitor->y;
1026 rect->right = monitor->x + monitor->width;
1027 rect->bottom = monitor->y + monitor->height;
1028 }
1029 rom->client_monitors_config_crc = qxl_crc32(
1030 (const uint8_t *)&rom->client_monitors_config,
1031 sizeof(rom->client_monitors_config));
1032 trace_qxl_client_monitors_config_crc(qxl->id,
1033 sizeof(rom->client_monitors_config),
1034 rom->client_monitors_config_crc);
1035
1036 trace_qxl_interrupt_client_monitors_config(qxl->id,
1037 rom->client_monitors_config.count,
1038 rom->client_monitors_config.heads);
1039 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1040 return 1;
1041}
a639ab04 1042
a19cbfb3
GH		 1043static const QXLInterface qxl_interface = {
1044 .base.type = SPICE_INTERFACE_QXL,
1045 .base.description = "qxl gpu",
1046 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1047 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1048
1049 .attache_worker = interface_attach_worker,
1050 .set_compression_level = interface_set_compression_level,
1051 .set_mm_time = interface_set_mm_time,
1052 .get_init_info = interface_get_init_info,
1053
1054 /* the callbacks below are called from spice server thread context */
1055 .get_command = interface_get_command,
1056 .req_cmd_notification = interface_req_cmd_notification,
1057 .release_resource = interface_release_resource,
1058 .get_cursor_command = interface_get_cursor_command,
1059 .req_cursor_notification = interface_req_cursor_notification,
1060 .notify_update = interface_notify_update,
1061 .flush_resources = interface_flush_resources,
5ff4e36c 1062 .async_complete = interface_async_complete,
81fb6f15 1063 .update_area_complete = interface_update_area_complete,
c10018d6 1064 .set_client_capabilities = interface_set_client_capabilities,
a639ab04 1065 .client_monitors_config = interface_client_monitors_config,
a19cbfb3
GH		 1066};
1067
1068static void qxl_enter_vga_mode(PCIQXLDevice *d)
1069{
1070 if (d->mode == QXL_MODE_VGA) {
1071 return;
1072 }
c480bb7d 1073 trace_qxl_enter_vga_mode(d->id);
a19cbfb3
GH		 1074 qemu_spice_create_host_primary(&d->ssd);
1075 d->mode = QXL_MODE_VGA;
0f7bfd81 1076 vga_dirty_log_start(&d->vga);
1dbfa005 1077 graphic_hw_update(d->vga.con);
a19cbfb3
GH		 1078}
1079
1080static void qxl_exit_vga_mode(PCIQXLDevice *d)
1081{
1082 if (d->mode != QXL_MODE_VGA) {
1083 return;
1084 }
c480bb7d 1085 trace_qxl_exit_vga_mode(d->id);
0f7bfd81 1086 vga_dirty_log_stop(&d->vga);
5ff4e36c 1087 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 1088}
1089
40010aea 1090static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 1091{
1092 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1093 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1094 int level = !!(pending & mask);
1095 qemu_set_irq(d->pci.irq[0], level);
1096 qxl_ring_set_dirty(d);
1097}
1098
a19cbfb3
GH		 1099static void qxl_check_state(PCIQXLDevice *d)
1100{
1101 QXLRam *ram = d->ram;
71d388d4 1102 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
a19cbfb3 1103
71d388d4
YH		 1104 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1105 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 1106}
1107
1108static void qxl_reset_state(PCIQXLDevice *d)
1109{
a19cbfb3
GH		 1110 QXLRom *rom = d->rom;
1111
be48e995 1112 qxl_check_state(d);
a19cbfb3
GH		 1113 d->shadow_rom.update_id = cpu_to_le32(0);
1114 *rom = d->shadow_rom;
1115 qxl_rom_set_dirty(d);
1116 init_qxl_ram(d);
1117 d->num_free_res = 0;
1118 d->last_release = NULL;
1119 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1120}
1121
1122static void qxl_soft_reset(PCIQXLDevice *d)
1123{
c480bb7d 1124 trace_qxl_soft_reset(d->id);
a19cbfb3 1125 qxl_check_state(d);
087e6a42 1126 qxl_clear_guest_bug(d);
a5f68c22 1127 d->current_async = QXL_UNDEFINED_IO;
a19cbfb3
GH		 1128
1129 if (d->id == 0) {
1130 qxl_enter_vga_mode(d);
1131 } else {
1132 d->mode = QXL_MODE_UNDEFINED;
1133 }
1134}
1135
1136static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1137{
c480bb7d 1138 trace_qxl_hard_reset(d->id, loadvm);
a19cbfb3 1139
aee32bf3
GH		 1140 qxl_spice_reset_cursor(d);
1141 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 1142 qxl_reset_surfaces(d);
1143 qxl_reset_memslots(d);
1144
1145 /* pre loadvm reset must not touch QXLRam. This lives in
1146 * device memory, is migrated together with RAM and thus
1147 * already loaded at this point */
1148 if (!loadvm) {
1149 qxl_reset_state(d);
1150 }
1151 qemu_spice_create_host_memslot(&d->ssd);
1152 qxl_soft_reset(d);
a19cbfb3
GH		 1153}
1154
1155static void qxl_reset_handler(DeviceState *dev)
1156{
1157 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
c480bb7d 1158
a19cbfb3
GH		 1159 qxl_hard_reset(d, 0);
1160}
1161
1162static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1163{
1164 VGACommonState *vga = opaque;
1165 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1166
c480bb7d 1167 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
a19cbfb3 1168 if (qxl->mode != QXL_MODE_VGA) {
5ff4e36c 1169 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 1170 qxl_soft_reset(qxl);
1171 }
1172 vga_ioport_write(opaque, addr, val);
1173}
1174
f67ab77a
GH		 1175static const MemoryRegionPortio qxl_vga_portio_list[] = {
1176 { 0x04, 2, 1, .read = vga_ioport_read,
1177 .write = qxl_vga_ioport_write }, /* 3b4 */
1178 { 0x0a, 1, 1, .read = vga_ioport_read,
1179 .write = qxl_vga_ioport_write }, /* 3ba */
1180 { 0x10, 16, 1, .read = vga_ioport_read,
1181 .write = qxl_vga_ioport_write }, /* 3c0 */
1182 { 0x24, 2, 1, .read = vga_ioport_read,
1183 .write = qxl_vga_ioport_write }, /* 3d4 */
1184 { 0x2a, 1, 1, .read = vga_ioport_read,
1185 .write = qxl_vga_ioport_write }, /* 3da */
1186 PORTIO_END_OF_LIST(),
1187};
1188
e954ea28
AL		 1189static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1190 qxl_async_io async)
a19cbfb3
GH		 1191{
1192 static const int regions[] = {
1193 QXL_RAM_RANGE_INDEX,
1194 QXL_VRAM_RANGE_INDEX,
6f2b175a 1195 QXL_VRAM64_RANGE_INDEX,
a19cbfb3
GH		 1196 };
1197 uint64_t guest_start;
1198 uint64_t guest_end;
1199 int pci_region;
1200 pcibus_t pci_start;
1201 pcibus_t pci_end;
1202 intptr_t virt_start;
1203 QXLDevMemSlot memslot;
1204 int i;
1205
1206 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1207 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1208
c480bb7d 1209 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
a19cbfb3 1210
e954ea28 1211 if (slot_id >= NUM_MEMSLOTS) {
0a530548 1212 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
e954ea28
AL		 1213 slot_id, NUM_MEMSLOTS);
1214 return 1;
1215 }
1216 if (guest_start > guest_end) {
0a530548 1217 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
e954ea28
AL		 1218 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1219 return 1;
1220 }
a19cbfb3
GH		 1221
1222 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1223 pci_region = regions[i];
1224 pci_start = d->pci.io_regions[pci_region].addr;
1225 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1226 /* mapped? */
1227 if (pci_start == -1) {
1228 continue;
1229 }
1230 /* start address in range ? */
1231 if (guest_start < pci_start || guest_start > pci_end) {
1232 continue;
1233 }
1234 /* end address in range ? */
1235 if (guest_end > pci_end) {
1236 continue;
1237 }
1238 /* passed */
1239 break;
1240 }
e954ea28 1241 if (i == ARRAY_SIZE(regions)) {
0a530548 1242 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
e954ea28
AL		 1243 return 1;
1244 }
a19cbfb3
GH		 1245
1246 switch (pci_region) {
1247 case QXL_RAM_RANGE_INDEX:
b1950430 1248 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
a19cbfb3
GH		 1249 break;
1250 case QXL_VRAM_RANGE_INDEX:
6f2b175a 1251 case 4 /* vram 64bit */:
b1950430 1252 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
a19cbfb3
GH		 1253 break;
1254 default:
1255 /* should not happen */
0a530548 1256 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
e954ea28 1257 return 1;
a19cbfb3
GH		 1258 }
1259
1260 memslot.slot_id = slot_id;
1261 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1262 memslot.virt_start = virt_start + (guest_start - pci_start);
1263 memslot.virt_end = virt_start + (guest_end - pci_start);
1264 memslot.addr_delta = memslot.virt_start - delta;
1265 memslot.generation = d->rom->slot_generation = 0;
1266 qxl_rom_set_dirty(d);
1267
5ff4e36c 1268 qemu_spice_add_memslot(&d->ssd, &memslot, async);
a19cbfb3
GH		 1269 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1270 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1271 d->guest_slots[slot_id].delta = delta;
1272 d->guest_slots[slot_id].active = 1;
e954ea28 1273 return 0;
a19cbfb3
GH		 1274}
1275
1276static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1277{
5c59d118 1278 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1279 d->guest_slots[slot_id].active = 0;
1280}
1281
1282static void qxl_reset_memslots(PCIQXLDevice *d)
1283{
aee32bf3 1284 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1285 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1286}
1287
1288static void qxl_reset_surfaces(PCIQXLDevice *d)
1289{
c480bb7d 1290 trace_qxl_reset_surfaces(d->id);
a19cbfb3 1291 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1292 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1293}
1294
e25139b3 1295/* can be also called from spice server thread context */
a19cbfb3
GH		 1296void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1297{
1298 uint64_t phys = le64_to_cpu(pqxl);
1299 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1300 uint64_t offset = phys & 0xffffffffffff;
1301
1302 switch (group_id) {
1303 case MEMSLOT_GROUP_HOST:
f4a8a424 1304 return (void *)(intptr_t)offset;
a19cbfb3 1305 case MEMSLOT_GROUP_GUEST:
4b635c59 1306 if (slot >= NUM_MEMSLOTS) {
0a530548
AL		 1307 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1308 NUM_MEMSLOTS);
4b635c59
AL		 1309 return NULL;
1310 }
1311 if (!qxl->guest_slots[slot].active) {
0a530548 1312 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
4b635c59
AL		 1313 return NULL;
1314 }
1315 if (offset < qxl->guest_slots[slot].delta) {
0a530548
AL		 1316 qxl_set_guest_bug(qxl,
1317 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
4b635c59
AL		 1318 slot, offset, qxl->guest_slots[slot].delta);
1319 return NULL;
1320 }
a19cbfb3 1321 offset -= qxl->guest_slots[slot].delta;
4b635c59 1322 if (offset > qxl->guest_slots[slot].size) {
0a530548
AL		 1323 qxl_set_guest_bug(qxl,
1324 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
4b635c59
AL		 1325 slot, offset, qxl->guest_slots[slot].size);
1326 return NULL;
1327 }
a19cbfb3 1328 return qxl->guest_slots[slot].ptr + offset;
a19cbfb3 1329 }
4b635c59 1330 return NULL;
a19cbfb3
GH		 1331}
1332
5ff4e36c
AL		 1333static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1334{
1335 /* for local rendering */
1336 qxl_render_resize(qxl);
1337}
1338
1339static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1340 qxl_async_io async)
a19cbfb3
GH		 1341{
1342 QXLDevSurfaceCreate surface;
1343 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
13d1fd44
AL		 1344 int size;
1345 int requested_height = le32_to_cpu(sc->height);
1346 int requested_stride = le32_to_cpu(sc->stride);
1347
1348 size = abs(requested_stride) * requested_height;
1349 if (size > qxl->vgamem_size) {
1350 qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer"
1351 " size", __func__);
1352 return;
1353 }
a19cbfb3 1354
ddf9f4b7 1355 if (qxl->mode == QXL_MODE_NATIVE) {
0a530548 1356 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
ddf9f4b7
AL		 1357 __func__);
1358 }
a19cbfb3
GH		 1359 qxl_exit_vga_mode(qxl);
1360
a19cbfb3
GH		 1361 surface.format = le32_to_cpu(sc->format);
1362 surface.height = le32_to_cpu(sc->height);
1363 surface.mem = le64_to_cpu(sc->mem);
1364 surface.position = le32_to_cpu(sc->position);
1365 surface.stride = le32_to_cpu(sc->stride);
1366 surface.width = le32_to_cpu(sc->width);
1367 surface.type = le32_to_cpu(sc->type);
1368 surface.flags = le32_to_cpu(sc->flags);
c480bb7d
AL		 1369 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1370 sc->format, sc->position);
1371 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1372 sc->flags);
a19cbfb3 1373
48f4ba67
AL		 1374 if ((surface.stride & 0x3) != 0) {
1375 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1376 surface.stride);
1377 return;
1378 }
1379
a19cbfb3
GH		 1380 surface.mouse_mode = true;
1381 surface.group_id = MEMSLOT_GROUP_GUEST;
1382 if (loadvm) {
1383 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1384 }
1385
1386 qxl->mode = QXL_MODE_NATIVE;
1387 qxl->cmdflags = 0;
5ff4e36c 1388 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1389
5ff4e36c
AL		 1390 if (async == QXL_SYNC) {
1391 qxl_create_guest_primary_complete(qxl);
1392 }
a19cbfb3
GH		 1393}
1394
5ff4e36c
AL		 1395/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1396 * done (in QXL_SYNC case), 0 otherwise. */
1397static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1398{
1399 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1400 return 0;
a19cbfb3 1401 }
c480bb7d 1402 trace_qxl_destroy_primary(d->id);
a19cbfb3 1403 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1404 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1405 qxl_spice_reset_cursor(d);
5ff4e36c 1406 return 1;
a19cbfb3
GH		 1407}
1408
1409static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1410{
1411 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1412 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1413 QXLMode *mode = d->modes->modes + modenr;
1414 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1415 QXLMemSlot slot = {
1416 .mem_start = start,
1417 .mem_end = end
1418 };
1419 QXLSurfaceCreate surface = {
1420 .width = mode->x_res,
1421 .height = mode->y_res,
1422 .stride = -mode->x_res * 4,
1423 .format = SPICE_SURFACE_FMT_32_xRGB,
1424 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1425 .mouse_mode = true,
1426 .mem = devmem + d->shadow_rom.draw_area_offset,
1427 };
1428
c480bb7d
AL		 1429 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1430 devmem);
a19cbfb3
GH		 1431 if (!loadvm) {
1432 qxl_hard_reset(d, 0);
1433 }
1434
1435 d->guest_slots[0].slot = slot;
e954ea28 1436 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
a19cbfb3
GH		 1437
1438 d->guest_primary.surface = surface;
5ff4e36c 1439 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1440
1441 d->mode = QXL_MODE_COMPAT;
1442 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
a19cbfb3
GH		 1443 if (mode->bits == 16) {
1444 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1445 }
a19cbfb3
GH		 1446 d->shadow_rom.mode = cpu_to_le32(modenr);
1447 d->rom->mode = cpu_to_le32(modenr);
1448 qxl_rom_set_dirty(d);
1449}
1450
a8170e5e 1451static void ioport_write(void *opaque, hwaddr addr,
b1950430 1452 uint64_t val, unsigned size)
a19cbfb3
GH		 1453{
1454 PCIQXLDevice *d = opaque;
b1950430 1455 uint32_t io_port = addr;
5ff4e36c 1456 qxl_async_io async = QXL_SYNC;
5ff4e36c 1457 uint32_t orig_io_port = io_port;
a19cbfb3 1458
d96aafca 1459 if (d->guest_bug && io_port != QXL_IO_RESET) {
087e6a42
AL		 1460 return;
1461 }
1462
020af1c4 1463 if (d->revision <= QXL_REVISION_STABLE_V10 &&
ffe01e59 1464 io_port > QXL_IO_FLUSH_RELEASE) {
020af1c4
AL		 1465 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1466 io_port, d->revision);
1467 return;
1468 }
1469
a19cbfb3
GH		 1470 switch (io_port) {
1471 case QXL_IO_RESET:
1472 case QXL_IO_SET_MODE:
1473 case QXL_IO_MEMSLOT_ADD:
1474 case QXL_IO_MEMSLOT_DEL:
1475 case QXL_IO_CREATE_PRIMARY:
81144d1a 1476 case QXL_IO_UPDATE_IRQ:
a3d14054 1477 case QXL_IO_LOG:
5ff4e36c
AL		 1478 case QXL_IO_MEMSLOT_ADD_ASYNC:
1479 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1480 break;
1481 default:
e21a298a 1482 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1483 break;
e21a298a 1484 }
c480bb7d 1485 trace_qxl_io_unexpected_vga_mode(d->id,
917ae08c 1486 addr, val, io_port_to_string(io_port));
5ff4e36c
AL		 1487 /* be nice to buggy guest drivers */
1488 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
020af1c4 1489 io_port < QXL_IO_RANGE_SIZE) {
5ff4e36c
AL		 1490 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1491 }
a19cbfb3
GH		 1492 return;
1493 }
1494
5ff4e36c
AL		 1495 /* we change the io_port to avoid ifdeffery in the main switch */
1496 orig_io_port = io_port;
1497 switch (io_port) {
1498 case QXL_IO_UPDATE_AREA_ASYNC:
1499 io_port = QXL_IO_UPDATE_AREA;
1500 goto async_common;
1501 case QXL_IO_MEMSLOT_ADD_ASYNC:
1502 io_port = QXL_IO_MEMSLOT_ADD;
1503 goto async_common;
1504 case QXL_IO_CREATE_PRIMARY_ASYNC:
1505 io_port = QXL_IO_CREATE_PRIMARY;
1506 goto async_common;
1507 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1508 io_port = QXL_IO_DESTROY_PRIMARY;
1509 goto async_common;
1510 case QXL_IO_DESTROY_SURFACE_ASYNC:
1511 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1512 goto async_common;
1513 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1514 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1515 goto async_common;
1516 case QXL_IO_FLUSH_SURFACES_ASYNC:
020af1c4 1517 case QXL_IO_MONITORS_CONFIG_ASYNC:
5ff4e36c
AL		 1518async_common:
1519 async = QXL_ASYNC;
1520 qemu_mutex_lock(&d->async_lock);
1521 if (d->current_async != QXL_UNDEFINED_IO) {
0a530548 1522 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
5ff4e36c
AL		 1523 io_port, d->current_async);
1524 qemu_mutex_unlock(&d->async_lock);
1525 return;
1526 }
1527 d->current_async = orig_io_port;
1528 qemu_mutex_unlock(&d->async_lock);
5ff4e36c
AL		 1529 break;
1530 default:
1531 break;
1532 }
c480bb7d
AL		 1533 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size,
1534 async);
5ff4e36c 1535
a19cbfb3
GH		 1536 switch (io_port) {
1537 case QXL_IO_UPDATE_AREA:
1538 {
81fb6f15 1539 QXLCookie *cookie = NULL;
a19cbfb3 1540 QXLRect update = d->ram->update_area;
81fb6f15 1541
ddd8fdc7 1542 if (d->ram->update_surface > d->ssd.num_surfaces) {
511b13e2
AL		 1543 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1544 d->ram->update_surface);
36a03e0b 1545 break;
511b13e2 1546 }
36a03e0b
MT		 1547 if (update.left >= update.right || update.top >= update.bottom ||
1548 update.left < 0 || update.top < 0) {
511b13e2
AL		 1549 qxl_set_guest_bug(d,
1550 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1551 update.left, update.top, update.right, update.bottom);
ccc2960d
DH		 1552 break;
1553 }
81fb6f15
AL		 1554 if (async == QXL_ASYNC) {
1555 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1556 QXL_IO_UPDATE_AREA_ASYNC);
1557 cookie->u.area = update;
1558 }
aee32bf3 1559 qxl_spice_update_area(d, d->ram->update_surface,
81fb6f15
AL		 1560 cookie ? &cookie->u.area : &update,
1561 NULL, 0, 0, async, cookie);
a19cbfb3
GH		 1562 break;
1563 }
1564 case QXL_IO_NOTIFY_CMD:
5c59d118 1565 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1566 break;
1567 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1568 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1569 break;
1570 case QXL_IO_UPDATE_IRQ:
40010aea 1571 qxl_update_irq(d);
a19cbfb3
GH		 1572 break;
1573 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1574 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1575 break;
1576 }
1577 d->oom_running = 1;
aee32bf3 1578 qxl_spice_oom(d);
a19cbfb3
GH		 1579 d->oom_running = 0;
1580 break;
1581 case QXL_IO_SET_MODE:
a19cbfb3
GH		 1582 qxl_set_mode(d, val, 0);
1583 break;
1584 case QXL_IO_LOG:
1a1bc085 1585 trace_qxl_io_log(d->id, d->ram->log_buf);
a19cbfb3 1586 if (d->guestdebug) {
a680f7e7 1587 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
6ebebb55 1588 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
a19cbfb3
GH		 1589 }
1590 break;
1591 case QXL_IO_RESET:
a19cbfb3
GH		 1592 qxl_hard_reset(d, 0);
1593 break;
1594 case QXL_IO_MEMSLOT_ADD:
2bce0400 1595 if (val >= NUM_MEMSLOTS) {
0a530548 1596 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
2bce0400
GH		 1597 break;
1598 }
1599 if (d->guest_slots[val].active) {
0a530548
AL		 1600 qxl_set_guest_bug(d,
1601 "QXL_IO_MEMSLOT_ADD: memory slot already active");
2bce0400
GH		 1602 break;
1603 }
a19cbfb3 1604 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1605 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1606 break;
1607 case QXL_IO_MEMSLOT_DEL:
2bce0400 1608 if (val >= NUM_MEMSLOTS) {
0a530548 1609 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
2bce0400
GH		 1610 break;
1611 }
a19cbfb3
GH		 1612 qxl_del_memslot(d, val);
1613 break;
1614 case QXL_IO_CREATE_PRIMARY:
2bce0400 1615 if (val != 0) {
0a530548 1616 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1617 async);
1618 goto cancel_async;
2bce0400 1619 }
a19cbfb3 1620 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1621 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1622 break;
1623 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1624 if (val != 0) {
0a530548 1625 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
5ff4e36c
AL		 1626 async);
1627 goto cancel_async;
1628 }
5ff4e36c 1629 if (!qxl_destroy_primary(d, async)) {
c480bb7d
AL		 1630 trace_qxl_io_destroy_primary_ignored(d->id,
1631 qxl_mode_to_string(d->mode));
5ff4e36c 1632 goto cancel_async;
2bce0400 1633 }
a19cbfb3
GH		 1634 break;
1635 case QXL_IO_DESTROY_SURFACE_WAIT:
ddd8fdc7 1636 if (val >= d->ssd.num_surfaces) {
0a530548 1637 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
5f8daf2e 1638 "%" PRIu64 " >= NUM_SURFACES", async, val);
5ff4e36c
AL		 1639 goto cancel_async;
1640 }
1641 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1642 break;
3e16b9c5
AL		 1643 case QXL_IO_FLUSH_RELEASE: {
1644 QXLReleaseRing *ring = &d->ram->release_ring;
1645 if (ring->prod - ring->cons + 1 == ring->num_items) {
1646 fprintf(stderr,
1647 "ERROR: no flush, full release ring [p%d,%dc]\n",
1648 ring->prod, ring->cons);
1649 }
1650 qxl_push_free_res(d, 1 /* flush */);
3e16b9c5
AL		 1651 break;
1652 }
1653 case QXL_IO_FLUSH_SURFACES_ASYNC:
3e16b9c5
AL		 1654 qxl_spice_flush_surfaces_async(d);
1655 break;
a19cbfb3 1656 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1657 d->mode = QXL_MODE_UNDEFINED;
1658 qxl_spice_destroy_surfaces(d, async);
a19cbfb3 1659 break;
020af1c4
AL		 1660 case QXL_IO_MONITORS_CONFIG_ASYNC:
1661 qxl_spice_monitors_config_async(d, 0);
1662 break;
a19cbfb3 1663 default:
0a530548 1664 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
a19cbfb3 1665 }
5ff4e36c
AL		 1666 return;
1667cancel_async:
5ff4e36c
AL		 1668 if (async) {
1669 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1670 qemu_mutex_lock(&d->async_lock);
1671 d->current_async = QXL_UNDEFINED_IO;
1672 qemu_mutex_unlock(&d->async_lock);
1673 }
a19cbfb3
GH		 1674}
1675
a8170e5e 1676static uint64_t ioport_read(void *opaque, hwaddr addr,
b1950430 1677 unsigned size)
a19cbfb3 1678{
917ae08c 1679 PCIQXLDevice *qxl = opaque;
a19cbfb3 1680
917ae08c 1681 trace_qxl_io_read_unexpected(qxl->id);
a19cbfb3
GH		 1682 return 0xff;
1683}
1684
b1950430
AK		 1685static const MemoryRegionOps qxl_io_ops = {
1686 .read = ioport_read,
1687 .write = ioport_write,
1688 .valid = {
1689 .min_access_size = 1,
1690 .max_access_size = 1,
1691 },
1692};
a19cbfb3
GH		 1693
1694static void pipe_read(void *opaque)
1695{
1696 PCIQXLDevice *d = opaque;
1697 char dummy;
1698 int len;
1699
1700 do {
1701 len = read(d->pipe[0], &dummy, sizeof(dummy));
1702 } while (len == sizeof(dummy));
40010aea 1703 qxl_update_irq(d);
a19cbfb3
GH		 1704}
1705
a19cbfb3
GH		 1706static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1707{
1708 uint32_t old_pending;
1709 uint32_t le_events = cpu_to_le32(events);
1710
917ae08c 1711 trace_qxl_send_events(d->id, events);
511aefb0
AL		 1712 if (!qemu_spice_display_is_running(&d->ssd)) {
1713 /* spice-server tracks guest running state and should not do this */
1714 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1715 __func__);
1716 trace_qxl_send_events_vm_stopped(d->id, events);
1717 return;
1718 }
a19cbfb3
GH		 1719 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1720 if ((old_pending & le_events) == le_events) {
1721 return;
1722 }
691f5c7b 1723 if (qemu_thread_is_self(&d->main)) {
40010aea 1724 qxl_update_irq(d);
a19cbfb3
GH		 1725 } else {
1726 if (write(d->pipe[1], d, 1) != 1) {
75fe0d7b 1727 dprint(d, 1, "%s: write to pipe failed\n", __func__);
a19cbfb3
GH		 1728 }
1729 }
1730}
1731
1732static void init_pipe_signaling(PCIQXLDevice *d)
1733{
aa3db423
AL		 1734 if (pipe(d->pipe) < 0) {
1735 fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
1736 __FILE__, __func__);
1737 exit(1);
1738 }
1739 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1740 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1741 fcntl(d->pipe[0], F_SETOWN, getpid());
1742
1743 qemu_thread_get_self(&d->main);
1744 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
a19cbfb3
GH		 1745}
1746
1747/* graphics console */
1748
1749static void qxl_hw_update(void *opaque)
1750{
1751 PCIQXLDevice *qxl = opaque;
1752 VGACommonState *vga = &qxl->vga;
1753
1754 switch (qxl->mode) {
1755 case QXL_MODE_VGA:
380cd056 1756 vga->hw_ops->gfx_update(vga);
a19cbfb3
GH		 1757 break;
1758 case QXL_MODE_COMPAT:
1759 case QXL_MODE_NATIVE:
1760 qxl_render_update(qxl);
1761 break;
1762 default:
1763 break;
1764 }
1765}
1766
1767static void qxl_hw_invalidate(void *opaque)
1768{
1769 PCIQXLDevice *qxl = opaque;
1770 VGACommonState *vga = &qxl->vga;
1771
380cd056 1772 vga->hw_ops->invalidate(vga);
a19cbfb3
GH		 1773}
1774
a19cbfb3
GH		 1775static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1776{
1777 PCIQXLDevice *qxl = opaque;
1778 VGACommonState *vga = &qxl->vga;
1779
1780 if (qxl->mode == QXL_MODE_VGA) {
380cd056 1781 vga->hw_ops->text_update(vga, chardata);
a19cbfb3
GH		 1782 return;
1783 }
1784}
1785
e25139b3
YH		 1786static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1787{
c5825ac6 1788 uintptr_t vram_start;
e25139b3
YH		 1789 int i;
1790
2aa9e85c 1791 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1792 return;
1793 }
1794
1795 /* dirty the primary surface */
1796 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1797 qxl->shadow_rom.surface0_area_size);
1798
c5825ac6 1799 vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
e25139b3
YH		 1800
1801 /* dirty the off-screen surfaces */
ddd8fdc7 1802 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
e25139b3
YH		 1803 QXLSurfaceCmd *cmd;
1804 intptr_t surface_offset;
1805 int surface_size;
1806
1807 if (qxl->guest_surfaces.cmds[i] == 0) {
1808 continue;
1809 }
1810
1811 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1812 MEMSLOT_GROUP_GUEST);
fae2afb1 1813 assert(cmd);
e25139b3
YH		 1814 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1815 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1816 cmd->u.surface_create.data,
1817 MEMSLOT_GROUP_GUEST);
fae2afb1 1818 assert(surface_offset);
e25139b3
YH		 1819 surface_offset -= vram_start;
1820 surface_size = cmd->u.surface_create.height *
1821 abs(cmd->u.surface_create.stride);
c480bb7d 1822 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
e25139b3
YH		 1823 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1824 }
1825}
1826
1dfb4dd9
LC		 1827static void qxl_vm_change_state_handler(void *opaque, int running,
1828 RunState state)
a19cbfb3
GH		 1829{
1830 PCIQXLDevice *qxl = opaque;
a19cbfb3 1831
efbf2950
YH		 1832 if (running) {
1833 /*
1834 * if qxl_send_events was called from spice server context before
40010aea 1835 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1836 * called
1837 */
40010aea 1838 qxl_update_irq(qxl);
e25139b3
YH		 1839 } else {
1840 /* make sure surfaces are saved before migration */
1841 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 1842 }
1843}
1844
1845/* display change listener */
1846
7c20b4a3 1847static void display_update(DisplayChangeListener *dcl,
7c20b4a3 1848 int x, int y, int w, int h)
a19cbfb3 1849{
c6c06853
GH		 1850 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1851
1852 if (qxl->mode == QXL_MODE_VGA) {
1853 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
a19cbfb3
GH		 1854 }
1855}
1856
c12aeb86 1857static void display_switch(DisplayChangeListener *dcl,
c12aeb86 1858 struct DisplaySurface *surface)
a19cbfb3 1859{
c6c06853
GH		 1860 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1861
71874c17 1862 qxl->ssd.ds = surface;
c6c06853 1863 if (qxl->mode == QXL_MODE_VGA) {
c12aeb86 1864 qemu_spice_display_switch(&qxl->ssd, surface);
a19cbfb3
GH		 1865 }
1866}
1867
bc2ed970 1868static void display_refresh(DisplayChangeListener *dcl)
a19cbfb3 1869{
c6c06853
GH		 1870 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
1871
1872 if (qxl->mode == QXL_MODE_VGA) {
1873 qemu_spice_display_refresh(&qxl->ssd);
bb5a8cd5 1874 } else {
c6c06853
GH		 1875 qemu_mutex_lock(&qxl->ssd.lock);
1876 qemu_spice_cursor_refresh_unlocked(&qxl->ssd);
1877 qemu_mutex_unlock(&qxl->ssd.lock);
a19cbfb3
GH		 1878 }
1879}
1880
7c20b4a3
GH		 1881static DisplayChangeListenerOps display_listener_ops = {
1882 .dpy_name = "spice/qxl",
a93a4a22 1883 .dpy_gfx_update = display_update,
c12aeb86 1884 .dpy_gfx_switch = display_switch,
7c20b4a3 1885 .dpy_refresh = display_refresh,
a19cbfb3
GH		 1886};
1887
13d1fd44 1888static void qxl_init_ramsize(PCIQXLDevice *qxl)
a974192c 1889{
13d1fd44
AL		 1890 /* vga mode framebuffer / primary surface (bar 0, first part) */
1891 if (qxl->vgamem_size_mb < 8) {
1892 qxl->vgamem_size_mb = 8;
1893 }
1894 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1895
1896 /* vga ram (bar 0, total) */
017438ee
GH		 1897 if (qxl->ram_size_mb != -1) {
1898 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1899 }
13d1fd44
AL		 1900 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1901 qxl->vga.vram_size = qxl->vgamem_size * 2;
a974192c
GH		 1902 }
1903
6f2b175a
GH		 1904 /* vram32 (surfaces, 32bit, bar 1) */
1905 if (qxl->vram32_size_mb != -1) {
1906 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1907 }
1908 if (qxl->vram32_size < 4096) {
1909 qxl->vram32_size = 4096;
1910 }
1911
1912 /* vram (surfaces, 64bit, bar 4+5) */
017438ee
GH		 1913 if (qxl->vram_size_mb != -1) {
1914 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1915 }
6f2b175a
GH		 1916 if (qxl->vram_size < qxl->vram32_size) {
1917 qxl->vram_size = qxl->vram32_size;
a974192c 1918 }
6f2b175a 1919
a974192c 1920 if (qxl->revision == 1) {
6f2b175a 1921 qxl->vram32_size = 4096;
a974192c
GH		 1922 qxl->vram_size = 4096;
1923 }
13d1fd44 1924 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
a974192c 1925 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
6f2b175a 1926 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
a974192c
GH		 1927 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1928}
1929
a19cbfb3
GH		 1930static int qxl_init_common(PCIQXLDevice *qxl)
1931{
1932 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1933 uint32_t pci_device_rev;
1934 uint32_t io_size;
1935
1936 qxl->mode = QXL_MODE_UNDEFINED;
1937 qxl->generation = 1;
1938 qxl->num_memslots = NUM_MEMSLOTS;
14898cf6 1939 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 1940 qemu_mutex_init(&qxl->async_lock);
1941 qxl->current_async = QXL_UNDEFINED_IO;
087e6a42 1942 qxl->guest_bug = 0;
a19cbfb3
GH		 1943
1944 switch (qxl->revision) {
1945 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3 1946 pci_device_rev = QXL_REVISION_STABLE_V04;
3f6297b9 1947 io_size = 8;
a19cbfb3
GH		 1948 break;
1949 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3 1950 pci_device_rev = QXL_REVISION_STABLE_V06;
3f6297b9 1951 io_size = 16;
a19cbfb3 1952 break;
9197a7c8 1953 case 3: /* qxl-3 */
020af1c4
AL		 1954 pci_device_rev = QXL_REVISION_STABLE_V10;
1955 io_size = 32; /* PCI region size must be pow2 */
1956 break;
020af1c4
AL		 1957 case 4: /* qxl-4 */
1958 pci_device_rev = QXL_REVISION_STABLE_V12;
3f6297b9 1959 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
9197a7c8 1960 break;
36839d35
AL		 1961 default:
1962 error_report("Invalid revision %d for qxl device (max %d)",
1963 qxl->revision, QXL_DEFAULT_REVISION);
1964 return -1;
a19cbfb3
GH		 1965 }
1966
a19cbfb3
GH		 1967 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1968 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1969
1970 qxl->rom_size = qxl_rom_size();
c5705a77
AK		 1971 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1972 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
a19cbfb3
GH		 1973 init_qxl_rom(qxl);
1974 init_qxl_ram(qxl);
1975
ddd8fdc7 1976 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
c5705a77
AK		 1977 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1978 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
6f2b175a
GH		 1979 memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
1980 0, qxl->vram32_size);
a19cbfb3 1981
b1950430
AK		 1982 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1983 "qxl-ioports", io_size);
1984 if (qxl->id == 0) {
1985 vga_dirty_log_start(&qxl->vga);
1986 }
bd8f2f5d 1987 memory_region_set_flush_coalesced(&qxl->io_bar);
b1950430
AK		 1988
1989
e824b2cc
AK		 1990 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1991 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 1992
e824b2cc
AK		 1993 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1994 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 1995
e824b2cc
AK		 1996 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1997 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 1998
e824b2cc 1999 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
6f2b175a
GH		 2000 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2001
2002 if (qxl->vram32_size < qxl->vram_size) {
2003 /*
2004 * Make the 64bit vram bar show up only in case it is
2005 * configured to be larger than the 32bit vram bar.
2006 */
2007 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2008 PCI_BASE_ADDRESS_SPACE_MEMORY |
2009 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2010 PCI_BASE_ADDRESS_MEM_PREFETCH,
2011 &qxl->vram_bar);
2012 }
2013
2014 /* print pci bar details */
2015 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2016 qxl->id == 0 ? "pri" : "sec",
2017 qxl->vga.vram_size / (1024*1024));
2018 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2019 qxl->vram32_size / (1024*1024));
2020 dprint(qxl, 1, "vram/64: %d MB %s\n",
2021 qxl->vram_size / (1024*1024),
2022 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
a19cbfb3
GH		 2023
2024 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2025 qxl->ssd.qxl.id = qxl->id;
e25a0651 2026 if (qemu_spice_add_interface(&qxl->ssd.qxl.base) != 0) {
312fd5f2 2027 error_report("qxl interface %d.%d not supported by spice-server",
e25a0651
AL		 2028 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2029 return -1;
2030 }
a19cbfb3
GH		 2031 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2032
2033 init_pipe_signaling(qxl);
2034 qxl_reset_state(qxl);
2035
81fb6f15
AL		 2036 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2037
a19cbfb3
GH		 2038 return 0;
2039}
2040
380cd056
GH		 2041static const GraphicHwOps qxl_ops = {
2042 .invalidate = qxl_hw_invalidate,
2043 .gfx_update = qxl_hw_update,
2044 .text_update = qxl_hw_text_update,
2045};
2046
a19cbfb3
GH		 2047static int qxl_init_primary(PCIDevice *dev)
2048{
2049 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2050 VGACommonState *vga = &qxl->vga;
f67ab77a 2051 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
c78f7137 2052 DisplayState *ds;
bdd4df33 2053 int rc;
a19cbfb3
GH		 2054
2055 qxl->id = 0;
13d1fd44 2056 qxl_init_ramsize(qxl);
4a1e244e
GH		 2057 vga->vram_size_mb = qxl->vga.vram_size >> 20;
2058 vga_common_init(vga);
0a039dc7 2059 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
f67ab77a
GH		 2060 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
2061 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
a19cbfb3 2062
380cd056 2063 vga->con = graphic_console_init(&qxl_ops, qxl);
c78f7137
GH		 2064 qxl->ssd.con = vga->con,
2065 qemu_spice_display_init_common(&qxl->ssd);
a19cbfb3 2066
bdd4df33
GH		 2067 rc = qxl_init_common(qxl);
2068 if (rc != 0) {
2069 return rc;
2070 }
2071
7c20b4a3 2072 qxl->ssd.dcl.ops = &display_listener_ops;
c78f7137
GH		 2073 ds = qemu_console_displaystate(vga->con);
2074 register_displaychangelistener(ds, &qxl->ssd.dcl);
bdd4df33 2075 return rc;
a19cbfb3
GH		 2076}
2077
2078static int qxl_init_secondary(PCIDevice *dev)
2079{
2080 static int device_id = 1;
2081 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
a19cbfb3
GH		 2082
2083 qxl->id = device_id++;
13d1fd44 2084 qxl_init_ramsize(qxl);
c5705a77
AK		 2085 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
2086 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
b1950430 2087 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
a19cbfb3 2088
a19cbfb3
GH		 2089 return qxl_init_common(qxl);
2090}
2091
2092static void qxl_pre_save(void *opaque)
2093{
2094 PCIQXLDevice* d = opaque;
2095 uint8_t *ram_start = d->vga.vram_ptr;
2096
c480bb7d 2097 trace_qxl_pre_save(d->id);
a19cbfb3
GH		 2098 if (d->last_release == NULL) {
2099 d->last_release_offset = 0;
2100 } else {
2101 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2102 }
2103 assert(d->last_release_offset < d->vga.vram_size);
2104}
2105
2106static int qxl_pre_load(void *opaque)
2107{
2108 PCIQXLDevice* d = opaque;
2109
c480bb7d 2110 trace_qxl_pre_load(d->id);
a19cbfb3
GH		 2111 qxl_hard_reset(d, 1);
2112 qxl_exit_vga_mode(d);
a19cbfb3
GH		 2113 return 0;
2114}
2115
54825d2e
AL		 2116static void qxl_create_memslots(PCIQXLDevice *d)
2117{
2118 int i;
2119
2120 for (i = 0; i < NUM_MEMSLOTS; i++) {
2121 if (!d->guest_slots[i].active) {
2122 continue;
2123 }
54825d2e
AL		 2124 qxl_add_memslot(d, i, 0, QXL_SYNC);
2125 }
2126}
2127
a19cbfb3
GH		 2128static int qxl_post_load(void *opaque, int version)
2129{
2130 PCIQXLDevice* d = opaque;
2131 uint8_t *ram_start = d->vga.vram_ptr;
2132 QXLCommandExt *cmds;
54825d2e 2133 int in, out, newmode;
a19cbfb3 2134
a19cbfb3
GH		 2135 assert(d->last_release_offset < d->vga.vram_size);
2136 if (d->last_release_offset == 0) {
2137 d->last_release = NULL;
2138 } else {
2139 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2140 }
2141
2142 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2143
c480bb7d 2144 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
a19cbfb3
GH		 2145 newmode = d->mode;
2146 d->mode = QXL_MODE_UNDEFINED;
54825d2e 2147
a19cbfb3
GH		 2148 switch (newmode) {
2149 case QXL_MODE_UNDEFINED:
fa98efe9 2150 qxl_create_memslots(d);
a19cbfb3
GH		 2151 break;
2152 case QXL_MODE_VGA:
54825d2e 2153 qxl_create_memslots(d);
a19cbfb3
GH		 2154 qxl_enter_vga_mode(d);
2155 break;
2156 case QXL_MODE_NATIVE:
54825d2e 2157 qxl_create_memslots(d);
5ff4e36c 2158 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 2159
2160 /* replay surface-create and cursor-set commands */
ddd8fdc7
GH		 2161 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2162 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
a19cbfb3
GH		 2163 if (d->guest_surfaces.cmds[in] == 0) {
2164 continue;
2165 }
2166 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2167 cmds[out].cmd.type = QXL_CMD_SURFACE;
2168 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2169 out++;
2170 }
30f6da66
YH		 2171 if (d->guest_cursor) {
2172 cmds[out].cmd.data = d->guest_cursor;
2173 cmds[out].cmd.type = QXL_CMD_CURSOR;
2174 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2175 out++;
2176 }
aee32bf3 2177 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 2178 g_free(cmds);
020af1c4
AL		 2179 if (d->guest_monitors_config) {
2180 qxl_spice_monitors_config_async(d, 1);
2181 }
a19cbfb3
GH		 2182 break;
2183 case QXL_MODE_COMPAT:
54825d2e
AL		 2184 /* note: no need to call qxl_create_memslots, qxl_set_mode
2185 * creates the mem slot. */
a19cbfb3
GH		 2186 qxl_set_mode(d, d->shadow_rom.mode, 1);
2187 break;
2188 }
a19cbfb3
GH		 2189 return 0;
2190}
2191
b67737a6 2192#define QXL_SAVE_VERSION 21
a19cbfb3 2193
020af1c4
AL		 2194static bool qxl_monitors_config_needed(void *opaque)
2195{
2196 PCIQXLDevice *qxl = opaque;
2197
2198 return qxl->guest_monitors_config != 0;
2199}
2200
2201
a19cbfb3
GH		 2202static VMStateDescription qxl_memslot = {
2203 .name = "qxl-memslot",
2204 .version_id = QXL_SAVE_VERSION,
2205 .minimum_version_id = QXL_SAVE_VERSION,
2206 .fields = (VMStateField[]) {
2207 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2208 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2209 VMSTATE_UINT32(active, struct guest_slots),
2210 VMSTATE_END_OF_LIST()
2211 }
2212};
2213
2214static VMStateDescription qxl_surface = {
2215 .name = "qxl-surface",
2216 .version_id = QXL_SAVE_VERSION,
2217 .minimum_version_id = QXL_SAVE_VERSION,
2218 .fields = (VMStateField[]) {
2219 VMSTATE_UINT32(width, QXLSurfaceCreate),
2220 VMSTATE_UINT32(height, QXLSurfaceCreate),
2221 VMSTATE_INT32(stride, QXLSurfaceCreate),
2222 VMSTATE_UINT32(format, QXLSurfaceCreate),
2223 VMSTATE_UINT32(position, QXLSurfaceCreate),
2224 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2225 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2226 VMSTATE_UINT32(type, QXLSurfaceCreate),
2227 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2228 VMSTATE_END_OF_LIST()
2229 }
2230};
2231
020af1c4
AL		 2232static VMStateDescription qxl_vmstate_monitors_config = {
2233 .name = "qxl/monitors-config",
2234 .version_id = 1,
2235 .minimum_version_id = 1,
2236 .fields = (VMStateField[]) {
2237 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2238 VMSTATE_END_OF_LIST()
2239 },
2240};
2241
a19cbfb3
GH		 2242static VMStateDescription qxl_vmstate = {
2243 .name = "qxl",
2244 .version_id = QXL_SAVE_VERSION,
2245 .minimum_version_id = QXL_SAVE_VERSION,
2246 .pre_save = qxl_pre_save,
2247 .pre_load = qxl_pre_load,
2248 .post_load = qxl_post_load,
020af1c4 2249 .fields = (VMStateField[]) {
a19cbfb3
GH		 2250 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2251 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2252 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2253 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2254 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2255 VMSTATE_UINT32(mode, PCIQXLDevice),
2256 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 2257 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2258 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2259 qxl_memslot, struct guest_slots),
2260 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2261 qxl_surface, QXLSurfaceCreate),
ddd8fdc7
GH		 2262 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2263 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2264 ssd.num_surfaces, 0,
2265 vmstate_info_uint64, uint64_t),
b67737a6 2266 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 2267 VMSTATE_END_OF_LIST()
2268 },
020af1c4
AL		 2269 .subsections = (VMStateSubsection[]) {
2270 {
2271 .vmsd = &qxl_vmstate_monitors_config,
2272 .needed = qxl_monitors_config_needed,
2273 }, {
2274 /* empty */
2275 }
2276 }
a19cbfb3
GH		 2277};
2278
78e60ba5
GH		 2279static Property qxl_properties[] = {
2280 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2281 64 * 1024 * 1024),
6f2b175a 2282 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
78e60ba5
GH		 2283 64 * 1024 * 1024),
2284 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2285 QXL_DEFAULT_REVISION),
2286 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2287 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2288 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee 2289 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
79ce3567
AL		 2290 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2291 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
9e56edcf 2292 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
ddd8fdc7 2293 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
78e60ba5
GH		 2294 DEFINE_PROP_END_OF_LIST(),
2295};
2296
40021f08
AL		 2297static void qxl_primary_class_init(ObjectClass *klass, void *data)
2298{
39bffca2 2299 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2300 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2301
2302 k->no_hotplug = 1;
2303 k->init = qxl_init_primary;
2304 k->romfile = "vgabios-qxl.bin";
2305 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2306 k->device_id = QXL_DEVICE_ID_STABLE;
2307 k->class_id = PCI_CLASS_DISPLAY_VGA;
39bffca2
AL		 2308 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2309 dc->reset = qxl_reset_handler;
2310 dc->vmsd = &qxl_vmstate;
2311 dc->props = qxl_properties;
40021f08
AL		 2312}
2313
8c43a6f0 2314static const TypeInfo qxl_primary_info = {
39bffca2
AL		 2315 .name = "qxl-vga",
2316 .parent = TYPE_PCI_DEVICE,
2317 .instance_size = sizeof(PCIQXLDevice),
2318 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 2319};
2320
40021f08
AL		 2321static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2322{
39bffca2 2323 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2324 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2325
2326 k->init = qxl_init_secondary;
2327 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2328 k->device_id = QXL_DEVICE_ID_STABLE;
2329 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2
AL		 2330 dc->desc = "Spice QXL GPU (secondary)";
2331 dc->reset = qxl_reset_handler;
2332 dc->vmsd = &qxl_vmstate;
2333 dc->props = qxl_properties;
40021f08
AL		 2334}
2335
8c43a6f0 2336static const TypeInfo qxl_secondary_info = {
39bffca2
AL		 2337 .name = "qxl",
2338 .parent = TYPE_PCI_DEVICE,
2339 .instance_size = sizeof(PCIQXLDevice),
2340 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 2341};
2342
83f7d43a 2343static void qxl_register_types(void)
a19cbfb3 2344{
39bffca2
AL		 2345 type_register_static(&qxl_primary_info);
2346 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 2347}
2348
83f7d43a 2349type_init(qxl_register_types)
Empty description
This page took 0.715078 seconds and 4 git commands to generate.