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target/ppc: Flush TLB on write to PIDR
[qemu.git] / target / ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
f7aa5583 5 * Copyright 2011 Freescale Semiconductor, Inc.
3fc6c082
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 19 */
20
0d75590d 21#include "qemu/osdep.h"
76cad711 22#include "disas/bfd.h"
022c62cb 23#include "exec/gdbstub.h"
a1e98583 24#include "kvm_ppc.h"
9c17d615 25#include "sysemu/arch_init.h"
fe828a4d 26#include "sysemu/cpus.h"
b3946626 27#include "sysemu/hw_accel.h"
953af181 28#include "cpu-models.h"
b632a148
DG		 29#include "mmu-hash32.h"
30#include "mmu-hash64.h"
4a44d85e 31#include "qemu/error-report.h"
8dfa3a5e
AK		 32#include "qapi/visitor.h"
33#include "hw/qdev-properties.h"
aa5a9e24 34#include "hw/ppc/ppc.h"
b2899495 35#include "mmu-book3s-v3.h"
237c0af0 36
3fc6c082
FB		 37//#define PPC_DUMP_CPU
38//#define PPC_DEBUG_SPR
80d11f44 39//#define PPC_DUMP_SPR_ACCESSES
b3cad3ab 40/* #define USE_APPLE_GDB */
3fc6c082 41
3fc6c082
FB		 42/* Generic callbacks:
43 * do nothing but store/retrieve spr value
44 */
91f477fd
AG		 45static void spr_load_dump_spr(int sprn)
46{
47#ifdef PPC_DUMP_SPR_ACCESSES
48 TCGv_i32 t0 = tcg_const_i32(sprn);
edbe35e0 49 gen_helper_load_dump_spr(cpu_env, t0);
91f477fd
AG		 50 tcg_temp_free_i32(t0);
51#endif
52}
53
69b058c8 54static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
a496775f 55{
45d827d2 56 gen_load_spr(cpu_gpr[gprn], sprn);
91f477fd
AG		 57 spr_load_dump_spr(sprn);
58}
59
60static void spr_store_dump_spr(int sprn)
61{
45d827d2 62#ifdef PPC_DUMP_SPR_ACCESSES
91f477fd 63 TCGv_i32 t0 = tcg_const_i32(sprn);
edbe35e0 64 gen_helper_store_dump_spr(cpu_env, t0);
91f477fd 65 tcg_temp_free_i32(t0);
45d827d2 66#endif
a496775f
JM		 67}
68
69b058c8 69static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
a496775f 70{
45d827d2 71 gen_store_spr(sprn, cpu_gpr[gprn]);
91f477fd 72 spr_store_dump_spr(sprn);
45d827d2 73}
a496775f
JM		 74
75#if !defined(CONFIG_USER_ONLY)
69b058c8 76static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
ba38ab8d
AG		 77{
78#ifdef TARGET_PPC64
79 TCGv t0 = tcg_temp_new();
80 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
81 gen_store_spr(sprn, t0);
82 tcg_temp_free(t0);
83 spr_store_dump_spr(sprn);
84#else
69b058c8 85 spr_write_generic(ctx, sprn, gprn);
ba38ab8d
AG		 86#endif
87}
88
69b058c8 89static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
a496775f 90{
45d827d2
AJ		 91 TCGv t0 = tcg_temp_new();
92 TCGv t1 = tcg_temp_new();
93 gen_load_spr(t0, sprn);
94 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
95 tcg_gen_and_tl(t0, t0, t1);
96 gen_store_spr(sprn, t0);
97 tcg_temp_free(t0);
98 tcg_temp_free(t1);
a496775f 99}
9633fcc6 100
69b058c8 101static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
9633fcc6
AG		 102{
103}
104
a496775f
JM		 105#endif
106
76a66253 107/* SPR common to all PowerPC */
3fc6c082 108/* XER */
69b058c8 109static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
3fc6c082 110{
dd09c361 111 gen_read_xer(ctx, cpu_gpr[gprn]);
3fc6c082
FB		 112}
113
69b058c8 114static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
3fc6c082 115{
da91a00f 116 gen_write_xer(cpu_gpr[gprn]);
3fc6c082
FB		 117}
118
119/* LR */
69b058c8 120static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
3fc6c082 121{
45d827d2 122 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 123}
124
69b058c8 125static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
3fc6c082 126{
45d827d2 127 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 128}
129
697ab892
DG		 130/* CFAR */
131#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
69b058c8 132static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
697ab892
DG		 133{
134 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
135}
136
69b058c8 137static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
697ab892
DG		 138{
139 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
140}
141#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
142
3fc6c082 143/* CTR */
69b058c8 144static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
3fc6c082 145{
45d827d2 146 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 147}
148
69b058c8 149static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
3fc6c082 150{
45d827d2 151 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 152}
153
154/* User read access to SPR */
155/* USPRx */
156/* UMMCRx */
157/* UPMCx */
158/* USIA */
159/* UDECR */
69b058c8 160static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
3fc6c082 161{
45d827d2 162 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 163}
164
fd51ff63 165#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
69b058c8 166static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
fd51ff63
AK		 167{
168 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
169}
170#endif
171
76a66253 172/* SPR common to all non-embedded PowerPC */
3fc6c082 173/* DECR */
76a66253 174#if !defined(CONFIG_USER_ONLY)
69b058c8 175static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
3fc6c082 176{
bd79255d 177 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0
TG		 178 gen_io_start();
179 }
d0f1562d 180 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
bd79255d 181 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0 182 gen_io_end();
69b058c8 183 gen_stop_exception(ctx);
630ecca0 184 }
3fc6c082
FB		 185}
186
69b058c8 187static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
3fc6c082 188{
bd79255d 189 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0
TG		 190 gen_io_start();
191 }
d0f1562d 192 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
bd79255d 193 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0 194 gen_io_end();
69b058c8 195 gen_stop_exception(ctx);
630ecca0 196 }
3fc6c082 197}
76a66253 198#endif
3fc6c082 199
76a66253 200/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 201/* Time base */
69b058c8 202static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
3fc6c082 203{
bd79255d 204 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0
TG		 205 gen_io_start();
206 }
d0f1562d 207 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
bd79255d 208 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0 209 gen_io_end();
69b058c8 210 gen_stop_exception(ctx);
630ecca0 211 }
3fc6c082
FB		 212}
213
69b058c8 214static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
3fc6c082 215{
bd79255d 216 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0
TG		 217 gen_io_start();
218 }
d0f1562d 219 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
bd79255d 220 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0 221 gen_io_end();
69b058c8 222 gen_stop_exception(ctx);
630ecca0 223 }
3fc6c082
FB		 224}
225
a062e36c 226__attribute__ (( unused ))
69b058c8 227static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
a062e36c 228{
d0f1562d 229 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 230}
231
232__attribute__ (( unused ))
69b058c8 233static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
a062e36c 234{
d0f1562d 235 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 236}
237
76a66253 238#if !defined(CONFIG_USER_ONLY)
69b058c8 239static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
3fc6c082 240{
bd79255d 241 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0
TG		 242 gen_io_start();
243 }
d0f1562d 244 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
bd79255d 245 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0 246 gen_io_end();
69b058c8 247 gen_stop_exception(ctx);
630ecca0 248 }
3fc6c082
FB		 249}
250
69b058c8 251static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
3fc6c082 252{
bd79255d 253 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0
TG		 254 gen_io_start();
255 }
d0f1562d 256 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
bd79255d 257 if (ctx->tb->cflags & CF_USE_ICOUNT) {
630ecca0 258 gen_io_end();
69b058c8 259 gen_stop_exception(ctx);
630ecca0 260 }
3fc6c082 261}
a062e36c
JM		 262
263__attribute__ (( unused ))
69b058c8 264static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
a062e36c 265{
d0f1562d 266 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
a062e36c
JM		 267}
268
269__attribute__ (( unused ))
69b058c8 270static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
a062e36c 271{
d0f1562d 272 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
a062e36c 273}
3a7f009a
DG		 274
275#if defined(TARGET_PPC64)
276__attribute__ (( unused ))
69b058c8 277static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
3a7f009a 278{
d0f1562d 279 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
3a7f009a 280}
4b236b62
BH		 281
282/* HDECR */
283static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
284{
285 if (ctx->tb->cflags & CF_USE_ICOUNT) {
286 gen_io_start();
287 }
288 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
289 if (ctx->tb->cflags & CF_USE_ICOUNT) {
290 gen_io_end();
291 gen_stop_exception(ctx);
292 }
293}
294
295static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
296{
297 if (ctx->tb->cflags & CF_USE_ICOUNT) {
298 gen_io_start();
299 }
300 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
301 if (ctx->tb->cflags & CF_USE_ICOUNT) {
302 gen_io_end();
303 gen_stop_exception(ctx);
304 }
305}
306
3a7f009a 307#endif
76a66253 308#endif
3fc6c082 309
76a66253 310#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 311/* IBAT0U...IBAT0U */
312/* IBAT0L...IBAT7L */
69b058c8 313static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
3fc6c082 314{
1328c2bf 315 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 316}
317
69b058c8 318static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
3fc6c082 319{
3ede8f69 320 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
3fc6c082
FB		 321}
322
69b058c8 323static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
3fc6c082 324{
45d827d2 325 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 326 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 327 tcg_temp_free_i32(t0);
3fc6c082
FB		 328}
329
69b058c8 330static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
3fc6c082 331{
8daf1781 332 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
c6c7cf05 333 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 334 tcg_temp_free_i32(t0);
3fc6c082
FB		 335}
336
69b058c8 337static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
3fc6c082 338{
45d827d2 339 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
c6c7cf05 340 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 341 tcg_temp_free_i32(t0);
3fc6c082
FB		 342}
343
69b058c8 344static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
3fc6c082 345{
8daf1781 346 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
c6c7cf05 347 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 348 tcg_temp_free_i32(t0);
3fc6c082
FB		 349}
350
351/* DBAT0U...DBAT7U */
352/* DBAT0L...DBAT7L */
69b058c8 353static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
3fc6c082 354{
1328c2bf 355 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 356}
357
69b058c8 358static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
3fc6c082 359{
1328c2bf 360 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 361}
362
69b058c8 363static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
3fc6c082 364{
45d827d2 365 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
c6c7cf05 366 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 367 tcg_temp_free_i32(t0);
3fc6c082
FB		 368}
369
69b058c8 370static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
3fc6c082 371{
45d827d2 372 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
c6c7cf05 373 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 374 tcg_temp_free_i32(t0);
3fc6c082
FB		 375}
376
69b058c8 377static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
3fc6c082 378{
45d827d2 379 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
c6c7cf05 380 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 381 tcg_temp_free_i32(t0);
3fc6c082
FB		 382}
383
69b058c8 384static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
3fc6c082 385{
45d827d2 386 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
c6c7cf05 387 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 388 tcg_temp_free_i32(t0);
3fc6c082
FB		 389}
390
391/* SDR1 */
69b058c8 392static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
3fc6c082 393{
d523dd00 394 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
3fc6c082
FB		 395}
396
578bb252 397#if defined(TARGET_PPC64)
31b2b0f8
SJS		 398/* 64 bits PowerPC specific SPRs */
399/* PIDR */
400static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
401{
402 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
403}
404
69b058c8 405static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
2adab7d6 406{
1328c2bf 407 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 408}
409
69b058c8 410static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
2adab7d6
BS		 411{
412 TCGv t0 = tcg_temp_new();
413 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
1328c2bf 414 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 415 tcg_temp_free(t0);
416}
76a66253 417#endif
a750fc0b 418#endif
76a66253
JM		 419
420/* PowerPC 601 specific registers */
421/* RTC */
69b058c8 422static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
76a66253 423{
d0f1562d 424 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
76a66253
JM		 425}
426
69b058c8 427static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
76a66253 428{
d0f1562d 429 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
76a66253
JM		 430}
431
432#if !defined(CONFIG_USER_ONLY)
69b058c8 433static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
76a66253 434{
d0f1562d 435 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 436}
437
69b058c8 438static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
76a66253 439{
d0f1562d 440 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
76a66253 441}
056401ea 442
69b058c8 443static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
056401ea 444{
d523dd00 445 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
056401ea 446 /* Must stop the translation as endianness may have changed */
e06fcd75 447 gen_stop_exception(ctx);
056401ea 448}
76a66253
JM		 449#endif
450
451/* Unified bats */
452#if !defined(CONFIG_USER_ONLY)
69b058c8 453static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
76a66253 454{
1328c2bf 455 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 456}
457
69b058c8 458static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
76a66253 459{
45d827d2 460 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 461 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 462 tcg_temp_free_i32(t0);
76a66253
JM		 463}
464
69b058c8 465static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
76a66253 466{
45d827d2 467 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 468 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 469 tcg_temp_free_i32(t0);
76a66253
JM		 470}
471#endif
472
473/* PowerPC 40x specific registers */
474#if !defined(CONFIG_USER_ONLY)
69b058c8 475static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
76a66253 476{
d0f1562d 477 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
76a66253
JM		 478}
479
69b058c8 480static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
76a66253 481{
d0f1562d 482 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 483}
484
69b058c8 485static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
8ecc7913 486{
d523dd00 487 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
8ecc7913 488 /* We must stop translation as we may have rebooted */
e06fcd75 489 gen_stop_exception(ctx);
8ecc7913
JM		 490}
491
69b058c8 492static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
c294fc58 493{
d523dd00 494 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
c294fc58
JM		 495}
496
69b058c8 497static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
76a66253 498{
d0f1562d 499 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 500}
501
69b058c8 502static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
76a66253 503{
d0f1562d 504 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 505}
506#endif
507
508/* PowerPC 403 specific registers */
509/* PBL1 / PBU1 / PBL2 / PBU2 */
510#if !defined(CONFIG_USER_ONLY)
69b058c8 511static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
76a66253 512{
1328c2bf 513 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 514}
515
69b058c8 516static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
76a66253 517{
45d827d2 518 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
d523dd00 519 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 520 tcg_temp_free_i32(t0);
76a66253
JM		 521}
522
69b058c8 523static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
3fc6c082 524{
45d827d2
AJ		 525 TCGv t0 = tcg_temp_new();
526 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
527 gen_store_spr(SPR_PIR, t0);
528 tcg_temp_free(t0);
3fc6c082 529}
76a66253 530#endif
3fc6c082 531
d34defbc 532/* SPE specific registers */
69b058c8 533static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
d34defbc
AJ		 534{
535 TCGv_i32 t0 = tcg_temp_new_i32();
1328c2bf 536 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 537 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
538 tcg_temp_free_i32(t0);
539}
540
69b058c8 541static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
d34defbc
AJ		 542{
543 TCGv_i32 t0 = tcg_temp_new_i32();
544 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1328c2bf 545 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 546 tcg_temp_free_i32(t0);
547}
548
6f5d427d
JM		 549#if !defined(CONFIG_USER_ONLY)
550/* Callback used to write the exception vector base */
69b058c8 551static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
6f5d427d 552{
45d827d2 553 TCGv t0 = tcg_temp_new();
1328c2bf 554 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
45d827d2 555 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 556 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
45d827d2 557 gen_store_spr(sprn, t0);
69bd5820 558 tcg_temp_free(t0);
6f5d427d
JM		 559}
560
69b058c8 561static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
6f5d427d 562{
e9205258 563 int sprn_offs;
6f5d427d
JM		 564
565 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
e9205258 566 sprn_offs = sprn - SPR_BOOKE_IVOR0;
6f5d427d 567 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
e9205258
AG		 568 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
569 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
570 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
6f5d427d
JM		 571 } else {
572 printf("Trying to write an unknown exception vector %d %03x\n",
573 sprn, sprn);
e06fcd75 574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
e9205258 575 return;
6f5d427d 576 }
e9205258
AG		 577
578 TCGv t0 = tcg_temp_new();
1328c2bf 579 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
e9205258 580 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 581 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
e9205258
AG		 582 gen_store_spr(sprn, t0);
583 tcg_temp_free(t0);
6f5d427d
JM		 584}
585#endif
586
cf8358c8
AJ		 587static inline void vscr_init (CPUPPCState *env, uint32_t val)
588{
589 env->vscr = val;
590 /* Altivec always uses round-to-nearest */
591 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
592 set_flush_to_zero(vscr_nj, &env->vec_status);
593}
594
d67d40ea
DG		 595#ifdef CONFIG_USER_ONLY
596#define spr_register_kvm(env, num, name, uea_read, uea_write, \
597 oea_read, oea_write, one_reg_id, initial_value) \
598 _spr_register(env, num, name, uea_read, uea_write, initial_value)
eb94268e
BH		 599#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
600 oea_read, oea_write, hea_read, hea_write, \
601 one_reg_id, initial_value) \
602 _spr_register(env, num, name, uea_read, uea_write, initial_value)
d67d40ea
DG		 603#else
604#if !defined(CONFIG_KVM)
605#define spr_register_kvm(env, num, name, uea_read, uea_write, \
eb94268e
BH		 606 oea_read, oea_write, one_reg_id, initial_value) \
607 _spr_register(env, num, name, uea_read, uea_write, \
608 oea_read, oea_write, oea_read, oea_write, initial_value)
609#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
610 oea_read, oea_write, hea_read, hea_write, \
611 one_reg_id, initial_value) \
d67d40ea 612 _spr_register(env, num, name, uea_read, uea_write, \
eb94268e 613 oea_read, oea_write, hea_read, hea_write, initial_value)
76a66253 614#else
d67d40ea 615#define spr_register_kvm(env, num, name, uea_read, uea_write, \
eb94268e
BH		 616 oea_read, oea_write, one_reg_id, initial_value) \
617 _spr_register(env, num, name, uea_read, uea_write, \
618 oea_read, oea_write, oea_read, oea_write, \
619 one_reg_id, initial_value)
620#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
621 oea_read, oea_write, hea_read, hea_write, \
622 one_reg_id, initial_value) \
d67d40ea 623 _spr_register(env, num, name, uea_read, uea_write, \
eb94268e
BH		 624 oea_read, oea_write, hea_read, hea_write, \
625 one_reg_id, initial_value)
d67d40ea
DG		 626#endif
627#endif
628
629#define spr_register(env, num, name, uea_read, uea_write, \
630 oea_read, oea_write, initial_value) \
631 spr_register_kvm(env, num, name, uea_read, uea_write, \
632 oea_read, oea_write, 0, initial_value)
633
eb94268e
BH		 634#define spr_register_hv(env, num, name, uea_read, uea_write, \
635 oea_read, oea_write, hea_read, hea_write, \
636 initial_value) \
637 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
638 oea_read, oea_write, hea_read, hea_write, \
639 0, initial_value)
640
d67d40ea 641static inline void _spr_register(CPUPPCState *env, int num,
b55266b5 642 const char *name,
69b058c8
PB		 643 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
644 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
d67d40ea
DG		 645#if !defined(CONFIG_USER_ONLY)
646
69b058c8
PB		 647 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
648 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
eb94268e
BH		 649 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
650 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
76a66253 651#endif
d67d40ea
DG		 652#if defined(CONFIG_KVM)
653 uint64_t one_reg_id,
654#endif
655 target_ulong initial_value)
3fc6c082 656{
c227f099 657 ppc_spr_t *spr;
3fc6c082
FB		 658
659 spr = &env->spr_cb[num];
660 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 661#if !defined(CONFIG_USER_ONLY)
662 spr->oea_read != NULL || spr->oea_write != NULL ||
663#endif
664 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 665 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
666 exit(1);
667 }
668#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 669 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
670 name, initial_value);
3fc6c082
FB		 671#endif
672 spr->name = name;
673 spr->uea_read = uea_read;
674 spr->uea_write = uea_write;
76a66253 675#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 676 spr->oea_read = oea_read;
677 spr->oea_write = oea_write;
eb94268e
BH		 678 spr->hea_read = hea_read;
679 spr->hea_write = hea_write;
7a7c05d7
AK		 680#endif
681#if defined(CONFIG_KVM)
682 spr->one_reg_id = one_reg_id,
76a66253 683#endif
d197fdbc 684 env->spr[num] = spr->default_value = initial_value;
3fc6c082
FB		 685}
686
687/* Generic PowerPC SPRs */
688static void gen_spr_generic (CPUPPCState *env)
689{
690 /* Integer processing */
691 spr_register(env, SPR_XER, "XER",
692 &spr_read_xer, &spr_write_xer,
693 &spr_read_xer, &spr_write_xer,
694 0x00000000);
695 /* Branch contol */
696 spr_register(env, SPR_LR, "LR",
697 &spr_read_lr, &spr_write_lr,
698 &spr_read_lr, &spr_write_lr,
699 0x00000000);
700 spr_register(env, SPR_CTR, "CTR",
701 &spr_read_ctr, &spr_write_ctr,
702 &spr_read_ctr, &spr_write_ctr,
703 0x00000000);
704 /* Interrupt processing */
705 spr_register(env, SPR_SRR0, "SRR0",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, &spr_write_generic,
708 0x00000000);
709 spr_register(env, SPR_SRR1, "SRR1",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713 /* Processor control */
714 spr_register(env, SPR_SPRG0, "SPRG0",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718 spr_register(env, SPR_SPRG1, "SPRG1",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, &spr_write_generic,
721 0x00000000);
722 spr_register(env, SPR_SPRG2, "SPRG2",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, &spr_write_generic,
725 0x00000000);
726 spr_register(env, SPR_SPRG3, "SPRG3",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, &spr_write_generic,
729 0x00000000);
730}
731
732/* SPR common to all non-embedded PowerPC, including 601 */
4f4f28ff 733static void gen_spr_ne_601(CPUPPCState *env)
3fc6c082
FB		 734{
735 /* Exception processing */
d67d40ea
DG		 736 spr_register_kvm(env, SPR_DSISR, "DSISR",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 KVM_REG_PPC_DSISR, 0x00000000);
740 spr_register_kvm(env, SPR_DAR, "DAR",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 KVM_REG_PPC_DAR, 0x00000000);
3fc6c082
FB		 744 /* Timer */
745 spr_register(env, SPR_DECR, "DECR",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_decr, &spr_write_decr,
748 0x00000000);
4f4f28ff
SJS		 749}
750
751/* Storage Description Register 1 */
752static void gen_spr_sdr1(CPUPPCState *env)
753{
7d6250e3
DG		 754#ifndef CONFIG_USER_ONLY
755 if (env->has_hv_mode) {
756 /* SDR1 is a hypervisor resource on CPUs which have a
757 * hypervisor mode */
758 spr_register_hv(env, SPR_SDR1, "SDR1",
759 SPR_NOACCESS, SPR_NOACCESS,
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_sdr1,
762 0x00000000);
763 } else {
764 spr_register(env, SPR_SDR1, "SDR1",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_generic, &spr_write_sdr1,
767 0x00000000);
768 }
769#endif
3fc6c082
FB		 770}
771
772/* BATs 0-3 */
773static void gen_low_BATs (CPUPPCState *env)
774{
f2e63a42 775#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 776 spr_register(env, SPR_IBAT0U, "IBAT0U",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat, &spr_write_ibatu,
779 0x00000000);
780 spr_register(env, SPR_IBAT0L, "IBAT0L",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat, &spr_write_ibatl,
783 0x00000000);
784 spr_register(env, SPR_IBAT1U, "IBAT1U",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_ibat, &spr_write_ibatu,
787 0x00000000);
788 spr_register(env, SPR_IBAT1L, "IBAT1L",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_ibat, &spr_write_ibatl,
791 0x00000000);
792 spr_register(env, SPR_IBAT2U, "IBAT2U",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat, &spr_write_ibatu,
795 0x00000000);
796 spr_register(env, SPR_IBAT2L, "IBAT2L",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_ibat, &spr_write_ibatl,
799 0x00000000);
800 spr_register(env, SPR_IBAT3U, "IBAT3U",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_ibat, &spr_write_ibatu,
803 0x00000000);
804 spr_register(env, SPR_IBAT3L, "IBAT3L",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_ibat, &spr_write_ibatl,
807 0x00000000);
808 spr_register(env, SPR_DBAT0U, "DBAT0U",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat, &spr_write_dbatu,
811 0x00000000);
812 spr_register(env, SPR_DBAT0L, "DBAT0L",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat, &spr_write_dbatl,
815 0x00000000);
816 spr_register(env, SPR_DBAT1U, "DBAT1U",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_dbat, &spr_write_dbatu,
819 0x00000000);
820 spr_register(env, SPR_DBAT1L, "DBAT1L",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_dbat, &spr_write_dbatl,
823 0x00000000);
824 spr_register(env, SPR_DBAT2U, "DBAT2U",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat, &spr_write_dbatu,
827 0x00000000);
828 spr_register(env, SPR_DBAT2L, "DBAT2L",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_dbat, &spr_write_dbatl,
831 0x00000000);
832 spr_register(env, SPR_DBAT3U, "DBAT3U",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_dbat, &spr_write_dbatu,
835 0x00000000);
836 spr_register(env, SPR_DBAT3L, "DBAT3L",
837 SPR_NOACCESS, SPR_NOACCESS,
838 &spr_read_dbat, &spr_write_dbatl,
839 0x00000000);
a750fc0b 840 env->nb_BATs += 4;
f2e63a42 841#endif
3fc6c082
FB		 842}
843
844/* BATs 4-7 */
845static void gen_high_BATs (CPUPPCState *env)
846{
f2e63a42 847#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 848 spr_register(env, SPR_IBAT4U, "IBAT4U",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_ibat_h, &spr_write_ibatu_h,
851 0x00000000);
852 spr_register(env, SPR_IBAT4L, "IBAT4L",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_ibat_h, &spr_write_ibatl_h,
855 0x00000000);
856 spr_register(env, SPR_IBAT5U, "IBAT5U",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_ibat_h, &spr_write_ibatu_h,
859 0x00000000);
860 spr_register(env, SPR_IBAT5L, "IBAT5L",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_ibat_h, &spr_write_ibatl_h,
863 0x00000000);
864 spr_register(env, SPR_IBAT6U, "IBAT6U",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_ibat_h, &spr_write_ibatu_h,
867 0x00000000);
868 spr_register(env, SPR_IBAT6L, "IBAT6L",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_ibat_h, &spr_write_ibatl_h,
871 0x00000000);
872 spr_register(env, SPR_IBAT7U, "IBAT7U",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_ibat_h, &spr_write_ibatu_h,
875 0x00000000);
876 spr_register(env, SPR_IBAT7L, "IBAT7L",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_ibat_h, &spr_write_ibatl_h,
879 0x00000000);
880 spr_register(env, SPR_DBAT4U, "DBAT4U",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_dbat_h, &spr_write_dbatu_h,
883 0x00000000);
884 spr_register(env, SPR_DBAT4L, "DBAT4L",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_dbat_h, &spr_write_dbatl_h,
887 0x00000000);
888 spr_register(env, SPR_DBAT5U, "DBAT5U",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_dbat_h, &spr_write_dbatu_h,
891 0x00000000);
892 spr_register(env, SPR_DBAT5L, "DBAT5L",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_dbat_h, &spr_write_dbatl_h,
895 0x00000000);
896 spr_register(env, SPR_DBAT6U, "DBAT6U",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_dbat_h, &spr_write_dbatu_h,
899 0x00000000);
900 spr_register(env, SPR_DBAT6L, "DBAT6L",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_dbat_h, &spr_write_dbatl_h,
903 0x00000000);
904 spr_register(env, SPR_DBAT7U, "DBAT7U",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_dbat_h, &spr_write_dbatu_h,
907 0x00000000);
908 spr_register(env, SPR_DBAT7L, "DBAT7L",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_dbat_h, &spr_write_dbatl_h,
911 0x00000000);
a750fc0b 912 env->nb_BATs += 4;
f2e63a42 913#endif
3fc6c082
FB		 914}
915
916/* Generic PowerPC time base */
917static void gen_tbl (CPUPPCState *env)
918{
919 spr_register(env, SPR_VTBL, "TBL",
920 &spr_read_tbl, SPR_NOACCESS,
921 &spr_read_tbl, SPR_NOACCESS,
922 0x00000000);
923 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 924 &spr_read_tbl, SPR_NOACCESS,
925 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 926 0x00000000);
927 spr_register(env, SPR_VTBU, "TBU",
928 &spr_read_tbu, SPR_NOACCESS,
929 &spr_read_tbu, SPR_NOACCESS,
930 0x00000000);
931 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 932 &spr_read_tbu, SPR_NOACCESS,
933 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 934 0x00000000);
935}
936
76a66253
JM		 937/* Softare table search registers */
938static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
939{
f2e63a42 940#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 941 env->nb_tlb = nb_tlbs;
942 env->nb_ways = nb_ways;
943 env->id_tlbs = 1;
1c53accc 944 env->tlb_type = TLB_6XX;
76a66253
JM		 945 spr_register(env, SPR_DMISS, "DMISS",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, SPR_NOACCESS,
948 0x00000000);
949 spr_register(env, SPR_DCMP, "DCMP",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, SPR_NOACCESS,
952 0x00000000);
953 spr_register(env, SPR_HASH1, "HASH1",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, SPR_NOACCESS,
956 0x00000000);
957 spr_register(env, SPR_HASH2, "HASH2",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, SPR_NOACCESS,
960 0x00000000);
961 spr_register(env, SPR_IMISS, "IMISS",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, SPR_NOACCESS,
964 0x00000000);
965 spr_register(env, SPR_ICMP, "ICMP",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, SPR_NOACCESS,
968 0x00000000);
969 spr_register(env, SPR_RPA, "RPA",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
f2e63a42 973#endif
76a66253
JM		 974}
975
976/* SPR common to MPC755 and G2 */
977static void gen_spr_G2_755 (CPUPPCState *env)
978{
979 /* SGPRs */
980 spr_register(env, SPR_SPRG4, "SPRG4",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
983 0x00000000);
984 spr_register(env, SPR_SPRG5, "SPRG5",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, &spr_write_generic,
987 0x00000000);
988 spr_register(env, SPR_SPRG6, "SPRG6",
989 SPR_NOACCESS, SPR_NOACCESS,
990 &spr_read_generic, &spr_write_generic,
991 0x00000000);
992 spr_register(env, SPR_SPRG7, "SPRG7",
993 SPR_NOACCESS, SPR_NOACCESS,
994 &spr_read_generic, &spr_write_generic,
995 0x00000000);
76a66253
JM		 996}
997
3fc6c082
FB		 998/* SPR common to all 7xx PowerPC implementations */
999static void gen_spr_7xx (CPUPPCState *env)
1000{
1001 /* Breakpoints */
1002 /* XXX : not implemented */
d67d40ea
DG		 1003 spr_register_kvm(env, SPR_DABR, "DABR",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 KVM_REG_PPC_DABR, 0x00000000);
3fc6c082
FB		 1007 /* XXX : not implemented */
1008 spr_register(env, SPR_IABR, "IABR",
1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, &spr_write_generic,
1011 0x00000000);
1012 /* Cache management */
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_ICTC, "ICTC",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 /* Performance monitors */
1019 /* XXX : not implemented */
cb8b8bf8 1020 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
3fc6c082
FB		 1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, &spr_write_generic,
1023 0x00000000);
1024 /* XXX : not implemented */
cb8b8bf8 1025 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
3fc6c082
FB		 1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* XXX : not implemented */
cb8b8bf8 1030 spr_register(env, SPR_7XX_PMC1, "PMC1",
3fc6c082
FB		 1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* XXX : not implemented */
cb8b8bf8 1035 spr_register(env, SPR_7XX_PMC2, "PMC2",
3fc6c082
FB		 1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* XXX : not implemented */
cb8b8bf8 1040 spr_register(env, SPR_7XX_PMC3, "PMC3",
3fc6c082
FB		 1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
cb8b8bf8 1045 spr_register(env, SPR_7XX_PMC4, "PMC4",
3fc6c082
FB		 1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
cb8b8bf8 1050 spr_register(env, SPR_7XX_SIAR, "SIAR",
3fc6c082
FB		 1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, SPR_NOACCESS,
1053 0x00000000);
578bb252 1054 /* XXX : not implemented */
cb8b8bf8 1055 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
3fc6c082
FB		 1056 &spr_read_ureg, SPR_NOACCESS,
1057 &spr_read_ureg, SPR_NOACCESS,
1058 0x00000000);
578bb252 1059 /* XXX : not implemented */
cb8b8bf8 1060 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
3fc6c082
FB		 1061 &spr_read_ureg, SPR_NOACCESS,
1062 &spr_read_ureg, SPR_NOACCESS,
1063 0x00000000);
578bb252 1064 /* XXX : not implemented */
cb8b8bf8 1065 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
3fc6c082
FB		 1066 &spr_read_ureg, SPR_NOACCESS,
1067 &spr_read_ureg, SPR_NOACCESS,
1068 0x00000000);
578bb252 1069 /* XXX : not implemented */
cb8b8bf8 1070 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
3fc6c082
FB		 1071 &spr_read_ureg, SPR_NOACCESS,
1072 &spr_read_ureg, SPR_NOACCESS,
1073 0x00000000);
578bb252 1074 /* XXX : not implemented */
cb8b8bf8 1075 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
3fc6c082
FB		 1076 &spr_read_ureg, SPR_NOACCESS,
1077 &spr_read_ureg, SPR_NOACCESS,
1078 0x00000000);
578bb252 1079 /* XXX : not implemented */
cb8b8bf8 1080 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
3fc6c082
FB		 1081 &spr_read_ureg, SPR_NOACCESS,
1082 &spr_read_ureg, SPR_NOACCESS,
1083 0x00000000);
578bb252 1084 /* XXX : not implemented */
cb8b8bf8 1085 spr_register(env, SPR_7XX_USIAR, "USIAR",
3fc6c082
FB		 1086 &spr_read_ureg, SPR_NOACCESS,
1087 &spr_read_ureg, SPR_NOACCESS,
1088 0x00000000);
a750fc0b 1089 /* External access control */
3fc6c082 1090 /* XXX : not implemented */
a750fc0b 1091 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_generic, &spr_write_generic,
1094 0x00000000);
a750fc0b
JM		 1095}
1096
f80872e2
DG		 1097#ifdef TARGET_PPC64
1098#ifndef CONFIG_USER_ONLY
97eaf30e 1099static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
f80872e2 1100{
97eaf30e
BH		 1101 TCGv t0 = tcg_temp_new();
1102 TCGv t1 = tcg_temp_new();
1103 TCGv t2 = tcg_temp_new();
f80872e2 1104
97eaf30e
BH		 1105 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1106 * spr_write_generic for HV mode in the SPR table
1107 */
1108
1109 /* Build insertion mask into t1 based on context */
1110 if (ctx->pr) {
1111 gen_load_spr(t1, SPR_UAMOR);
1112 } else {
1113 gen_load_spr(t1, SPR_AMOR);
1114 }
1115
1116 /* Mask new bits into t2 */
1117 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1118
1119 /* Load AMR and clear new bits in t0 */
1120 gen_load_spr(t0, SPR_AMR);
1121 tcg_gen_andc_tl(t0, t0, t1);
1122
1123 /* Or'in new bits and write it out */
1124 tcg_gen_or_tl(t0, t0, t2);
1125 gen_store_spr(SPR_AMR, t0);
f80872e2 1126 spr_store_dump_spr(SPR_AMR);
97eaf30e
BH		 1127
1128 tcg_temp_free(t0);
1129 tcg_temp_free(t1);
1130 tcg_temp_free(t2);
f80872e2
DG		 1131}
1132
97eaf30e 1133static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
f80872e2
DG		 1134{
1135 TCGv t0 = tcg_temp_new();
97eaf30e
BH		 1136 TCGv t1 = tcg_temp_new();
1137 TCGv t2 = tcg_temp_new();
1138
1139 /* Note, the HV=1 case is handled earlier by simply using
1140 * spr_write_generic for HV mode in the SPR table
1141 */
f80872e2 1142
97eaf30e
BH		 1143 /* Build insertion mask into t1 based on context */
1144 gen_load_spr(t1, SPR_AMOR);
1145
1146 /* Mask new bits into t2 */
1147 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1148
1149 /* Load AMR and clear new bits in t0 */
f80872e2 1150 gen_load_spr(t0, SPR_UAMOR);
97eaf30e
BH		 1151 tcg_gen_andc_tl(t0, t0, t1);
1152
1153 /* Or'in new bits and write it out */
1154 tcg_gen_or_tl(t0, t0, t2);
1155 gen_store_spr(SPR_UAMOR, t0);
1156 spr_store_dump_spr(SPR_UAMOR);
1157
1158 tcg_temp_free(t0);
1159 tcg_temp_free(t1);
1160 tcg_temp_free(t2);
f80872e2 1161}
a6eabb9e
BH		 1162
1163static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1164{
1165 TCGv t0 = tcg_temp_new();
1166 TCGv t1 = tcg_temp_new();
1167 TCGv t2 = tcg_temp_new();
1168
1169 /* Note, the HV=1 case is handled earlier by simply using
1170 * spr_write_generic for HV mode in the SPR table
1171 */
1172
1173 /* Build insertion mask into t1 based on context */
1174 gen_load_spr(t1, SPR_AMOR);
1175
1176 /* Mask new bits into t2 */
1177 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1178
1179 /* Load AMR and clear new bits in t0 */
1180 gen_load_spr(t0, SPR_IAMR);
1181 tcg_gen_andc_tl(t0, t0, t1);
1182
1183 /* Or'in new bits and write it out */
1184 tcg_gen_or_tl(t0, t0, t2);
1185 gen_store_spr(SPR_IAMR, t0);
1186 spr_store_dump_spr(SPR_IAMR);
1187
1188 tcg_temp_free(t0);
1189 tcg_temp_free(t1);
1190 tcg_temp_free(t2);
1191}
f80872e2
DG		 1192#endif /* CONFIG_USER_ONLY */
1193
4f4f28ff 1194static void gen_spr_amr(CPUPPCState *env)
f80872e2
DG		 1195{
1196#ifndef CONFIG_USER_ONLY
1197 /* Virtual Page Class Key protection */
1198 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1199 * userspace accessible, 29 is privileged. So we only need to set
1200 * the kvm ONE_REG id on one of them, we use 29 */
1201 spr_register(env, SPR_UAMR, "UAMR",
97eaf30e
BH		 1202 &spr_read_generic, &spr_write_amr,
1203 &spr_read_generic, &spr_write_amr,
f80872e2 1204 0);
97eaf30e 1205 spr_register_kvm_hv(env, SPR_AMR, "AMR",
f80872e2 1206 SPR_NOACCESS, SPR_NOACCESS,
97eaf30e 1207 &spr_read_generic, &spr_write_amr,
f80872e2 1208 &spr_read_generic, &spr_write_generic,
0dc083fe 1209 KVM_REG_PPC_AMR, 0);
97eaf30e 1210 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
f80872e2 1211 SPR_NOACCESS, SPR_NOACCESS,
97eaf30e 1212 &spr_read_generic, &spr_write_uamor,
f80872e2
DG		 1213 &spr_read_generic, &spr_write_generic,
1214 KVM_REG_PPC_UAMOR, 0);
f401dd32
BH		 1215 spr_register_hv(env, SPR_AMOR, "AMOR",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0);
4f4f28ff
SJS		 1220#endif /* !CONFIG_USER_ONLY */
1221}
1222
1223static void gen_spr_iamr(CPUPPCState *env)
1224{
1225#ifndef CONFIG_USER_ONLY
1226 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_iamr,
1229 &spr_read_generic, &spr_write_generic,
1230 KVM_REG_PPC_IAMR, 0);
f80872e2
DG		 1231#endif /* !CONFIG_USER_ONLY */
1232}
1233#endif /* TARGET_PPC64 */
1234
f0278900
BH		 1235#ifndef CONFIG_USER_ONLY
1236static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1237{
1238 gen_helper_fixup_thrm(cpu_env);
1239 gen_load_spr(cpu_gpr[gprn], sprn);
1240 spr_load_dump_spr(sprn);
1241}
1242#endif /* !CONFIG_USER_ONLY */
1243
a750fc0b
JM		 1244static void gen_spr_thrm (CPUPPCState *env)
1245{
1246 /* Thermal management */
3fc6c082 1247 /* XXX : not implemented */
a750fc0b 1248 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082 1249 SPR_NOACCESS, SPR_NOACCESS,
f0278900 1250 &spr_read_thrm, &spr_write_generic,
3fc6c082
FB		 1251 0x00000000);
1252 /* XXX : not implemented */
a750fc0b 1253 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082 1254 SPR_NOACCESS, SPR_NOACCESS,
f0278900 1255 &spr_read_thrm, &spr_write_generic,
3fc6c082 1256 0x00000000);
3fc6c082 1257 /* XXX : not implemented */
a750fc0b 1258 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082 1259 SPR_NOACCESS, SPR_NOACCESS,
f0278900 1260 &spr_read_thrm, &spr_write_generic,
3fc6c082
FB		 1261 0x00000000);
1262}
1263
1264/* SPR specific to PowerPC 604 implementation */
1265static void gen_spr_604 (CPUPPCState *env)
1266{
1267 /* Processor identification */
1268 spr_register(env, SPR_PIR, "PIR",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_pir,
1271 0x00000000);
1272 /* Breakpoints */
1273 /* XXX : not implemented */
1274 spr_register(env, SPR_IABR, "IABR",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
1278 /* XXX : not implemented */
d67d40ea
DG		 1279 spr_register_kvm(env, SPR_DABR, "DABR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 KVM_REG_PPC_DABR, 0x00000000);
3fc6c082
FB		 1283 /* Performance counters */
1284 /* XXX : not implemented */
cb8b8bf8 1285 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
3fc6c082
FB		 1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289 /* XXX : not implemented */
cb8b8bf8 1290 spr_register(env, SPR_7XX_PMC1, "PMC1",
3fc6c082
FB		 1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* XXX : not implemented */
cb8b8bf8 1295 spr_register(env, SPR_7XX_PMC2, "PMC2",
3fc6c082
FB		 1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* XXX : not implemented */
cb8b8bf8 1300 spr_register(env, SPR_7XX_SIAR, "SIAR",
3fc6c082
FB		 1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, SPR_NOACCESS,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_SDA, "SDA",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, SPR_NOACCESS,
1308 0x00000000);
1309 /* External access control */
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_EAR, "EAR",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315}
1316
76a66253
JM		 1317/* SPR specific to PowerPC 603 implementation */
1318static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1319{
76a66253
JM		 1320 /* External access control */
1321 /* XXX : not implemented */
1322 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1323 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
2bc17322
FC		 1326 /* Breakpoints */
1327 /* XXX : not implemented */
1328 spr_register(env, SPR_IABR, "IABR",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, &spr_write_generic,
1331 0x00000000);
1332
3fc6c082
FB		 1333}
1334
76a66253
JM		 1335/* SPR specific to PowerPC G2 implementation */
1336static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1337{
76a66253
JM		 1338 /* Memory base address */
1339 /* MBAR */
578bb252 1340 /* XXX : not implemented */
76a66253
JM		 1341 spr_register(env, SPR_MBAR, "MBAR",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
76a66253 1345 /* Exception processing */
363be49c 1346 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
363be49c 1350 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* Breakpoints */
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_DABR, "DABR",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 /* XXX : not implemented */
1361 spr_register(env, SPR_DABR2, "DABR2",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 /* XXX : not implemented */
1366 spr_register(env, SPR_IABR, "IABR",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370 /* XXX : not implemented */
1371 spr_register(env, SPR_IABR2, "IABR2",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_IBCR, "IBCR",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 /* XXX : not implemented */
1381 spr_register(env, SPR_DBCR, "DBCR",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385}
1386
1387/* SPR specific to PowerPC 602 implementation */
1388static void gen_spr_602 (CPUPPCState *env)
1389{
1390 /* ESA registers */
1391 /* XXX : not implemented */
1392 spr_register(env, SPR_SER, "SER",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396 /* XXX : not implemented */
1397 spr_register(env, SPR_SEBR, "SEBR",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401 /* XXX : not implemented */
a750fc0b 1402 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_generic,
1405 0x00000000);
1406 /* Floating point status */
1407 /* XXX : not implemented */
1408 spr_register(env, SPR_SP, "SP",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412 /* XXX : not implemented */
1413 spr_register(env, SPR_LT, "LT",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 /* Watchdog timer */
1418 /* XXX : not implemented */
1419 spr_register(env, SPR_TCR, "TCR",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 /* Interrupt base */
1424 spr_register(env, SPR_IBR, "IBR",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
a750fc0b
JM		 1428 /* XXX : not implemented */
1429 spr_register(env, SPR_IABR, "IABR",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
76a66253
JM		 1433}
1434
1435/* SPR specific to PowerPC 601 implementation */
1436static void gen_spr_601 (CPUPPCState *env)
1437{
1438 /* Multiplication/division register */
1439 /* MQ */
1440 spr_register(env, SPR_MQ, "MQ",
1441 &spr_read_generic, &spr_write_generic,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
1444 /* RTC registers */
1445 spr_register(env, SPR_601_RTCU, "RTCU",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 SPR_NOACCESS, &spr_write_601_rtcu,
1448 0x00000000);
1449 spr_register(env, SPR_601_VRTCU, "RTCU",
1450 &spr_read_601_rtcu, SPR_NOACCESS,
1451 &spr_read_601_rtcu, SPR_NOACCESS,
1452 0x00000000);
1453 spr_register(env, SPR_601_RTCL, "RTCL",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 SPR_NOACCESS, &spr_write_601_rtcl,
1456 0x00000000);
1457 spr_register(env, SPR_601_VRTCL, "RTCL",
1458 &spr_read_601_rtcl, SPR_NOACCESS,
1459 &spr_read_601_rtcl, SPR_NOACCESS,
1460 0x00000000);
1461 /* Timer */
1462#if 0 /* ? */
1463 spr_register(env, SPR_601_UDECR, "UDECR",
1464 &spr_read_decr, SPR_NOACCESS,
1465 &spr_read_decr, SPR_NOACCESS,
1466 0x00000000);
1467#endif
1468 /* External access control */
1469 /* XXX : not implemented */
1470 spr_register(env, SPR_EAR, "EAR",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 /* Memory management */
f2e63a42 1475#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1476 spr_register(env, SPR_IBAT0U, "IBAT0U",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_601_ubat, &spr_write_601_ubatu,
1479 0x00000000);
1480 spr_register(env, SPR_IBAT0L, "IBAT0L",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_601_ubat, &spr_write_601_ubatl,
1483 0x00000000);
1484 spr_register(env, SPR_IBAT1U, "IBAT1U",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_601_ubat, &spr_write_601_ubatu,
1487 0x00000000);
1488 spr_register(env, SPR_IBAT1L, "IBAT1L",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_601_ubat, &spr_write_601_ubatl,
1491 0x00000000);
1492 spr_register(env, SPR_IBAT2U, "IBAT2U",
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_601_ubat, &spr_write_601_ubatu,
1495 0x00000000);
1496 spr_register(env, SPR_IBAT2L, "IBAT2L",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_601_ubat, &spr_write_601_ubatl,
1499 0x00000000);
1500 spr_register(env, SPR_IBAT3U, "IBAT3U",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_601_ubat, &spr_write_601_ubatu,
1503 0x00000000);
1504 spr_register(env, SPR_IBAT3L, "IBAT3L",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_601_ubat, &spr_write_601_ubatl,
1507 0x00000000);
a750fc0b 1508 env->nb_BATs = 4;
f2e63a42 1509#endif
a750fc0b
JM		 1510}
1511
1512static void gen_spr_74xx (CPUPPCState *env)
1513{
1514 /* Processor identification */
1515 spr_register(env, SPR_PIR, "PIR",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_pir,
1518 0x00000000);
1519 /* XXX : not implemented */
cb8b8bf8 1520 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
a750fc0b
JM		 1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_generic,
1523 0x00000000);
578bb252 1524 /* XXX : not implemented */
cb8b8bf8 1525 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
a750fc0b
JM		 1526 &spr_read_ureg, SPR_NOACCESS,
1527 &spr_read_ureg, SPR_NOACCESS,
1528 0x00000000);
1529 /* XXX: not implemented */
1530 spr_register(env, SPR_BAMR, "BAMR",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_generic,
1533 0x00000000);
578bb252 1534 /* XXX : not implemented */
a750fc0b
JM		 1535 spr_register(env, SPR_MSSCR0, "MSSCR0",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539 /* Hardware implementation registers */
1540 /* XXX : not implemented */
1541 spr_register(env, SPR_HID0, "HID0",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_HID1, "HID1",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 /* Altivec */
1551 spr_register(env, SPR_VRSAVE, "VRSAVE",
1552 &spr_read_generic, &spr_write_generic,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
bd928eba
JM		 1555 /* XXX : not implemented */
1556 spr_register(env, SPR_L2CR, "L2CR",
1557 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 1558 &spr_read_generic, spr_access_nop,
bd928eba 1559 0x00000000);
cf8358c8
AJ		 1560 /* Not strictly an SPR */
1561 vscr_init(env, 0x00010000);
a750fc0b
JM		 1562}
1563
a750fc0b
JM		 1564static void gen_l3_ctrl (CPUPPCState *env)
1565{
1566 /* L3CR */
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_L3CR, "L3CR",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572 /* L3ITCR0 */
578bb252 1573 /* XXX : not implemented */
a750fc0b
JM		 1574 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
a750fc0b 1578 /* L3PM */
578bb252 1579 /* XXX : not implemented */
a750fc0b
JM		 1580 spr_register(env, SPR_L3PM, "L3PM",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584}
a750fc0b 1585
578bb252 1586static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1587{
f2e63a42 1588#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1589 env->nb_tlb = nb_tlbs;
1590 env->nb_ways = nb_ways;
1591 env->id_tlbs = 1;
1c53accc 1592 env->tlb_type = TLB_6XX;
578bb252 1593 /* XXX : not implemented */
a750fc0b
JM		 1594 spr_register(env, SPR_PTEHI, "PTEHI",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
578bb252 1598 /* XXX : not implemented */
a750fc0b
JM		 1599 spr_register(env, SPR_PTELO, "PTELO",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
578bb252 1603 /* XXX : not implemented */
a750fc0b
JM		 1604 spr_register(env, SPR_TLBMISS, "TLBMISS",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
f2e63a42 1608#endif
76a66253
JM		 1609}
1610
01662f3e 1611#if !defined(CONFIG_USER_ONLY)
69b058c8 1612static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
01662f3e
AG		 1613{
1614 TCGv t0 = tcg_temp_new();
1615
ea71258d
AG		 1616 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1617 gen_store_spr(sprn, t0);
1618 tcg_temp_free(t0);
1619}
1620
69b058c8 1621static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
ea71258d
AG		 1622{
1623 TCGv t0 = tcg_temp_new();
1624
1625 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
01662f3e
AG		 1626 gen_store_spr(sprn, t0);
1627 tcg_temp_free(t0);
1628}
1629
69b058c8 1630static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
01662f3e 1631{
a721d390 1632 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
01662f3e
AG		 1633}
1634
69b058c8 1635static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
01662f3e 1636{
1ff7854e 1637 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1638 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1ff7854e 1639 tcg_temp_free_i32(t0);
01662f3e
AG		 1640}
1641#endif
1642
80d11f44 1643static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1644{
80d11f44
JM		 1645 spr_register(env, SPR_USPRG4, "USPRG4",
1646 &spr_read_ureg, SPR_NOACCESS,
1647 &spr_read_ureg, SPR_NOACCESS,
1648 0x00000000);
1649 spr_register(env, SPR_USPRG5, "USPRG5",
1650 &spr_read_ureg, SPR_NOACCESS,
1651 &spr_read_ureg, SPR_NOACCESS,
1652 0x00000000);
1653 spr_register(env, SPR_USPRG6, "USPRG6",
1654 &spr_read_ureg, SPR_NOACCESS,
1655 &spr_read_ureg, SPR_NOACCESS,
1656 0x00000000);
1657 spr_register(env, SPR_USPRG7, "USPRG7",
1658 &spr_read_ureg, SPR_NOACCESS,
1659 &spr_read_ureg, SPR_NOACCESS,
76a66253 1660 0x00000000);
80d11f44
JM		 1661}
1662
1663/* PowerPC BookE SPR */
1664static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1665{
b55266b5 1666 const char *ivor_names[64] = {
80d11f44
JM		 1667 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1668 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1669 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1670 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1671 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1672 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1673 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1674 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1675 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1676 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1677 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1678 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1679 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1680 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1681 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1682 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1683 };
1684#define SPR_BOOKE_IVORxx (-1)
1685 int ivor_sprn[64] = {
1686 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1687 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1688 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1689 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1692 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1693 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1694 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
e9205258
AG		 1695 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1696 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
80d11f44
JM		 1697 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1698 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1699 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1700 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1701 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1702 };
1703 int i;
1704
76a66253 1705 /* Interrupt processing */
363be49c 1706 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
363be49c
JM		 1710 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
76a66253
JM		 1714 /* Debug */
1715 /* XXX : not implemented */
1716 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_generic,
1719 0x00000000);
1720 /* XXX : not implemented */
1721 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_generic,
1724 0x00000000);
1725 /* XXX : not implemented */
76a66253
JM		 1726 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_generic,
1729 0x00000000);
1730 /* XXX : not implemented */
1731 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_generic,
1734 0x00000000);
1735 /* XXX : not implemented */
76a66253
JM		 1736 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1737 SPR_NOACCESS, SPR_NOACCESS,
e598a9c5 1738 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1739 0x00000000);
1740 /* XXX : not implemented */
1741 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, &spr_write_generic,
1744 0x00000000);
1745 /* XXX : not implemented */
1746 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1747 SPR_NOACCESS, SPR_NOACCESS,
1748 &spr_read_generic, &spr_write_generic,
1749 0x00000000);
1750 /* XXX : not implemented */
1751 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1752 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1753 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1754 0x00000000);
1755 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, &spr_write_generic,
1758 0x00000000);
1759 spr_register(env, SPR_BOOKE_ESR, "ESR",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_generic,
1762 0x00000000);
363be49c
JM		 1763 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1764 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1765 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1766 0x00000000);
1767 /* Exception vectors */
80d11f44
JM		 1768 for (i = 0; i < 64; i++) {
1769 if (ivor_mask & (1ULL << i)) {
1770 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1771 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1772 exit(1);
1773 }
1774 spr_register(env, ivor_sprn[i], ivor_names[i],
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_excp_vector,
1777 0x00000000);
1778 }
1779 }
76a66253
JM		 1780 spr_register(env, SPR_BOOKE_PID, "PID",
1781 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1782 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 1783 0x00000000);
1784 spr_register(env, SPR_BOOKE_TCR, "TCR",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, &spr_write_booke_tcr,
1787 0x00000000);
1788 spr_register(env, SPR_BOOKE_TSR, "TSR",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_booke_tsr,
1791 0x00000000);
1792 /* Timer */
1793 spr_register(env, SPR_DECR, "DECR",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_decr, &spr_write_decr,
1796 0x00000000);
1797 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 SPR_NOACCESS, &spr_write_generic,
1800 0x00000000);
1801 /* SPRGs */
1802 spr_register(env, SPR_USPRG0, "USPRG0",
1803 &spr_read_generic, &spr_write_generic,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 spr_register(env, SPR_SPRG4, "SPRG4",
1807 SPR_NOACCESS, SPR_NOACCESS,
1808 &spr_read_generic, &spr_write_generic,
1809 0x00000000);
76a66253
JM		 1810 spr_register(env, SPR_SPRG5, "SPRG5",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
76a66253
JM		 1814 spr_register(env, SPR_SPRG6, "SPRG6",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
76a66253
JM		 1818 spr_register(env, SPR_SPRG7, "SPRG7",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
76a66253
JM		 1822}
1823
01662f3e
AG		 1824static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1825 uint32_t maxsize, uint32_t flags,
1826 uint32_t nentries)
1827{
1828 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1829 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1830 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1831 flags | nentries;
1832}
1833
1834/* BookE 2.06 storage control registers */
1835static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1836 uint32_t *tlbncfg)
363be49c 1837{
f2e63a42 1838#if !defined(CONFIG_USER_ONLY)
b55266b5 1839 const char *mas_names[8] = {
80d11f44
JM		 1840 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1841 };
1842 int mas_sprn[8] = {
1843 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1844 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1845 };
1846 int i;
1847
363be49c 1848 /* TLB assist registers */
578bb252 1849 /* XXX : not implemented */
80d11f44 1850 for (i = 0; i < 8; i++) {
69b058c8 1851 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
ba38ab8d
AG		 1852 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1853 uea_write = &spr_write_generic;
1854 }
80d11f44
JM		 1855 if (mas_mask & (1 << i)) {
1856 spr_register(env, mas_sprn[i], mas_names[i],
1857 SPR_NOACCESS, SPR_NOACCESS,
ba38ab8d 1858 &spr_read_generic, uea_write,
80d11f44
JM		 1859 0x00000000);
1860 }
1861 }
363be49c 1862 if (env->nb_pids > 1) {
578bb252 1863 /* XXX : not implemented */
363be49c
JM		 1864 spr_register(env, SPR_BOOKE_PID1, "PID1",
1865 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1866 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1867 0x00000000);
1868 }
1869 if (env->nb_pids > 2) {
578bb252 1870 /* XXX : not implemented */
363be49c
JM		 1871 spr_register(env, SPR_BOOKE_PID2, "PID2",
1872 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1873 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1874 0x00000000);
1875 }
578bb252 1876 /* XXX : not implemented */
65f9ee8d 1877 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, SPR_NOACCESS,
1880 0x00000000); /* TOFIX */
363be49c
JM		 1881 switch (env->nb_ways) {
1882 case 4:
1883 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, SPR_NOACCESS,
01662f3e 1886 tlbncfg[3]);
363be49c
JM		 1887 /* Fallthru */
1888 case 3:
1889 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, SPR_NOACCESS,
01662f3e 1892 tlbncfg[2]);
363be49c
JM		 1893 /* Fallthru */
1894 case 2:
1895 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1896 SPR_NOACCESS, SPR_NOACCESS,
1897 &spr_read_generic, SPR_NOACCESS,
01662f3e 1898 tlbncfg[1]);
363be49c
JM		 1899 /* Fallthru */
1900 case 1:
1901 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1902 SPR_NOACCESS, SPR_NOACCESS,
1903 &spr_read_generic, SPR_NOACCESS,
01662f3e 1904 tlbncfg[0]);
363be49c
JM		 1905 /* Fallthru */
1906 case 0:
1907 default:
1908 break;
1909 }
f2e63a42 1910#endif
01662f3e
AG		 1911
1912 gen_spr_usprgh(env);
363be49c
JM		 1913}
1914
76a66253
JM		 1915/* SPR specific to PowerPC 440 implementation */
1916static void gen_spr_440 (CPUPPCState *env)
1917{
1918 /* Cache control */
1919 /* XXX : not implemented */
1920 spr_register(env, SPR_440_DNV0, "DNV0",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 /* XXX : not implemented */
1925 spr_register(env, SPR_440_DNV1, "DNV1",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 /* XXX : not implemented */
1930 spr_register(env, SPR_440_DNV2, "DNV2",
1931 SPR_NOACCESS, SPR_NOACCESS,
1932 &spr_read_generic, &spr_write_generic,
1933 0x00000000);
1934 /* XXX : not implemented */
1935 spr_register(env, SPR_440_DNV3, "DNV3",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 &spr_read_generic, &spr_write_generic,
1938 0x00000000);
1939 /* XXX : not implemented */
2662a059 1940 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1941 SPR_NOACCESS, SPR_NOACCESS,
1942 &spr_read_generic, &spr_write_generic,
1943 0x00000000);
1944 /* XXX : not implemented */
2662a059 1945 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1946 SPR_NOACCESS, SPR_NOACCESS,
1947 &spr_read_generic, &spr_write_generic,
1948 0x00000000);
1949 /* XXX : not implemented */
2662a059 1950 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1951 SPR_NOACCESS, SPR_NOACCESS,
1952 &spr_read_generic, &spr_write_generic,
1953 0x00000000);
1954 /* XXX : not implemented */
2662a059 1955 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_generic, &spr_write_generic,
1958 0x00000000);
1959 /* XXX : not implemented */
1960 spr_register(env, SPR_440_DVLIM, "DVLIM",
1961 SPR_NOACCESS, SPR_NOACCESS,
1962 &spr_read_generic, &spr_write_generic,
1963 0x00000000);
1964 /* XXX : not implemented */
1965 spr_register(env, SPR_440_INV0, "INV0",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, &spr_write_generic,
1968 0x00000000);
1969 /* XXX : not implemented */
1970 spr_register(env, SPR_440_INV1, "INV1",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, &spr_write_generic,
1973 0x00000000);
1974 /* XXX : not implemented */
1975 spr_register(env, SPR_440_INV2, "INV2",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979 /* XXX : not implemented */
1980 spr_register(env, SPR_440_INV3, "INV3",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, &spr_write_generic,
1983 0x00000000);
1984 /* XXX : not implemented */
2662a059 1985 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, &spr_write_generic,
1988 0x00000000);
1989 /* XXX : not implemented */
2662a059 1990 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994 /* XXX : not implemented */
2662a059 1995 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999 /* XXX : not implemented */
2662a059 2000 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004 /* XXX : not implemented */
2005 spr_register(env, SPR_440_IVLIM, "IVLIM",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 /* Cache debug */
2010 /* XXX : not implemented */
2662a059 2011 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, SPR_NOACCESS,
2014 0x00000000);
2015 /* XXX : not implemented */
2662a059 2016 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, SPR_NOACCESS,
2019 0x00000000);
2020 /* XXX : not implemented */
2662a059 2021 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, SPR_NOACCESS,
2024 0x00000000);
2025 /* XXX : not implemented */
2662a059 2026 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, SPR_NOACCESS,
2029 0x00000000);
2030 /* XXX : not implemented */
2662a059 2031 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, SPR_NOACCESS,
2034 0x00000000);
2035 /* XXX : not implemented */
2036 spr_register(env, SPR_440_DBDR, "DBDR",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, &spr_write_generic,
2039 0x00000000);
2040 /* Processor control */
2041 spr_register(env, SPR_4xx_CCR0, "CCR0",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 &spr_read_generic, &spr_write_generic,
2044 0x00000000);
2045 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, SPR_NOACCESS,
2048 0x00000000);
2049 /* Storage control */
2050 spr_register(env, SPR_440_MMUCR, "MMUCR",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_generic,
2053 0x00000000);
2054}
2055
2056/* SPR shared between PowerPC 40x implementations */
2057static void gen_spr_40x (CPUPPCState *env)
2058{
2059 /* Cache */
5cbdb3a3 2060 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 2061 spr_register(env, SPR_40x_DCCR, "DCCR",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 &spr_read_generic, &spr_write_generic,
2064 0x00000000);
5cbdb3a3 2065 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 2066 spr_register(env, SPR_40x_ICCR, "ICCR",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_generic, &spr_write_generic,
2069 0x00000000);
5cbdb3a3 2070 /* not emulated, as QEMU do not emulate caches */
2662a059 2071 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, SPR_NOACCESS,
2074 0x00000000);
76a66253
JM		 2075 /* Exception */
2076 spr_register(env, SPR_40x_DEAR, "DEAR",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, &spr_write_generic,
2079 0x00000000);
2080 spr_register(env, SPR_40x_ESR, "ESR",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084 spr_register(env, SPR_40x_EVPR, "EVPR",
2085 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 2086 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 2087 0x00000000);
2088 spr_register(env, SPR_40x_SRR2, "SRR2",
2089 &spr_read_generic, &spr_write_generic,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 spr_register(env, SPR_40x_SRR3, "SRR3",
2093 &spr_read_generic, &spr_write_generic,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
2096 /* Timers */
2097 spr_register(env, SPR_40x_PIT, "PIT",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_40x_pit, &spr_write_40x_pit,
2100 0x00000000);
2101 spr_register(env, SPR_40x_TCR, "TCR",
2102 SPR_NOACCESS, SPR_NOACCESS,
2103 &spr_read_generic, &spr_write_booke_tcr,
2104 0x00000000);
2105 spr_register(env, SPR_40x_TSR, "TSR",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_booke_tsr,
2108 0x00000000);
2662a059
JM		 2109}
2110
2111/* SPR specific to PowerPC 405 implementation */
2112static void gen_spr_405 (CPUPPCState *env)
2113{
2114 /* MMU */
2115 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 2116 SPR_NOACCESS, SPR_NOACCESS,
2117 &spr_read_generic, &spr_write_generic,
2118 0x00000000);
2662a059 2119 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2662a059
JM		 2122 0x00700000);
2123 /* Debug interface */
76a66253
JM		 2124 /* XXX : not implemented */
2125 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2126 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 2127 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 2128 0x00000000);
2129 /* XXX : not implemented */
2662a059
JM		 2130 spr_register(env, SPR_405_DBCR1, "DBCR1",
2131 SPR_NOACCESS, SPR_NOACCESS,
2132 &spr_read_generic, &spr_write_generic,
2133 0x00000000);
2134 /* XXX : not implemented */
76a66253
JM		 2135 spr_register(env, SPR_40x_DBSR, "DBSR",
2136 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 2137 &spr_read_generic, &spr_write_clear,
2138 /* Last reset was system reset */
76a66253
JM		 2139 0x00000300);
2140 /* XXX : not implemented */
2662a059 2141 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, &spr_write_generic,
2144 0x00000000);
2662a059 2145 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
2662a059
JM		 2149 /* XXX : not implemented */
2150 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2662a059 2153 0x00000000);
76a66253 2154 /* XXX : not implemented */
2662a059 2155 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
2159 /* XXX : not implemented */
2662a059 2160 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2662a059 2164 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_405_IAC3, "IAC3",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
2173 /* XXX : not implemented */
2174 spr_register(env, SPR_405_IAC4, "IAC4",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, &spr_write_generic,
2177 0x00000000);
2178 /* Storage control */
035feb88 2179 /* XXX: TODO: not implemented */
76a66253
JM		 2180 spr_register(env, SPR_405_SLER, "SLER",
2181 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 2182 &spr_read_generic, &spr_write_40x_sler,
76a66253 2183 0x00000000);
2662a059
JM		 2184 spr_register(env, SPR_40x_ZPR, "ZPR",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
76a66253
JM		 2188 /* XXX : not implemented */
2189 spr_register(env, SPR_405_SU0R, "SU0R",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2193 /* SPRG */
2194 spr_register(env, SPR_USPRG0, "USPRG0",
2195 &spr_read_ureg, SPR_NOACCESS,
2196 &spr_read_ureg, SPR_NOACCESS,
2197 0x00000000);
2198 spr_register(env, SPR_SPRG4, "SPRG4",
2199 SPR_NOACCESS, SPR_NOACCESS,
04f20795 2200 &spr_read_generic, &spr_write_generic,
76a66253 2201 0x00000000);
76a66253
JM		 2202 spr_register(env, SPR_SPRG5, "SPRG5",
2203 SPR_NOACCESS, SPR_NOACCESS,
04f20795 2204 spr_read_generic, &spr_write_generic,
76a66253 2205 0x00000000);
76a66253
JM		 2206 spr_register(env, SPR_SPRG6, "SPRG6",
2207 SPR_NOACCESS, SPR_NOACCESS,
04f20795 2208 spr_read_generic, &spr_write_generic,
76a66253 2209 0x00000000);
76a66253
JM		 2210 spr_register(env, SPR_SPRG7, "SPRG7",
2211 SPR_NOACCESS, SPR_NOACCESS,
04f20795 2212 spr_read_generic, &spr_write_generic,
76a66253 2213 0x00000000);
80d11f44 2214 gen_spr_usprgh(env);
76a66253
JM		 2215}
2216
2217/* SPR shared between PowerPC 401 & 403 implementations */
2218static void gen_spr_401_403 (CPUPPCState *env)
2219{
2220 /* Time base */
2221 spr_register(env, SPR_403_VTBL, "TBL",
2222 &spr_read_tbl, SPR_NOACCESS,
2223 &spr_read_tbl, SPR_NOACCESS,
2224 0x00000000);
2225 spr_register(env, SPR_403_TBL, "TBL",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 SPR_NOACCESS, &spr_write_tbl,
2228 0x00000000);
2229 spr_register(env, SPR_403_VTBU, "TBU",
2230 &spr_read_tbu, SPR_NOACCESS,
2231 &spr_read_tbu, SPR_NOACCESS,
2232 0x00000000);
2233 spr_register(env, SPR_403_TBU, "TBU",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 SPR_NOACCESS, &spr_write_tbu,
2236 0x00000000);
2237 /* Debug */
5cbdb3a3 2238 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 2239 spr_register(env, SPR_403_CDBCR, "CDBCR",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243}
2244
2662a059
JM		 2245/* SPR specific to PowerPC 401 implementation */
2246static void gen_spr_401 (CPUPPCState *env)
2247{
2248 /* Debug interface */
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_40x_DBCR0, "DBCR",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_40x_dbcr0,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_40x_DBSR, "DBSR",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_clear,
2258 /* Last reset was system reset */
2259 0x00000300);
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_40x_DAC1, "DAC",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 /* XXX : not implemented */
2266 spr_register(env, SPR_40x_IAC1, "IAC",
2267 SPR_NOACCESS, SPR_NOACCESS,
2268 &spr_read_generic, &spr_write_generic,
2269 0x00000000);
2270 /* Storage control */
035feb88 2271 /* XXX: TODO: not implemented */
2662a059
JM		 2272 spr_register(env, SPR_405_SLER, "SLER",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_40x_sler,
2275 0x00000000);
5cbdb3a3 2276 /* not emulated, as QEMU never does speculative access */
035feb88
JM		 2277 spr_register(env, SPR_40x_SGR, "SGR",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0xFFFFFFFF);
5cbdb3a3 2281 /* not emulated, as QEMU do not emulate caches */
035feb88
JM		 2282 spr_register(env, SPR_40x_DCWR, "DCWR",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2662a059
JM		 2286}
2287
a750fc0b
JM		 2288static void gen_spr_401x2 (CPUPPCState *env)
2289{
2290 gen_spr_401(env);
2291 spr_register(env, SPR_40x_PID, "PID",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_generic,
2294 0x00000000);
2295 spr_register(env, SPR_40x_ZPR, "ZPR",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299}
2300
76a66253
JM		 2301/* SPR specific to PowerPC 403 implementation */
2302static void gen_spr_403 (CPUPPCState *env)
2303{
2662a059
JM		 2304 /* Debug interface */
2305 /* XXX : not implemented */
2306 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_40x_dbcr0,
2309 0x00000000);
2310 /* XXX : not implemented */
2311 spr_register(env, SPR_40x_DBSR, "DBSR",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_generic, &spr_write_clear,
2314 /* Last reset was system reset */
2315 0x00000300);
2316 /* XXX : not implemented */
2317 spr_register(env, SPR_40x_DAC1, "DAC1",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_generic, &spr_write_generic,
2320 0x00000000);
578bb252 2321 /* XXX : not implemented */
2662a059
JM		 2322 spr_register(env, SPR_40x_DAC2, "DAC2",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 0x00000000);
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_40x_IAC1, "IAC1",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
578bb252 2331 /* XXX : not implemented */
2662a059
JM		 2332 spr_register(env, SPR_40x_IAC2, "IAC2",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
a750fc0b
JM		 2336}
2337
2338static void gen_spr_403_real (CPUPPCState *env)
2339{
76a66253
JM		 2340 spr_register(env, SPR_403_PBL1, "PBL1",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_403_pbr, &spr_write_403_pbr,
2343 0x00000000);
2344 spr_register(env, SPR_403_PBU1, "PBU1",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_403_pbr, &spr_write_403_pbr,
2347 0x00000000);
2348 spr_register(env, SPR_403_PBL2, "PBL2",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_403_pbr, &spr_write_403_pbr,
2351 0x00000000);
2352 spr_register(env, SPR_403_PBU2, "PBU2",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_403_pbr, &spr_write_403_pbr,
2355 0x00000000);
a750fc0b
JM		 2356}
2357
2358static void gen_spr_403_mmu (CPUPPCState *env)
2359{
2360 /* MMU */
2361 spr_register(env, SPR_40x_PID, "PID",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2662a059 2365 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2366 SPR_NOACCESS, SPR_NOACCESS,
2367 &spr_read_generic, &spr_write_generic,
2368 0x00000000);
2369}
2370
2371/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2372static void gen_spr_compress (CPUPPCState *env)
2373{
578bb252 2374 /* XXX : not implemented */
76a66253
JM		 2375 spr_register(env, SPR_401_SKR, "SKR",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379}
a750fc0b 2380
80d11f44 2381static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2382{
80d11f44 2383 /* Exception processing */
d67d40ea
DG		 2384 spr_register_kvm(env, SPR_DSISR, "DSISR",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 KVM_REG_PPC_DSISR, 0x00000000);
2388 spr_register_kvm(env, SPR_DAR, "DAR",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 KVM_REG_PPC_DAR, 0x00000000);
80d11f44
JM		 2392 /* Timer */
2393 spr_register(env, SPR_DECR, "DECR",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_decr, &spr_write_decr,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_EIE, "EIE",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_MPC_EID, "EID",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_NRI, "NRI",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_CMPA, "CMPA",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_MPC_CMPB, "CMPB",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_CMPC, "CMPC",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_MPC_CMPD, "CMPD",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_MPC_ECR, "ECR",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_MPC_DER, "DER",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_CMPE, "CMPE",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_CMPF, "CMPF",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_CMPG, "CMPG",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_CMPH, "CMPH",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_BAR, "BAR",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_DPDR, "DPDR",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_IMMR, "IMMR",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497}
2498
2499static void gen_spr_5xx (CPUPPCState *env)
2500{
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 /* XXX : not implemented */
2577 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2578 SPR_NOACCESS, SPR_NOACCESS,
2579 &spr_read_generic, &spr_write_generic,
2580 0x00000000);
2581 /* XXX : not implemented */
2582 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2583 SPR_NOACCESS, SPR_NOACCESS,
2584 &spr_read_generic, &spr_write_generic,
2585 0x00000000);
2586 /* XXX : not implemented */
2587 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2588 SPR_NOACCESS, SPR_NOACCESS,
2589 &spr_read_generic, &spr_write_generic,
2590 0x00000000);
2591 /* XXX : not implemented */
2592 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2593 SPR_NOACCESS, SPR_NOACCESS,
2594 &spr_read_generic, &spr_write_generic,
2595 0x00000000);
2596 /* XXX : not implemented */
2597 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2598 SPR_NOACCESS, SPR_NOACCESS,
2599 &spr_read_generic, &spr_write_generic,
2600 0x00000000);
2601 /* XXX : not implemented */
2602 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2603 SPR_NOACCESS, SPR_NOACCESS,
2604 &spr_read_generic, &spr_write_generic,
2605 0x00000000);
2606}
2607
2608static void gen_spr_8xx (CPUPPCState *env)
2609{
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 /* XXX : not implemented */
2641 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645 /* XXX : not implemented */
2646 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 /* XXX : not implemented */
2651 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
2655 /* XXX : not implemented */
2656 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660 /* XXX : not implemented */
2661 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665 /* XXX : not implemented */
2666 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2667 SPR_NOACCESS, SPR_NOACCESS,
2668 &spr_read_generic, &spr_write_generic,
2669 0x00000000);
2670 /* XXX : not implemented */
2671 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2672 SPR_NOACCESS, SPR_NOACCESS,
2673 &spr_read_generic, &spr_write_generic,
2674 0x00000000);
2675 /* XXX : not implemented */
2676 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2677 SPR_NOACCESS, SPR_NOACCESS,
2678 &spr_read_generic, &spr_write_generic,
2679 0x00000000);
2680 /* XXX : not implemented */
2681 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2682 SPR_NOACCESS, SPR_NOACCESS,
2683 &spr_read_generic, &spr_write_generic,
2684 0x00000000);
2685 /* XXX : not implemented */
2686 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2687 SPR_NOACCESS, SPR_NOACCESS,
2688 &spr_read_generic, &spr_write_generic,
2689 0x00000000);
2690 /* XXX : not implemented */
2691 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2692 SPR_NOACCESS, SPR_NOACCESS,
2693 &spr_read_generic, &spr_write_generic,
2694 0x00000000);
2695 /* XXX : not implemented */
2696 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2697 SPR_NOACCESS, SPR_NOACCESS,
2698 &spr_read_generic, &spr_write_generic,
2699 0x00000000);
2700 /* XXX : not implemented */
2701 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2702 SPR_NOACCESS, SPR_NOACCESS,
2703 &spr_read_generic, &spr_write_generic,
2704 0x00000000);
2705 /* XXX : not implemented */
2706 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2707 SPR_NOACCESS, SPR_NOACCESS,
2708 &spr_read_generic, &spr_write_generic,
2709 0x00000000);
2710 /* XXX : not implemented */
2711 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2712 SPR_NOACCESS, SPR_NOACCESS,
2713 &spr_read_generic, &spr_write_generic,
2714 0x00000000);
2715 /* XXX : not implemented */
2716 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2717 SPR_NOACCESS, SPR_NOACCESS,
2718 &spr_read_generic, &spr_write_generic,
2719 0x00000000);
2720 /* XXX : not implemented */
2721 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2722 SPR_NOACCESS, SPR_NOACCESS,
2723 &spr_read_generic, &spr_write_generic,
2724 0x00000000);
2725 /* XXX : not implemented */
2726 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2727 SPR_NOACCESS, SPR_NOACCESS,
2728 &spr_read_generic, &spr_write_generic,
2729 0x00000000);
2730 /* XXX : not implemented */
2731 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2732 SPR_NOACCESS, SPR_NOACCESS,
2733 &spr_read_generic, &spr_write_generic,
2734 0x00000000);
2735}
2736
2737// XXX: TODO
2738/*
2739 * AMR => SPR 29 (Power 2.04)
2740 * CTRL => SPR 136 (Power 2.04)
2741 * CTRL => SPR 152 (Power 2.04)
2742 * SCOMC => SPR 276 (64 bits ?)
2743 * SCOMD => SPR 277 (64 bits ?)
2744 * TBU40 => SPR 286 (Power 2.04 hypv)
2745 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2746 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2747 * HDSISR => SPR 306 (Power 2.04 hypv)
2748 * HDAR => SPR 307 (Power 2.04 hypv)
2749 * PURR => SPR 309 (Power 2.04 hypv)
2750 * HDEC => SPR 310 (Power 2.04 hypv)
2751 * HIOR => SPR 311 (hypv)
2752 * RMOR => SPR 312 (970)
2753 * HRMOR => SPR 313 (Power 2.04 hypv)
2754 * HSRR0 => SPR 314 (Power 2.04 hypv)
2755 * HSRR1 => SPR 315 (Power 2.04 hypv)
80d11f44 2756 * LPIDR => SPR 317 (970)
80d11f44
JM		 2757 * EPR => SPR 702 (Power 2.04 emb)
2758 * perf => 768-783 (Power 2.04)
2759 * perf => 784-799 (Power 2.04)
2760 * PPR => SPR 896 (Power 2.04)
2761 * EPLC => SPR 947 (Power 2.04 emb)
2762 * EPSC => SPR 948 (Power 2.04 emb)
2763 * DABRX => 1015 (Power 2.04 hypv)
2764 * FPECR => SPR 1022 (?)
2765 * ... and more (thermal management, performance counters, ...)
2766 */
2767
2768/*****************************************************************************/
2769/* Exception vectors models */
2770static void init_excp_4xx_real (CPUPPCState *env)
2771{
2772#if !defined(CONFIG_USER_ONLY)
2773 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2774 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2775 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2776 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2777 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2778 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2779 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2780 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2781 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2782 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
80d11f44 2783 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2784 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2785 /* Hardware reset vector */
2786 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2787#endif
2788}
2789
80d11f44
JM		 2790static void init_excp_4xx_softmmu (CPUPPCState *env)
2791{
2792#if !defined(CONFIG_USER_ONLY)
2793 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2794 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2795 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2796 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2797 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2798 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2799 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2800 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2801 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2802 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2803 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2804 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2805 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2806 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
80d11f44
JM		 2807 env->ivor_mask = 0x0000FFF0UL;
2808 env->ivpr_mask = 0xFFFF0000UL;
2809 /* Hardware reset vector */
2810 env->hreset_vector = 0xFFFFFFFCUL;
2811#endif
2812}
2813
2814static void init_excp_MPC5xx (CPUPPCState *env)
2815{
2816#if !defined(CONFIG_USER_ONLY)
2817 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2818 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2819 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2820 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2821 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2822 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2823 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2824 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2825 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2826 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2827 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2828 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2829 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2830 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2831 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
80d11f44
JM		 2832 env->ivor_mask = 0x0000FFF0UL;
2833 env->ivpr_mask = 0xFFFF0000UL;
2834 /* Hardware reset vector */
09d9828a 2835 env->hreset_vector = 0x00000100UL;
80d11f44
JM		 2836#endif
2837}
2838
2839static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2840{
2841#if !defined(CONFIG_USER_ONLY)
2842 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2843 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2844 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2845 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2846 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2847 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2848 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2849 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2850 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2851 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2852 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2853 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2854 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2855 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2856 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2857 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2858 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2859 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2860 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2861 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2862 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
80d11f44
JM		 2863 env->ivor_mask = 0x0000FFF0UL;
2864 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2865 /* Hardware reset vector */
09d9828a 2866 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2867#endif
2868}
2869
80d11f44 2870static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2871{
2872#if !defined(CONFIG_USER_ONLY)
2873 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2874 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2875 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2876 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2877 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2878 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2879 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2880 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2881 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2882 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2883 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2884 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2885 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2886 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2887 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2888 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2889 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44 2890 /* Hardware reset vector */
09d9828a 2891 env->hreset_vector = 0x00000100UL;
80d11f44
JM		 2892#endif
2893}
2894
e9cd84b9 2895static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
80d11f44
JM		 2896{
2897#if !defined(CONFIG_USER_ONLY)
2898 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2899 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2900 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2901 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2902 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2903 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2904 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2905 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2906 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2907 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2908 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2909 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2910 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2911 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2912 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2913 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2914 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2915 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2916 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2917 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
80d11f44 2918 env->ivor_mask = 0x0000FFF7UL;
e9cd84b9 2919 env->ivpr_mask = ivpr_mask;
80d11f44
JM		 2920 /* Hardware reset vector */
2921 env->hreset_vector = 0xFFFFFFFCUL;
2922#endif
2923}
2924
2925static void init_excp_BookE (CPUPPCState *env)
2926{
2927#if !defined(CONFIG_USER_ONLY)
2928 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2929 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2930 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2931 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2932 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2933 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2934 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2935 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2936 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2937 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2938 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2939 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2940 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2941 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2942 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2943 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
8412d112 2944 env->ivor_mask = 0x0000FFF0UL;
80d11f44
JM		 2945 env->ivpr_mask = 0xFFFF0000UL;
2946 /* Hardware reset vector */
2947 env->hreset_vector = 0xFFFFFFFCUL;
2948#endif
2949}
2950
2951static void init_excp_601 (CPUPPCState *env)
2952{
2953#if !defined(CONFIG_USER_ONLY)
2954 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2955 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2956 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2957 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2958 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2959 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2960 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2961 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2962 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2963 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2964 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2965 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
1c27f8fb 2966 /* Hardware reset vector */
80d11f44 2967 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2968#endif
2969}
2970
80d11f44 2971static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2972{
2973#if !defined(CONFIG_USER_ONLY)
082c6681 2974 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2975 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2976 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2977 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2978 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2979 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2980 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2981 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2982 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2983 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2984 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2985 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2986 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2987 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2988 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2989 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2990 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2991 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2992 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
1c27f8fb 2993 /* Hardware reset vector */
09d9828a 2994 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2995#endif
2996}
2997
80d11f44 2998static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2999{
3000#if !defined(CONFIG_USER_ONLY)
3001 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3002 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3003 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3004 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3005 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3006 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3007 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3008 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3009 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 3010 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3011 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3012 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3013 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3014 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3015 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3016 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb 3017 /* Hardware reset vector */
09d9828a 3018 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 3019#endif
3020}
3021
3022static void init_excp_604 (CPUPPCState *env)
3023{
3024#if !defined(CONFIG_USER_ONLY)
3025 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3026 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3027 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3028 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3029 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3030 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3031 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3032 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3033 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3034 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3035 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3036 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3037 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3038 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb 3039 /* Hardware reset vector */
2d3eb7bf 3040 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 3041#endif
3042}
3043
e1833e1f
JM		 3044static void init_excp_7x0 (CPUPPCState *env)
3045{
3046#if !defined(CONFIG_USER_ONLY)
3047 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3048 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3049 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3050 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3051 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3052 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3053 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3054 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3055 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3056 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3057 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3058 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3059 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 3060 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 3061 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 3062 /* Hardware reset vector */
09d9828a 3063 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 3064#endif
3065}
3066
bd928eba 3067static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 3068{
3069#if !defined(CONFIG_USER_ONLY)
3070 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3071 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3072 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3073 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3074 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3075 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3076 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3077 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3078 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3079 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3080 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3081 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3082 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3083 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3084 /* Hardware reset vector */
09d9828a 3085 env->hreset_vector = 0x00000100UL;
bd928eba
JM		 3086#endif
3087}
3088
3089static void init_excp_750cx (CPUPPCState *env)
3090{
3091#if !defined(CONFIG_USER_ONLY)
3092 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3093 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3094 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3095 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3096 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3097 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3098 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3099 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3100 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3101 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3102 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3103 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3104 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 3105 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 3106 /* Hardware reset vector */
09d9828a 3107 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 3108#endif
3109}
3110
7a3a6927
JM		 3111/* XXX: Check if this is correct */
3112static void init_excp_7x5 (CPUPPCState *env)
3113{
3114#if !defined(CONFIG_USER_ONLY)
3115 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3116 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3117 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3118 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3119 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3120 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3121 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3122 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3123 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3124 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3125 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 3126 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 3127 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3128 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3129 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 3130 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3131 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3132 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
7a3a6927 3133 /* Hardware reset vector */
09d9828a 3134 env->hreset_vector = 0x00000100UL;
7a3a6927
JM		 3135#endif
3136}
3137
e1833e1f
JM		 3138static void init_excp_7400 (CPUPPCState *env)
3139{
3140#if !defined(CONFIG_USER_ONLY)
3141 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3142 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3143 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3144 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3145 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3146 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3147 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3148 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3149 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3150 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3151 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3152 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3153 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3154 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3155 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3156 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3157 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 3158 /* Hardware reset vector */
09d9828a 3159 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 3160#endif
3161}
3162
e1833e1f
JM		 3163static void init_excp_7450 (CPUPPCState *env)
3164{
3165#if !defined(CONFIG_USER_ONLY)
3166 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3167 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3168 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3169 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3170 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3171 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3172 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3173 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3174 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3175 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3176 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3177 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3178 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3179 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3180 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3181 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3182 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3183 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3184 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1c27f8fb 3185 /* Hardware reset vector */
09d9828a 3186 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 3187#endif
3188}
e1833e1f
JM		 3189
3190#if defined (TARGET_PPC64)
3191static void init_excp_970 (CPUPPCState *env)
3192{
3193#if !defined(CONFIG_USER_ONLY)
3194 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3195 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3196 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3197 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3198 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3199 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3200 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3201 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3202 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3203 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3204 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3205 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3206 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3207 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3208 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3209 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3210 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3211 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3212 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3213 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
1c27f8fb
JM		 3214 /* Hardware reset vector */
3215 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3216#endif
3217}
9d52e907
DG		 3218
3219static void init_excp_POWER7 (CPUPPCState *env)
3220{
3221#if !defined(CONFIG_USER_ONLY)
3222 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3223 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3224 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3225 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3226 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3227 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3228 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3229 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3230 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3231 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3232 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3233 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3234 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3235 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
f03a1af5
BH		 3236 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
3237 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
3238 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
3239 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
9d52e907
DG		 3240 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3241 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1f29871c 3242 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
9d52e907
DG		 3243 /* Hardware reset vector */
3244 env->hreset_vector = 0x0000000000000100ULL;
3245#endif
3246}
f03a1af5
BH		 3247
3248static void init_excp_POWER8(CPUPPCState *env)
3249{
3250 init_excp_POWER7(env);
3251
3252#if !defined(CONFIG_USER_ONLY)
3253 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
3254 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3255 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
3256 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3257#endif
3258}
3259
e1833e1f
JM		 3260#endif
3261
2f462816
JM		 3262/*****************************************************************************/
3263/* Power management enable checks */
3264static int check_pow_none (CPUPPCState *env)
3265{
3266 return 0;
3267}
3268
3269static int check_pow_nocheck (CPUPPCState *env)
3270{
3271 return 1;
3272}
3273
3274static int check_pow_hid0 (CPUPPCState *env)
3275{
3276 if (env->spr[SPR_HID0] & 0x00E00000)
3277 return 1;
3278
3279 return 0;
3280}
3281
4e777442
JM		 3282static int check_pow_hid0_74xx (CPUPPCState *env)
3283{
3284 if (env->spr[SPR_HID0] & 0x00600000)
3285 return 1;
3286
3287 return 0;
3288}
3289
382d2db6
GK		 3290static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3291{
3292 return true;
3293}
3294
3295#ifdef TARGET_PPC64
3296static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3297{
3298 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3299}
3300#endif
3301
a750fc0b
JM		 3302/*****************************************************************************/
3303/* PowerPC implementations definitions */
76a66253 3304
7856e3a4
AF		 3305#define POWERPC_FAMILY(_name) \
3306 static void \
3307 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3308 \
3309 static const TypeInfo \
3310 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3311 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3312 .parent = TYPE_POWERPC_CPU, \
3313 .abstract = true, \
3314 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3315 }; \
3316 \
3317 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3318 { \
3319 type_register_static( \
3320 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3321 } \
3322 \
3323 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3324 \
3325 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3326
a750fc0b
JM		 3327static void init_proc_401 (CPUPPCState *env)
3328{
3329 gen_spr_40x(env);
3330 gen_spr_401_403(env);
3331 gen_spr_401(env);
e1833e1f 3332 init_excp_4xx_real(env);
d63001d1
JM		 3333 env->dcache_line_size = 32;
3334 env->icache_line_size = 32;
4e290a0b 3335 /* Allocate hardware IRQ controller */
aa5a9e24 3336 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 3337
3338 SET_FIT_PERIOD(12, 16, 20, 24);
3339 SET_WDT_PERIOD(16, 20, 24, 28);
a750fc0b 3340}
76a66253 3341
7856e3a4
AF		 3342POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3343{
ca5dff0a 3344 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3345 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3346
ca5dff0a 3347 dc->desc = "PowerPC 401";
7856e3a4
AF		 3348 pcc->init_proc = init_proc_401;
3349 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3350 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3351 PPC_WRTEE | PPC_DCR |
3352 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3353 PPC_CACHE_DCBZ |
3354 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3355 PPC_4xx_COMMON | PPC_40x_EXCP;
9df5a466
TM		 3356 pcc->msr_mask = (1ull << MSR_KEY) |
3357 (1ull << MSR_POW) |
3358 (1ull << MSR_CE) |
3359 (1ull << MSR_ILE) |
3360 (1ull << MSR_EE) |
3361 (1ull << MSR_PR) |
3362 (1ull << MSR_ME) |
3363 (1ull << MSR_DE) |
3364 (1ull << MSR_LE);
ba9fd9f1
AF		 3365 pcc->mmu_model = POWERPC_MMU_REAL;
3366 pcc->excp_model = POWERPC_EXCP_40x;
3367 pcc->bus_model = PPC_FLAGS_INPUT_401;
3368 pcc->bfd_mach = bfd_mach_ppc_403;
3369 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3370 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3371}
3372
a750fc0b
JM		 3373static void init_proc_401x2 (CPUPPCState *env)
3374{
3375 gen_spr_40x(env);
3376 gen_spr_401_403(env);
3377 gen_spr_401x2(env);
3378 gen_spr_compress(env);
a750fc0b 3379 /* Memory management */
f2e63a42 3380#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3381 env->nb_tlb = 64;
3382 env->nb_ways = 1;
3383 env->id_tlbs = 0;
1c53accc 3384 env->tlb_type = TLB_EMB;
f2e63a42 3385#endif
e1833e1f 3386 init_excp_4xx_softmmu(env);
d63001d1
JM		 3387 env->dcache_line_size = 32;
3388 env->icache_line_size = 32;
4e290a0b 3389 /* Allocate hardware IRQ controller */
aa5a9e24 3390 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 3391
3392 SET_FIT_PERIOD(12, 16, 20, 24);
3393 SET_WDT_PERIOD(16, 20, 24, 28);
76a66253
JM		 3394}
3395
7856e3a4
AF		 3396POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3397{
ca5dff0a 3398 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3399 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3400
ca5dff0a 3401 dc->desc = "PowerPC 401x2";
7856e3a4
AF		 3402 pcc->init_proc = init_proc_401x2;
3403 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3404 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3405 PPC_DCR | PPC_WRTEE |
3406 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3407 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3408 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3409 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3410 PPC_4xx_COMMON | PPC_40x_EXCP;
9df5a466
TM		 3411 pcc->msr_mask = (1ull << 20) |
3412 (1ull << MSR_KEY) |
3413 (1ull << MSR_POW) |
3414 (1ull << MSR_CE) |
3415 (1ull << MSR_ILE) |
3416 (1ull << MSR_EE) |
3417 (1ull << MSR_PR) |
3418 (1ull << MSR_ME) |
3419 (1ull << MSR_DE) |
3420 (1ull << MSR_IR) |
3421 (1ull << MSR_DR) |
3422 (1ull << MSR_LE);
ba9fd9f1
AF		 3423 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3424 pcc->excp_model = POWERPC_EXCP_40x;
3425 pcc->bus_model = PPC_FLAGS_INPUT_401;
3426 pcc->bfd_mach = bfd_mach_ppc_403;
3427 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3428 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3429}
3430
e1833e1f 3431static void init_proc_401x3 (CPUPPCState *env)
76a66253 3432{
4e290a0b
JM		 3433 gen_spr_40x(env);
3434 gen_spr_401_403(env);
3435 gen_spr_401(env);
3436 gen_spr_401x2(env);
3437 gen_spr_compress(env);
e1833e1f 3438 init_excp_4xx_softmmu(env);
d63001d1
JM		 3439 env->dcache_line_size = 32;
3440 env->icache_line_size = 32;
4e290a0b 3441 /* Allocate hardware IRQ controller */
aa5a9e24 3442 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 3443
3444 SET_FIT_PERIOD(12, 16, 20, 24);
3445 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082 3446}
a750fc0b 3447
7856e3a4
AF		 3448POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3449{
ca5dff0a 3450 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3451 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3452
ca5dff0a 3453 dc->desc = "PowerPC 401x3";
7856e3a4
AF		 3454 pcc->init_proc = init_proc_401x3;
3455 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3456 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3457 PPC_DCR | PPC_WRTEE |
3458 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3459 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3460 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3461 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3462 PPC_4xx_COMMON | PPC_40x_EXCP;
9df5a466
TM		 3463 pcc->msr_mask = (1ull << 20) |
3464 (1ull << MSR_KEY) |
3465 (1ull << MSR_POW) |
3466 (1ull << MSR_CE) |
3467 (1ull << MSR_ILE) |
3468 (1ull << MSR_EE) |
3469 (1ull << MSR_PR) |
3470 (1ull << MSR_ME) |
3471 (1ull << MSR_DWE) |
3472 (1ull << MSR_DE) |
3473 (1ull << MSR_IR) |
3474 (1ull << MSR_DR) |
3475 (1ull << MSR_LE);
ba9fd9f1
AF		 3476 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3477 pcc->excp_model = POWERPC_EXCP_40x;
3478 pcc->bus_model = PPC_FLAGS_INPUT_401;
3479 pcc->bfd_mach = bfd_mach_ppc_403;
3480 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3481 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3482}
3483
a750fc0b 3484static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3485{
a750fc0b
JM		 3486 gen_spr_40x(env);
3487 gen_spr_401_403(env);
3488 gen_spr_401x2(env);
3489 gen_spr_compress(env);
a750fc0b 3490 /* Memory management */
f2e63a42 3491#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3492 env->nb_tlb = 64;
3493 env->nb_ways = 1;
3494 env->id_tlbs = 0;
1c53accc 3495 env->tlb_type = TLB_EMB;
f2e63a42 3496#endif
e1833e1f 3497 init_excp_4xx_softmmu(env);
d63001d1
JM		 3498 env->dcache_line_size = 32;
3499 env->icache_line_size = 32;
4e290a0b 3500 /* Allocate hardware IRQ controller */
aa5a9e24 3501 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 3502
3503 SET_FIT_PERIOD(8, 12, 16, 20);
3504 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3505}
3506
7856e3a4
AF		 3507POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3508{
ca5dff0a 3509 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3510 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3511
ca5dff0a 3512 dc->desc = "IOP480";
7856e3a4
AF		 3513 pcc->init_proc = init_proc_IOP480;
3514 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3515 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3516 PPC_DCR | PPC_WRTEE |
3517 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3518 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3519 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3520 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3521 PPC_4xx_COMMON | PPC_40x_EXCP;
9df5a466
TM		 3522 pcc->msr_mask = (1ull << 20) |
3523 (1ull << MSR_KEY) |
3524 (1ull << MSR_POW) |
3525 (1ull << MSR_CE) |
3526 (1ull << MSR_ILE) |
3527 (1ull << MSR_EE) |
3528 (1ull << MSR_PR) |
3529 (1ull << MSR_ME) |
3530 (1ull << MSR_DE) |
3531 (1ull << MSR_IR) |
3532 (1ull << MSR_DR) |
3533 (1ull << MSR_LE);
ba9fd9f1
AF		 3534 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3535 pcc->excp_model = POWERPC_EXCP_40x;
3536 pcc->bus_model = PPC_FLAGS_INPUT_401;
3537 pcc->bfd_mach = bfd_mach_ppc_403;
3538 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3539 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3540}
3541
a750fc0b 3542static void init_proc_403 (CPUPPCState *env)
3fc6c082 3543{
a750fc0b
JM		 3544 gen_spr_40x(env);
3545 gen_spr_401_403(env);
3546 gen_spr_403(env);
3547 gen_spr_403_real(env);
e1833e1f 3548 init_excp_4xx_real(env);
d63001d1
JM		 3549 env->dcache_line_size = 32;
3550 env->icache_line_size = 32;
4e290a0b 3551 /* Allocate hardware IRQ controller */
aa5a9e24 3552 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 3553
3554 SET_FIT_PERIOD(8, 12, 16, 20);
3555 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3556}
3557
7856e3a4
AF		 3558POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3559{
ca5dff0a 3560 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3561 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3562
ca5dff0a 3563 dc->desc = "PowerPC 403";
7856e3a4
AF		 3564 pcc->init_proc = init_proc_403;
3565 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3566 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3567 PPC_DCR | PPC_WRTEE |
3568 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3569 PPC_CACHE_DCBZ |
3570 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3571 PPC_4xx_COMMON | PPC_40x_EXCP;
9df5a466
TM		 3572 pcc->msr_mask = (1ull << MSR_POW) |
3573 (1ull << MSR_CE) |
3574 (1ull << MSR_ILE) |
3575 (1ull << MSR_EE) |
3576 (1ull << MSR_PR) |
3577 (1ull << MSR_ME) |
3578 (1ull << MSR_PE) |
3579 (1ull << MSR_PX) |
3580 (1ull << MSR_LE);
ba9fd9f1
AF		 3581 pcc->mmu_model = POWERPC_MMU_REAL;
3582 pcc->excp_model = POWERPC_EXCP_40x;
3583 pcc->bus_model = PPC_FLAGS_INPUT_401;
3584 pcc->bfd_mach = bfd_mach_ppc_403;
3585 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3586 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3587}
3588
a750fc0b 3589static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3590{
a750fc0b
JM		 3591 gen_spr_40x(env);
3592 gen_spr_401_403(env);
3593 gen_spr_403(env);
3594 gen_spr_403_real(env);
3595 gen_spr_403_mmu(env);
3596 /* Bus access control */
5cbdb3a3 3597 /* not emulated, as QEMU never does speculative access */
a750fc0b
JM		 3598 spr_register(env, SPR_40x_SGR, "SGR",
3599 SPR_NOACCESS, SPR_NOACCESS,
3600 &spr_read_generic, &spr_write_generic,
3601 0xFFFFFFFF);
5cbdb3a3 3602 /* not emulated, as QEMU do not emulate caches */
a750fc0b
JM		 3603 spr_register(env, SPR_40x_DCWR, "DCWR",
3604 SPR_NOACCESS, SPR_NOACCESS,
3605 &spr_read_generic, &spr_write_generic,
3606 0x00000000);
3607 /* Memory management */
f2e63a42 3608#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3609 env->nb_tlb = 64;
3610 env->nb_ways = 1;
3611 env->id_tlbs = 0;
1c53accc 3612 env->tlb_type = TLB_EMB;
f2e63a42 3613#endif
80d11f44
JM		 3614 init_excp_4xx_softmmu(env);
3615 env->dcache_line_size = 32;
3616 env->icache_line_size = 32;
3617 /* Allocate hardware IRQ controller */
aa5a9e24 3618 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 3619
3620 SET_FIT_PERIOD(8, 12, 16, 20);
3621 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3622}
3623
7856e3a4
AF		 3624POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3625{
ca5dff0a 3626 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3627 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3628
ca5dff0a 3629 dc->desc = "PowerPC 403 GCX";
7856e3a4
AF		 3630 pcc->init_proc = init_proc_403GCX;
3631 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3632 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3633 PPC_DCR | PPC_WRTEE |
3634 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3635 PPC_CACHE_DCBZ |
3636 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3637 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3638 PPC_4xx_COMMON | PPC_40x_EXCP;
9df5a466
TM		 3639 pcc->msr_mask = (1ull << MSR_POW) |
3640 (1ull << MSR_CE) |
3641 (1ull << MSR_ILE) |
3642 (1ull << MSR_EE) |
3643 (1ull << MSR_PR) |
3644 (1ull << MSR_ME) |
3645 (1ull << MSR_PE) |
3646 (1ull << MSR_PX) |
3647 (1ull << MSR_LE);
ba9fd9f1
AF		 3648 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3649 pcc->excp_model = POWERPC_EXCP_40x;
3650 pcc->bus_model = PPC_FLAGS_INPUT_401;
3651 pcc->bfd_mach = bfd_mach_ppc_403;
3652 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3653 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3654}
3655
80d11f44
JM		 3656static void init_proc_405 (CPUPPCState *env)
3657{
3658 /* Time base */
3659 gen_tbl(env);
3660 gen_spr_40x(env);
3661 gen_spr_405(env);
3662 /* Bus access control */
5cbdb3a3 3663 /* not emulated, as QEMU never does speculative access */
80d11f44
JM		 3664 spr_register(env, SPR_40x_SGR, "SGR",
3665 SPR_NOACCESS, SPR_NOACCESS,
3666 &spr_read_generic, &spr_write_generic,
3667 0xFFFFFFFF);
5cbdb3a3 3668 /* not emulated, as QEMU do not emulate caches */
80d11f44
JM		 3669 spr_register(env, SPR_40x_DCWR, "DCWR",
3670 SPR_NOACCESS, SPR_NOACCESS,
3671 &spr_read_generic, &spr_write_generic,
3672 0x00000000);
3673 /* Memory management */
3674#if !defined(CONFIG_USER_ONLY)
3675 env->nb_tlb = 64;
3676 env->nb_ways = 1;
3677 env->id_tlbs = 0;
1c53accc 3678 env->tlb_type = TLB_EMB;
80d11f44
JM		 3679#endif
3680 init_excp_4xx_softmmu(env);
3681 env->dcache_line_size = 32;
3682 env->icache_line_size = 32;
3683 /* Allocate hardware IRQ controller */
aa5a9e24 3684 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 3685
3686 SET_FIT_PERIOD(8, 12, 16, 20);
3687 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3688}
3689
7856e3a4
AF		 3690POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3691{
ca5dff0a 3692 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3693 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3694
ca5dff0a 3695 dc->desc = "PowerPC 405";
7856e3a4
AF		 3696 pcc->init_proc = init_proc_405;
3697 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3698 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3699 PPC_DCR | PPC_WRTEE |
3700 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3701 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3702 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3703 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3704 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
9df5a466
TM		 3705 pcc->msr_mask = (1ull << MSR_POW) |
3706 (1ull << MSR_CE) |
3707 (1ull << MSR_EE) |
3708 (1ull << MSR_PR) |
3709 (1ull << MSR_FP) |
3710 (1ull << MSR_DWE) |
3711 (1ull << MSR_DE) |
3712 (1ull << MSR_IR) |
3713 (1ull << MSR_DR);
ba9fd9f1
AF		 3714 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3715 pcc->excp_model = POWERPC_EXCP_40x;
3716 pcc->bus_model = PPC_FLAGS_INPUT_405;
3717 pcc->bfd_mach = bfd_mach_ppc_403;
3718 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3719 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3720}
3721
80d11f44
JM		 3722static void init_proc_440EP (CPUPPCState *env)
3723{
3724 /* Time base */
3725 gen_tbl(env);
3726 gen_spr_BookE(env, 0x000000000000FFFFULL);
3727 gen_spr_440(env);
3728 gen_spr_usprgh(env);
3729 /* Processor identification */
3730 spr_register(env, SPR_BOOKE_PIR, "PIR",
3731 SPR_NOACCESS, SPR_NOACCESS,
3732 &spr_read_generic, &spr_write_pir,
3733 0x00000000);
3734 /* XXX : not implemented */
3735 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3736 SPR_NOACCESS, SPR_NOACCESS,
3737 &spr_read_generic, &spr_write_generic,
3738 0x00000000);
3739 /* XXX : not implemented */
3740 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3741 SPR_NOACCESS, SPR_NOACCESS,
3742 &spr_read_generic, &spr_write_generic,
3743 0x00000000);
3744 /* XXX : not implemented */
3745 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3746 SPR_NOACCESS, SPR_NOACCESS,
3747 &spr_read_generic, &spr_write_generic,
3748 0x00000000);
3749 /* XXX : not implemented */
3750 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3751 SPR_NOACCESS, SPR_NOACCESS,
3752 &spr_read_generic, &spr_write_generic,
3753 0x00000000);
3754 /* XXX : not implemented */
3755 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3756 SPR_NOACCESS, SPR_NOACCESS,
3757 &spr_read_generic, &spr_write_generic,
3758 0x00000000);
3759 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3760 SPR_NOACCESS, SPR_NOACCESS,
3761 &spr_read_generic, &spr_write_generic,
3762 0x00000000);
3763 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3764 SPR_NOACCESS, SPR_NOACCESS,
3765 &spr_read_generic, &spr_write_generic,
3766 0x00000000);
3767 /* XXX : not implemented */
3768 spr_register(env, SPR_440_CCR1, "CCR1",
3769 SPR_NOACCESS, SPR_NOACCESS,
3770 &spr_read_generic, &spr_write_generic,
3771 0x00000000);
3772 /* Memory management */
3773#if !defined(CONFIG_USER_ONLY)
3774 env->nb_tlb = 64;
3775 env->nb_ways = 1;
3776 env->id_tlbs = 0;
1c53accc 3777 env->tlb_type = TLB_EMB;
80d11f44
JM		 3778#endif
3779 init_excp_BookE(env);
3780 env->dcache_line_size = 32;
3781 env->icache_line_size = 32;
aa5a9e24 3782 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 3783
3784 SET_FIT_PERIOD(12, 16, 20, 24);
3785 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3786}
3787
7856e3a4
AF		 3788POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3789{
ca5dff0a 3790 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3791 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3792
ca5dff0a 3793 dc->desc = "PowerPC 440 EP";
7856e3a4
AF		 3794 pcc->init_proc = init_proc_440EP;
3795 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3796 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3797 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3798 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3799 PPC_FLOAT_STFIWX |
3800 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3801 PPC_CACHE | PPC_CACHE_ICBI |
3802 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3803 PPC_MEM_TLBSYNC | PPC_MFTB |
3804 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3805 PPC_440_SPEC;
9df5a466
TM		 3806 pcc->msr_mask = (1ull << MSR_POW) |
3807 (1ull << MSR_CE) |
3808 (1ull << MSR_EE) |
3809 (1ull << MSR_PR) |
3810 (1ull << MSR_FP) |
3811 (1ull << MSR_ME) |
3812 (1ull << MSR_FE0) |
3813 (1ull << MSR_DWE) |
3814 (1ull << MSR_DE) |
3815 (1ull << MSR_FE1) |
3816 (1ull << MSR_IR) |
3817 (1ull << MSR_DR);
ba9fd9f1
AF		 3818 pcc->mmu_model = POWERPC_MMU_BOOKE;
3819 pcc->excp_model = POWERPC_EXCP_BOOKE;
3820 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3821 pcc->bfd_mach = bfd_mach_ppc_403;
3822 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3823 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3824}
3825
80d11f44
JM		 3826static void init_proc_440GP (CPUPPCState *env)
3827{
3828 /* Time base */
3829 gen_tbl(env);
3830 gen_spr_BookE(env, 0x000000000000FFFFULL);
3831 gen_spr_440(env);
3832 gen_spr_usprgh(env);
3833 /* Processor identification */
3834 spr_register(env, SPR_BOOKE_PIR, "PIR",
3835 SPR_NOACCESS, SPR_NOACCESS,
3836 &spr_read_generic, &spr_write_pir,
3837 0x00000000);
3838 /* XXX : not implemented */
3839 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3840 SPR_NOACCESS, SPR_NOACCESS,
3841 &spr_read_generic, &spr_write_generic,
3842 0x00000000);
3843 /* XXX : not implemented */
3844 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848 /* XXX : not implemented */
3849 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3850 SPR_NOACCESS, SPR_NOACCESS,
3851 &spr_read_generic, &spr_write_generic,
3852 0x00000000);
3853 /* XXX : not implemented */
3854 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3855 SPR_NOACCESS, SPR_NOACCESS,
3856 &spr_read_generic, &spr_write_generic,
3857 0x00000000);
3858 /* Memory management */
3859#if !defined(CONFIG_USER_ONLY)
3860 env->nb_tlb = 64;
3861 env->nb_ways = 1;
3862 env->id_tlbs = 0;
1c53accc 3863 env->tlb_type = TLB_EMB;
80d11f44
JM		 3864#endif
3865 init_excp_BookE(env);
3866 env->dcache_line_size = 32;
3867 env->icache_line_size = 32;
3868 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3869
3870 SET_FIT_PERIOD(12, 16, 20, 24);
3871 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3872}
3873
7856e3a4
AF		 3874POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3875{
ca5dff0a 3876 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3877 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3878
ca5dff0a 3879 dc->desc = "PowerPC 440 GP";
7856e3a4
AF		 3880 pcc->init_proc = init_proc_440GP;
3881 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3882 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3883 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3884 PPC_CACHE | PPC_CACHE_ICBI |
3885 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3886 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3887 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3888 PPC_440_SPEC;
9df5a466
TM		 3889 pcc->msr_mask = (1ull << MSR_POW) |
3890 (1ull << MSR_CE) |
3891 (1ull << MSR_EE) |
3892 (1ull << MSR_PR) |
3893 (1ull << MSR_FP) |
3894 (1ull << MSR_ME) |
3895 (1ull << MSR_FE0) |
3896 (1ull << MSR_DWE) |
3897 (1ull << MSR_DE) |
3898 (1ull << MSR_FE1) |
3899 (1ull << MSR_IR) |
3900 (1ull << MSR_DR);
ba9fd9f1
AF		 3901 pcc->mmu_model = POWERPC_MMU_BOOKE;
3902 pcc->excp_model = POWERPC_EXCP_BOOKE;
3903 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3904 pcc->bfd_mach = bfd_mach_ppc_403;
3905 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3906 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3907}
3908
80d11f44
JM		 3909static void init_proc_440x4 (CPUPPCState *env)
3910{
3911 /* Time base */
3912 gen_tbl(env);
3913 gen_spr_BookE(env, 0x000000000000FFFFULL);
3914 gen_spr_440(env);
3915 gen_spr_usprgh(env);
3916 /* Processor identification */
3917 spr_register(env, SPR_BOOKE_PIR, "PIR",
3918 SPR_NOACCESS, SPR_NOACCESS,
3919 &spr_read_generic, &spr_write_pir,
3920 0x00000000);
3921 /* XXX : not implemented */
3922 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3923 SPR_NOACCESS, SPR_NOACCESS,
3924 &spr_read_generic, &spr_write_generic,
3925 0x00000000);
3926 /* XXX : not implemented */
3927 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3928 SPR_NOACCESS, SPR_NOACCESS,
3929 &spr_read_generic, &spr_write_generic,
3930 0x00000000);
3931 /* XXX : not implemented */
3932 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3933 SPR_NOACCESS, SPR_NOACCESS,
3934 &spr_read_generic, &spr_write_generic,
3935 0x00000000);
3936 /* XXX : not implemented */
3937 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3938 SPR_NOACCESS, SPR_NOACCESS,
3939 &spr_read_generic, &spr_write_generic,
3940 0x00000000);
3941 /* Memory management */
3942#if !defined(CONFIG_USER_ONLY)
3943 env->nb_tlb = 64;
3944 env->nb_ways = 1;
3945 env->id_tlbs = 0;
1c53accc 3946 env->tlb_type = TLB_EMB;
80d11f44
JM		 3947#endif
3948 init_excp_BookE(env);
d63001d1
JM		 3949 env->dcache_line_size = 32;
3950 env->icache_line_size = 32;
80d11f44 3951 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3952
3953 SET_FIT_PERIOD(12, 16, 20, 24);
3954 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3955}
3956
7856e3a4
AF		 3957POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3958{
ca5dff0a 3959 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3960 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3961
ca5dff0a 3962 dc->desc = "PowerPC 440x4";
7856e3a4
AF		 3963 pcc->init_proc = init_proc_440x4;
3964 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3965 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3966 PPC_DCR | PPC_WRTEE |
3967 PPC_CACHE | PPC_CACHE_ICBI |
3968 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3969 PPC_MEM_TLBSYNC | PPC_MFTB |
3970 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3971 PPC_440_SPEC;
9df5a466
TM		 3972 pcc->msr_mask = (1ull << MSR_POW) |
3973 (1ull << MSR_CE) |
3974 (1ull << MSR_EE) |
3975 (1ull << MSR_PR) |
3976 (1ull << MSR_FP) |
3977 (1ull << MSR_ME) |
3978 (1ull << MSR_FE0) |
3979 (1ull << MSR_DWE) |
3980 (1ull << MSR_DE) |
3981 (1ull << MSR_FE1) |
3982 (1ull << MSR_IR) |
3983 (1ull << MSR_DR);
ba9fd9f1
AF		 3984 pcc->mmu_model = POWERPC_MMU_BOOKE;
3985 pcc->excp_model = POWERPC_EXCP_BOOKE;
3986 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3987 pcc->bfd_mach = bfd_mach_ppc_403;
3988 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3989 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3990}
3991
80d11f44 3992static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3993{
a750fc0b
JM		 3994 /* Time base */
3995 gen_tbl(env);
80d11f44
JM		 3996 gen_spr_BookE(env, 0x000000000000FFFFULL);
3997 gen_spr_440(env);
3998 gen_spr_usprgh(env);
3999 /* Processor identification */
4000 spr_register(env, SPR_BOOKE_PIR, "PIR",
4001 SPR_NOACCESS, SPR_NOACCESS,
4002 &spr_read_generic, &spr_write_pir,
4003 0x00000000);
4004 /* XXX : not implemented */
4005 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 4006 SPR_NOACCESS, SPR_NOACCESS,
4007 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4008 0x00000000);
4009 /* XXX : not implemented */
4010 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4011 SPR_NOACCESS, SPR_NOACCESS,
4012 &spr_read_generic, &spr_write_generic,
4013 0x00000000);
4014 /* XXX : not implemented */
4015 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4016 SPR_NOACCESS, SPR_NOACCESS,
4017 &spr_read_generic, &spr_write_generic,
4018 0x00000000);
4019 /* XXX : not implemented */
4020 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4021 SPR_NOACCESS, SPR_NOACCESS,
4022 &spr_read_generic, &spr_write_generic,
4023 0x00000000);
4024 /* XXX : not implemented */
4025 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4026 SPR_NOACCESS, SPR_NOACCESS,
4027 &spr_read_generic, &spr_write_generic,
4028 0x00000000);
4029 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4030 SPR_NOACCESS, SPR_NOACCESS,
4031 &spr_read_generic, &spr_write_generic,
4032 0x00000000);
4033 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4034 SPR_NOACCESS, SPR_NOACCESS,
4035 &spr_read_generic, &spr_write_generic,
4036 0x00000000);
4037 /* XXX : not implemented */
4038 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 4039 SPR_NOACCESS, SPR_NOACCESS,
4040 &spr_read_generic, &spr_write_generic,
4041 0x00000000);
4042 /* Memory management */
f2e63a42 4043#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4044 env->nb_tlb = 64;
4045 env->nb_ways = 1;
4046 env->id_tlbs = 0;
1c53accc 4047 env->tlb_type = TLB_EMB;
f2e63a42 4048#endif
80d11f44 4049 init_excp_BookE(env);
d63001d1
JM		 4050 env->dcache_line_size = 32;
4051 env->icache_line_size = 32;
aa5a9e24 4052 ppc40x_irq_init(ppc_env_get_cpu(env));
ddd1055b
FC		 4053
4054 SET_FIT_PERIOD(12, 16, 20, 24);
4055 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4056}
4057
7856e3a4
AF		 4058POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4059{
ca5dff0a 4060 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4061 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4062
ca5dff0a 4063 dc->desc = "PowerPC 440x5";
7856e3a4
AF		 4064 pcc->init_proc = init_proc_440x5;
4065 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 4066 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4067 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4068 PPC_CACHE | PPC_CACHE_ICBI |
4069 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4070 PPC_MEM_TLBSYNC | PPC_MFTB |
4071 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4072 PPC_440_SPEC;
9df5a466
TM		 4073 pcc->msr_mask = (1ull << MSR_POW) |
4074 (1ull << MSR_CE) |
4075 (1ull << MSR_EE) |
4076 (1ull << MSR_PR) |
4077 (1ull << MSR_FP) |
4078 (1ull << MSR_ME) |
4079 (1ull << MSR_FE0) |
4080 (1ull << MSR_DWE) |
4081 (1ull << MSR_DE) |
4082 (1ull << MSR_FE1) |
4083 (1ull << MSR_IR) |
4084 (1ull << MSR_DR);
ba9fd9f1
AF		 4085 pcc->mmu_model = POWERPC_MMU_BOOKE;
4086 pcc->excp_model = POWERPC_EXCP_BOOKE;
4087 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4088 pcc->bfd_mach = bfd_mach_ppc_403;
4089 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4090 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4091}
4092
b8c867ed
PM		 4093POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4094{
4095 DeviceClass *dc = DEVICE_CLASS(oc);
4096 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4097
4098 dc->desc = "PowerPC 440x5 with double precision FPU";
4099 pcc->init_proc = init_proc_440x5;
4100 pcc->check_pow = check_pow_nocheck;
4101 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4102 PPC_FLOAT | PPC_FLOAT_FSQRT |
4103 PPC_FLOAT_STFIWX |
4104 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4105 PPC_CACHE | PPC_CACHE_ICBI |
4106 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4107 PPC_MEM_TLBSYNC | PPC_MFTB |
4108 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4109 PPC_440_SPEC;
4110 pcc->insns_flags2 = PPC2_FP_CVT_S64;
4111 pcc->msr_mask = (1ull << MSR_POW) |
4112 (1ull << MSR_CE) |
4113 (1ull << MSR_EE) |
4114 (1ull << MSR_PR) |
4115 (1ull << MSR_FP) |
4116 (1ull << MSR_ME) |
4117 (1ull << MSR_FE0) |
4118 (1ull << MSR_DWE) |
4119 (1ull << MSR_DE) |
4120 (1ull << MSR_FE1) |
4121 (1ull << MSR_IR) |
4122 (1ull << MSR_DR);
4123 pcc->mmu_model = POWERPC_MMU_BOOKE;
4124 pcc->excp_model = POWERPC_EXCP_BOOKE;
4125 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4126 pcc->bfd_mach = bfd_mach_ppc_403;
4127 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4128 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4129}
4130
80d11f44 4131static void init_proc_460 (CPUPPCState *env)
3fc6c082 4132{
a750fc0b
JM		 4133 /* Time base */
4134 gen_tbl(env);
80d11f44 4135 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 4136 gen_spr_440(env);
80d11f44
JM		 4137 gen_spr_usprgh(env);
4138 /* Processor identification */
4139 spr_register(env, SPR_BOOKE_PIR, "PIR",
4140 SPR_NOACCESS, SPR_NOACCESS,
4141 &spr_read_generic, &spr_write_pir,
4142 0x00000000);
4143 /* XXX : not implemented */
4144 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0x00000000);
4148 /* XXX : not implemented */
4149 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
4153 /* XXX : not implemented */
4154 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4155 SPR_NOACCESS, SPR_NOACCESS,
4156 &spr_read_generic, &spr_write_generic,
4157 0x00000000);
4158 /* XXX : not implemented */
4159 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4160 SPR_NOACCESS, SPR_NOACCESS,
4161 &spr_read_generic, &spr_write_generic,
4162 0x00000000);
578bb252 4163 /* XXX : not implemented */
a750fc0b
JM		 4164 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4165 SPR_NOACCESS, SPR_NOACCESS,
4166 &spr_read_generic, &spr_write_generic,
4167 0x00000000);
4168 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4169 SPR_NOACCESS, SPR_NOACCESS,
4170 &spr_read_generic, &spr_write_generic,
4171 0x00000000);
4172 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4173 SPR_NOACCESS, SPR_NOACCESS,
4174 &spr_read_generic, &spr_write_generic,
4175 0x00000000);
578bb252 4176 /* XXX : not implemented */
a750fc0b
JM		 4177 spr_register(env, SPR_440_CCR1, "CCR1",
4178 SPR_NOACCESS, SPR_NOACCESS,
4179 &spr_read_generic, &spr_write_generic,
4180 0x00000000);
80d11f44
JM		 4181 /* XXX : not implemented */
4182 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4183 &spr_read_generic, &spr_write_generic,
4184 &spr_read_generic, &spr_write_generic,
4185 0x00000000);
a750fc0b 4186 /* Memory management */
f2e63a42 4187#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4188 env->nb_tlb = 64;
4189 env->nb_ways = 1;
4190 env->id_tlbs = 0;
1c53accc 4191 env->tlb_type = TLB_EMB;
f2e63a42 4192#endif
e1833e1f 4193 init_excp_BookE(env);
d63001d1
JM		 4194 env->dcache_line_size = 32;
4195 env->icache_line_size = 32;
a750fc0b 4196 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 4197
4198 SET_FIT_PERIOD(12, 16, 20, 24);
4199 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4200}
4201
7856e3a4
AF		 4202POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4203{
ca5dff0a 4204 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4205 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4206
ca5dff0a 4207 dc->desc = "PowerPC 460 (guessed)";
7856e3a4
AF		 4208 pcc->init_proc = init_proc_460;
4209 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 4210 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4211 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4212 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4213 PPC_CACHE | PPC_CACHE_ICBI |
4214 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4215 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4216 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4217 PPC_440_SPEC;
9df5a466
TM		 4218 pcc->msr_mask = (1ull << MSR_POW) |
4219 (1ull << MSR_CE) |
4220 (1ull << MSR_EE) |
4221 (1ull << MSR_PR) |
4222 (1ull << MSR_FP) |
4223 (1ull << MSR_ME) |
4224 (1ull << MSR_FE0) |
4225 (1ull << MSR_DWE) |
4226 (1ull << MSR_DE) |
4227 (1ull << MSR_FE1) |
4228 (1ull << MSR_IR) |
4229 (1ull << MSR_DR);
ba9fd9f1
AF		 4230 pcc->mmu_model = POWERPC_MMU_BOOKE;
4231 pcc->excp_model = POWERPC_EXCP_BOOKE;
4232 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4233 pcc->bfd_mach = bfd_mach_ppc_403;
4234 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4235 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4236}
4237
80d11f44 4238static void init_proc_460F (CPUPPCState *env)
3fc6c082 4239{
a750fc0b
JM		 4240 /* Time base */
4241 gen_tbl(env);
80d11f44 4242 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 4243 gen_spr_440(env);
80d11f44
JM		 4244 gen_spr_usprgh(env);
4245 /* Processor identification */
4246 spr_register(env, SPR_BOOKE_PIR, "PIR",
4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_pir,
4249 0x00000000);
4250 /* XXX : not implemented */
4251 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4252 SPR_NOACCESS, SPR_NOACCESS,
4253 &spr_read_generic, &spr_write_generic,
4254 0x00000000);
4255 /* XXX : not implemented */
4256 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4257 SPR_NOACCESS, SPR_NOACCESS,
4258 &spr_read_generic, &spr_write_generic,
4259 0x00000000);
4260 /* XXX : not implemented */
4261 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4262 SPR_NOACCESS, SPR_NOACCESS,
4263 &spr_read_generic, &spr_write_generic,
4264 0x00000000);
4265 /* XXX : not implemented */
4266 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4267 SPR_NOACCESS, SPR_NOACCESS,
4268 &spr_read_generic, &spr_write_generic,
4269 0x00000000);
4270 /* XXX : not implemented */
4271 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4272 SPR_NOACCESS, SPR_NOACCESS,
4273 &spr_read_generic, &spr_write_generic,
4274 0x00000000);
4275 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4276 SPR_NOACCESS, SPR_NOACCESS,
4277 &spr_read_generic, &spr_write_generic,
4278 0x00000000);
4279 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4280 SPR_NOACCESS, SPR_NOACCESS,
4281 &spr_read_generic, &spr_write_generic,
4282 0x00000000);
4283 /* XXX : not implemented */
4284 spr_register(env, SPR_440_CCR1, "CCR1",
4285 SPR_NOACCESS, SPR_NOACCESS,
4286 &spr_read_generic, &spr_write_generic,
4287 0x00000000);
4288 /* XXX : not implemented */
4289 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4290 &spr_read_generic, &spr_write_generic,
4291 &spr_read_generic, &spr_write_generic,
4292 0x00000000);
a750fc0b 4293 /* Memory management */
f2e63a42 4294#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4295 env->nb_tlb = 64;
4296 env->nb_ways = 1;
4297 env->id_tlbs = 0;
1c53accc 4298 env->tlb_type = TLB_EMB;
f2e63a42 4299#endif
e1833e1f 4300 init_excp_BookE(env);
d63001d1
JM		 4301 env->dcache_line_size = 32;
4302 env->icache_line_size = 32;
a750fc0b 4303 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 4304
4305 SET_FIT_PERIOD(12, 16, 20, 24);
4306 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4307}
4308
7856e3a4
AF		 4309POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4310{
ca5dff0a 4311 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4312 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4313
ca5dff0a 4314 dc->desc = "PowerPC 460F (guessed)";
7856e3a4
AF		 4315 pcc->init_proc = init_proc_460F;
4316 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 4317 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4318 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4319 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4320 PPC_FLOAT_STFIWX | PPC_MFTB |
4321 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4322 PPC_WRTEE | PPC_MFAPIDI |
4323 PPC_CACHE | PPC_CACHE_ICBI |
4324 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4325 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4326 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4327 PPC_440_SPEC;
9df5a466
TM		 4328 pcc->msr_mask = (1ull << MSR_POW) |
4329 (1ull << MSR_CE) |
4330 (1ull << MSR_EE) |
4331 (1ull << MSR_PR) |
4332 (1ull << MSR_FP) |
4333 (1ull << MSR_ME) |
4334 (1ull << MSR_FE0) |
4335 (1ull << MSR_DWE) |
4336 (1ull << MSR_DE) |
4337 (1ull << MSR_FE1) |
4338 (1ull << MSR_IR) |
4339 (1ull << MSR_DR);
ba9fd9f1
AF		 4340 pcc->mmu_model = POWERPC_MMU_BOOKE;
4341 pcc->excp_model = POWERPC_EXCP_BOOKE;
4342 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4343 pcc->bfd_mach = bfd_mach_ppc_403;
4344 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4345 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4346}
4347
80d11f44
JM		 4348static void init_proc_MPC5xx (CPUPPCState *env)
4349{
4350 /* Time base */
4351 gen_tbl(env);
4352 gen_spr_5xx_8xx(env);
4353 gen_spr_5xx(env);
4354 init_excp_MPC5xx(env);
4355 env->dcache_line_size = 32;
4356 env->icache_line_size = 32;
4357 /* XXX: TODO: allocate internal IRQ controller */
4358}
4359
7856e3a4
AF		 4360POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4361{
ca5dff0a 4362 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4363 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4364
ca5dff0a 4365 dc->desc = "Freescale 5xx cores (aka RCPU)";
7856e3a4
AF		 4366 pcc->init_proc = init_proc_MPC5xx;
4367 pcc->check_pow = check_pow_none;
53116ebf
AF		 4368 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4369 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4370 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4371 PPC_MFTB;
9df5a466
TM		 4372 pcc->msr_mask = (1ull << MSR_ILE) |
4373 (1ull << MSR_EE) |
4374 (1ull << MSR_PR) |
4375 (1ull << MSR_FP) |
4376 (1ull << MSR_ME) |
4377 (1ull << MSR_FE0) |
4378 (1ull << MSR_SE) |
4379 (1ull << MSR_DE) |
4380 (1ull << MSR_FE1) |
4381 (1ull << MSR_EP) |
4382 (1ull << MSR_RI) |
4383 (1ull << MSR_LE);
ba9fd9f1
AF		 4384 pcc->mmu_model = POWERPC_MMU_REAL;
4385 pcc->excp_model = POWERPC_EXCP_603;
4386 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4387 pcc->bfd_mach = bfd_mach_ppc_505;
4388 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4389 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4390}
4391
80d11f44
JM		 4392static void init_proc_MPC8xx (CPUPPCState *env)
4393{
4394 /* Time base */
4395 gen_tbl(env);
4396 gen_spr_5xx_8xx(env);
4397 gen_spr_8xx(env);
4398 init_excp_MPC8xx(env);
4399 env->dcache_line_size = 32;
4400 env->icache_line_size = 32;
4401 /* XXX: TODO: allocate internal IRQ controller */
4402}
4403
7856e3a4
AF		 4404POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4405{
ca5dff0a 4406 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4407 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4408
ca5dff0a 4409 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
7856e3a4
AF		 4410 pcc->init_proc = init_proc_MPC8xx;
4411 pcc->check_pow = check_pow_none;
53116ebf
AF		 4412 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4413 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4414 PPC_CACHE_ICBI | PPC_MFTB;
9df5a466
TM		 4415 pcc->msr_mask = (1ull << MSR_ILE) |
4416 (1ull << MSR_EE) |
4417 (1ull << MSR_PR) |
4418 (1ull << MSR_FP) |
4419 (1ull << MSR_ME) |
4420 (1ull << MSR_SE) |
4421 (1ull << MSR_DE) |
4422 (1ull << MSR_EP) |
4423 (1ull << MSR_IR) |
4424 (1ull << MSR_DR) |
4425 (1ull << MSR_RI) |
4426 (1ull << MSR_LE);
ba9fd9f1
AF		 4427 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4428 pcc->excp_model = POWERPC_EXCP_603;
4429 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4430 pcc->bfd_mach = bfd_mach_ppc_860;
4431 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4432 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4433}
4434
80d11f44 4435/* Freescale 82xx cores (aka PowerQUICC-II) */
ca5dff0a 4436
80d11f44 4437static void init_proc_G2 (CPUPPCState *env)
3fc6c082 4438{
80d11f44 4439 gen_spr_ne_601(env);
4f4f28ff 4440 gen_spr_sdr1(env);
80d11f44
JM		 4441 gen_spr_G2_755(env);
4442 gen_spr_G2(env);
a750fc0b
JM		 4443 /* Time base */
4444 gen_tbl(env);
bd928eba
JM		 4445 /* External access control */
4446 /* XXX : not implemented */
4447 spr_register(env, SPR_EAR, "EAR",
4448 SPR_NOACCESS, SPR_NOACCESS,
4449 &spr_read_generic, &spr_write_generic,
4450 0x00000000);
80d11f44
JM		 4451 /* Hardware implementation register */
4452 /* XXX : not implemented */
4453 spr_register(env, SPR_HID0, "HID0",
4454 SPR_NOACCESS, SPR_NOACCESS,
4455 &spr_read_generic, &spr_write_generic,
4456 0x00000000);
4457 /* XXX : not implemented */
4458 spr_register(env, SPR_HID1, "HID1",
4459 SPR_NOACCESS, SPR_NOACCESS,
4460 &spr_read_generic, &spr_write_generic,
4461 0x00000000);
4462 /* XXX : not implemented */
4463 spr_register(env, SPR_HID2, "HID2",
4464 SPR_NOACCESS, SPR_NOACCESS,
4465 &spr_read_generic, &spr_write_generic,
4466 0x00000000);
a750fc0b 4467 /* Memory management */
80d11f44
JM		 4468 gen_low_BATs(env);
4469 gen_high_BATs(env);
4470 gen_6xx_7xx_soft_tlb(env, 64, 2);
4471 init_excp_G2(env);
d63001d1
JM		 4472 env->dcache_line_size = 32;
4473 env->icache_line_size = 32;
80d11f44 4474 /* Allocate hardware IRQ controller */
aa5a9e24 4475 ppc6xx_irq_init(ppc_env_get_cpu(env));
3fc6c082 4476}
a750fc0b 4477
7856e3a4
AF		 4478POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4479{
ca5dff0a 4480 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4481 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4482
ca5dff0a 4483 dc->desc = "PowerPC G2";
7856e3a4
AF		 4484 pcc->init_proc = init_proc_G2;
4485 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4486 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4487 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4488 PPC_FLOAT_STFIWX |
4489 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4490 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4491 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4492 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 4493 pcc->msr_mask = (1ull << MSR_POW) |
4494 (1ull << MSR_TGPR) |
4495 (1ull << MSR_EE) |
4496 (1ull << MSR_PR) |
4497 (1ull << MSR_FP) |
4498 (1ull << MSR_ME) |
4499 (1ull << MSR_FE0) |
4500 (1ull << MSR_SE) |
4501 (1ull << MSR_DE) |
4502 (1ull << MSR_FE1) |
4503 (1ull << MSR_AL) |
4504 (1ull << MSR_EP) |
4505 (1ull << MSR_IR) |
4506 (1ull << MSR_DR) |
4507 (1ull << MSR_RI);
ba9fd9f1
AF		 4508 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4509 pcc->excp_model = POWERPC_EXCP_G2;
4510 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4511 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4512 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4513 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4514}
4515
80d11f44 4516static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4517{
80d11f44 4518 gen_spr_ne_601(env);
4f4f28ff 4519 gen_spr_sdr1(env);
80d11f44
JM		 4520 gen_spr_G2_755(env);
4521 gen_spr_G2(env);
a750fc0b
JM		 4522 /* Time base */
4523 gen_tbl(env);
bd928eba
JM		 4524 /* External access control */
4525 /* XXX : not implemented */
4526 spr_register(env, SPR_EAR, "EAR",
4527 SPR_NOACCESS, SPR_NOACCESS,
4528 &spr_read_generic, &spr_write_generic,
4529 0x00000000);
80d11f44 4530 /* Hardware implementation register */
578bb252 4531 /* XXX : not implemented */
80d11f44 4532 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4533 SPR_NOACCESS, SPR_NOACCESS,
4534 &spr_read_generic, &spr_write_generic,
4535 0x00000000);
80d11f44
JM		 4536 /* XXX : not implemented */
4537 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4538 SPR_NOACCESS, SPR_NOACCESS,
4539 &spr_read_generic, &spr_write_generic,
4540 0x00000000);
578bb252 4541 /* XXX : not implemented */
80d11f44 4542 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4543 SPR_NOACCESS, SPR_NOACCESS,
4544 &spr_read_generic, &spr_write_generic,
4545 0x00000000);
2bc17322 4546
a750fc0b 4547 /* Memory management */
80d11f44
JM		 4548 gen_low_BATs(env);
4549 gen_high_BATs(env);
4550 gen_6xx_7xx_soft_tlb(env, 64, 2);
4551 init_excp_G2(env);
d63001d1
JM		 4552 env->dcache_line_size = 32;
4553 env->icache_line_size = 32;
80d11f44 4554 /* Allocate hardware IRQ controller */
aa5a9e24 4555 ppc6xx_irq_init(ppc_env_get_cpu(env));
3fc6c082
FB		 4556}
4557
7856e3a4
AF		 4558POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4559{
ca5dff0a 4560 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4561 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4562
ca5dff0a 4563 dc->desc = "PowerPC G2LE";
7856e3a4
AF		 4564 pcc->init_proc = init_proc_G2LE;
4565 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4566 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4567 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4568 PPC_FLOAT_STFIWX |
4569 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4570 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4571 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4572 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 4573 pcc->msr_mask = (1ull << MSR_POW) |
4574 (1ull << MSR_TGPR) |
4575 (1ull << MSR_ILE) |
4576 (1ull << MSR_EE) |
4577 (1ull << MSR_PR) |
4578 (1ull << MSR_FP) |
4579 (1ull << MSR_ME) |
4580 (1ull << MSR_FE0) |
4581 (1ull << MSR_SE) |
4582 (1ull << MSR_DE) |
4583 (1ull << MSR_FE1) |
4584 (1ull << MSR_AL) |
4585 (1ull << MSR_EP) |
4586 (1ull << MSR_IR) |
4587 (1ull << MSR_DR) |
4588 (1ull << MSR_RI) |
4589 (1ull << MSR_LE);
ba9fd9f1
AF		 4590 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4591 pcc->excp_model = POWERPC_EXCP_G2;
4592 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4593 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4594 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4595 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4596}
4597
80d11f44 4598static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4599{
e1833e1f
JM		 4600 /* Time base */
4601 gen_tbl(env);
80d11f44 4602 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4603 /* XXX : not implemented */
80d11f44 4604 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4605 &spr_read_spefscr, &spr_write_spefscr,
4606 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4607 0x00000000);
80d11f44 4608 /* Memory management */
01662f3e 4609 gen_spr_BookE206(env, 0x0000005D, NULL);
80d11f44
JM		 4610 /* XXX : not implemented */
4611 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4612 SPR_NOACCESS, SPR_NOACCESS,
4613 &spr_read_generic, &spr_write_generic,
4614 0x00000000);
80d11f44
JM		 4615 /* XXX : not implemented */
4616 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4617 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_generic,
4619 0x00000000);
578bb252 4620 /* XXX : not implemented */
80d11f44 4621 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000);
578bb252 4625 /* XXX : not implemented */
80d11f44
JM		 4626 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4627 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4628 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4629 0x00000000);
4630 /* XXX : not implemented */
4631 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4632 SPR_NOACCESS, SPR_NOACCESS,
4633 &spr_read_generic, &spr_write_generic,
4634 0x00000000);
4635 /* XXX : not implemented */
4636 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4637 SPR_NOACCESS, SPR_NOACCESS,
4638 &spr_read_generic, &spr_write_generic,
4639 0x00000000);
4640 /* XXX : not implemented */
4641 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4642 SPR_NOACCESS, SPR_NOACCESS,
4643 &spr_read_generic, &spr_write_generic,
4644 0x00000000);
4645 /* XXX : not implemented */
4646 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
deb05c4c
AG		 4647 &spr_read_generic, SPR_NOACCESS,
4648 &spr_read_generic, SPR_NOACCESS,
80d11f44
JM		 4649 0x00000000);
4650 /* XXX : not implemented */
4651 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4652 SPR_NOACCESS, SPR_NOACCESS,
4653 &spr_read_generic, &spr_write_generic,
4654 0x00000000);
4655 /* XXX : not implemented */
4656 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4657 SPR_NOACCESS, SPR_NOACCESS,
4658 &spr_read_generic, &spr_write_generic,
4659 0x00000000);
4660 /* XXX : not implemented */
4661 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4662 SPR_NOACCESS, SPR_NOACCESS,
4663 &spr_read_generic, &spr_write_generic,
4664 0x00000000);
4665 /* XXX : not implemented */
4666 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4667 SPR_NOACCESS, SPR_NOACCESS,
4668 &spr_read_generic, &spr_write_generic,
4669 0x00000000);
4670 /* XXX : not implemented */
4671 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4672 SPR_NOACCESS, SPR_NOACCESS,
4673 &spr_read_generic, &spr_write_generic,
4674 0x00000000);
4675 /* XXX : not implemented */
4676 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4677 SPR_NOACCESS, SPR_NOACCESS,
4678 &spr_read_generic, &spr_write_generic,
4679 0x00000000);
01662f3e
AG		 4680 /* XXX : not implemented */
4681 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4682 SPR_NOACCESS, SPR_NOACCESS,
4683 &spr_read_generic, &spr_write_generic,
4684 0x00000000); /* TOFIX */
80d11f44
JM		 4685 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4686 SPR_NOACCESS, SPR_NOACCESS,
4687 &spr_read_generic, &spr_write_generic,
4688 0x00000000);
4689 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4690 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4691 &spr_read_generic, &spr_write_generic,
4692 0x00000000);
f2e63a42 4693#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4694 env->nb_tlb = 64;
4695 env->nb_ways = 1;
4696 env->id_tlbs = 0;
1c53accc 4697 env->tlb_type = TLB_EMB;
f2e63a42 4698#endif
e9cd84b9 4699 init_excp_e200(env, 0xFFFF0000UL);
d63001d1
JM		 4700 env->dcache_line_size = 32;
4701 env->icache_line_size = 32;
e1833e1f 4702 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4703}
a750fc0b 4704
7856e3a4
AF		 4705POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4706{
ca5dff0a 4707 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4708 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4709
ca5dff0a 4710 dc->desc = "e200 core";
7856e3a4
AF		 4711 pcc->init_proc = init_proc_e200;
4712 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4713 /* XXX: unimplemented instructions:
4714 * dcblc
4715 * dcbtlst
4716 * dcbtstls
4717 * icblc
4718 * icbtls
4719 * tlbivax
4720 * all SPE multiply-accumulate instructions
4721 */
4722 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4723 PPC_SPE | PPC_SPE_SINGLE |
4724 PPC_WRTEE | PPC_RFDI |
4725 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4726 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4727 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4728 PPC_BOOKE;
9df5a466
TM		 4729 pcc->msr_mask = (1ull << MSR_UCLE) |
4730 (1ull << MSR_SPE) |
4731 (1ull << MSR_POW) |
4732 (1ull << MSR_CE) |
4733 (1ull << MSR_EE) |
4734 (1ull << MSR_PR) |
4735 (1ull << MSR_FP) |
4736 (1ull << MSR_ME) |
4737 (1ull << MSR_FE0) |
4738 (1ull << MSR_DWE) |
4739 (1ull << MSR_DE) |
4740 (1ull << MSR_FE1) |
4741 (1ull << MSR_IR) |
4742 (1ull << MSR_DR);
ba9fd9f1
AF		 4743 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4744 pcc->excp_model = POWERPC_EXCP_BOOKE;
4745 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4746 pcc->bfd_mach = bfd_mach_ppc_860;
4747 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4748 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4749 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4750}
4751
80d11f44 4752static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4753{
80d11f44 4754 gen_spr_ne_601(env);
4f4f28ff 4755 gen_spr_sdr1(env);
80d11f44 4756 gen_spr_603(env);
a750fc0b
JM		 4757 /* Time base */
4758 gen_tbl(env);
80d11f44
JM		 4759 /* hardware implementation registers */
4760 /* XXX : not implemented */
4761 spr_register(env, SPR_HID0, "HID0",
4762 SPR_NOACCESS, SPR_NOACCESS,
4763 &spr_read_generic, &spr_write_generic,
4764 0x00000000);
4765 /* XXX : not implemented */
4766 spr_register(env, SPR_HID1, "HID1",
4767 SPR_NOACCESS, SPR_NOACCESS,
4768 &spr_read_generic, &spr_write_generic,
4769 0x00000000);
8daf1781
TM		 4770 /* XXX : not implemented */
4771 spr_register(env, SPR_HID2, "HID2",
4772 SPR_NOACCESS, SPR_NOACCESS,
4773 &spr_read_generic, &spr_write_generic,
4774 0x00000000);
3ade1a05
FC		 4775 /* Breakpoints */
4776 /* XXX : not implemented */
4777 spr_register(env, SPR_DABR, "DABR",
4778 SPR_NOACCESS, SPR_NOACCESS,
4779 &spr_read_generic, &spr_write_generic,
4780 0x00000000);
4781 /* XXX : not implemented */
4782 spr_register(env, SPR_DABR2, "DABR2",
4783 SPR_NOACCESS, SPR_NOACCESS,
4784 &spr_read_generic, &spr_write_generic,
4785 0x00000000);
4786 /* XXX : not implemented */
4787 spr_register(env, SPR_IABR2, "IABR2",
4788 SPR_NOACCESS, SPR_NOACCESS,
4789 &spr_read_generic, &spr_write_generic,
4790 0x00000000);
4791 /* XXX : not implemented */
4792 spr_register(env, SPR_IBCR, "IBCR",
4793 SPR_NOACCESS, SPR_NOACCESS,
4794 &spr_read_generic, &spr_write_generic,
4795 0x00000000);
4796 /* XXX : not implemented */
4797 spr_register(env, SPR_DBCR, "DBCR",
4798 SPR_NOACCESS, SPR_NOACCESS,
4799 &spr_read_generic, &spr_write_generic,
4800 0x00000000);
80d11f44
JM		 4801 /* Memory management */
4802 gen_low_BATs(env);
8daf1781 4803 gen_high_BATs(env);
80d11f44
JM		 4804 gen_6xx_7xx_soft_tlb(env, 64, 2);
4805 init_excp_603(env);
4806 env->dcache_line_size = 32;
4807 env->icache_line_size = 32;
4808 /* Allocate hardware IRQ controller */
aa5a9e24 4809 ppc6xx_irq_init(ppc_env_get_cpu(env));
80d11f44
JM		 4810}
4811
7856e3a4
AF		 4812POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4813{
ca5dff0a 4814 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4815 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4816
ca5dff0a 4817 dc->desc = "e300 core";
7856e3a4
AF		 4818 pcc->init_proc = init_proc_e300;
4819 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4820 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4821 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4822 PPC_FLOAT_STFIWX |
4823 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4824 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4825 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4826 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 4827 pcc->msr_mask = (1ull << MSR_POW) |
4828 (1ull << MSR_TGPR) |
4829 (1ull << MSR_ILE) |
4830 (1ull << MSR_EE) |
4831 (1ull << MSR_PR) |
4832 (1ull << MSR_FP) |
4833 (1ull << MSR_ME) |
4834 (1ull << MSR_FE0) |
4835 (1ull << MSR_SE) |
4836 (1ull << MSR_DE) |
4837 (1ull << MSR_FE1) |
4838 (1ull << MSR_AL) |
4839 (1ull << MSR_EP) |
4840 (1ull << MSR_IR) |
4841 (1ull << MSR_DR) |
4842 (1ull << MSR_RI) |
4843 (1ull << MSR_LE);
ba9fd9f1
AF		 4844 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4845 pcc->excp_model = POWERPC_EXCP_603;
4846 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4847 pcc->bfd_mach = bfd_mach_ppc_603;
4848 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4849 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4850}
4851
b81ccf8a 4852#if !defined(CONFIG_USER_ONLY)
69b058c8 4853static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
b81ccf8a
AG		 4854{
4855 TCGv val = tcg_temp_new();
4856 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4857 gen_store_spr(SPR_BOOKE_MAS3, val);
cfee0218 4858 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
b81ccf8a
AG		 4859 gen_store_spr(SPR_BOOKE_MAS7, val);
4860 tcg_temp_free(val);
4861}
4862
69b058c8 4863static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
b81ccf8a
AG		 4864{
4865 TCGv mas7 = tcg_temp_new();
4866 TCGv mas3 = tcg_temp_new();
4867 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4868 tcg_gen_shli_tl(mas7, mas7, 32);
4869 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4870 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4871 tcg_temp_free(mas3);
4872 tcg_temp_free(mas7);
4873}
4874
b81ccf8a
AG		 4875#endif
4876
f7aa5583
VS		 4877enum fsl_e500_version {
4878 fsl_e500v1,
4879 fsl_e500v2,
4880 fsl_e500mc,
b81ccf8a 4881 fsl_e5500,
f7aa5583
VS		 4882};
4883
01662f3e 4884static void init_proc_e500 (CPUPPCState *env, int version)
80d11f44 4885{
a47dddd7 4886 PowerPCCPU *cpu = ppc_env_get_cpu(env);
01662f3e 4887 uint32_t tlbncfg[2];
b81ccf8a 4888 uint64_t ivor_mask;
e9cd84b9 4889 uint64_t ivpr_mask = 0xFFFF0000ULL;
a496e8ee
AG		 4890 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4891 | 0x0020; /* 32 kb */
d2ea2bf7
AG		 4892 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4893 | 0x0020; /* 32 kb */
01662f3e
AG		 4894#if !defined(CONFIG_USER_ONLY)
4895 int i;
4896#endif
4897
80d11f44
JM		 4898 /* Time base */
4899 gen_tbl(env);
01662f3e
AG		 4900 /*
4901 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4902 * complain when accessing them.
4903 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4904 */
b81ccf8a
AG		 4905 switch (version) {
4906 case fsl_e500v1:
4907 case fsl_e500v2:
4908 default:
4909 ivor_mask = 0x0000000F0000FFFFULL;
4910 break;
4911 case fsl_e500mc:
4912 case fsl_e5500:
4913 ivor_mask = 0x000003FE0000FFFFULL;
4914 break;
2c9732db
AG		 4915 }
4916 gen_spr_BookE(env, ivor_mask);
80d11f44
JM		 4917 /* Processor identification */
4918 spr_register(env, SPR_BOOKE_PIR, "PIR",
4919 SPR_NOACCESS, SPR_NOACCESS,
4920 &spr_read_generic, &spr_write_pir,
4921 0x00000000);
4922 /* XXX : not implemented */
4923 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4924 &spr_read_spefscr, &spr_write_spefscr,
4925 &spr_read_spefscr, &spr_write_spefscr,
80d11f44 4926 0x00000000);
892c587f 4927#if !defined(CONFIG_USER_ONLY)
80d11f44 4928 /* Memory management */
80d11f44 4929 env->nb_pids = 3;
01662f3e
AG		 4930 env->nb_ways = 2;
4931 env->id_tlbs = 0;
4932 switch (version) {
f7aa5583 4933 case fsl_e500v1:
01662f3e
AG		 4934 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4935 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4936 break;
f7aa5583 4937 case fsl_e500v2:
01662f3e
AG		 4938 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4939 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
f7aa5583
VS		 4940 break;
4941 case fsl_e500mc:
b81ccf8a 4942 case fsl_e5500:
f7aa5583
VS		 4943 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4944 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
892c587f
AG		 4945 break;
4946 default:
a47dddd7 4947 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
892c587f
AG		 4948 }
4949#endif
4950 /* Cache sizes */
4951 switch (version) {
4952 case fsl_e500v1:
4953 case fsl_e500v2:
4954 env->dcache_line_size = 32;
4955 env->icache_line_size = 32;
4956 break;
4957 case fsl_e500mc:
b81ccf8a 4958 case fsl_e5500:
f7aa5583
VS		 4959 env->dcache_line_size = 64;
4960 env->icache_line_size = 64;
a496e8ee 4961 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
d2ea2bf7 4962 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
01662f3e
AG		 4963 break;
4964 default:
a47dddd7 4965 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
01662f3e 4966 }
01662f3e 4967 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
80d11f44
JM		 4968 /* XXX : not implemented */
4969 spr_register(env, SPR_HID0, "HID0",
4970 SPR_NOACCESS, SPR_NOACCESS,
4971 &spr_read_generic, &spr_write_generic,
4972 0x00000000);
4973 /* XXX : not implemented */
4974 spr_register(env, SPR_HID1, "HID1",
4975 SPR_NOACCESS, SPR_NOACCESS,
4976 &spr_read_generic, &spr_write_generic,
4977 0x00000000);
4978 /* XXX : not implemented */
4979 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4980 SPR_NOACCESS, SPR_NOACCESS,
4981 &spr_read_generic, &spr_write_generic,
4982 0x00000000);
4983 /* XXX : not implemented */
4984 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4985 SPR_NOACCESS, SPR_NOACCESS,
4986 &spr_read_generic, &spr_write_generic,
4987 0x00000000);
4988 /* XXX : not implemented */
4989 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4990 SPR_NOACCESS, SPR_NOACCESS,
4991 &spr_read_generic, &spr_write_generic,
4992 0x00000000);
578bb252 4993 /* XXX : not implemented */
a750fc0b
JM		 4994 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4995 SPR_NOACCESS, SPR_NOACCESS,
4996 &spr_read_generic, &spr_write_generic,
4997 0x00000000);
80d11f44
JM		 4998 /* XXX : not implemented */
4999 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 5000 SPR_NOACCESS, SPR_NOACCESS,
5001 &spr_read_generic, &spr_write_generic,
5002 0x00000000);
80d11f44
JM		 5003 /* XXX : not implemented */
5004 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 5005 SPR_NOACCESS, SPR_NOACCESS,
5006 &spr_read_generic, &spr_write_generic,
5007 0x00000000);
578bb252 5008 /* XXX : not implemented */
80d11f44 5009 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
deb05c4c
AG		 5010 &spr_read_generic, SPR_NOACCESS,
5011 &spr_read_generic, SPR_NOACCESS,
a496e8ee 5012 l1cfg0);
d2ea2bf7
AG		 5013 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
5014 &spr_read_generic, SPR_NOACCESS,
5015 &spr_read_generic, SPR_NOACCESS,
5016 l1cfg1);
80d11f44
JM		 5017 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
5018 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 5019 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44 5020 0x00000000);
80d11f44
JM		 5021 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
5022 SPR_NOACCESS, SPR_NOACCESS,
ea71258d 5023 &spr_read_generic, &spr_write_e500_l1csr1,
80d11f44 5024 0x00000000);
80d11f44
JM		 5025 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
5026 SPR_NOACCESS, SPR_NOACCESS,
5027 &spr_read_generic, &spr_write_generic,
5028 0x00000000);
5029 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
5030 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 5031 &spr_read_generic, &spr_write_generic,
5032 0x00000000);
01662f3e
AG		 5033 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5034 SPR_NOACCESS, SPR_NOACCESS,
5035 &spr_read_generic, &spr_write_booke206_mmucsr0,
5036 0x00000000);
b81ccf8a
AG		 5037 spr_register(env, SPR_BOOKE_EPR, "EPR",
5038 SPR_NOACCESS, SPR_NOACCESS,
68c2dd70 5039 &spr_read_generic, SPR_NOACCESS,
b81ccf8a
AG		 5040 0x00000000);
5041 /* XXX better abstract into Emb.xxx features */
5042 if (version == fsl_e5500) {
5043 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
5044 SPR_NOACCESS, SPR_NOACCESS,
5045 &spr_read_generic, &spr_write_generic,
5046 0x00000000);
5047 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
5048 SPR_NOACCESS, SPR_NOACCESS,
5049 &spr_read_mas73, &spr_write_mas73,
5050 0x00000000);
5051 ivpr_mask = (target_ulong)~0xFFFFULL;
5052 }
01662f3e 5053
f2e63a42 5054#if !defined(CONFIG_USER_ONLY)
01662f3e 5055 env->nb_tlb = 0;
1c53accc 5056 env->tlb_type = TLB_MAS;
01662f3e
AG		 5057 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
5058 env->nb_tlb += booke206_tlb_size(env, i);
5059 }
f2e63a42 5060#endif
01662f3e 5061
e9cd84b9 5062 init_excp_e200(env, ivpr_mask);
9fdc60bf 5063 /* Allocate hardware IRQ controller */
aa5a9e24 5064 ppce500_irq_init(ppc_env_get_cpu(env));
3fc6c082 5065}
a750fc0b 5066
01662f3e
AG		 5067static void init_proc_e500v1(CPUPPCState *env)
5068{
f7aa5583 5069 init_proc_e500(env, fsl_e500v1);
01662f3e
AG		 5070}
5071
7856e3a4
AF		 5072POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
5073{
ca5dff0a 5074 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5075 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5076
ca5dff0a 5077 dc->desc = "e500v1 core";
7856e3a4
AF		 5078 pcc->init_proc = init_proc_e500v1;
5079 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5080 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5081 PPC_SPE | PPC_SPE_SINGLE |
5082 PPC_WRTEE | PPC_RFDI |
5083 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5084 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5085 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5086 pcc->insns_flags2 = PPC2_BOOKE206;
9df5a466
TM		 5087 pcc->msr_mask = (1ull << MSR_UCLE) |
5088 (1ull << MSR_SPE) |
5089 (1ull << MSR_POW) |
5090 (1ull << MSR_CE) |
5091 (1ull << MSR_EE) |
5092 (1ull << MSR_PR) |
5093 (1ull << MSR_FP) |
5094 (1ull << MSR_ME) |
5095 (1ull << MSR_FE0) |
5096 (1ull << MSR_DWE) |
5097 (1ull << MSR_DE) |
5098 (1ull << MSR_FE1) |
5099 (1ull << MSR_IR) |
5100 (1ull << MSR_DR);
ba9fd9f1
AF		 5101 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5102 pcc->excp_model = POWERPC_EXCP_BOOKE;
5103 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5104 pcc->bfd_mach = bfd_mach_ppc_860;
5105 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5106 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5107 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5108}
5109
01662f3e
AG		 5110static void init_proc_e500v2(CPUPPCState *env)
5111{
f7aa5583
VS		 5112 init_proc_e500(env, fsl_e500v2);
5113}
5114
7856e3a4
AF		 5115POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5116{
ca5dff0a 5117 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5118 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5119
ca5dff0a 5120 dc->desc = "e500v2 core";
7856e3a4
AF		 5121 pcc->init_proc = init_proc_e500v2;
5122 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5123 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5124 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5125 PPC_WRTEE | PPC_RFDI |
5126 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5127 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5128 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5129 pcc->insns_flags2 = PPC2_BOOKE206;
9df5a466
TM		 5130 pcc->msr_mask = (1ull << MSR_UCLE) |
5131 (1ull << MSR_SPE) |
5132 (1ull << MSR_POW) |
5133 (1ull << MSR_CE) |
5134 (1ull << MSR_EE) |
5135 (1ull << MSR_PR) |
5136 (1ull << MSR_FP) |
5137 (1ull << MSR_ME) |
5138 (1ull << MSR_FE0) |
5139 (1ull << MSR_DWE) |
5140 (1ull << MSR_DE) |
5141 (1ull << MSR_FE1) |
5142 (1ull << MSR_IR) |
5143 (1ull << MSR_DR);
ba9fd9f1
AF		 5144 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5145 pcc->excp_model = POWERPC_EXCP_BOOKE;
5146 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5147 pcc->bfd_mach = bfd_mach_ppc_860;
5148 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5149 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5150 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5151}
5152
f7aa5583
VS		 5153static void init_proc_e500mc(CPUPPCState *env)
5154{
5155 init_proc_e500(env, fsl_e500mc);
01662f3e
AG		 5156}
5157
7856e3a4
AF		 5158POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5159{
ca5dff0a 5160 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5161 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5162
ca5dff0a 5163 dc->desc = "e500mc core";
7856e3a4
AF		 5164 pcc->init_proc = init_proc_e500mc;
5165 pcc->check_pow = check_pow_none;
2fff4bad 5166 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
53116ebf
AF		 5167 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5168 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5169 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5170 PPC_FLOAT | PPC_FLOAT_FRES |
5171 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5172 PPC_FLOAT_STFIWX | PPC_WAIT |
5173 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5174 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
9df5a466
TM		 5175 pcc->msr_mask = (1ull << MSR_GS) |
5176 (1ull << MSR_UCLE) |
5177 (1ull << MSR_CE) |
5178 (1ull << MSR_EE) |
5179 (1ull << MSR_PR) |
5180 (1ull << MSR_FP) |
5181 (1ull << MSR_ME) |
5182 (1ull << MSR_FE0) |
5183 (1ull << MSR_DE) |
5184 (1ull << MSR_FE1) |
5185 (1ull << MSR_IR) |
5186 (1ull << MSR_DR) |
5187 (1ull << MSR_PX) |
5188 (1ull << MSR_RI);
ba9fd9f1
AF		 5189 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5190 pcc->excp_model = POWERPC_EXCP_BOOKE;
5191 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5192 /* FIXME: figure out the correct flag for e500mc */
5193 pcc->bfd_mach = bfd_mach_ppc_e500;
5194 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5195 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5196}
5197
b81ccf8a
AG		 5198#ifdef TARGET_PPC64
5199static void init_proc_e5500(CPUPPCState *env)
5200{
5201 init_proc_e500(env, fsl_e5500);
5202}
7856e3a4
AF		 5203
5204POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5205{
ca5dff0a 5206 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5207 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5208
ca5dff0a 5209 dc->desc = "e5500 core";
7856e3a4
AF		 5210 pcc->init_proc = init_proc_e5500;
5211 pcc->check_pow = check_pow_none;
2fff4bad 5212 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
53116ebf
AF		 5213 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5214 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5215 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5216 PPC_FLOAT | PPC_FLOAT_FRES |
5217 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5218 PPC_FLOAT_STFIWX | PPC_WAIT |
5219 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5220 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4171853c
PM		 5221 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5222 PPC2_FP_CVT_S64;
9df5a466
TM		 5223 pcc->msr_mask = (1ull << MSR_CM) |
5224 (1ull << MSR_GS) |
5225 (1ull << MSR_UCLE) |
5226 (1ull << MSR_CE) |
5227 (1ull << MSR_EE) |
5228 (1ull << MSR_PR) |
5229 (1ull << MSR_FP) |
5230 (1ull << MSR_ME) |
5231 (1ull << MSR_FE0) |
5232 (1ull << MSR_DE) |
5233 (1ull << MSR_FE1) |
5234 (1ull << MSR_IR) |
5235 (1ull << MSR_DR) |
5236 (1ull << MSR_PX) |
5237 (1ull << MSR_RI);
ba9fd9f1
AF		 5238 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5239 pcc->excp_model = POWERPC_EXCP_BOOKE;
5240 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5241 /* FIXME: figure out the correct flag for e5500 */
5242 pcc->bfd_mach = bfd_mach_ppc_e500;
5243 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5244 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4 5245}
b81ccf8a
AG		 5246#endif
5247
a750fc0b 5248/* Non-embedded PowerPC */
a750fc0b 5249
082c6681 5250#define POWERPC_MSRR_601 (0x0000000000001040ULL)
a750fc0b
JM		 5251
5252static void init_proc_601 (CPUPPCState *env)
3fc6c082 5253{
a750fc0b 5254 gen_spr_ne_601(env);
4f4f28ff 5255 gen_spr_sdr1(env);
a750fc0b
JM		 5256 gen_spr_601(env);
5257 /* Hardware implementation registers */
5258 /* XXX : not implemented */
5259 spr_register(env, SPR_HID0, "HID0",
5260 SPR_NOACCESS, SPR_NOACCESS,
056401ea 5261 &spr_read_generic, &spr_write_hid0_601,
faadf50e 5262 0x80010080);
a750fc0b
JM		 5263 /* XXX : not implemented */
5264 spr_register(env, SPR_HID1, "HID1",
5265 SPR_NOACCESS, SPR_NOACCESS,
5266 &spr_read_generic, &spr_write_generic,
5267 0x00000000);
5268 /* XXX : not implemented */
5269 spr_register(env, SPR_601_HID2, "HID2",
5270 SPR_NOACCESS, SPR_NOACCESS,
5271 &spr_read_generic, &spr_write_generic,
5272 0x00000000);
5273 /* XXX : not implemented */
5274 spr_register(env, SPR_601_HID5, "HID5",
5275 SPR_NOACCESS, SPR_NOACCESS,
5276 &spr_read_generic, &spr_write_generic,
5277 0x00000000);
a750fc0b 5278 /* Memory management */
e1833e1f 5279 init_excp_601(env);
082c6681
JM		 5280 /* XXX: beware that dcache line size is 64
5281 * but dcbz uses 32 bytes "sectors"
5282 * XXX: this breaks clcs instruction !
5283 */
5284 env->dcache_line_size = 32;
d63001d1 5285 env->icache_line_size = 64;
faadf50e 5286 /* Allocate hardware IRQ controller */
aa5a9e24 5287 ppc6xx_irq_init(ppc_env_get_cpu(env));
3fc6c082
FB		 5288}
5289
7856e3a4
AF		 5290POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5291{
ca5dff0a 5292 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5293 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5294
ca5dff0a 5295 dc->desc = "PowerPC 601";
7856e3a4
AF		 5296 pcc->init_proc = init_proc_601;
5297 pcc->check_pow = check_pow_none;
53116ebf
AF		 5298 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5299 PPC_FLOAT |
5300 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5301 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5302 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 5303 pcc->msr_mask = (1ull << MSR_EE) |
5304 (1ull << MSR_PR) |
5305 (1ull << MSR_FP) |
5306 (1ull << MSR_ME) |
5307 (1ull << MSR_FE0) |
5308 (1ull << MSR_SE) |
5309 (1ull << MSR_FE1) |
5310 (1ull << MSR_EP) |
5311 (1ull << MSR_IR) |
5312 (1ull << MSR_DR);
ba9fd9f1 5313 pcc->mmu_model = POWERPC_MMU_601;
b632a148
DG		 5314#if defined(CONFIG_SOFTMMU)
5315 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5316#endif
ba9fd9f1
AF		 5317 pcc->excp_model = POWERPC_EXCP_601;
5318 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5319 pcc->bfd_mach = bfd_mach_ppc_601;
5320 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
7856e3a4
AF		 5321}
5322
082c6681 5323#define POWERPC_MSRR_601v (0x0000000000001040ULL)
082c6681
JM		 5324
5325static void init_proc_601v (CPUPPCState *env)
5326{
5327 init_proc_601(env);
5328 /* XXX : not implemented */
5329 spr_register(env, SPR_601_HID15, "HID15",
5330 SPR_NOACCESS, SPR_NOACCESS,
5331 &spr_read_generic, &spr_write_generic,
5332 0x00000000);
5333}
5334
7856e3a4
AF		 5335POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5336{
ca5dff0a 5337 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5338 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5339
ca5dff0a 5340 dc->desc = "PowerPC 601v";
7856e3a4
AF		 5341 pcc->init_proc = init_proc_601v;
5342 pcc->check_pow = check_pow_none;
53116ebf
AF		 5343 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5344 PPC_FLOAT |
5345 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5346 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5347 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 5348 pcc->msr_mask = (1ull << MSR_EE) |
5349 (1ull << MSR_PR) |
5350 (1ull << MSR_FP) |
5351 (1ull << MSR_ME) |
5352 (1ull << MSR_FE0) |
5353 (1ull << MSR_SE) |
5354 (1ull << MSR_FE1) |
5355 (1ull << MSR_EP) |
5356 (1ull << MSR_IR) |
5357 (1ull << MSR_DR);
ba9fd9f1 5358 pcc->mmu_model = POWERPC_MMU_601;
b632a148
DG		 5359#if defined(CONFIG_SOFTMMU)
5360 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5361#endif
ba9fd9f1
AF		 5362 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5363 pcc->bfd_mach = bfd_mach_ppc_601;
5364 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
7856e3a4
AF		 5365}
5366
a750fc0b 5367static void init_proc_602 (CPUPPCState *env)
3fc6c082 5368{
a750fc0b 5369 gen_spr_ne_601(env);
4f4f28ff 5370 gen_spr_sdr1(env);
a750fc0b
JM		 5371 gen_spr_602(env);
5372 /* Time base */
5373 gen_tbl(env);
5374 /* hardware implementation registers */
5375 /* XXX : not implemented */
5376 spr_register(env, SPR_HID0, "HID0",
5377 SPR_NOACCESS, SPR_NOACCESS,
5378 &spr_read_generic, &spr_write_generic,
5379 0x00000000);
5380 /* XXX : not implemented */
5381 spr_register(env, SPR_HID1, "HID1",
5382 SPR_NOACCESS, SPR_NOACCESS,
5383 &spr_read_generic, &spr_write_generic,
5384 0x00000000);
5385 /* Memory management */
5386 gen_low_BATs(env);
5387 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5388 init_excp_602(env);
d63001d1
JM		 5389 env->dcache_line_size = 32;
5390 env->icache_line_size = 32;
a750fc0b 5391 /* Allocate hardware IRQ controller */
aa5a9e24 5392 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b 5393}
3fc6c082 5394
7856e3a4
AF		 5395POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5396{
ca5dff0a 5397 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5398 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5399
ca5dff0a 5400 dc->desc = "PowerPC 602";
7856e3a4
AF		 5401 pcc->init_proc = init_proc_602;
5402 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5403 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5404 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5405 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5406 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5407 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5408 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5409 PPC_SEGMENT | PPC_602_SPEC;
9df5a466
TM		 5410 pcc->msr_mask = (1ull << MSR_VSX) |
5411 (1ull << MSR_SA) |
5412 (1ull << MSR_POW) |
5413 (1ull << MSR_TGPR) |
5414 (1ull << MSR_ILE) |
5415 (1ull << MSR_EE) |
5416 (1ull << MSR_PR) |
5417 (1ull << MSR_FP) |
5418 (1ull << MSR_ME) |
5419 (1ull << MSR_FE0) |
5420 (1ull << MSR_SE) |
5421 (1ull << MSR_DE) |
5422 (1ull << MSR_FE1) |
5423 (1ull << MSR_EP) |
5424 (1ull << MSR_IR) |
5425 (1ull << MSR_DR) |
5426 (1ull << MSR_RI) |
5427 (1ull << MSR_LE);
ba9fd9f1
AF		 5428 /* XXX: 602 MMU is quite specific. Should add a special case */
5429 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5430 pcc->excp_model = POWERPC_EXCP_602;
5431 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5432 pcc->bfd_mach = bfd_mach_ppc_602;
5433 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5434 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5435}
5436
a750fc0b
JM		 5437static void init_proc_603 (CPUPPCState *env)
5438{
5439 gen_spr_ne_601(env);
4f4f28ff 5440 gen_spr_sdr1(env);
a750fc0b
JM		 5441 gen_spr_603(env);
5442 /* Time base */
5443 gen_tbl(env);
5444 /* hardware implementation registers */
5445 /* XXX : not implemented */
5446 spr_register(env, SPR_HID0, "HID0",
5447 SPR_NOACCESS, SPR_NOACCESS,
5448 &spr_read_generic, &spr_write_generic,
5449 0x00000000);
5450 /* XXX : not implemented */
5451 spr_register(env, SPR_HID1, "HID1",
5452 SPR_NOACCESS, SPR_NOACCESS,
5453 &spr_read_generic, &spr_write_generic,
5454 0x00000000);
5455 /* Memory management */
5456 gen_low_BATs(env);
5457 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5458 init_excp_603(env);
d63001d1
JM		 5459 env->dcache_line_size = 32;
5460 env->icache_line_size = 32;
a750fc0b 5461 /* Allocate hardware IRQ controller */
aa5a9e24 5462 ppc6xx_irq_init(ppc_env_get_cpu(env));
3fc6c082
FB		 5463}
5464
7856e3a4
AF		 5465POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5466{
ca5dff0a 5467 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5468 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5469
ca5dff0a 5470 dc->desc = "PowerPC 603";
7856e3a4
AF		 5471 pcc->init_proc = init_proc_603;
5472 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5473 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5474 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5475 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5476 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5477 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5478 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5479 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 5480 pcc->msr_mask = (1ull << MSR_POW) |
5481 (1ull << MSR_TGPR) |
5482 (1ull << MSR_ILE) |
5483 (1ull << MSR_EE) |
5484 (1ull << MSR_PR) |
5485 (1ull << MSR_FP) |
5486 (1ull << MSR_ME) |
5487 (1ull << MSR_FE0) |
5488 (1ull << MSR_SE) |
5489 (1ull << MSR_DE) |
5490 (1ull << MSR_FE1) |
5491 (1ull << MSR_EP) |
5492 (1ull << MSR_IR) |
5493 (1ull << MSR_DR) |
5494 (1ull << MSR_RI) |
5495 (1ull << MSR_LE);
ba9fd9f1
AF		 5496 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5497 pcc->excp_model = POWERPC_EXCP_603;
5498 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5499 pcc->bfd_mach = bfd_mach_ppc_603;
5500 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5501 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5502}
5503
a750fc0b
JM		 5504static void init_proc_603E (CPUPPCState *env)
5505{
5506 gen_spr_ne_601(env);
4f4f28ff 5507 gen_spr_sdr1(env);
a750fc0b
JM		 5508 gen_spr_603(env);
5509 /* Time base */
5510 gen_tbl(env);
5511 /* hardware implementation registers */
5512 /* XXX : not implemented */
5513 spr_register(env, SPR_HID0, "HID0",
5514 SPR_NOACCESS, SPR_NOACCESS,
5515 &spr_read_generic, &spr_write_generic,
5516 0x00000000);
5517 /* XXX : not implemented */
5518 spr_register(env, SPR_HID1, "HID1",
5519 SPR_NOACCESS, SPR_NOACCESS,
5520 &spr_read_generic, &spr_write_generic,
5521 0x00000000);
a750fc0b
JM		 5522 /* Memory management */
5523 gen_low_BATs(env);
5524 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5525 init_excp_603(env);
d63001d1
JM		 5526 env->dcache_line_size = 32;
5527 env->icache_line_size = 32;
a750fc0b 5528 /* Allocate hardware IRQ controller */
aa5a9e24 5529 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b
JM		 5530}
5531
7856e3a4
AF		 5532POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5533{
ca5dff0a 5534 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5535 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5536
ca5dff0a 5537 dc->desc = "PowerPC 603e";
7856e3a4
AF		 5538 pcc->init_proc = init_proc_603E;
5539 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5540 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5541 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5542 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5543 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5544 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5545 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5546 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 5547 pcc->msr_mask = (1ull << MSR_POW) |
5548 (1ull << MSR_TGPR) |
5549 (1ull << MSR_ILE) |
5550 (1ull << MSR_EE) |
5551 (1ull << MSR_PR) |
5552 (1ull << MSR_FP) |
5553 (1ull << MSR_ME) |
5554 (1ull << MSR_FE0) |
5555 (1ull << MSR_SE) |
5556 (1ull << MSR_DE) |
5557 (1ull << MSR_FE1) |
5558 (1ull << MSR_EP) |
5559 (1ull << MSR_IR) |
5560 (1ull << MSR_DR) |
5561 (1ull << MSR_RI) |
5562 (1ull << MSR_LE);
ba9fd9f1
AF		 5563 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5564 pcc->excp_model = POWERPC_EXCP_603E;
5565 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5566 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5567 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5568 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5569}
5570
a750fc0b
JM		 5571static void init_proc_604 (CPUPPCState *env)
5572{
5573 gen_spr_ne_601(env);
4f4f28ff 5574 gen_spr_sdr1(env);
a750fc0b
JM		 5575 gen_spr_604(env);
5576 /* Time base */
5577 gen_tbl(env);
5578 /* Hardware implementation registers */
5579 /* XXX : not implemented */
082c6681
JM		 5580 spr_register(env, SPR_HID0, "HID0",
5581 SPR_NOACCESS, SPR_NOACCESS,
5582 &spr_read_generic, &spr_write_generic,
5583 0x00000000);
5584 /* Memory management */
5585 gen_low_BATs(env);
5586 init_excp_604(env);
5587 env->dcache_line_size = 32;
5588 env->icache_line_size = 32;
5589 /* Allocate hardware IRQ controller */
aa5a9e24 5590 ppc6xx_irq_init(ppc_env_get_cpu(env));
082c6681
JM		 5591}
5592
7856e3a4
AF		 5593POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5594{
ca5dff0a 5595 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5596 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5597
ca5dff0a 5598 dc->desc = "PowerPC 604";
7856e3a4
AF		 5599 pcc->init_proc = init_proc_604;
5600 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 5601 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5602 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5603 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5604 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5605 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5606 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5607 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 5608 pcc->msr_mask = (1ull << MSR_POW) |
5609 (1ull << MSR_ILE) |
5610 (1ull << MSR_EE) |
5611 (1ull << MSR_PR) |
5612 (1ull << MSR_FP) |
5613 (1ull << MSR_ME) |
5614 (1ull << MSR_FE0) |
5615 (1ull << MSR_SE) |
5616 (1ull << MSR_DE) |
5617 (1ull << MSR_FE1) |
5618 (1ull << MSR_EP) |
5619 (1ull << MSR_IR) |
5620 (1ull << MSR_DR) |
5621 (1ull << MSR_PMM) |
5622 (1ull << MSR_RI) |
5623 (1ull << MSR_LE);
ba9fd9f1 5624 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5625#if defined(CONFIG_SOFTMMU)
5626 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5627#endif
ba9fd9f1
AF		 5628 pcc->excp_model = POWERPC_EXCP_604;
5629 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5630 pcc->bfd_mach = bfd_mach_ppc_604;
5631 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5632 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5633}
5634
082c6681
JM		 5635static void init_proc_604E (CPUPPCState *env)
5636{
5637 gen_spr_ne_601(env);
4f4f28ff 5638 gen_spr_sdr1(env);
082c6681
JM		 5639 gen_spr_604(env);
5640 /* XXX : not implemented */
cb8b8bf8 5641 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
082c6681
JM		 5642 SPR_NOACCESS, SPR_NOACCESS,
5643 &spr_read_generic, &spr_write_generic,
5644 0x00000000);
5645 /* XXX : not implemented */
cb8b8bf8 5646 spr_register(env, SPR_7XX_PMC3, "PMC3",
082c6681
JM		 5647 SPR_NOACCESS, SPR_NOACCESS,
5648 &spr_read_generic, &spr_write_generic,
5649 0x00000000);
5650 /* XXX : not implemented */
cb8b8bf8 5651 spr_register(env, SPR_7XX_PMC4, "PMC4",
082c6681
JM		 5652 SPR_NOACCESS, SPR_NOACCESS,
5653 &spr_read_generic, &spr_write_generic,
5654 0x00000000);
5655 /* Time base */
5656 gen_tbl(env);
5657 /* Hardware implementation registers */
5658 /* XXX : not implemented */
a750fc0b
JM		 5659 spr_register(env, SPR_HID0, "HID0",
5660 SPR_NOACCESS, SPR_NOACCESS,
5661 &spr_read_generic, &spr_write_generic,
5662 0x00000000);
5663 /* XXX : not implemented */
5664 spr_register(env, SPR_HID1, "HID1",
5665 SPR_NOACCESS, SPR_NOACCESS,
5666 &spr_read_generic, &spr_write_generic,
5667 0x00000000);
5668 /* Memory management */
5669 gen_low_BATs(env);
e1833e1f 5670 init_excp_604(env);
d63001d1
JM		 5671 env->dcache_line_size = 32;
5672 env->icache_line_size = 32;
a750fc0b 5673 /* Allocate hardware IRQ controller */
aa5a9e24 5674 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b
JM		 5675}
5676
7856e3a4
AF		 5677POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5678{
ca5dff0a 5679 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5680 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5681
ca5dff0a 5682 dc->desc = "PowerPC 604E";
7856e3a4
AF		 5683 pcc->init_proc = init_proc_604E;
5684 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 5685 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5686 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5687 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5688 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5689 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5690 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5691 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 5692 pcc->msr_mask = (1ull << MSR_POW) |
5693 (1ull << MSR_ILE) |
5694 (1ull << MSR_EE) |
5695 (1ull << MSR_PR) |
5696 (1ull << MSR_FP) |
5697 (1ull << MSR_ME) |
5698 (1ull << MSR_FE0) |
5699 (1ull << MSR_SE) |
5700 (1ull << MSR_DE) |
5701 (1ull << MSR_FE1) |
5702 (1ull << MSR_EP) |
5703 (1ull << MSR_IR) |
5704 (1ull << MSR_DR) |
5705 (1ull << MSR_PMM) |
5706 (1ull << MSR_RI) |
5707 (1ull << MSR_LE);
ba9fd9f1 5708 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5709#if defined(CONFIG_SOFTMMU)
5710 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5711#endif
ba9fd9f1
AF		 5712 pcc->excp_model = POWERPC_EXCP_604;
5713 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5714 pcc->bfd_mach = bfd_mach_ppc_604;
5715 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5716 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5717}
5718
bd928eba 5719static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 5720{
5721 gen_spr_ne_601(env);
4f4f28ff 5722 gen_spr_sdr1(env);
a750fc0b
JM		 5723 gen_spr_7xx(env);
5724 /* Time base */
5725 gen_tbl(env);
5726 /* Thermal management */
5727 gen_spr_thrm(env);
5728 /* Hardware implementation registers */
5729 /* XXX : not implemented */
5730 spr_register(env, SPR_HID0, "HID0",
5731 SPR_NOACCESS, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_generic,
5733 0x00000000);
5734 /* XXX : not implemented */
5735 spr_register(env, SPR_HID1, "HID1",
5736 SPR_NOACCESS, SPR_NOACCESS,
5737 &spr_read_generic, &spr_write_generic,
5738 0x00000000);
5739 /* Memory management */
5740 gen_low_BATs(env);
e1833e1f 5741 init_excp_7x0(env);
d63001d1
JM		 5742 env->dcache_line_size = 32;
5743 env->icache_line_size = 32;
a750fc0b 5744 /* Allocate hardware IRQ controller */
aa5a9e24 5745 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b
JM		 5746}
5747
7856e3a4
AF		 5748POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5749{
ca5dff0a 5750 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5751 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5752
ca5dff0a 5753 dc->desc = "PowerPC 740";
7856e3a4
AF		 5754 pcc->init_proc = init_proc_740;
5755 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5756 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5757 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5758 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5759 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5760 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5761 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5762 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 5763 pcc->msr_mask = (1ull << MSR_POW) |
5764 (1ull << MSR_ILE) |
5765 (1ull << MSR_EE) |
5766 (1ull << MSR_PR) |
5767 (1ull << MSR_FP) |
5768 (1ull << MSR_ME) |
5769 (1ull << MSR_FE0) |
5770 (1ull << MSR_SE) |
5771 (1ull << MSR_DE) |
5772 (1ull << MSR_FE1) |
5773 (1ull << MSR_EP) |
5774 (1ull << MSR_IR) |
5775 (1ull << MSR_DR) |
5776 (1ull << MSR_PMM) |
5777 (1ull << MSR_RI) |
5778 (1ull << MSR_LE);
ba9fd9f1 5779 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5780#if defined(CONFIG_SOFTMMU)
5781 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5782#endif
ba9fd9f1
AF		 5783 pcc->excp_model = POWERPC_EXCP_7x0;
5784 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5785 pcc->bfd_mach = bfd_mach_ppc_750;
5786 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5787 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5788}
5789
bd928eba
JM		 5790static void init_proc_750 (CPUPPCState *env)
5791{
5792 gen_spr_ne_601(env);
4f4f28ff 5793 gen_spr_sdr1(env);
bd928eba
JM		 5794 gen_spr_7xx(env);
5795 /* XXX : not implemented */
5796 spr_register(env, SPR_L2CR, "L2CR",
5797 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 5798 &spr_read_generic, spr_access_nop,
bd928eba
JM		 5799 0x00000000);
5800 /* Time base */
5801 gen_tbl(env);
5802 /* Thermal management */
5803 gen_spr_thrm(env);
5804 /* Hardware implementation registers */
5805 /* XXX : not implemented */
5806 spr_register(env, SPR_HID0, "HID0",
5807 SPR_NOACCESS, SPR_NOACCESS,
5808 &spr_read_generic, &spr_write_generic,
5809 0x00000000);
5810 /* XXX : not implemented */
5811 spr_register(env, SPR_HID1, "HID1",
5812 SPR_NOACCESS, SPR_NOACCESS,
5813 &spr_read_generic, &spr_write_generic,
5814 0x00000000);
5815 /* Memory management */
5816 gen_low_BATs(env);
5817 /* XXX: high BATs are also present but are known to be bugged on
5818 * die version 1.x
5819 */
5820 init_excp_7x0(env);
5821 env->dcache_line_size = 32;
5822 env->icache_line_size = 32;
5823 /* Allocate hardware IRQ controller */
aa5a9e24 5824 ppc6xx_irq_init(ppc_env_get_cpu(env));
bd928eba
JM		 5825}
5826
7856e3a4
AF		 5827POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5828{
ca5dff0a 5829 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5830 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5831
ca5dff0a 5832 dc->desc = "PowerPC 750";
7856e3a4
AF		 5833 pcc->init_proc = init_proc_750;
5834 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5835 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5836 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5837 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5838 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5839 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5840 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5841 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 5842 pcc->msr_mask = (1ull << MSR_POW) |
5843 (1ull << MSR_ILE) |
5844 (1ull << MSR_EE) |
5845 (1ull << MSR_PR) |
5846 (1ull << MSR_FP) |
5847 (1ull << MSR_ME) |
5848 (1ull << MSR_FE0) |
5849 (1ull << MSR_SE) |
5850 (1ull << MSR_DE) |
5851 (1ull << MSR_FE1) |
5852 (1ull << MSR_EP) |
5853 (1ull << MSR_IR) |
5854 (1ull << MSR_DR) |
5855 (1ull << MSR_PMM) |
5856 (1ull << MSR_RI) |
5857 (1ull << MSR_LE);
ba9fd9f1 5858 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 5859#if defined(CONFIG_SOFTMMU)
5860 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5861#endif
ba9fd9f1
AF		 5862 pcc->excp_model = POWERPC_EXCP_7x0;
5863 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5864 pcc->bfd_mach = bfd_mach_ppc_750;
5865 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5866 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 5867}
5868
bd928eba
JM		 5869static void init_proc_750cl (CPUPPCState *env)
5870{
5871 gen_spr_ne_601(env);
4f4f28ff 5872 gen_spr_sdr1(env);
bd928eba
JM		 5873 gen_spr_7xx(env);
5874 /* XXX : not implemented */
5875 spr_register(env, SPR_L2CR, "L2CR",
5876 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 5877 &spr_read_generic, spr_access_nop,
bd928eba
JM		 5878 0x00000000);
5879 /* Time base */
5880 gen_tbl(env);
5881 /* Thermal management */
5882 /* Those registers are fake on 750CL */
5883 spr_register(env, SPR_THRM1, "THRM1",
5884 SPR_NOACCESS, SPR_NOACCESS,
5885 &spr_read_generic, &spr_write_generic,
5886 0x00000000);
5887 spr_register(env, SPR_THRM2, "THRM2",
5888 SPR_NOACCESS, SPR_NOACCESS,
5889 &spr_read_generic, &spr_write_generic,
5890 0x00000000);
5891 spr_register(env, SPR_THRM3, "THRM3",
5892 SPR_NOACCESS, SPR_NOACCESS,
5893 &spr_read_generic, &spr_write_generic,
5894 0x00000000);
5895 /* XXX: not implemented */
5896 spr_register(env, SPR_750_TDCL, "TDCL",
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_generic,
5899 0x00000000);
5900 spr_register(env, SPR_750_TDCH, "TDCH",
5901 SPR_NOACCESS, SPR_NOACCESS,
5902 &spr_read_generic, &spr_write_generic,
5903 0x00000000);
5904 /* DMA */
5905 /* XXX : not implemented */
5906 spr_register(env, SPR_750_WPAR, "WPAR",
5907 SPR_NOACCESS, SPR_NOACCESS,
5908 &spr_read_generic, &spr_write_generic,
5909 0x00000000);
5910 spr_register(env, SPR_750_DMAL, "DMAL",
5911 SPR_NOACCESS, SPR_NOACCESS,
5912 &spr_read_generic, &spr_write_generic,
5913 0x00000000);
5914 spr_register(env, SPR_750_DMAU, "DMAU",
5915 SPR_NOACCESS, SPR_NOACCESS,
5916 &spr_read_generic, &spr_write_generic,
5917 0x00000000);
5918 /* Hardware implementation registers */
5919 /* XXX : not implemented */
5920 spr_register(env, SPR_HID0, "HID0",
5921 SPR_NOACCESS, SPR_NOACCESS,
5922 &spr_read_generic, &spr_write_generic,
5923 0x00000000);
5924 /* XXX : not implemented */
5925 spr_register(env, SPR_HID1, "HID1",
5926 SPR_NOACCESS, SPR_NOACCESS,
5927 &spr_read_generic, &spr_write_generic,
5928 0x00000000);
5929 /* XXX : not implemented */
5930 spr_register(env, SPR_750CL_HID2, "HID2",
5931 SPR_NOACCESS, SPR_NOACCESS,
5932 &spr_read_generic, &spr_write_generic,
5933 0x00000000);
5934 /* XXX : not implemented */
5935 spr_register(env, SPR_750CL_HID4, "HID4",
5936 SPR_NOACCESS, SPR_NOACCESS,
5937 &spr_read_generic, &spr_write_generic,
5938 0x00000000);
5939 /* Quantization registers */
5940 /* XXX : not implemented */
5941 spr_register(env, SPR_750_GQR0, "GQR0",
5942 SPR_NOACCESS, SPR_NOACCESS,
5943 &spr_read_generic, &spr_write_generic,
5944 0x00000000);
5945 /* XXX : not implemented */
5946 spr_register(env, SPR_750_GQR1, "GQR1",
5947 SPR_NOACCESS, SPR_NOACCESS,
5948 &spr_read_generic, &spr_write_generic,
5949 0x00000000);
5950 /* XXX : not implemented */
5951 spr_register(env, SPR_750_GQR2, "GQR2",
5952 SPR_NOACCESS, SPR_NOACCESS,
5953 &spr_read_generic, &spr_write_generic,
5954 0x00000000);
5955 /* XXX : not implemented */
5956 spr_register(env, SPR_750_GQR3, "GQR3",
5957 SPR_NOACCESS, SPR_NOACCESS,
5958 &spr_read_generic, &spr_write_generic,
5959 0x00000000);
5960 /* XXX : not implemented */
5961 spr_register(env, SPR_750_GQR4, "GQR4",
5962 SPR_NOACCESS, SPR_NOACCESS,
5963 &spr_read_generic, &spr_write_generic,
5964 0x00000000);
5965 /* XXX : not implemented */
5966 spr_register(env, SPR_750_GQR5, "GQR5",
5967 SPR_NOACCESS, SPR_NOACCESS,
5968 &spr_read_generic, &spr_write_generic,
5969 0x00000000);
5970 /* XXX : not implemented */
5971 spr_register(env, SPR_750_GQR6, "GQR6",
5972 SPR_NOACCESS, SPR_NOACCESS,
5973 &spr_read_generic, &spr_write_generic,
5974 0x00000000);
5975 /* XXX : not implemented */
5976 spr_register(env, SPR_750_GQR7, "GQR7",
5977 SPR_NOACCESS, SPR_NOACCESS,
5978 &spr_read_generic, &spr_write_generic,
5979 0x00000000);
5980 /* Memory management */
5981 gen_low_BATs(env);
5982 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5983 gen_high_BATs(env);
5984 init_excp_750cl(env);
5985 env->dcache_line_size = 32;
5986 env->icache_line_size = 32;
5987 /* Allocate hardware IRQ controller */
aa5a9e24 5988 ppc6xx_irq_init(ppc_env_get_cpu(env));
bd928eba
JM		 5989}
5990
7856e3a4
AF		 5991POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5992{
ca5dff0a 5993 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5994 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5995
ca5dff0a 5996 dc->desc = "PowerPC 750 CL";
7856e3a4
AF		 5997 pcc->init_proc = init_proc_750cl;
5998 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5999 /* XXX: not implemented:
6000 * cache lock instructions:
6001 * dcbz_l
6002 * floating point paired instructions
6003 * psq_lux
6004 * psq_lx
6005 * psq_stux
6006 * psq_stx
6007 * ps_abs
6008 * ps_add
6009 * ps_cmpo0
6010 * ps_cmpo1
6011 * ps_cmpu0
6012 * ps_cmpu1
6013 * ps_div
6014 * ps_madd
6015 * ps_madds0
6016 * ps_madds1
6017 * ps_merge00
6018 * ps_merge01
6019 * ps_merge10
6020 * ps_merge11
6021 * ps_mr
6022 * ps_msub
6023 * ps_mul
6024 * ps_muls0
6025 * ps_muls1
6026 * ps_nabs
6027 * ps_neg
6028 * ps_nmadd
6029 * ps_nmsub
6030 * ps_res
6031 * ps_rsqrte
6032 * ps_sel
6033 * ps_sub
6034 * ps_sum0
6035 * ps_sum1
6036 */
6037 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6038 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6039 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6040 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6041 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6042 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6043 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 6044 pcc->msr_mask = (1ull << MSR_POW) |
6045 (1ull << MSR_ILE) |
6046 (1ull << MSR_EE) |
6047 (1ull << MSR_PR) |
6048 (1ull << MSR_FP) |
6049 (1ull << MSR_ME) |
6050 (1ull << MSR_FE0) |
6051 (1ull << MSR_SE) |
6052 (1ull << MSR_DE) |
6053 (1ull << MSR_FE1) |
6054 (1ull << MSR_EP) |
6055 (1ull << MSR_IR) |
6056 (1ull << MSR_DR) |
6057 (1ull << MSR_PMM) |
6058 (1ull << MSR_RI) |
6059 (1ull << MSR_LE);
ba9fd9f1 6060 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 6061#if defined(CONFIG_SOFTMMU)
6062 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6063#endif
ba9fd9f1
AF		 6064 pcc->excp_model = POWERPC_EXCP_7x0;
6065 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6066 pcc->bfd_mach = bfd_mach_ppc_750;
6067 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6068 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6069}
6070
bd928eba
JM		 6071static void init_proc_750cx (CPUPPCState *env)
6072{
6073 gen_spr_ne_601(env);
4f4f28ff 6074 gen_spr_sdr1(env);
bd928eba
JM		 6075 gen_spr_7xx(env);
6076 /* XXX : not implemented */
6077 spr_register(env, SPR_L2CR, "L2CR",
6078 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 6079 &spr_read_generic, spr_access_nop,
bd928eba
JM		 6080 0x00000000);
6081 /* Time base */
6082 gen_tbl(env);
6083 /* Thermal management */
6084 gen_spr_thrm(env);
6085 /* This register is not implemented but is present for compatibility */
6086 spr_register(env, SPR_SDA, "SDA",
6087 SPR_NOACCESS, SPR_NOACCESS,
6088 &spr_read_generic, &spr_write_generic,
6089 0x00000000);
6090 /* Hardware implementation registers */
6091 /* XXX : not implemented */
6092 spr_register(env, SPR_HID0, "HID0",
6093 SPR_NOACCESS, SPR_NOACCESS,
6094 &spr_read_generic, &spr_write_generic,
6095 0x00000000);
6096 /* XXX : not implemented */
6097 spr_register(env, SPR_HID1, "HID1",
6098 SPR_NOACCESS, SPR_NOACCESS,
6099 &spr_read_generic, &spr_write_generic,
6100 0x00000000);
6101 /* Memory management */
6102 gen_low_BATs(env);
4e777442
JM		 6103 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6104 gen_high_BATs(env);
bd928eba
JM		 6105 init_excp_750cx(env);
6106 env->dcache_line_size = 32;
6107 env->icache_line_size = 32;
6108 /* Allocate hardware IRQ controller */
aa5a9e24 6109 ppc6xx_irq_init(ppc_env_get_cpu(env));
bd928eba
JM		 6110}
6111
7856e3a4
AF		 6112POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6113{
ca5dff0a 6114 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6115 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6116
ca5dff0a 6117 dc->desc = "PowerPC 750CX";
7856e3a4
AF		 6118 pcc->init_proc = init_proc_750cx;
6119 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6120 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6121 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6122 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6123 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6124 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6125 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6126 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 6127 pcc->msr_mask = (1ull << MSR_POW) |
6128 (1ull << MSR_ILE) |
6129 (1ull << MSR_EE) |
6130 (1ull << MSR_PR) |
6131 (1ull << MSR_FP) |
6132 (1ull << MSR_ME) |
6133 (1ull << MSR_FE0) |
6134 (1ull << MSR_SE) |
6135 (1ull << MSR_DE) |
6136 (1ull << MSR_FE1) |
6137 (1ull << MSR_EP) |
6138 (1ull << MSR_IR) |
6139 (1ull << MSR_DR) |
6140 (1ull << MSR_PMM) |
6141 (1ull << MSR_RI) |
6142 (1ull << MSR_LE);
ba9fd9f1 6143 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 6144#if defined(CONFIG_SOFTMMU)
6145 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6146#endif
ba9fd9f1
AF		 6147 pcc->excp_model = POWERPC_EXCP_7x0;
6148 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6149 pcc->bfd_mach = bfd_mach_ppc_750;
6150 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6151 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6152}
6153
a750fc0b
JM		 6154static void init_proc_750fx (CPUPPCState *env)
6155{
6156 gen_spr_ne_601(env);
4f4f28ff 6157 gen_spr_sdr1(env);
a750fc0b 6158 gen_spr_7xx(env);
bd928eba
JM		 6159 /* XXX : not implemented */
6160 spr_register(env, SPR_L2CR, "L2CR",
6161 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 6162 &spr_read_generic, spr_access_nop,
bd928eba 6163 0x00000000);
a750fc0b
JM		 6164 /* Time base */
6165 gen_tbl(env);
6166 /* Thermal management */
6167 gen_spr_thrm(env);
bd928eba
JM		 6168 /* XXX : not implemented */
6169 spr_register(env, SPR_750_THRM4, "THRM4",
6170 SPR_NOACCESS, SPR_NOACCESS,
6171 &spr_read_generic, &spr_write_generic,
6172 0x00000000);
a750fc0b
JM		 6173 /* Hardware implementation registers */
6174 /* XXX : not implemented */
6175 spr_register(env, SPR_HID0, "HID0",
6176 SPR_NOACCESS, SPR_NOACCESS,
6177 &spr_read_generic, &spr_write_generic,
6178 0x00000000);
6179 /* XXX : not implemented */
6180 spr_register(env, SPR_HID1, "HID1",
6181 SPR_NOACCESS, SPR_NOACCESS,
6182 &spr_read_generic, &spr_write_generic,
6183 0x00000000);
6184 /* XXX : not implemented */
bd928eba 6185 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6186 SPR_NOACCESS, SPR_NOACCESS,
6187 &spr_read_generic, &spr_write_generic,
6188 0x00000000);
6189 /* Memory management */
6190 gen_low_BATs(env);
6191 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6192 gen_high_BATs(env);
bd928eba 6193 init_excp_7x0(env);
d63001d1
JM		 6194 env->dcache_line_size = 32;
6195 env->icache_line_size = 32;
a750fc0b 6196 /* Allocate hardware IRQ controller */
aa5a9e24 6197 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b
JM		 6198}
6199
7856e3a4
AF		 6200POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6201{
ca5dff0a 6202 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6203 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6204
ca5dff0a 6205 dc->desc = "PowerPC 750FX";
7856e3a4
AF		 6206 pcc->init_proc = init_proc_750fx;
6207 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6208 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6209 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6210 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6211 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6212 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6213 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6214 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 6215 pcc->msr_mask = (1ull << MSR_POW) |
6216 (1ull << MSR_ILE) |
6217 (1ull << MSR_EE) |
6218 (1ull << MSR_PR) |
6219 (1ull << MSR_FP) |
6220 (1ull << MSR_ME) |
6221 (1ull << MSR_FE0) |
6222 (1ull << MSR_SE) |
6223 (1ull << MSR_DE) |
6224 (1ull << MSR_FE1) |
6225 (1ull << MSR_EP) |
6226 (1ull << MSR_IR) |
6227 (1ull << MSR_DR) |
6228 (1ull << MSR_PMM) |
6229 (1ull << MSR_RI) |
6230 (1ull << MSR_LE);
ba9fd9f1 6231 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 6232#if defined(CONFIG_SOFTMMU)
6233 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6234#endif
ba9fd9f1
AF		 6235 pcc->excp_model = POWERPC_EXCP_7x0;
6236 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6237 pcc->bfd_mach = bfd_mach_ppc_750;
6238 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6239 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6240}
6241
bd928eba
JM		 6242static void init_proc_750gx (CPUPPCState *env)
6243{
6244 gen_spr_ne_601(env);
4f4f28ff 6245 gen_spr_sdr1(env);
bd928eba
JM		 6246 gen_spr_7xx(env);
6247 /* XXX : not implemented (XXX: different from 750fx) */
6248 spr_register(env, SPR_L2CR, "L2CR",
6249 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 6250 &spr_read_generic, spr_access_nop,
bd928eba
JM		 6251 0x00000000);
6252 /* Time base */
6253 gen_tbl(env);
6254 /* Thermal management */
6255 gen_spr_thrm(env);
6256 /* XXX : not implemented */
6257 spr_register(env, SPR_750_THRM4, "THRM4",
6258 SPR_NOACCESS, SPR_NOACCESS,
6259 &spr_read_generic, &spr_write_generic,
6260 0x00000000);
6261 /* Hardware implementation registers */
6262 /* XXX : not implemented (XXX: different from 750fx) */
6263 spr_register(env, SPR_HID0, "HID0",
6264 SPR_NOACCESS, SPR_NOACCESS,
6265 &spr_read_generic, &spr_write_generic,
6266 0x00000000);
6267 /* XXX : not implemented */
6268 spr_register(env, SPR_HID1, "HID1",
6269 SPR_NOACCESS, SPR_NOACCESS,
6270 &spr_read_generic, &spr_write_generic,
6271 0x00000000);
6272 /* XXX : not implemented (XXX: different from 750fx) */
6273 spr_register(env, SPR_750FX_HID2, "HID2",
6274 SPR_NOACCESS, SPR_NOACCESS,
6275 &spr_read_generic, &spr_write_generic,
6276 0x00000000);
6277 /* Memory management */
6278 gen_low_BATs(env);
6279 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6280 gen_high_BATs(env);
6281 init_excp_7x0(env);
6282 env->dcache_line_size = 32;
6283 env->icache_line_size = 32;
6284 /* Allocate hardware IRQ controller */
aa5a9e24 6285 ppc6xx_irq_init(ppc_env_get_cpu(env));
bd928eba
JM		 6286}
6287
7856e3a4
AF		 6288POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6289{
ca5dff0a 6290 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6291 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6292
ca5dff0a 6293 dc->desc = "PowerPC 750GX";
7856e3a4
AF		 6294 pcc->init_proc = init_proc_750gx;
6295 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6296 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6297 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6298 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6299 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6300 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6301 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6302 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 6303 pcc->msr_mask = (1ull << MSR_POW) |
6304 (1ull << MSR_ILE) |
6305 (1ull << MSR_EE) |
6306 (1ull << MSR_PR) |
6307 (1ull << MSR_FP) |
6308 (1ull << MSR_ME) |
6309 (1ull << MSR_FE0) |
6310 (1ull << MSR_SE) |
6311 (1ull << MSR_DE) |
6312 (1ull << MSR_FE1) |
6313 (1ull << MSR_EP) |
6314 (1ull << MSR_IR) |
6315 (1ull << MSR_DR) |
6316 (1ull << MSR_PMM) |
6317 (1ull << MSR_RI) |
6318 (1ull << MSR_LE);
ba9fd9f1 6319 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 6320#if defined(CONFIG_SOFTMMU)
6321 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6322#endif
ba9fd9f1
AF		 6323 pcc->excp_model = POWERPC_EXCP_7x0;
6324 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6325 pcc->bfd_mach = bfd_mach_ppc_750;
6326 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6327 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6328}
6329
bd928eba
JM		 6330static void init_proc_745 (CPUPPCState *env)
6331{
6332 gen_spr_ne_601(env);
4f4f28ff 6333 gen_spr_sdr1(env);
bd928eba
JM		 6334 gen_spr_7xx(env);
6335 gen_spr_G2_755(env);
6336 /* Time base */
6337 gen_tbl(env);
6338 /* Thermal management */
6339 gen_spr_thrm(env);
6340 /* Hardware implementation registers */
6341 /* XXX : not implemented */
6342 spr_register(env, SPR_HID0, "HID0",
6343 SPR_NOACCESS, SPR_NOACCESS,
6344 &spr_read_generic, &spr_write_generic,
6345 0x00000000);
6346 /* XXX : not implemented */
6347 spr_register(env, SPR_HID1, "HID1",
6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, &spr_write_generic,
6350 0x00000000);
6351 /* XXX : not implemented */
6352 spr_register(env, SPR_HID2, "HID2",
6353 SPR_NOACCESS, SPR_NOACCESS,
6354 &spr_read_generic, &spr_write_generic,
6355 0x00000000);
6356 /* Memory management */
6357 gen_low_BATs(env);
6358 gen_high_BATs(env);
6359 gen_6xx_7xx_soft_tlb(env, 64, 2);
6360 init_excp_7x5(env);
6361 env->dcache_line_size = 32;
6362 env->icache_line_size = 32;
6363 /* Allocate hardware IRQ controller */
aa5a9e24 6364 ppc6xx_irq_init(ppc_env_get_cpu(env));
bd928eba
JM		 6365}
6366
7856e3a4
AF		 6367POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6368{
ca5dff0a 6369 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6370 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6371
ca5dff0a 6372 dc->desc = "PowerPC 745";
7856e3a4
AF		 6373 pcc->init_proc = init_proc_745;
6374 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6375 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6376 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6377 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6378 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6379 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6380 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6381 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 6382 pcc->msr_mask = (1ull << MSR_POW) |
6383 (1ull << MSR_ILE) |
6384 (1ull << MSR_EE) |
6385 (1ull << MSR_PR) |
6386 (1ull << MSR_FP) |
6387 (1ull << MSR_ME) |
6388 (1ull << MSR_FE0) |
6389 (1ull << MSR_SE) |
6390 (1ull << MSR_DE) |
6391 (1ull << MSR_FE1) |
6392 (1ull << MSR_EP) |
6393 (1ull << MSR_IR) |
6394 (1ull << MSR_DR) |
6395 (1ull << MSR_PMM) |
6396 (1ull << MSR_RI) |
6397 (1ull << MSR_LE);
ba9fd9f1
AF		 6398 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6399 pcc->excp_model = POWERPC_EXCP_7x5;
6400 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6401 pcc->bfd_mach = bfd_mach_ppc_750;
6402 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6403 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6404}
6405
bd928eba 6406static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 6407{
6408 gen_spr_ne_601(env);
4f4f28ff 6409 gen_spr_sdr1(env);
bd928eba 6410 gen_spr_7xx(env);
a750fc0b
JM		 6411 gen_spr_G2_755(env);
6412 /* Time base */
6413 gen_tbl(env);
6414 /* L2 cache control */
6415 /* XXX : not implemented */
bd928eba 6416 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b 6417 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 6418 &spr_read_generic, spr_access_nop,
a750fc0b
JM		 6419 0x00000000);
6420 /* XXX : not implemented */
6421 spr_register(env, SPR_L2PMCR, "L2PMCR",
6422 SPR_NOACCESS, SPR_NOACCESS,
6423 &spr_read_generic, &spr_write_generic,
6424 0x00000000);
bd928eba
JM		 6425 /* Thermal management */
6426 gen_spr_thrm(env);
a750fc0b
JM		 6427 /* Hardware implementation registers */
6428 /* XXX : not implemented */
6429 spr_register(env, SPR_HID0, "HID0",
6430 SPR_NOACCESS, SPR_NOACCESS,
6431 &spr_read_generic, &spr_write_generic,
6432 0x00000000);
6433 /* XXX : not implemented */
6434 spr_register(env, SPR_HID1, "HID1",
6435 SPR_NOACCESS, SPR_NOACCESS,
6436 &spr_read_generic, &spr_write_generic,
6437 0x00000000);
6438 /* XXX : not implemented */
6439 spr_register(env, SPR_HID2, "HID2",
6440 SPR_NOACCESS, SPR_NOACCESS,
6441 &spr_read_generic, &spr_write_generic,
6442 0x00000000);
6443 /* Memory management */
6444 gen_low_BATs(env);
6445 gen_high_BATs(env);
6446 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 6447 init_excp_7x5(env);
d63001d1
JM		 6448 env->dcache_line_size = 32;
6449 env->icache_line_size = 32;
a750fc0b 6450 /* Allocate hardware IRQ controller */
aa5a9e24 6451 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b
JM		 6452}
6453
7856e3a4
AF		 6454POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6455{
ca5dff0a 6456 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6457 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6458
ca5dff0a 6459 dc->desc = "PowerPC 755";
7856e3a4
AF		 6460 pcc->init_proc = init_proc_755;
6461 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6462 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6463 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6464 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6465 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6466 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6467 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6468 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 6469 pcc->msr_mask = (1ull << MSR_POW) |
6470 (1ull << MSR_ILE) |
6471 (1ull << MSR_EE) |
6472 (1ull << MSR_PR) |
6473 (1ull << MSR_FP) |
6474 (1ull << MSR_ME) |
6475 (1ull << MSR_FE0) |
6476 (1ull << MSR_SE) |
6477 (1ull << MSR_DE) |
6478 (1ull << MSR_FE1) |
6479 (1ull << MSR_EP) |
6480 (1ull << MSR_IR) |
6481 (1ull << MSR_DR) |
6482 (1ull << MSR_PMM) |
6483 (1ull << MSR_RI) |
6484 (1ull << MSR_LE);
ba9fd9f1
AF		 6485 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6486 pcc->excp_model = POWERPC_EXCP_7x5;
6487 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6488 pcc->bfd_mach = bfd_mach_ppc_750;
6489 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6490 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6491}
6492
a750fc0b
JM		 6493static void init_proc_7400 (CPUPPCState *env)
6494{
6495 gen_spr_ne_601(env);
4f4f28ff 6496 gen_spr_sdr1(env);
a750fc0b
JM		 6497 gen_spr_7xx(env);
6498 /* Time base */
6499 gen_tbl(env);
6500 /* 74xx specific SPR */
6501 gen_spr_74xx(env);
4e777442
JM		 6502 /* XXX : not implemented */
6503 spr_register(env, SPR_UBAMR, "UBAMR",
6504 &spr_read_ureg, SPR_NOACCESS,
6505 &spr_read_ureg, SPR_NOACCESS,
6506 0x00000000);
6507 /* XXX: this seems not implemented on all revisions. */
6508 /* XXX : not implemented */
6509 spr_register(env, SPR_MSSCR1, "MSSCR1",
6510 SPR_NOACCESS, SPR_NOACCESS,
6511 &spr_read_generic, &spr_write_generic,
6512 0x00000000);
a750fc0b
JM		 6513 /* Thermal management */
6514 gen_spr_thrm(env);
6515 /* Memory management */
6516 gen_low_BATs(env);
e1833e1f 6517 init_excp_7400(env);
d63001d1
JM		 6518 env->dcache_line_size = 32;
6519 env->icache_line_size = 32;
a750fc0b 6520 /* Allocate hardware IRQ controller */
aa5a9e24 6521 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b
JM		 6522}
6523
7856e3a4
AF		 6524POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6525{
ca5dff0a 6526 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6527 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6528
ca5dff0a 6529 dc->desc = "PowerPC 7400 (aka G4)";
7856e3a4
AF		 6530 pcc->init_proc = init_proc_7400;
6531 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6532 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6533 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6534 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6535 PPC_FLOAT_STFIWX |
6536 PPC_CACHE | PPC_CACHE_ICBI |
6537 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6538 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6539 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6540 PPC_MEM_TLBIA |
6541 PPC_SEGMENT | PPC_EXTERN |
6542 PPC_ALTIVEC;
9df5a466
TM		 6543 pcc->msr_mask = (1ull << MSR_VR) |
6544 (1ull << MSR_POW) |
6545 (1ull << MSR_ILE) |
6546 (1ull << MSR_EE) |
6547 (1ull << MSR_PR) |
6548 (1ull << MSR_FP) |
6549 (1ull << MSR_ME) |
6550 (1ull << MSR_FE0) |
6551 (1ull << MSR_SE) |
6552 (1ull << MSR_DE) |
6553 (1ull << MSR_FE1) |
6554 (1ull << MSR_EP) |
6555 (1ull << MSR_IR) |
6556 (1ull << MSR_DR) |
6557 (1ull << MSR_PMM) |
6558 (1ull << MSR_RI) |
6559 (1ull << MSR_LE);
ba9fd9f1 6560 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 6561#if defined(CONFIG_SOFTMMU)
6562 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6563#endif
ba9fd9f1
AF		 6564 pcc->excp_model = POWERPC_EXCP_74xx;
6565 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6566 pcc->bfd_mach = bfd_mach_ppc_7400;
6567 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6568 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6569 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6570}
6571
a750fc0b
JM		 6572static void init_proc_7410 (CPUPPCState *env)
6573{
6574 gen_spr_ne_601(env);
4f4f28ff 6575 gen_spr_sdr1(env);
a750fc0b
JM		 6576 gen_spr_7xx(env);
6577 /* Time base */
6578 gen_tbl(env);
6579 /* 74xx specific SPR */
6580 gen_spr_74xx(env);
4e777442
JM		 6581 /* XXX : not implemented */
6582 spr_register(env, SPR_UBAMR, "UBAMR",
6583 &spr_read_ureg, SPR_NOACCESS,
6584 &spr_read_ureg, SPR_NOACCESS,
6585 0x00000000);
a750fc0b
JM		 6586 /* Thermal management */
6587 gen_spr_thrm(env);
6588 /* L2PMCR */
6589 /* XXX : not implemented */
6590 spr_register(env, SPR_L2PMCR, "L2PMCR",
6591 SPR_NOACCESS, SPR_NOACCESS,
6592 &spr_read_generic, &spr_write_generic,
6593 0x00000000);
6594 /* LDSTDB */
6595 /* XXX : not implemented */
6596 spr_register(env, SPR_LDSTDB, "LDSTDB",
6597 SPR_NOACCESS, SPR_NOACCESS,
6598 &spr_read_generic, &spr_write_generic,
6599 0x00000000);
6600 /* Memory management */
6601 gen_low_BATs(env);
e1833e1f 6602 init_excp_7400(env);
d63001d1
JM		 6603 env->dcache_line_size = 32;
6604 env->icache_line_size = 32;
a750fc0b 6605 /* Allocate hardware IRQ controller */
aa5a9e24 6606 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b
JM		 6607}
6608
7856e3a4
AF		 6609POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6610{
ca5dff0a 6611 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6612 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6613
ca5dff0a 6614 dc->desc = "PowerPC 7410 (aka G4)";
7856e3a4
AF		 6615 pcc->init_proc = init_proc_7410;
6616 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6617 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6618 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6619 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6620 PPC_FLOAT_STFIWX |
6621 PPC_CACHE | PPC_CACHE_ICBI |
6622 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6623 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6624 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6625 PPC_MEM_TLBIA |
6626 PPC_SEGMENT | PPC_EXTERN |
6627 PPC_ALTIVEC;
9df5a466
TM		 6628 pcc->msr_mask = (1ull << MSR_VR) |
6629 (1ull << MSR_POW) |
6630 (1ull << MSR_ILE) |
6631 (1ull << MSR_EE) |
6632 (1ull << MSR_PR) |
6633 (1ull << MSR_FP) |
6634 (1ull << MSR_ME) |
6635 (1ull << MSR_FE0) |
6636 (1ull << MSR_SE) |
6637 (1ull << MSR_DE) |
6638 (1ull << MSR_FE1) |
6639 (1ull << MSR_EP) |
6640 (1ull << MSR_IR) |
6641 (1ull << MSR_DR) |
6642 (1ull << MSR_PMM) |
6643 (1ull << MSR_RI) |
6644 (1ull << MSR_LE);
ba9fd9f1 6645 pcc->mmu_model = POWERPC_MMU_32B;
b632a148
DG		 6646#if defined(CONFIG_SOFTMMU)
6647 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6648#endif
ba9fd9f1
AF		 6649 pcc->excp_model = POWERPC_EXCP_74xx;
6650 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6651 pcc->bfd_mach = bfd_mach_ppc_7400;
6652 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6653 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6654 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6655}
6656
a750fc0b
JM		 6657static void init_proc_7440 (CPUPPCState *env)
6658{
6659 gen_spr_ne_601(env);
4f4f28ff 6660 gen_spr_sdr1(env);
a750fc0b
JM		 6661 gen_spr_7xx(env);
6662 /* Time base */
6663 gen_tbl(env);
6664 /* 74xx specific SPR */
6665 gen_spr_74xx(env);
4e777442
JM		 6666 /* XXX : not implemented */
6667 spr_register(env, SPR_UBAMR, "UBAMR",
6668 &spr_read_ureg, SPR_NOACCESS,
6669 &spr_read_ureg, SPR_NOACCESS,
6670 0x00000000);
a750fc0b
JM		 6671 /* LDSTCR */
6672 /* XXX : not implemented */
6673 spr_register(env, SPR_LDSTCR, "LDSTCR",
6674 SPR_NOACCESS, SPR_NOACCESS,
6675 &spr_read_generic, &spr_write_generic,
6676 0x00000000);
6677 /* ICTRL */
6678 /* XXX : not implemented */
6679 spr_register(env, SPR_ICTRL, "ICTRL",
6680 SPR_NOACCESS, SPR_NOACCESS,
6681 &spr_read_generic, &spr_write_generic,
6682 0x00000000);
6683 /* MSSSR0 */
578bb252 6684 /* XXX : not implemented */
a750fc0b
JM		 6685 spr_register(env, SPR_MSSSR0, "MSSSR0",
6686 SPR_NOACCESS, SPR_NOACCESS,
6687 &spr_read_generic, &spr_write_generic,
6688 0x00000000);
6689 /* PMC */
6690 /* XXX : not implemented */
cb8b8bf8 6691 spr_register(env, SPR_7XX_PMC5, "PMC5",
a750fc0b
JM		 6692 SPR_NOACCESS, SPR_NOACCESS,
6693 &spr_read_generic, &spr_write_generic,
6694 0x00000000);
578bb252 6695 /* XXX : not implemented */
cb8b8bf8 6696 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
a750fc0b
JM		 6697 &spr_read_ureg, SPR_NOACCESS,
6698 &spr_read_ureg, SPR_NOACCESS,
6699 0x00000000);
578bb252 6700 /* XXX : not implemented */
cb8b8bf8 6701 spr_register(env, SPR_7XX_PMC6, "PMC6",
a750fc0b
JM		 6702 SPR_NOACCESS, SPR_NOACCESS,
6703 &spr_read_generic, &spr_write_generic,
6704 0x00000000);
578bb252 6705 /* XXX : not implemented */
cb8b8bf8 6706 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
a750fc0b
JM		 6707 &spr_read_ureg, SPR_NOACCESS,
6708 &spr_read_ureg, SPR_NOACCESS,
6709 0x00000000);
6710 /* Memory management */
6711 gen_low_BATs(env);
578bb252 6712 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 6713 init_excp_7450(env);
d63001d1
JM		 6714 env->dcache_line_size = 32;
6715 env->icache_line_size = 32;
a750fc0b 6716 /* Allocate hardware IRQ controller */
aa5a9e24 6717 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b 6718}
a750fc0b 6719
7856e3a4
AF		 6720POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6721{
ca5dff0a 6722 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6723 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6724
ca5dff0a 6725 dc->desc = "PowerPC 7440 (aka G4)";
7856e3a4
AF		 6726 pcc->init_proc = init_proc_7440;
6727 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6728 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6729 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6730 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6731 PPC_FLOAT_STFIWX |
6732 PPC_CACHE | PPC_CACHE_ICBI |
6733 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6734 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6735 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6736 PPC_MEM_TLBIA | PPC_74xx_TLB |
6737 PPC_SEGMENT | PPC_EXTERN |
6738 PPC_ALTIVEC;
9df5a466
TM		 6739 pcc->msr_mask = (1ull << MSR_VR) |
6740 (1ull << MSR_POW) |
6741 (1ull << MSR_ILE) |
6742 (1ull << MSR_EE) |
6743 (1ull << MSR_PR) |
6744 (1ull << MSR_FP) |
6745 (1ull << MSR_ME) |
6746 (1ull << MSR_FE0) |
6747 (1ull << MSR_SE) |
6748 (1ull << MSR_DE) |
6749 (1ull << MSR_FE1) |
6750 (1ull << MSR_EP) |
6751 (1ull << MSR_IR) |
6752 (1ull << MSR_DR) |
6753 (1ull << MSR_PMM) |
6754 (1ull << MSR_RI) |
6755 (1ull << MSR_LE);
ba9fd9f1
AF		 6756 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6757 pcc->excp_model = POWERPC_EXCP_74xx;
6758 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6759 pcc->bfd_mach = bfd_mach_ppc_7400;
6760 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6761 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6762 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6763}
6764
a750fc0b
JM		 6765static void init_proc_7450 (CPUPPCState *env)
6766{
6767 gen_spr_ne_601(env);
4f4f28ff 6768 gen_spr_sdr1(env);
a750fc0b
JM		 6769 gen_spr_7xx(env);
6770 /* Time base */
6771 gen_tbl(env);
6772 /* 74xx specific SPR */
6773 gen_spr_74xx(env);
6774 /* Level 3 cache control */
6775 gen_l3_ctrl(env);
4e777442
JM		 6776 /* L3ITCR1 */
6777 /* XXX : not implemented */
6778 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6779 SPR_NOACCESS, SPR_NOACCESS,
6780 &spr_read_generic, &spr_write_generic,
6781 0x00000000);
6782 /* L3ITCR2 */
6783 /* XXX : not implemented */
6784 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6785 SPR_NOACCESS, SPR_NOACCESS,
6786 &spr_read_generic, &spr_write_generic,
6787 0x00000000);
6788 /* L3ITCR3 */
6789 /* XXX : not implemented */
6790 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6791 SPR_NOACCESS, SPR_NOACCESS,
6792 &spr_read_generic, &spr_write_generic,
6793 0x00000000);
6794 /* L3OHCR */
6795 /* XXX : not implemented */
6796 spr_register(env, SPR_L3OHCR, "L3OHCR",
6797 SPR_NOACCESS, SPR_NOACCESS,
6798 &spr_read_generic, &spr_write_generic,
6799 0x00000000);
6800 /* XXX : not implemented */
6801 spr_register(env, SPR_UBAMR, "UBAMR",
6802 &spr_read_ureg, SPR_NOACCESS,
6803 &spr_read_ureg, SPR_NOACCESS,
6804 0x00000000);
a750fc0b
JM		 6805 /* LDSTCR */
6806 /* XXX : not implemented */
6807 spr_register(env, SPR_LDSTCR, "LDSTCR",
6808 SPR_NOACCESS, SPR_NOACCESS,
6809 &spr_read_generic, &spr_write_generic,
6810 0x00000000);
6811 /* ICTRL */
6812 /* XXX : not implemented */
6813 spr_register(env, SPR_ICTRL, "ICTRL",
6814 SPR_NOACCESS, SPR_NOACCESS,
6815 &spr_read_generic, &spr_write_generic,
6816 0x00000000);
6817 /* MSSSR0 */
578bb252 6818 /* XXX : not implemented */
a750fc0b
JM		 6819 spr_register(env, SPR_MSSSR0, "MSSSR0",
6820 SPR_NOACCESS, SPR_NOACCESS,
6821 &spr_read_generic, &spr_write_generic,
6822 0x00000000);
6823 /* PMC */
6824 /* XXX : not implemented */
cb8b8bf8 6825 spr_register(env, SPR_7XX_PMC5, "PMC5",
a750fc0b
JM		 6826 SPR_NOACCESS, SPR_NOACCESS,
6827 &spr_read_generic, &spr_write_generic,
6828 0x00000000);
578bb252 6829 /* XXX : not implemented */
cb8b8bf8 6830 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
a750fc0b
JM		 6831 &spr_read_ureg, SPR_NOACCESS,
6832 &spr_read_ureg, SPR_NOACCESS,
6833 0x00000000);
578bb252 6834 /* XXX : not implemented */
cb8b8bf8 6835 spr_register(env, SPR_7XX_PMC6, "PMC6",
a750fc0b
JM		 6836 SPR_NOACCESS, SPR_NOACCESS,
6837 &spr_read_generic, &spr_write_generic,
6838 0x00000000);
578bb252 6839 /* XXX : not implemented */
cb8b8bf8 6840 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
a750fc0b
JM		 6841 &spr_read_ureg, SPR_NOACCESS,
6842 &spr_read_ureg, SPR_NOACCESS,
6843 0x00000000);
6844 /* Memory management */
6845 gen_low_BATs(env);
578bb252 6846 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6847 init_excp_7450(env);
d63001d1
JM		 6848 env->dcache_line_size = 32;
6849 env->icache_line_size = 32;
a750fc0b 6850 /* Allocate hardware IRQ controller */
aa5a9e24 6851 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b 6852}
a750fc0b 6853
7856e3a4
AF		 6854POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6855{
ca5dff0a 6856 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6857 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6858
ca5dff0a 6859 dc->desc = "PowerPC 7450 (aka G4)";
7856e3a4
AF		 6860 pcc->init_proc = init_proc_7450;
6861 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6862 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6863 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6864 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6865 PPC_FLOAT_STFIWX |
6866 PPC_CACHE | PPC_CACHE_ICBI |
6867 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6868 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6869 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6870 PPC_MEM_TLBIA | PPC_74xx_TLB |
6871 PPC_SEGMENT | PPC_EXTERN |
6872 PPC_ALTIVEC;
9df5a466
TM		 6873 pcc->msr_mask = (1ull << MSR_VR) |
6874 (1ull << MSR_POW) |
6875 (1ull << MSR_ILE) |
6876 (1ull << MSR_EE) |
6877 (1ull << MSR_PR) |
6878 (1ull << MSR_FP) |
6879 (1ull << MSR_ME) |
6880 (1ull << MSR_FE0) |
6881 (1ull << MSR_SE) |
6882 (1ull << MSR_DE) |
6883 (1ull << MSR_FE1) |
6884 (1ull << MSR_EP) |
6885 (1ull << MSR_IR) |
6886 (1ull << MSR_DR) |
6887 (1ull << MSR_PMM) |
6888 (1ull << MSR_RI) |
6889 (1ull << MSR_LE);
ba9fd9f1
AF		 6890 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6891 pcc->excp_model = POWERPC_EXCP_74xx;
6892 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6893 pcc->bfd_mach = bfd_mach_ppc_7400;
6894 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6895 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6896 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 6897}
6898
a750fc0b
JM		 6899static void init_proc_7445 (CPUPPCState *env)
6900{
6901 gen_spr_ne_601(env);
4f4f28ff 6902 gen_spr_sdr1(env);
a750fc0b
JM		 6903 gen_spr_7xx(env);
6904 /* Time base */
6905 gen_tbl(env);
6906 /* 74xx specific SPR */
6907 gen_spr_74xx(env);
6908 /* LDSTCR */
6909 /* XXX : not implemented */
6910 spr_register(env, SPR_LDSTCR, "LDSTCR",
6911 SPR_NOACCESS, SPR_NOACCESS,
6912 &spr_read_generic, &spr_write_generic,
6913 0x00000000);
6914 /* ICTRL */
6915 /* XXX : not implemented */
6916 spr_register(env, SPR_ICTRL, "ICTRL",
6917 SPR_NOACCESS, SPR_NOACCESS,
6918 &spr_read_generic, &spr_write_generic,
6919 0x00000000);
6920 /* MSSSR0 */
578bb252 6921 /* XXX : not implemented */
a750fc0b
JM		 6922 spr_register(env, SPR_MSSSR0, "MSSSR0",
6923 SPR_NOACCESS, SPR_NOACCESS,
6924 &spr_read_generic, &spr_write_generic,
6925 0x00000000);
6926 /* PMC */
6927 /* XXX : not implemented */
cb8b8bf8 6928 spr_register(env, SPR_7XX_PMC5, "PMC5",
a750fc0b
JM		 6929 SPR_NOACCESS, SPR_NOACCESS,
6930 &spr_read_generic, &spr_write_generic,
6931 0x00000000);
578bb252 6932 /* XXX : not implemented */
cb8b8bf8 6933 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
a750fc0b
JM		 6934 &spr_read_ureg, SPR_NOACCESS,
6935 &spr_read_ureg, SPR_NOACCESS,
6936 0x00000000);
578bb252 6937 /* XXX : not implemented */
cb8b8bf8 6938 spr_register(env, SPR_7XX_PMC6, "PMC6",
a750fc0b
JM		 6939 SPR_NOACCESS, SPR_NOACCESS,
6940 &spr_read_generic, &spr_write_generic,
6941 0x00000000);
578bb252 6942 /* XXX : not implemented */
cb8b8bf8 6943 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
a750fc0b
JM		 6944 &spr_read_ureg, SPR_NOACCESS,
6945 &spr_read_ureg, SPR_NOACCESS,
6946 0x00000000);
6947 /* SPRGs */
6948 spr_register(env, SPR_SPRG4, "SPRG4",
6949 SPR_NOACCESS, SPR_NOACCESS,
6950 &spr_read_generic, &spr_write_generic,
6951 0x00000000);
6952 spr_register(env, SPR_USPRG4, "USPRG4",
6953 &spr_read_ureg, SPR_NOACCESS,
6954 &spr_read_ureg, SPR_NOACCESS,
6955 0x00000000);
6956 spr_register(env, SPR_SPRG5, "SPRG5",
6957 SPR_NOACCESS, SPR_NOACCESS,
6958 &spr_read_generic, &spr_write_generic,
6959 0x00000000);
6960 spr_register(env, SPR_USPRG5, "USPRG5",
6961 &spr_read_ureg, SPR_NOACCESS,
6962 &spr_read_ureg, SPR_NOACCESS,
6963 0x00000000);
6964 spr_register(env, SPR_SPRG6, "SPRG6",
6965 SPR_NOACCESS, SPR_NOACCESS,
6966 &spr_read_generic, &spr_write_generic,
6967 0x00000000);
6968 spr_register(env, SPR_USPRG6, "USPRG6",
6969 &spr_read_ureg, SPR_NOACCESS,
6970 &spr_read_ureg, SPR_NOACCESS,
6971 0x00000000);
6972 spr_register(env, SPR_SPRG7, "SPRG7",
6973 SPR_NOACCESS, SPR_NOACCESS,
6974 &spr_read_generic, &spr_write_generic,
6975 0x00000000);
6976 spr_register(env, SPR_USPRG7, "USPRG7",
6977 &spr_read_ureg, SPR_NOACCESS,
6978 &spr_read_ureg, SPR_NOACCESS,
6979 0x00000000);
6980 /* Memory management */
6981 gen_low_BATs(env);
6982 gen_high_BATs(env);
578bb252 6983 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6984 init_excp_7450(env);
d63001d1
JM		 6985 env->dcache_line_size = 32;
6986 env->icache_line_size = 32;
a750fc0b 6987 /* Allocate hardware IRQ controller */
aa5a9e24 6988 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b 6989}
a750fc0b 6990
7856e3a4
AF		 6991POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6992{
ca5dff0a 6993 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 6994 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6995
ca5dff0a 6996 dc->desc = "PowerPC 7445 (aka G4)";
7856e3a4
AF		 6997 pcc->init_proc = init_proc_7445;
6998 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6999 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7000 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7001 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7002 PPC_FLOAT_STFIWX |
7003 PPC_CACHE | PPC_CACHE_ICBI |
7004 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7005 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7006 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7007 PPC_MEM_TLBIA | PPC_74xx_TLB |
7008 PPC_SEGMENT | PPC_EXTERN |
7009 PPC_ALTIVEC;
9df5a466
TM		 7010 pcc->msr_mask = (1ull << MSR_VR) |
7011 (1ull << MSR_POW) |
7012 (1ull << MSR_ILE) |
7013 (1ull << MSR_EE) |
7014 (1ull << MSR_PR) |
7015 (1ull << MSR_FP) |
7016 (1ull << MSR_ME) |
7017 (1ull << MSR_FE0) |
7018 (1ull << MSR_SE) |
7019 (1ull << MSR_DE) |
7020 (1ull << MSR_FE1) |
7021 (1ull << MSR_EP) |
7022 (1ull << MSR_IR) |
7023 (1ull << MSR_DR) |
7024 (1ull << MSR_PMM) |
7025 (1ull << MSR_RI) |
7026 (1ull << MSR_LE);
ba9fd9f1
AF		 7027 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7028 pcc->excp_model = POWERPC_EXCP_74xx;
7029 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7030 pcc->bfd_mach = bfd_mach_ppc_7400;
7031 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7032 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7033 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 7034}
7035
a750fc0b
JM		 7036static void init_proc_7455 (CPUPPCState *env)
7037{
7038 gen_spr_ne_601(env);
4f4f28ff 7039 gen_spr_sdr1(env);
a750fc0b
JM		 7040 gen_spr_7xx(env);
7041 /* Time base */
7042 gen_tbl(env);
7043 /* 74xx specific SPR */
7044 gen_spr_74xx(env);
7045 /* Level 3 cache control */
7046 gen_l3_ctrl(env);
7047 /* LDSTCR */
7048 /* XXX : not implemented */
7049 spr_register(env, SPR_LDSTCR, "LDSTCR",
7050 SPR_NOACCESS, SPR_NOACCESS,
7051 &spr_read_generic, &spr_write_generic,
7052 0x00000000);
7053 /* ICTRL */
7054 /* XXX : not implemented */
7055 spr_register(env, SPR_ICTRL, "ICTRL",
7056 SPR_NOACCESS, SPR_NOACCESS,
7057 &spr_read_generic, &spr_write_generic,
7058 0x00000000);
7059 /* MSSSR0 */
578bb252 7060 /* XXX : not implemented */
a750fc0b
JM		 7061 spr_register(env, SPR_MSSSR0, "MSSSR0",
7062 SPR_NOACCESS, SPR_NOACCESS,
7063 &spr_read_generic, &spr_write_generic,
7064 0x00000000);
7065 /* PMC */
7066 /* XXX : not implemented */
cb8b8bf8 7067 spr_register(env, SPR_7XX_PMC5, "PMC5",
a750fc0b
JM		 7068 SPR_NOACCESS, SPR_NOACCESS,
7069 &spr_read_generic, &spr_write_generic,
7070 0x00000000);
578bb252 7071 /* XXX : not implemented */
cb8b8bf8 7072 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
a750fc0b
JM		 7073 &spr_read_ureg, SPR_NOACCESS,
7074 &spr_read_ureg, SPR_NOACCESS,
7075 0x00000000);
578bb252 7076 /* XXX : not implemented */
cb8b8bf8 7077 spr_register(env, SPR_7XX_PMC6, "PMC6",
a750fc0b
JM		 7078 SPR_NOACCESS, SPR_NOACCESS,
7079 &spr_read_generic, &spr_write_generic,
7080 0x00000000);
578bb252 7081 /* XXX : not implemented */
cb8b8bf8 7082 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
a750fc0b
JM		 7083 &spr_read_ureg, SPR_NOACCESS,
7084 &spr_read_ureg, SPR_NOACCESS,
7085 0x00000000);
7086 /* SPRGs */
7087 spr_register(env, SPR_SPRG4, "SPRG4",
7088 SPR_NOACCESS, SPR_NOACCESS,
7089 &spr_read_generic, &spr_write_generic,
7090 0x00000000);
7091 spr_register(env, SPR_USPRG4, "USPRG4",
7092 &spr_read_ureg, SPR_NOACCESS,
7093 &spr_read_ureg, SPR_NOACCESS,
7094 0x00000000);
7095 spr_register(env, SPR_SPRG5, "SPRG5",
7096 SPR_NOACCESS, SPR_NOACCESS,
7097 &spr_read_generic, &spr_write_generic,
7098 0x00000000);
7099 spr_register(env, SPR_USPRG5, "USPRG5",
7100 &spr_read_ureg, SPR_NOACCESS,
7101 &spr_read_ureg, SPR_NOACCESS,
7102 0x00000000);
7103 spr_register(env, SPR_SPRG6, "SPRG6",
7104 SPR_NOACCESS, SPR_NOACCESS,
7105 &spr_read_generic, &spr_write_generic,
7106 0x00000000);
7107 spr_register(env, SPR_USPRG6, "USPRG6",
7108 &spr_read_ureg, SPR_NOACCESS,
7109 &spr_read_ureg, SPR_NOACCESS,
7110 0x00000000);
7111 spr_register(env, SPR_SPRG7, "SPRG7",
7112 SPR_NOACCESS, SPR_NOACCESS,
7113 &spr_read_generic, &spr_write_generic,
7114 0x00000000);
7115 spr_register(env, SPR_USPRG7, "USPRG7",
7116 &spr_read_ureg, SPR_NOACCESS,
7117 &spr_read_ureg, SPR_NOACCESS,
7118 0x00000000);
7119 /* Memory management */
7120 gen_low_BATs(env);
7121 gen_high_BATs(env);
578bb252 7122 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 7123 init_excp_7450(env);
d63001d1
JM		 7124 env->dcache_line_size = 32;
7125 env->icache_line_size = 32;
a750fc0b 7126 /* Allocate hardware IRQ controller */
aa5a9e24 7127 ppc6xx_irq_init(ppc_env_get_cpu(env));
a750fc0b 7128}
a750fc0b 7129
7856e3a4
AF		 7130POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7131{
ca5dff0a 7132 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 7133 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7134
ca5dff0a 7135 dc->desc = "PowerPC 7455 (aka G4)";
7856e3a4
AF		 7136 pcc->init_proc = init_proc_7455;
7137 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 7138 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7139 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7140 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7141 PPC_FLOAT_STFIWX |
7142 PPC_CACHE | PPC_CACHE_ICBI |
7143 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7144 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7145 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7146 PPC_MEM_TLBIA | PPC_74xx_TLB |
7147 PPC_SEGMENT | PPC_EXTERN |
7148 PPC_ALTIVEC;
9df5a466
TM		 7149 pcc->msr_mask = (1ull << MSR_VR) |
7150 (1ull << MSR_POW) |
7151 (1ull << MSR_ILE) |
7152 (1ull << MSR_EE) |
7153 (1ull << MSR_PR) |
7154 (1ull << MSR_FP) |
7155 (1ull << MSR_ME) |
7156 (1ull << MSR_FE0) |
7157 (1ull << MSR_SE) |
7158 (1ull << MSR_DE) |
7159 (1ull << MSR_FE1) |
7160 (1ull << MSR_EP) |
7161 (1ull << MSR_IR) |
7162 (1ull << MSR_DR) |
7163 (1ull << MSR_PMM) |
7164 (1ull << MSR_RI) |
7165 (1ull << MSR_LE);
ba9fd9f1
AF		 7166 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7167 pcc->excp_model = POWERPC_EXCP_74xx;
7168 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7169 pcc->bfd_mach = bfd_mach_ppc_7400;
7170 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7171 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7172 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 7173}
7174
4e777442
JM		 7175static void init_proc_7457 (CPUPPCState *env)
7176{
7177 gen_spr_ne_601(env);
4f4f28ff 7178 gen_spr_sdr1(env);
4e777442
JM		 7179 gen_spr_7xx(env);
7180 /* Time base */
7181 gen_tbl(env);
7182 /* 74xx specific SPR */
7183 gen_spr_74xx(env);
7184 /* Level 3 cache control */
7185 gen_l3_ctrl(env);
7186 /* L3ITCR1 */
7187 /* XXX : not implemented */
7188 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7189 SPR_NOACCESS, SPR_NOACCESS,
7190 &spr_read_generic, &spr_write_generic,
7191 0x00000000);
7192 /* L3ITCR2 */
7193 /* XXX : not implemented */
7194 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7195 SPR_NOACCESS, SPR_NOACCESS,
7196 &spr_read_generic, &spr_write_generic,
7197 0x00000000);
7198 /* L3ITCR3 */
7199 /* XXX : not implemented */
7200 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7201 SPR_NOACCESS, SPR_NOACCESS,
7202 &spr_read_generic, &spr_write_generic,
7203 0x00000000);
7204 /* L3OHCR */
7205 /* XXX : not implemented */
7206 spr_register(env, SPR_L3OHCR, "L3OHCR",
7207 SPR_NOACCESS, SPR_NOACCESS,
7208 &spr_read_generic, &spr_write_generic,
7209 0x00000000);
7210 /* LDSTCR */
7211 /* XXX : not implemented */
7212 spr_register(env, SPR_LDSTCR, "LDSTCR",
7213 SPR_NOACCESS, SPR_NOACCESS,
7214 &spr_read_generic, &spr_write_generic,
7215 0x00000000);
7216 /* ICTRL */
7217 /* XXX : not implemented */
7218 spr_register(env, SPR_ICTRL, "ICTRL",
7219 SPR_NOACCESS, SPR_NOACCESS,
7220 &spr_read_generic, &spr_write_generic,
7221 0x00000000);
7222 /* MSSSR0 */
7223 /* XXX : not implemented */
7224 spr_register(env, SPR_MSSSR0, "MSSSR0",
7225 SPR_NOACCESS, SPR_NOACCESS,
7226 &spr_read_generic, &spr_write_generic,
7227 0x00000000);
7228 /* PMC */
7229 /* XXX : not implemented */
cb8b8bf8 7230 spr_register(env, SPR_7XX_PMC5, "PMC5",
4e777442
JM		 7231 SPR_NOACCESS, SPR_NOACCESS,
7232 &spr_read_generic, &spr_write_generic,
7233 0x00000000);
7234 /* XXX : not implemented */
cb8b8bf8 7235 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4e777442
JM		 7236 &spr_read_ureg, SPR_NOACCESS,
7237 &spr_read_ureg, SPR_NOACCESS,
7238 0x00000000);
7239 /* XXX : not implemented */
cb8b8bf8 7240 spr_register(env, SPR_7XX_PMC6, "PMC6",
4e777442
JM		 7241 SPR_NOACCESS, SPR_NOACCESS,
7242 &spr_read_generic, &spr_write_generic,
7243 0x00000000);
7244 /* XXX : not implemented */
cb8b8bf8 7245 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4e777442
JM		 7246 &spr_read_ureg, SPR_NOACCESS,
7247 &spr_read_ureg, SPR_NOACCESS,
7248 0x00000000);
7249 /* SPRGs */
7250 spr_register(env, SPR_SPRG4, "SPRG4",
7251 SPR_NOACCESS, SPR_NOACCESS,
7252 &spr_read_generic, &spr_write_generic,
7253 0x00000000);
7254 spr_register(env, SPR_USPRG4, "USPRG4",
7255 &spr_read_ureg, SPR_NOACCESS,
7256 &spr_read_ureg, SPR_NOACCESS,
7257 0x00000000);
7258 spr_register(env, SPR_SPRG5, "SPRG5",
7259 SPR_NOACCESS, SPR_NOACCESS,
7260 &spr_read_generic, &spr_write_generic,
7261 0x00000000);
7262 spr_register(env, SPR_USPRG5, "USPRG5",
7263 &spr_read_ureg, SPR_NOACCESS,
7264 &spr_read_ureg, SPR_NOACCESS,
7265 0x00000000);
7266 spr_register(env, SPR_SPRG6, "SPRG6",
7267 SPR_NOACCESS, SPR_NOACCESS,
7268 &spr_read_generic, &spr_write_generic,
7269 0x00000000);
7270 spr_register(env, SPR_USPRG6, "USPRG6",
7271 &spr_read_ureg, SPR_NOACCESS,
7272 &spr_read_ureg, SPR_NOACCESS,
7273 0x00000000);
7274 spr_register(env, SPR_SPRG7, "SPRG7",
7275 SPR_NOACCESS, SPR_NOACCESS,
7276 &spr_read_generic, &spr_write_generic,
7277 0x00000000);
7278 spr_register(env, SPR_USPRG7, "USPRG7",
7279 &spr_read_ureg, SPR_NOACCESS,
7280 &spr_read_ureg, SPR_NOACCESS,
7281 0x00000000);
7282 /* Memory management */
7283 gen_low_BATs(env);
7284 gen_high_BATs(env);
7285 gen_74xx_soft_tlb(env, 128, 2);
7286 init_excp_7450(env);
7287 env->dcache_line_size = 32;
7288 env->icache_line_size = 32;
7289 /* Allocate hardware IRQ controller */
aa5a9e24 7290 ppc6xx_irq_init(ppc_env_get_cpu(env));
4e777442
JM		 7291}
7292
7856e3a4
AF		 7293POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7294{
ca5dff0a 7295 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 7296 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7297
ca5dff0a 7298 dc->desc = "PowerPC 7457 (aka G4)";
7856e3a4
AF		 7299 pcc->init_proc = init_proc_7457;
7300 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 7301 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7302 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7303 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7304 PPC_FLOAT_STFIWX |
7305 PPC_CACHE | PPC_CACHE_ICBI |
7306 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7307 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7308 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7309 PPC_MEM_TLBIA | PPC_74xx_TLB |
7310 PPC_SEGMENT | PPC_EXTERN |
7311 PPC_ALTIVEC;
9df5a466
TM		 7312 pcc->msr_mask = (1ull << MSR_VR) |
7313 (1ull << MSR_POW) |
7314 (1ull << MSR_ILE) |
7315 (1ull << MSR_EE) |
7316 (1ull << MSR_PR) |
7317 (1ull << MSR_FP) |
7318 (1ull << MSR_ME) |
7319 (1ull << MSR_FE0) |
7320 (1ull << MSR_SE) |
7321 (1ull << MSR_DE) |
7322 (1ull << MSR_FE1) |
7323 (1ull << MSR_EP) |
7324 (1ull << MSR_IR) |
7325 (1ull << MSR_DR) |
7326 (1ull << MSR_PMM) |
7327 (1ull << MSR_RI) |
7328 (1ull << MSR_LE);
ba9fd9f1
AF		 7329 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7330 pcc->excp_model = POWERPC_EXCP_74xx;
7331 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7332 pcc->bfd_mach = bfd_mach_ppc_7400;
7333 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7334 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7335 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 7336}
7337
7162bdea
JG		 7338static void init_proc_e600 (CPUPPCState *env)
7339{
7340 gen_spr_ne_601(env);
4f4f28ff 7341 gen_spr_sdr1(env);
7162bdea
JG		 7342 gen_spr_7xx(env);
7343 /* Time base */
7344 gen_tbl(env);
7345 /* 74xx specific SPR */
7346 gen_spr_74xx(env);
7347 /* XXX : not implemented */
7348 spr_register(env, SPR_UBAMR, "UBAMR",
7349 &spr_read_ureg, SPR_NOACCESS,
7350 &spr_read_ureg, SPR_NOACCESS,
7351 0x00000000);
7352 /* XXX : not implemented */
7353 spr_register(env, SPR_LDSTCR, "LDSTCR",
7354 SPR_NOACCESS, SPR_NOACCESS,
7355 &spr_read_generic, &spr_write_generic,
7356 0x00000000);
7357 /* XXX : not implemented */
7358 spr_register(env, SPR_ICTRL, "ICTRL",
7359 SPR_NOACCESS, SPR_NOACCESS,
7360 &spr_read_generic, &spr_write_generic,
7361 0x00000000);
7362 /* XXX : not implemented */
7363 spr_register(env, SPR_MSSSR0, "MSSSR0",
7364 SPR_NOACCESS, SPR_NOACCESS,
7365 &spr_read_generic, &spr_write_generic,
7366 0x00000000);
7367 /* XXX : not implemented */
cb8b8bf8 7368 spr_register(env, SPR_7XX_PMC5, "PMC5",
7162bdea
JG		 7369 SPR_NOACCESS, SPR_NOACCESS,
7370 &spr_read_generic, &spr_write_generic,
7371 0x00000000);
7372 /* XXX : not implemented */
cb8b8bf8 7373 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7162bdea
JG		 7374 &spr_read_ureg, SPR_NOACCESS,
7375 &spr_read_ureg, SPR_NOACCESS,
7376 0x00000000);
7377 /* XXX : not implemented */
cb8b8bf8 7378 spr_register(env, SPR_7XX_PMC6, "PMC6",
7162bdea
JG		 7379 SPR_NOACCESS, SPR_NOACCESS,
7380 &spr_read_generic, &spr_write_generic,
7381 0x00000000);
7382 /* XXX : not implemented */
cb8b8bf8 7383 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7162bdea
JG		 7384 &spr_read_ureg, SPR_NOACCESS,
7385 &spr_read_ureg, SPR_NOACCESS,
7386 0x00000000);
7387 /* SPRGs */
7388 spr_register(env, SPR_SPRG4, "SPRG4",
7389 SPR_NOACCESS, SPR_NOACCESS,
7390 &spr_read_generic, &spr_write_generic,
7391 0x00000000);
7392 spr_register(env, SPR_USPRG4, "USPRG4",
7393 &spr_read_ureg, SPR_NOACCESS,
7394 &spr_read_ureg, SPR_NOACCESS,
7395 0x00000000);
7396 spr_register(env, SPR_SPRG5, "SPRG5",
7397 SPR_NOACCESS, SPR_NOACCESS,
7398 &spr_read_generic, &spr_write_generic,
7399 0x00000000);
7400 spr_register(env, SPR_USPRG5, "USPRG5",
7401 &spr_read_ureg, SPR_NOACCESS,
7402 &spr_read_ureg, SPR_NOACCESS,
7403 0x00000000);
7404 spr_register(env, SPR_SPRG6, "SPRG6",
7405 SPR_NOACCESS, SPR_NOACCESS,
7406 &spr_read_generic, &spr_write_generic,
7407 0x00000000);
7408 spr_register(env, SPR_USPRG6, "USPRG6",
7409 &spr_read_ureg, SPR_NOACCESS,
7410 &spr_read_ureg, SPR_NOACCESS,
7411 0x00000000);
7412 spr_register(env, SPR_SPRG7, "SPRG7",
7413 SPR_NOACCESS, SPR_NOACCESS,
7414 &spr_read_generic, &spr_write_generic,
7415 0x00000000);
7416 spr_register(env, SPR_USPRG7, "USPRG7",
7417 &spr_read_ureg, SPR_NOACCESS,
7418 &spr_read_ureg, SPR_NOACCESS,
7419 0x00000000);
7420 /* Memory management */
7421 gen_low_BATs(env);
7422 gen_high_BATs(env);
7423 gen_74xx_soft_tlb(env, 128, 2);
7424 init_excp_7450(env);
7425 env->dcache_line_size = 32;
7426 env->icache_line_size = 32;
7427 /* Allocate hardware IRQ controller */
aa5a9e24 7428 ppc6xx_irq_init(ppc_env_get_cpu(env));
7162bdea
JG		 7429}
7430
7431POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7432{
7433 DeviceClass *dc = DEVICE_CLASS(oc);
7434 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7435
7436 dc->desc = "PowerPC e600";
7437 pcc->init_proc = init_proc_e600;
7438 pcc->check_pow = check_pow_hid0_74xx;
7439 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7440 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7441 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7442 PPC_FLOAT_STFIWX |
7443 PPC_CACHE | PPC_CACHE_ICBI |
7444 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7445 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7446 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7447 PPC_MEM_TLBIA | PPC_74xx_TLB |
7448 PPC_SEGMENT | PPC_EXTERN |
7449 PPC_ALTIVEC;
7450 pcc->insns_flags2 = PPC_NONE;
9df5a466
TM		 7451 pcc->msr_mask = (1ull << MSR_VR) |
7452 (1ull << MSR_POW) |
7453 (1ull << MSR_ILE) |
7454 (1ull << MSR_EE) |
7455 (1ull << MSR_PR) |
7456 (1ull << MSR_FP) |
7457 (1ull << MSR_ME) |
7458 (1ull << MSR_FE0) |
7459 (1ull << MSR_SE) |
7460 (1ull << MSR_DE) |
7461 (1ull << MSR_FE1) |
7462 (1ull << MSR_EP) |
7463 (1ull << MSR_IR) |
7464 (1ull << MSR_DR) |
7465 (1ull << MSR_PMM) |
7466 (1ull << MSR_RI) |
7467 (1ull << MSR_LE);
7162bdea
JG		 7468 pcc->mmu_model = POWERPC_MMU_32B;
7469#if defined(CONFIG_SOFTMMU)
7470 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7471#endif
7472 pcc->excp_model = POWERPC_EXCP_74xx;
7473 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7474 pcc->bfd_mach = bfd_mach_ppc_7400;
7475 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7476 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7477 POWERPC_FLAG_BUS_CLK;
7478}
7479
a750fc0b 7480#if defined (TARGET_PPC64)
417bf010
JM		 7481#if defined(CONFIG_USER_ONLY)
7482#define POWERPC970_HID5_INIT 0x00000080
7483#else
7484#define POWERPC970_HID5_INIT 0x00000000
7485#endif
7486
69b058c8
PB		 7487static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7488 int bit, int sprn, int cause)
45ed0be1
AK		 7489{
7490 TCGv_i32 t1 = tcg_const_i32(bit);
7491 TCGv_i32 t2 = tcg_const_i32(sprn);
7492 TCGv_i32 t3 = tcg_const_i32(cause);
7493
45ed0be1
AK		 7494 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7495
7496 tcg_temp_free_i32(t3);
7497 tcg_temp_free_i32(t2);
7498 tcg_temp_free_i32(t1);
7499}
7500
69b058c8
PB		 7501static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7502 int bit, int sprn, int cause)
cdcdda27
AK		 7503{
7504 TCGv_i32 t1 = tcg_const_i32(bit);
7505 TCGv_i32 t2 = tcg_const_i32(sprn);
7506 TCGv_i32 t3 = tcg_const_i32(cause);
7507
cdcdda27
AK		 7508 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7509
7510 tcg_temp_free_i32(t3);
7511 tcg_temp_free_i32(t2);
7512 tcg_temp_free_i32(t1);
7513}
7514
69b058c8 7515static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
cdcdda27
AK		 7516{
7517 TCGv spr_up = tcg_temp_new();
7518 TCGv spr = tcg_temp_new();
7519
7520 gen_load_spr(spr, sprn - 1);
7521 tcg_gen_shri_tl(spr_up, spr, 32);
7522 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7523
7524 tcg_temp_free(spr);
7525 tcg_temp_free(spr_up);
7526}
7527
69b058c8 7528static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
cdcdda27
AK		 7529{
7530 TCGv spr = tcg_temp_new();
7531
7532 gen_load_spr(spr, sprn - 1);
7533 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7534 gen_store_spr(sprn - 1, spr);
7535
7536 tcg_temp_free(spr);
7537}
7538
2f462816
JM		 7539static int check_pow_970 (CPUPPCState *env)
7540{
bbc01ca7 7541 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
2f462816 7542 return 1;
bbc01ca7 7543 }
2f462816
JM		 7544
7545 return 0;
7546}
7547
42382f62 7548static void gen_spr_970_hid(CPUPPCState *env)
a750fc0b 7549{
a750fc0b
JM		 7550 /* Hardware implementation registers */
7551 /* XXX : not implemented */
7552 spr_register(env, SPR_HID0, "HID0",
7553 SPR_NOACCESS, SPR_NOACCESS,
06403421 7554 &spr_read_generic, &spr_write_clear,
d63001d1 7555 0x60000000);
a750fc0b
JM		 7556 spr_register(env, SPR_HID1, "HID1",
7557 SPR_NOACCESS, SPR_NOACCESS,
7558 &spr_read_generic, &spr_write_generic,
7559 0x00000000);
e57448f1
JM		 7560 spr_register(env, SPR_970_HID5, "HID5",
7561 SPR_NOACCESS, SPR_NOACCESS,
7562 &spr_read_generic, &spr_write_generic,
417bf010 7563 POWERPC970_HID5_INIT);
42382f62
AK		 7564}
7565
7566static void gen_spr_970_hior(CPUPPCState *env)
7567{
12de9a39
JM		 7568 spr_register(env, SPR_HIOR, "SPR_HIOR",
7569 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 7570 &spr_read_hior, &spr_write_hior,
7571 0x00000000);
42382f62 7572}
7856e3a4 7573
4f4f28ff 7574static void gen_spr_book3s_ctrl(CPUPPCState *env)
42382f62 7575{
4e98d8cf
BS		 7576 spr_register(env, SPR_CTRL, "SPR_CTRL",
7577 SPR_NOACCESS, SPR_NOACCESS,
4e381819 7578 SPR_NOACCESS, &spr_write_generic,
4e98d8cf
BS		 7579 0x00000000);
7580 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
eb16dd9c
AK		 7581 &spr_read_ureg, SPR_NOACCESS,
7582 &spr_read_ureg, SPR_NOACCESS,
4e98d8cf 7583 0x00000000);
42382f62
AK		 7584}
7585
7586static void gen_spr_book3s_altivec(CPUPPCState *env)
7587{
7588 if (!(env->insns_flags & PPC_ALTIVEC)) {
7589 return;
7590 }
7591
7303f83d
AK		 7592 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7593 &spr_read_generic, &spr_write_generic,
7594 &spr_read_generic, &spr_write_generic,
7595 KVM_REG_PPC_VRSAVE, 0x00000000);
42382f62
AK		 7596
7597 /* Can't find information on what this should be on reset. This
7598 * value is the one used by 74xx processors. */
7599 vscr_init(env, 0x00010000);
7600}
7601
fd51ff63
AK		 7602static void gen_spr_book3s_dbg(CPUPPCState *env)
7603{
cd9adfdd
AK		 7604 /*
7605 * TODO: different specs define different scopes for these,
7606 * will have to address this:
7607 * 970: super/write and super/read
7608 * powerisa 2.03..2.04: hypv/write and super/read.
7609 * powerisa 2.05 and newer: hypv/write and hypv/read.
7610 */
fd51ff63
AK		 7611 spr_register_kvm(env, SPR_DABR, "DABR",
7612 SPR_NOACCESS, SPR_NOACCESS,
7613 &spr_read_generic, &spr_write_generic,
7614 KVM_REG_PPC_DABR, 0x00000000);
cd9adfdd
AK		 7615 spr_register_kvm(env, SPR_DABRX, "DABRX",
7616 SPR_NOACCESS, SPR_NOACCESS,
7617 &spr_read_generic, &spr_write_generic,
7618 KVM_REG_PPC_DABRX, 0x00000000);
fd51ff63
AK		 7619}
7620
f401dd32
BH		 7621static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7622{
7623 spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7624 SPR_NOACCESS, SPR_NOACCESS,
7625 SPR_NOACCESS, SPR_NOACCESS,
7626 &spr_read_generic, &spr_write_generic,
7627 KVM_REG_PPC_DAWR, 0x00000000);
7628 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7629 SPR_NOACCESS, SPR_NOACCESS,
7630 SPR_NOACCESS, SPR_NOACCESS,
7631 &spr_read_generic, &spr_write_generic,
7632 KVM_REG_PPC_DAWRX, 0x00000000);
eb5ceb4d
BH		 7633 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7634 SPR_NOACCESS, SPR_NOACCESS,
7635 SPR_NOACCESS, SPR_NOACCESS,
7636 &spr_read_generic, &spr_write_generic,
7637 KVM_REG_PPC_CIABR, 0x00000000);
f401dd32
BH		 7638}
7639
fd51ff63
AK		 7640static void gen_spr_970_dbg(CPUPPCState *env)
7641{
7642 /* Breakpoints */
7643 spr_register(env, SPR_IABR, "IABR",
7644 SPR_NOACCESS, SPR_NOACCESS,
7645 &spr_read_generic, &spr_write_generic,
7646 0x00000000);
7647}
7648
7649static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7650{
83cc6f8c
AK		 7651 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7652 SPR_NOACCESS, SPR_NOACCESS,
7653 &spr_read_generic, &spr_write_generic,
7654 KVM_REG_PPC_MMCR0, 0x00000000);
7655 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7656 SPR_NOACCESS, SPR_NOACCESS,
7657 &spr_read_generic, &spr_write_generic,
7658 KVM_REG_PPC_MMCR1, 0x00000000);
7659 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7660 SPR_NOACCESS, SPR_NOACCESS,
7661 &spr_read_generic, &spr_write_generic,
7662 KVM_REG_PPC_MMCRA, 0x00000000);
7663 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7664 SPR_NOACCESS, SPR_NOACCESS,
7665 &spr_read_generic, &spr_write_generic,
7666 KVM_REG_PPC_PMC1, 0x00000000);
7667 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7668 SPR_NOACCESS, SPR_NOACCESS,
7669 &spr_read_generic, &spr_write_generic,
7670 KVM_REG_PPC_PMC2, 0x00000000);
7671 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7672 SPR_NOACCESS, SPR_NOACCESS,
7673 &spr_read_generic, &spr_write_generic,
7674 KVM_REG_PPC_PMC3, 0x00000000);
7675 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7676 SPR_NOACCESS, SPR_NOACCESS,
7677 &spr_read_generic, &spr_write_generic,
7678 KVM_REG_PPC_PMC4, 0x00000000);
7679 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7680 SPR_NOACCESS, SPR_NOACCESS,
7681 &spr_read_generic, &spr_write_generic,
7682 KVM_REG_PPC_PMC5, 0x00000000);
7683 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7684 SPR_NOACCESS, SPR_NOACCESS,
7685 &spr_read_generic, &spr_write_generic,
7686 KVM_REG_PPC_PMC6, 0x00000000);
7687 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7688 SPR_NOACCESS, SPR_NOACCESS,
7689 &spr_read_generic, &spr_write_generic,
7690 KVM_REG_PPC_SIAR, 0x00000000);
7691 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7692 SPR_NOACCESS, SPR_NOACCESS,
7693 &spr_read_generic, &spr_write_generic,
7694 KVM_REG_PPC_SDAR, 0x00000000);
fd51ff63
AK		 7695}
7696
7697static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7698{
7699 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7700 &spr_read_ureg, SPR_NOACCESS,
7701 &spr_read_ureg, &spr_write_ureg,
7702 0x00000000);
7703 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7704 &spr_read_ureg, SPR_NOACCESS,
7705 &spr_read_ureg, &spr_write_ureg,
7706 0x00000000);
077850b0
AK		 7707 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7708 &spr_read_ureg, SPR_NOACCESS,
7709 &spr_read_ureg, &spr_write_ureg,
7710 0x00000000);
fd51ff63
AK		 7711 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7712 &spr_read_ureg, SPR_NOACCESS,
7713 &spr_read_ureg, &spr_write_ureg,
7714 0x00000000);
7715 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7716 &spr_read_ureg, SPR_NOACCESS,
7717 &spr_read_ureg, &spr_write_ureg,
7718 0x00000000);
7719 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7720 &spr_read_ureg, SPR_NOACCESS,
7721 &spr_read_ureg, &spr_write_ureg,
7722 0x00000000);
7723 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7724 &spr_read_ureg, SPR_NOACCESS,
7725 &spr_read_ureg, &spr_write_ureg,
7726 0x00000000);
077850b0
AK		 7727 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7728 &spr_read_ureg, SPR_NOACCESS,
7729 &spr_read_ureg, &spr_write_ureg,
7730 0x00000000);
7731 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7732 &spr_read_ureg, SPR_NOACCESS,
7733 &spr_read_ureg, &spr_write_ureg,
7734 0x00000000);
fd51ff63
AK		 7735 spr_register(env, SPR_POWER_USIAR, "USIAR",
7736 &spr_read_ureg, SPR_NOACCESS,
7737 &spr_read_ureg, &spr_write_ureg,
7738 0x00000000);
077850b0
AK		 7739 spr_register(env, SPR_POWER_USDAR, "USDAR",
7740 &spr_read_ureg, SPR_NOACCESS,
7741 &spr_read_ureg, &spr_write_ureg,
7742 0x00000000);
fd51ff63
AK		 7743}
7744
c36c97f8
AK		 7745static void gen_spr_970_pmu_sup(CPUPPCState *env)
7746{
83cc6f8c
AK		 7747 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7748 SPR_NOACCESS, SPR_NOACCESS,
7749 &spr_read_generic, &spr_write_generic,
7750 KVM_REG_PPC_PMC7, 0x00000000);
7751 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7752 SPR_NOACCESS, SPR_NOACCESS,
7753 &spr_read_generic, &spr_write_generic,
7754 KVM_REG_PPC_PMC8, 0x00000000);
c36c97f8
AK		 7755}
7756
7757static void gen_spr_970_pmu_user(CPUPPCState *env)
7758{
7759 spr_register(env, SPR_970_UPMC7, "UPMC7",
7760 &spr_read_ureg, SPR_NOACCESS,
7761 &spr_read_ureg, &spr_write_ureg,
7762 0x00000000);
7763 spr_register(env, SPR_970_UPMC8, "UPMC8",
7764 &spr_read_ureg, SPR_NOACCESS,
7765 &spr_read_ureg, &spr_write_ureg,
7766 0x00000000);
7767}
7768
70c53407
AK		 7769static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7770{
7771 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7772 SPR_NOACCESS, SPR_NOACCESS,
7773 &spr_read_generic, &spr_write_generic,
7774 KVM_REG_PPC_MMCR2, 0x00000000);
7775 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7776 SPR_NOACCESS, SPR_NOACCESS,
7777 &spr_read_generic, &spr_write_generic,
7778 KVM_REG_PPC_MMCRS, 0x00000000);
14646457
BH		 7779 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7780 SPR_NOACCESS, SPR_NOACCESS,
7781 &spr_read_generic, &spr_write_generic,
7782 KVM_REG_PPC_SIER, 0x00000000);
7783 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7784 SPR_NOACCESS, SPR_NOACCESS,
7785 &spr_read_generic, &spr_write_generic,
7786 KVM_REG_PPC_SPMC1, 0x00000000);
7787 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7788 SPR_NOACCESS, SPR_NOACCESS,
7789 &spr_read_generic, &spr_write_generic,
7790 KVM_REG_PPC_SPMC2, 0x00000000);
7791 spr_register_kvm(env, SPR_TACR, "TACR",
7792 SPR_NOACCESS, SPR_NOACCESS,
7793 &spr_read_generic, &spr_write_generic,
7794 KVM_REG_PPC_TACR, 0x00000000);
7795 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7796 SPR_NOACCESS, SPR_NOACCESS,
7797 &spr_read_generic, &spr_write_generic,
7798 KVM_REG_PPC_TCSCR, 0x00000000);
7799 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7800 SPR_NOACCESS, SPR_NOACCESS,
7801 &spr_read_generic, &spr_write_generic,
7802 KVM_REG_PPC_CSIGR, 0x00000000);
70c53407
AK		 7803}
7804
7805static void gen_spr_power8_pmu_user(CPUPPCState *env)
7806{
7807 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7808 &spr_read_ureg, SPR_NOACCESS,
7809 &spr_read_ureg, &spr_write_ureg,
7810 0x00000000);
14646457
BH		 7811 spr_register(env, SPR_POWER_USIER, "USIER",
7812 &spr_read_generic, SPR_NOACCESS,
7813 &spr_read_generic, &spr_write_generic,
7814 0x00000000);
70c53407
AK		 7815}
7816
fd51ff63
AK		 7817static void gen_spr_power5p_ear(CPUPPCState *env)
7818{
7819 /* External access control */
7820 spr_register(env, SPR_EAR, "EAR",
7821 SPR_NOACCESS, SPR_NOACCESS,
7822 &spr_read_generic, &spr_write_generic,
7823 0x00000000);
7824}
7825
8eeb330c
BH		 7826#if !defined(CONFIG_USER_ONLY)
7827static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
7828{
7829 TCGv hmer = tcg_temp_new();
7830
7831 gen_load_spr(hmer, sprn);
7832 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
7833 gen_store_spr(sprn, hmer);
7834 spr_store_dump_spr(sprn);
7835 tcg_temp_free(hmer);
7836}
4b3fc377
BH		 7837
7838static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
7839{
7840 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7841}
7842
7843static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
7844{
7845#if defined(TARGET_PPC64)
7846 spr_write_generic(ctx, sprn, gprn);
7847 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7848#endif
7849}
7850
7851#endif /* !defined(CONFIG_USER_ONLY) */
7852
7853static void gen_spr_970_lpar(CPUPPCState *env)
7854{
7855#if !defined(CONFIG_USER_ONLY)
7856 /* Logical partitionning */
7857 /* PPC970: HID4 is effectively the LPCR */
7858 spr_register(env, SPR_970_HID4, "HID4",
7859 SPR_NOACCESS, SPR_NOACCESS,
7860 &spr_read_generic, &spr_write_970_hid4,
7861 0x00000000);
7862#endif
7863}
7864
7865static void gen_spr_power5p_lpar(CPUPPCState *env)
7866{
7867#if !defined(CONFIG_USER_ONLY)
7868 /* Logical partitionning */
635dff20
BH		 7869 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7870 SPR_NOACCESS, SPR_NOACCESS,
7871 SPR_NOACCESS, SPR_NOACCESS,
7872 &spr_read_generic, &spr_write_lpcr,
7873 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
4b236b62
BH		 7874 spr_register_hv(env, SPR_HDEC, "HDEC",
7875 SPR_NOACCESS, SPR_NOACCESS,
7876 SPR_NOACCESS, SPR_NOACCESS,
7877 &spr_read_hdecr, &spr_write_hdecr, 0);
8eeb330c 7878#endif
4b3fc377 7879}
8eeb330c 7880
e61716aa
AK		 7881static void gen_spr_book3s_ids(CPUPPCState *env)
7882{
8eeb330c
BH		 7883 /* FIXME: Will need to deal with thread vs core only SPRs */
7884
e61716aa 7885 /* Processor identification */
8eeb330c 7886 spr_register_hv(env, SPR_PIR, "PIR",
e61716aa 7887 SPR_NOACCESS, SPR_NOACCESS,
8eeb330c
BH		 7888 SPR_NOACCESS, SPR_NOACCESS,
7889 &spr_read_generic, NULL,
7890 0x00000000);
7891 spr_register_hv(env, SPR_HID0, "HID0",
7892 SPR_NOACCESS, SPR_NOACCESS,
7893 SPR_NOACCESS, SPR_NOACCESS,
7894 &spr_read_generic, &spr_write_generic,
7895 0x00000000);
7896 spr_register_hv(env, SPR_TSCR, "TSCR",
7897 SPR_NOACCESS, SPR_NOACCESS,
7898 SPR_NOACCESS, SPR_NOACCESS,
7899 &spr_read_generic, &spr_write_generic,
7900 0x00000000);
7901 spr_register_hv(env, SPR_HMER, "HMER",
7902 SPR_NOACCESS, SPR_NOACCESS,
7903 SPR_NOACCESS, SPR_NOACCESS,
7904 &spr_read_generic, &spr_write_hmer,
7905 0x00000000);
7906 spr_register_hv(env, SPR_HMEER, "HMEER",
7907 SPR_NOACCESS, SPR_NOACCESS,
7908 SPR_NOACCESS, SPR_NOACCESS,
7909 &spr_read_generic, &spr_write_generic,
7910 0x00000000);
7911 spr_register_hv(env, SPR_TFMR, "TFMR",
7912 SPR_NOACCESS, SPR_NOACCESS,
7913 SPR_NOACCESS, SPR_NOACCESS,
7914 &spr_read_generic, &spr_write_generic,
7915 0x00000000);
7916 spr_register_hv(env, SPR_LPIDR, "LPIDR",
7917 SPR_NOACCESS, SPR_NOACCESS,
7918 SPR_NOACCESS, SPR_NOACCESS,
7919 &spr_read_generic, &spr_write_generic,
7920 0x00000000);
7921 spr_register_hv(env, SPR_HFSCR, "HFSCR",
7922 SPR_NOACCESS, SPR_NOACCESS,
7923 SPR_NOACCESS, SPR_NOACCESS,
7924 &spr_read_generic, &spr_write_generic,
7925 0x00000000);
7926 spr_register_hv(env, SPR_MMCRC, "MMCRC",
7927 SPR_NOACCESS, SPR_NOACCESS,
7928 SPR_NOACCESS, SPR_NOACCESS,
7929 &spr_read_generic, &spr_write_generic,
7930 0x00000000);
7931 spr_register_hv(env, SPR_MMCRH, "MMCRH",
7932 SPR_NOACCESS, SPR_NOACCESS,
7933 SPR_NOACCESS, SPR_NOACCESS,
7934 &spr_read_generic, &spr_write_generic,
7935 0x00000000);
7936 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7937 SPR_NOACCESS, SPR_NOACCESS,
7938 SPR_NOACCESS, SPR_NOACCESS,
7939 &spr_read_generic, &spr_write_generic,
7940 0x00000000);
7941 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7942 SPR_NOACCESS, SPR_NOACCESS,
7943 SPR_NOACCESS, SPR_NOACCESS,
7944 &spr_read_generic, &spr_write_generic,
7945 0x00000000);
7946 spr_register_hv(env, SPR_HSRR0, "HSRR0",
7947 SPR_NOACCESS, SPR_NOACCESS,
7948 SPR_NOACCESS, SPR_NOACCESS,
7949 &spr_read_generic, &spr_write_generic,
7950 0x00000000);
7951 spr_register_hv(env, SPR_HSRR1, "HSRR1",
7952 SPR_NOACCESS, SPR_NOACCESS,
7953 SPR_NOACCESS, SPR_NOACCESS,
7954 &spr_read_generic, &spr_write_generic,
7955 0x00000000);
7956 spr_register_hv(env, SPR_HDAR, "HDAR",
7957 SPR_NOACCESS, SPR_NOACCESS,
7958 SPR_NOACCESS, SPR_NOACCESS,
7959 &spr_read_generic, &spr_write_generic,
7960 0x00000000);
7961 spr_register_hv(env, SPR_HDSISR, "HDSISR",
7962 SPR_NOACCESS, SPR_NOACCESS,
7963 SPR_NOACCESS, SPR_NOACCESS,
7964 &spr_read_generic, &spr_write_generic,
7965 0x00000000);
7966 spr_register_hv(env, SPR_RMOR, "RMOR",
7967 SPR_NOACCESS, SPR_NOACCESS,
7968 SPR_NOACCESS, SPR_NOACCESS,
7969 &spr_read_generic, &spr_write_generic,
7970 0x00000000);
7971 spr_register_hv(env, SPR_HRMOR, "HRMOR",
7972 SPR_NOACCESS, SPR_NOACCESS,
7973 SPR_NOACCESS, SPR_NOACCESS,
7974 &spr_read_generic, &spr_write_generic,
e61716aa
AK		 7975 0x00000000);
7976}
7977
d1a721ab
AK		 7978static void gen_spr_power8_ids(CPUPPCState *env)
7979{
7980 /* Thread identification */
7981 spr_register(env, SPR_TIR, "TIR",
7982 SPR_NOACCESS, SPR_NOACCESS,
7983 &spr_read_generic, SPR_NOACCESS,
7984 0x00000000);
7985}
7986
e61716aa
AK		 7987static void gen_spr_book3s_purr(CPUPPCState *env)
7988{
7989#if !defined(CONFIG_USER_ONLY)
7990 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7991 spr_register_kvm(env, SPR_PURR, "PURR",
7992 &spr_read_purr, SPR_NOACCESS,
7993 &spr_read_purr, SPR_NOACCESS,
7994 KVM_REG_PPC_PURR, 0x00000000);
7995 spr_register_kvm(env, SPR_SPURR, "SPURR",
7996 &spr_read_purr, SPR_NOACCESS,
7997 &spr_read_purr, SPR_NOACCESS,
7998 KVM_REG_PPC_SPURR, 0x00000000);
7999#endif
8000}
8001
5db7d4fa
AK		 8002static void gen_spr_power6_dbg(CPUPPCState *env)
8003{
8004#if !defined(CONFIG_USER_ONLY)
8005 spr_register(env, SPR_CFAR, "SPR_CFAR",
8006 SPR_NOACCESS, SPR_NOACCESS,
8007 &spr_read_cfar, &spr_write_cfar,
8008 0x00000000);
8009#endif
8010}
8011
8012static void gen_spr_power5p_common(CPUPPCState *env)
8013{
7303f83d
AK		 8014 spr_register_kvm(env, SPR_PPR, "PPR",
8015 &spr_read_generic, &spr_write_generic,
8016 &spr_read_generic, &spr_write_generic,
8017 KVM_REG_PPC_PPR, 0x00000000);
5db7d4fa
AK		 8018}
8019
8020static void gen_spr_power6_common(CPUPPCState *env)
8021{
8022#if !defined(CONFIG_USER_ONLY)
8023 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
8024 SPR_NOACCESS, SPR_NOACCESS,
8025 &spr_read_generic, &spr_write_generic,
8026 KVM_REG_PPC_DSCR, 0x00000000);
8027#endif
8028 /*
8029 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
8030 * POWERPC_EXCP_INVAL_SPR.
8031 */
8032 spr_register(env, SPR_PCR, "PCR",
8033 SPR_NOACCESS, SPR_NOACCESS,
8034 SPR_NOACCESS, SPR_NOACCESS,
8035 0x00000000);
8036}
8037
69b058c8 8038static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
45ed0be1 8039{
69b058c8
PB		 8040 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8041 spr_read_generic(ctx, gprn, sprn);
45ed0be1
AK		 8042}
8043
69b058c8 8044static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
45ed0be1 8045{
69b058c8
PB		 8046 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8047 spr_write_generic(ctx, sprn, gprn);
45ed0be1
AK		 8048}
8049
768167ab
AK		 8050static void gen_spr_power8_tce_address_control(CPUPPCState *env)
8051{
1e440cbc
TH		 8052 spr_register_kvm(env, SPR_TAR, "TAR",
8053 &spr_read_tar, &spr_write_tar,
8054 &spr_read_generic, &spr_write_generic,
8055 KVM_REG_PPC_TAR, 0x00000000);
768167ab
AK		 8056}
8057
69b058c8 8058static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
cdcdda27 8059{
69b058c8
PB		 8060 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8061 spr_read_generic(ctx, gprn, sprn);
cdcdda27
AK		 8062}
8063
69b058c8 8064static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
cdcdda27 8065{
69b058c8
PB		 8066 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8067 spr_write_generic(ctx, sprn, gprn);
cdcdda27
AK		 8068}
8069
69b058c8 8070static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
cdcdda27 8071{
69b058c8
PB		 8072 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8073 spr_read_prev_upper32(ctx, gprn, sprn);
cdcdda27
AK		 8074}
8075
69b058c8 8076static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
cdcdda27 8077{
69b058c8
PB		 8078 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8079 spr_write_prev_upper32(ctx, sprn, gprn);
cdcdda27
AK		 8080}
8081
8082static void gen_spr_power8_tm(CPUPPCState *env)
8083{
8084 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
8085 &spr_read_tm, &spr_write_tm,
8086 &spr_read_tm, &spr_write_tm,
8087 KVM_REG_PPC_TFHAR, 0x00000000);
8088 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
8089 &spr_read_tm, &spr_write_tm,
8090 &spr_read_tm, &spr_write_tm,
8091 KVM_REG_PPC_TFIAR, 0x00000000);
8092 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
8093 &spr_read_tm, &spr_write_tm,
8094 &spr_read_tm, &spr_write_tm,
8095 KVM_REG_PPC_TEXASR, 0x00000000);
8096 spr_register(env, SPR_TEXASRU, "TEXASRU",
8097 &spr_read_tm_upper32, &spr_write_tm_upper32,
8098 &spr_read_tm_upper32, &spr_write_tm_upper32,
8099 0x00000000);
8100}
8101
69b058c8 8102static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
4ee4a03b 8103{
69b058c8
PB		 8104 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8105 spr_read_generic(ctx, gprn, sprn);
4ee4a03b
AK		 8106}
8107
69b058c8 8108static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
4ee4a03b 8109{
69b058c8
PB		 8110 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8111 spr_write_generic(ctx, sprn, gprn);
4ee4a03b
AK		 8112}
8113
69b058c8 8114static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
4ee4a03b 8115{
69b058c8
PB		 8116 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8117 spr_read_prev_upper32(ctx, gprn, sprn);
4ee4a03b
AK		 8118}
8119
69b058c8 8120static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
4ee4a03b 8121{
69b058c8
PB		 8122 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8123 spr_write_prev_upper32(ctx, sprn, gprn);
4ee4a03b
AK		 8124}
8125
8126static void gen_spr_power8_ebb(CPUPPCState *env)
8127{
8128 spr_register(env, SPR_BESCRS, "BESCRS",
8129 &spr_read_ebb, &spr_write_ebb,
8130 &spr_read_generic, &spr_write_generic,
8131 0x00000000);
8132 spr_register(env, SPR_BESCRSU, "BESCRSU",
8133 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8134 &spr_read_prev_upper32, &spr_write_prev_upper32,
8135 0x00000000);
8136 spr_register(env, SPR_BESCRR, "BESCRR",
8137 &spr_read_ebb, &spr_write_ebb,
8138 &spr_read_generic, &spr_write_generic,
8139 0x00000000);
8140 spr_register(env, SPR_BESCRRU, "BESCRRU",
8141 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8142 &spr_read_prev_upper32, &spr_write_prev_upper32,
8143 0x00000000);
8144 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
8145 &spr_read_ebb, &spr_write_ebb,
8146 &spr_read_generic, &spr_write_generic,
8147 KVM_REG_PPC_EBBHR, 0x00000000);
8148 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
8149 &spr_read_ebb, &spr_write_ebb,
8150 &spr_read_generic, &spr_write_generic,
8151 KVM_REG_PPC_EBBRR, 0x00000000);
8152 spr_register_kvm(env, SPR_BESCR, "BESCR",
8153 &spr_read_ebb, &spr_write_ebb,
8154 &spr_read_generic, &spr_write_generic,
8155 KVM_REG_PPC_BESCR, 0x00000000);
8156}
8157
3ba55e39
CB		 8158/* Virtual Time Base */
8159static void gen_spr_vtb(CPUPPCState *env)
8160{
8161 spr_register(env, SPR_VTB, "VTB",
8162 SPR_NOACCESS, SPR_NOACCESS,
8163 &spr_read_tbl, SPR_NOACCESS,
8164 0x00000000);
8165}
8166
7019cb3d
AK		 8167static void gen_spr_power8_fscr(CPUPPCState *env)
8168{
45ed0be1
AK		 8169#if defined(CONFIG_USER_ONLY)
8170 target_ulong initval = 1ULL << FSCR_TAR;
8171#else
8172 target_ulong initval = 0;
8173#endif
7019cb3d
AK		 8174 spr_register_kvm(env, SPR_FSCR, "FSCR",
8175 SPR_NOACCESS, SPR_NOACCESS,
8176 &spr_read_generic, &spr_write_generic,
45ed0be1 8177 KVM_REG_PPC_FSCR, initval);
7019cb3d
AK		 8178}
8179
d6f1445f
TH		 8180static void gen_spr_power8_pspb(CPUPPCState *env)
8181{
8182 spr_register_kvm(env, SPR_PSPB, "PSPB",
8183 SPR_NOACCESS, SPR_NOACCESS,
8184 &spr_read_generic, &spr_write_generic32,
8185 KVM_REG_PPC_PSPB, 0);
8186}
8187
21a558be
BH		 8188static void gen_spr_power8_ic(CPUPPCState *env)
8189{
8190#if !defined(CONFIG_USER_ONLY)
8191 spr_register_hv(env, SPR_IC, "IC",
8192 SPR_NOACCESS, SPR_NOACCESS,
8193 &spr_read_generic, SPR_NOACCESS,
8194 &spr_read_generic, &spr_write_generic,
8195 0);
9d0e5c8c
CLG		 8196#endif
8197}
8198
8199static void gen_spr_power8_book4(CPUPPCState *env)
8200{
8201 /* Add a number of P8 book4 registers */
8202#if !defined(CONFIG_USER_ONLY)
9c1cf38d
BH		 8203 spr_register_kvm(env, SPR_ACOP, "ACOP",
8204 SPR_NOACCESS, SPR_NOACCESS,
8205 &spr_read_generic, &spr_write_generic,
8206 KVM_REG_PPC_ACOP, 0);
8207 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8208 SPR_NOACCESS, SPR_NOACCESS,
31b2b0f8 8209 &spr_read_generic, &spr_write_pidr,
9c1cf38d
BH		 8210 KVM_REG_PPC_PID, 0);
8211 spr_register_kvm(env, SPR_WORT, "WORT",
8212 SPR_NOACCESS, SPR_NOACCESS,
8213 &spr_read_generic, &spr_write_generic,
8214 KVM_REG_PPC_WORT, 0);
21a558be
BH		 8215#endif
8216}
8217
8eb0f563
BH		 8218static void gen_spr_power7_book4(CPUPPCState *env)
8219{
8220 /* Add a number of P7 book4 registers */
8221#if !defined(CONFIG_USER_ONLY)
8222 spr_register_kvm(env, SPR_ACOP, "ACOP",
8223 SPR_NOACCESS, SPR_NOACCESS,
8224 &spr_read_generic, &spr_write_generic,
8225 KVM_REG_PPC_ACOP, 0);
8226 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8227 SPR_NOACCESS, SPR_NOACCESS,
8228 &spr_read_generic, &spr_write_generic,
8229 KVM_REG_PPC_PID, 0);
8230#endif
8231}
8232
8eeb330c
BH		 8233static void gen_spr_power8_rpr(CPUPPCState *env)
8234{
8235#if !defined(CONFIG_USER_ONLY)
8236 spr_register_hv(env, SPR_RPR, "RPR",
8237 SPR_NOACCESS, SPR_NOACCESS,
8238 SPR_NOACCESS, SPR_NOACCESS,
8239 &spr_read_generic, &spr_write_generic,
8240 0x00000103070F1F3F);
8241#endif
8242}
8243
4f4f28ff 8244static void init_proc_book3s_common(CPUPPCState *env)
42382f62
AK		 8245{
8246 gen_spr_ne_601(env);
42382f62
AK		 8247 gen_tbl(env);
8248 gen_spr_book3s_altivec(env);
fd51ff63
AK		 8249 gen_spr_book3s_pmu_sup(env);
8250 gen_spr_book3s_pmu_user(env);
4f4f28ff
SJS		 8251 gen_spr_book3s_ctrl(env);
8252}
fd51ff63 8253
4f4f28ff
SJS		 8254static void init_proc_970(CPUPPCState *env)
8255{
8256 /* Common Registers */
8257 init_proc_book3s_common(env);
8258 gen_spr_sdr1(env);
8259 gen_spr_book3s_dbg(env);
8260
8261 /* 970 Specific Registers */
8262 gen_spr_970_hid(env);
8263 gen_spr_970_hior(env);
8264 gen_low_BATs(env);
8265 gen_spr_970_pmu_sup(env);
8266 gen_spr_970_pmu_user(env);
8267 gen_spr_970_lpar(env);
8268 gen_spr_970_dbg(env);
8269
8270 /* env variables */
f2e63a42 8271#if !defined(CONFIG_USER_ONLY)
4f4f28ff 8272 env->slb_nr = 64;
f2e63a42 8273#endif
d63001d1
JM		 8274 env->dcache_line_size = 128;
8275 env->icache_line_size = 128;
a750fc0b 8276
4f4f28ff
SJS		 8277 /* Allocate hardware IRQ controller */
8278 init_excp_970(env);
8279 ppc970_irq_init(ppc_env_get_cpu(env));
7488d481
AK		 8280}
8281
bbc01ca7 8282POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7856e3a4 8283{
ca5dff0a 8284 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 8285 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8286
bbc01ca7
AK		 8287 dc->desc = "PowerPC 970";
8288 pcc->init_proc = init_proc_970;
8289 pcc->check_pow = check_pow_970;
53116ebf
AF		 8290 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8291 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8292 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8293 PPC_FLOAT_STFIWX |
8294 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8295 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8296 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8297 PPC_64B | PPC_ALTIVEC |
8298 PPC_SEGMENT_64B | PPC_SLBI;
4171853c 8299 pcc->insns_flags2 = PPC2_FP_CVT_S64;
9df5a466
TM		 8300 pcc->msr_mask = (1ull << MSR_SF) |
8301 (1ull << MSR_VR) |
8302 (1ull << MSR_POW) |
8303 (1ull << MSR_EE) |
8304 (1ull << MSR_PR) |
8305 (1ull << MSR_FP) |
8306 (1ull << MSR_ME) |
8307 (1ull << MSR_FE0) |
8308 (1ull << MSR_SE) |
8309 (1ull << MSR_DE) |
8310 (1ull << MSR_FE1) |
8311 (1ull << MSR_IR) |
8312 (1ull << MSR_DR) |
8313 (1ull << MSR_PMM) |
8314 (1ull << MSR_RI);
ba9fd9f1 8315 pcc->mmu_model = POWERPC_MMU_64B;
b632a148
DG		 8316#if defined(CONFIG_SOFTMMU)
8317 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8318#endif
ba9fd9f1
AF		 8319 pcc->excp_model = POWERPC_EXCP_970;
8320 pcc->bus_model = PPC_FLAGS_INPUT_970;
8321 pcc->bfd_mach = bfd_mach_ppc64;
8322 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8323 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8324 POWERPC_FLAG_BUS_CLK;
06f6e124
AG		 8325 pcc->l1_dcache_size = 0x8000;
8326 pcc->l1_icache_size = 0x10000;
7856e3a4
AF		 8327}
8328
35ebcb2b
AF		 8329static void init_proc_power5plus(CPUPPCState *env)
8330{
4f4f28ff
SJS		 8331 /* Common Registers */
8332 init_proc_book3s_common(env);
8333 gen_spr_sdr1(env);
8334 gen_spr_book3s_dbg(env);
8335
8336 /* POWER5+ Specific Registers */
8337 gen_spr_970_hid(env);
8338 gen_spr_970_hior(env);
8339 gen_low_BATs(env);
8340 gen_spr_970_pmu_sup(env);
8341 gen_spr_970_pmu_user(env);
8342 gen_spr_power5p_common(env);
8343 gen_spr_power5p_lpar(env);
8344 gen_spr_power5p_ear(env);
8345
8346 /* env variables */
8347#if !defined(CONFIG_USER_ONLY)
8348 env->slb_nr = 64;
8349#endif
8350 env->dcache_line_size = 128;
8351 env->icache_line_size = 128;
8352
8353 /* Allocate hardware IRQ controller */
8354 init_excp_970(env);
8355 ppc970_irq_init(ppc_env_get_cpu(env));
35ebcb2b
AF		 8356}
8357
8358POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8359{
8360 DeviceClass *dc = DEVICE_CLASS(oc);
8361 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8362
793826cd 8363 dc->fw_name = "PowerPC,POWER5";
35ebcb2b
AF		 8364 dc->desc = "POWER5+";
8365 pcc->init_proc = init_proc_power5plus;
90618f4f 8366 pcc->check_pow = check_pow_970;
35ebcb2b
AF		 8367 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8368 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8369 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8370 PPC_FLOAT_STFIWX |
8371 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8372 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8373 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8374 PPC_64B |
8375 PPC_SEGMENT_64B | PPC_SLBI;
4171853c 8376 pcc->insns_flags2 = PPC2_FP_CVT_S64;
9df5a466
TM		 8377 pcc->msr_mask = (1ull << MSR_SF) |
8378 (1ull << MSR_VR) |
8379 (1ull << MSR_POW) |
8380 (1ull << MSR_EE) |
8381 (1ull << MSR_PR) |
8382 (1ull << MSR_FP) |
8383 (1ull << MSR_ME) |
8384 (1ull << MSR_FE0) |
8385 (1ull << MSR_SE) |
8386 (1ull << MSR_DE) |
8387 (1ull << MSR_FE1) |
8388 (1ull << MSR_IR) |
8389 (1ull << MSR_DR) |
8390 (1ull << MSR_PMM) |
8391 (1ull << MSR_RI);
aa4bb587 8392 pcc->mmu_model = POWERPC_MMU_2_03;
35ebcb2b
AF		 8393#if defined(CONFIG_SOFTMMU)
8394 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8395#endif
8396 pcc->excp_model = POWERPC_EXCP_970;
8397 pcc->bus_model = PPC_FLAGS_INPUT_970;
8398 pcc->bfd_mach = bfd_mach_ppc64;
8399 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8400 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8401 POWERPC_FLAG_BUS_CLK;
06f6e124
AG		 8402 pcc->l1_dcache_size = 0x8000;
8403 pcc->l1_icache_size = 0x10000;
35ebcb2b
AF		 8404}
8405
d7bce999
EB		 8406static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
8407 void *opaque, Error **errp)
8dfa3a5e
AK		 8408{
8409 char *value = (char *)"";
8410 Property *prop = opaque;
8411 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8412
8413 switch (*max_compat) {
8414 case CPU_POWERPC_LOGICAL_2_05:
8415 value = (char *)"power6";
8416 break;
8417 case CPU_POWERPC_LOGICAL_2_06:
8418 value = (char *)"power7";
8419 break;
8420 case CPU_POWERPC_LOGICAL_2_07:
8421 value = (char *)"power8";
8422 break;
8423 case 0:
8424 break;
8425 default:
c4dfc14b
GK		 8426 error_report("Internal error: compat is set to %x", *max_compat);
8427 abort();
8dfa3a5e
AK		 8428 break;
8429 }
8430
51e72bc1 8431 visit_type_str(v, name, &value, errp);
8dfa3a5e
AK		 8432}
8433
d7bce999
EB		 8434static void powerpc_set_compat(Object *obj, Visitor *v, const char *name,
8435 void *opaque, Error **errp)
8dfa3a5e
AK		 8436{
8437 Error *error = NULL;
8438 char *value = NULL;
8439 Property *prop = opaque;
8440 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8441
51e72bc1 8442 visit_type_str(v, name, &value, &error);
8dfa3a5e
AK		 8443 if (error) {
8444 error_propagate(errp, error);
8445 return;
8446 }
8447
8448 if (strcmp(value, "power6") == 0) {
8449 *max_compat = CPU_POWERPC_LOGICAL_2_05;
8450 } else if (strcmp(value, "power7") == 0) {
8451 *max_compat = CPU_POWERPC_LOGICAL_2_06;
8452 } else if (strcmp(value, "power8") == 0) {
8453 *max_compat = CPU_POWERPC_LOGICAL_2_07;
8454 } else {
8455 error_setg(errp, "Invalid compatibility mode \"%s\"", value);
8456 }
8457
8458 g_free(value);
8459}
8460
8461static PropertyInfo powerpc_compat_propinfo = {
8462 .name = "str",
51b2e8c3 8463 .description = "compatibility mode, power6/power7/power8",
8dfa3a5e
AK		 8464 .get = powerpc_get_compat,
8465 .set = powerpc_set_compat,
8466};
8467
8468#define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
8469 DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
8470
8471static Property powerpc_servercpu_properties[] = {
8472 DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat),
8473 DEFINE_PROP_END_OF_LIST(),
8474};
8475
a8891fbf
DG		 8476#ifdef CONFIG_SOFTMMU
8477static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
8478 .sps = {
8479 {
8480 .page_shift = 12, /* 4K */
8481 .slb_enc = 0,
8482 .enc = { { .page_shift = 12, .pte_enc = 0 },
8483 { .page_shift = 16, .pte_enc = 0x7 },
8484 { .page_shift = 24, .pte_enc = 0x38 }, },
8485 },
8486 {
8487 .page_shift = 16, /* 64K */
8488 .slb_enc = SLB_VSID_64K,
8489 .enc = { { .page_shift = 16, .pte_enc = 0x1 },
8490 { .page_shift = 24, .pte_enc = 0x8 }, },
8491 },
8492 {
8493 .page_shift = 24, /* 16M */
8494 .slb_enc = SLB_VSID_16M,
8495 .enc = { { .page_shift = 24, .pte_enc = 0 }, },
8496 },
8497 {
8498 .page_shift = 34, /* 16G */
8499 .slb_enc = SLB_VSID_16G,
8500 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
8501 },
8502 }
8503};
8504#endif /* CONFIG_SOFTMMU */
8505
9d52e907
DG		 8506static void init_proc_POWER7 (CPUPPCState *env)
8507{
4f4f28ff
SJS		 8508 /* Common Registers */
8509 init_proc_book3s_common(env);
8510 gen_spr_sdr1(env);
8511 gen_spr_book3s_dbg(env);
8512
8513 /* POWER7 Specific Registers */
8514 gen_spr_book3s_ids(env);
8515 gen_spr_amr(env);
8516 gen_spr_book3s_purr(env);
8517 gen_spr_power5p_common(env);
8518 gen_spr_power5p_lpar(env);
8519 gen_spr_power5p_ear(env);
8520 gen_spr_power6_common(env);
8521 gen_spr_power6_dbg(env);
8522 gen_spr_power7_book4(env);
8523
8524 /* env variables */
8525#if !defined(CONFIG_USER_ONLY)
8526 env->slb_nr = 32;
8527#endif
8528 env->ci_large_pages = true;
8529 env->dcache_line_size = 128;
8530 env->icache_line_size = 128;
8531
8532 /* Allocate hardware IRQ controller */
8533 init_excp_POWER7(env);
8534 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
9d52e907 8535}
9d52e907 8536
03ae4133
AK		 8537static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8538{
8539 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8540 return true;
8541 }
8542 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8543 return true;
8544 }
8545 return false;
8546}
8547
7778a575
BH		 8548static bool cpu_has_work_POWER7(CPUState *cs)
8549{
8550 PowerPCCPU *cpu = POWERPC_CPU(cs);
8551 CPUPPCState *env = &cpu->env;
8552
8553 if (cs->halted) {
8554 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8555 return false;
8556 }
8557 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8558 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
8559 return true;
8560 }
8561 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8562 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
8563 return true;
8564 }
8565 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8566 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8567 return true;
8568 }
8569 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8570 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8571 return true;
8572 }
8573 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8574 return true;
8575 }
8576 return false;
8577 } else {
8578 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8579 }
8580}
8581
7856e3a4
AF		 8582POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8583{
ca5dff0a 8584 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4 8585 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7778a575 8586 CPUClass *cc = CPU_CLASS(oc);
7856e3a4 8587
793826cd 8588 dc->fw_name = "PowerPC,POWER7";
ca5dff0a 8589 dc->desc = "POWER7";
8dfa3a5e 8590 dc->props = powerpc_servercpu_properties;
03ae4133 8591 pcc->pvr_match = ppc_pvr_match_power7;
8cd2ce7a
TH		 8592 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8593 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7856e3a4
AF		 8594 pcc->init_proc = init_proc_POWER7;
8595 pcc->check_pow = check_pow_nocheck;
7778a575 8596 cc->has_work = cpu_has_work_POWER7;
e71ec2e9 8597 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
53116ebf
AF		 8598 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8599 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
ce8ca30b 8600 PPC_FLOAT_FRSQRTES |
53116ebf 8601 PPC_FLOAT_STFIWX |
c7386080 8602 PPC_FLOAT_EXT |
53116ebf
AF		 8603 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8604 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8605 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
dfdd3e43 8606 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
53116ebf 8607 PPC_SEGMENT_64B | PPC_SLBI |
b7815375
BH		 8608 PPC_POPCNTB | PPC_POPCNTWD |
8609 PPC_CILDST;
86ba37ed 8610 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
1fa6c533 8611 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
29a0e4e9 8612 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7778a575
BH		 8613 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
8614 PPC2_PM_ISA206;
9df5a466
TM		 8615 pcc->msr_mask = (1ull << MSR_SF) |
8616 (1ull << MSR_VR) |
8617 (1ull << MSR_VSX) |
8618 (1ull << MSR_EE) |
8619 (1ull << MSR_PR) |
8620 (1ull << MSR_FP) |
8621 (1ull << MSR_ME) |
8622 (1ull << MSR_FE0) |
8623 (1ull << MSR_SE) |
8624 (1ull << MSR_DE) |
8625 (1ull << MSR_FE1) |
8626 (1ull << MSR_IR) |
8627 (1ull << MSR_DR) |
8628 (1ull << MSR_PMM) |
8629 (1ull << MSR_RI) |
8630 (1ull << MSR_LE);
ba9fd9f1 8631 pcc->mmu_model = POWERPC_MMU_2_06;
b632a148
DG		 8632#if defined(CONFIG_SOFTMMU)
8633 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
a8891fbf 8634 pcc->sps = &POWER7_POWER8_sps;
b650d6a2
AK		 8635#endif
8636 pcc->excp_model = POWERPC_EXCP_POWER7;
8637 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8638 pcc->bfd_mach = bfd_mach_ppc64;
8639 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8640 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8641 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8642 POWERPC_FLAG_VSX;
8643 pcc->l1_dcache_size = 0x8000;
8644 pcc->l1_icache_size = 0x8000;
382d2db6 8645 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
b650d6a2
AK		 8646}
8647
60511041
TM		 8648static void init_proc_POWER8(CPUPPCState *env)
8649{
4f4f28ff
SJS		 8650 /* Common Registers */
8651 init_proc_book3s_common(env);
8652 gen_spr_sdr1(env);
8653 gen_spr_book3s_207_dbg(env);
8654
8655 /* POWER8 Specific Registers */
8656 gen_spr_book3s_ids(env);
8657 gen_spr_amr(env);
8658 gen_spr_iamr(env);
8659 gen_spr_book3s_purr(env);
8660 gen_spr_power5p_common(env);
8661 gen_spr_power5p_lpar(env);
8662 gen_spr_power5p_ear(env);
8663 gen_spr_power6_common(env);
8664 gen_spr_power6_dbg(env);
8665 gen_spr_power8_tce_address_control(env);
8666 gen_spr_power8_ids(env);
8667 gen_spr_power8_ebb(env);
8668 gen_spr_power8_fscr(env);
8669 gen_spr_power8_pmu_sup(env);
8670 gen_spr_power8_pmu_user(env);
8671 gen_spr_power8_tm(env);
8672 gen_spr_power8_pspb(env);
8673 gen_spr_vtb(env);
8674 gen_spr_power8_ic(env);
8675 gen_spr_power8_book4(env);
8676 gen_spr_power8_rpr(env);
8677
8678 /* env variables */
8679#if !defined(CONFIG_USER_ONLY)
8680 env->slb_nr = 32;
8681#endif
8682 env->ci_large_pages = true;
8683 env->dcache_line_size = 128;
8684 env->icache_line_size = 128;
8685
8686 /* Allocate hardware IRQ controller */
8687 init_excp_POWER8(env);
8688 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
60511041
TM		 8689}
8690
03ae4133
AK		 8691static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8692{
a88dced8
AK		 8693 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8694 return true;
8695 }
03ae4133
AK		 8696 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8697 return true;
8698 }
8699 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8700 return true;
8701 }
8702 return false;
8703}
8704
7778a575
BH		 8705static bool cpu_has_work_POWER8(CPUState *cs)
8706{
8707 PowerPCCPU *cpu = POWERPC_CPU(cs);
8708 CPUPPCState *env = &cpu->env;
8709
8710 if (cs->halted) {
8711 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8712 return false;
8713 }
8714 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8715 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
8716 return true;
8717 }
8718 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8719 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
8720 return true;
8721 }
8722 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8723 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8724 return true;
8725 }
8726 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8727 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8728 return true;
8729 }
8730 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8731 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
8732 return true;
8733 }
8734 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8735 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
8736 return true;
8737 }
8738 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8739 return true;
8740 }
8741 return false;
8742 } else {
8743 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8744 }
8745}
8746
b60c6007 8747POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8d43ea1c
PS		 8748{
8749 DeviceClass *dc = DEVICE_CLASS(oc);
8750 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7778a575 8751 CPUClass *cc = CPU_CLASS(oc);
8d43ea1c 8752
793826cd 8753 dc->fw_name = "PowerPC,POWER8";
b60c6007 8754 dc->desc = "POWER8";
8dfa3a5e 8755 dc->props = powerpc_servercpu_properties;
03ae4133 8756 pcc->pvr_match = ppc_pvr_match_power8;
8cd2ce7a
TH		 8757 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8758 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
60511041 8759 pcc->init_proc = init_proc_POWER8;
8d43ea1c 8760 pcc->check_pow = check_pow_nocheck;
7778a575 8761 cc->has_work = cpu_has_work_POWER8;
536492eb 8762 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8d43ea1c
PS		 8763 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8764 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
ce8ca30b 8765 PPC_FLOAT_FRSQRTES |
8d43ea1c 8766 PPC_FLOAT_STFIWX |
c7386080 8767 PPC_FLOAT_EXT |
8d43ea1c
PS		 8768 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8769 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8770 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4e080611 8771 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8d43ea1c 8772 PPC_SEGMENT_64B | PPC_SLBI |
b7815375
BH		 8773 PPC_POPCNTB | PPC_POPCNTWD |
8774 PPC_CILDST;
86ba37ed 8775 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
1fa6c533 8776 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
29a0e4e9 8777 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
38a85337 8778 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
df99d30d 8779 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
3e28c5e3 8780 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7778a575 8781 PPC2_TM | PPC2_PM_ISA206;
9df5a466 8782 pcc->msr_mask = (1ull << MSR_SF) |
932ccbdd 8783 (1ull << MSR_SHV) |
cdcdda27 8784 (1ull << MSR_TM) |
9df5a466
TM		 8785 (1ull << MSR_VR) |
8786 (1ull << MSR_VSX) |
8787 (1ull << MSR_EE) |
8788 (1ull << MSR_PR) |
8789 (1ull << MSR_FP) |
8790 (1ull << MSR_ME) |
8791 (1ull << MSR_FE0) |
8792 (1ull << MSR_SE) |
8793 (1ull << MSR_DE) |
8794 (1ull << MSR_FE1) |
8795 (1ull << MSR_IR) |
8796 (1ull << MSR_DR) |
8797 (1ull << MSR_PMM) |
8798 (1ull << MSR_RI) |
8799 (1ull << MSR_LE);
aa4bb587 8800 pcc->mmu_model = POWERPC_MMU_2_07;
8d43ea1c
PS		 8801#if defined(CONFIG_SOFTMMU)
8802 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
a8891fbf 8803 pcc->sps = &POWER7_POWER8_sps;
706d6467
AK		 8804#endif
8805 pcc->excp_model = POWERPC_EXCP_POWER8;
8806 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8807 pcc->bfd_mach = bfd_mach_ppc64;
8808 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8809 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8810 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8811 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8812 pcc->l1_dcache_size = 0x8000;
8813 pcc->l1_icache_size = 0x8000;
8814 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8815}
4f4f28ff 8816
ccd531b9
SJS		 8817#ifdef CONFIG_SOFTMMU
8818/*
8819 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8820 * Encoded as array of int_32s in the form:
8821 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8822 * x -> AP encoding
8823 * y -> radix mode supported page size (encoded as a shift)
8824 */
8825static struct ppc_radix_page_info POWER9_radix_page_info = {
8826 .count = 4,
8827 .entries = {
8828 0x0000000c, /* 4K - enc: 0x0 */
8829 0xa0000010, /* 64K - enc: 0x5 */
8830 0x20000015, /* 2M - enc: 0x1 */
8831 0x4000001e /* 1G - enc: 0x2 */
8832 }
8833};
8834#endif /* CONFIG_SOFTMMU */
8835
706d6467
AK		 8836static void init_proc_POWER9(CPUPPCState *env)
8837{
4f4f28ff
SJS		 8838 /* Common Registers */
8839 init_proc_book3s_common(env);
8840 gen_spr_book3s_207_dbg(env);
8841
8842 /* POWER8 Specific Registers */
8843 gen_spr_book3s_ids(env);
8844 gen_spr_amr(env);
8845 gen_spr_iamr(env);
8846 gen_spr_book3s_purr(env);
8847 gen_spr_power5p_common(env);
8848 gen_spr_power5p_lpar(env);
8849 gen_spr_power5p_ear(env);
8850 gen_spr_power6_common(env);
8851 gen_spr_power6_dbg(env);
8852 gen_spr_power8_tce_address_control(env);
8853 gen_spr_power8_ids(env);
8854 gen_spr_power8_ebb(env);
8855 gen_spr_power8_fscr(env);
8856 gen_spr_power8_pmu_sup(env);
8857 gen_spr_power8_pmu_user(env);
8858 gen_spr_power8_tm(env);
8859 gen_spr_power8_pspb(env);
8860 gen_spr_vtb(env);
8861 gen_spr_power8_ic(env);
8862 gen_spr_power8_book4(env);
8863 gen_spr_power8_rpr(env);
8864
8865 /* env variables */
8866#if !defined(CONFIG_USER_ONLY)
8867 env->slb_nr = 32;
8868#endif
8869 env->ci_large_pages = true;
8870 env->dcache_line_size = 128;
8871 env->icache_line_size = 128;
8872
8873 /* Allocate hardware IRQ controller */
8874 init_excp_POWER8(env);
8875 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
706d6467
AK		 8876}
8877
8878static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
8879{
8880 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
8881 return true;
8882 }
8883 return false;
8884}
8885
6f46dcb3
SJS		 8886static bool cpu_has_work_POWER9(CPUState *cs)
8887{
8888 PowerPCCPU *cpu = POWERPC_CPU(cs);
8889 CPUPPCState *env = &cpu->env;
8890
8891 if (cs->halted) {
8892 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8893 return false;
8894 }
8895 /* External Exception */
8896 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8897 (env->spr[SPR_LPCR] & LPCR_EEE)) {
8898 return true;
8899 }
8900 /* Decrementer Exception */
8901 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8902 (env->spr[SPR_LPCR] & LPCR_DEE)) {
8903 return true;
8904 }
8905 /* Machine Check or Hypervisor Maintenance Exception */
8906 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8907 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8908 return true;
8909 }
8910 /* Privileged Doorbell Exception */
8911 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8912 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8913 return true;
8914 }
8915 /* Hypervisor Doorbell Exception */
8916 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8917 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8918 return true;
8919 }
8920 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8921 return true;
8922 }
8923 return false;
8924 } else {
8925 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8926 }
8927}
8928
706d6467
AK		 8929POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8930{
8931 DeviceClass *dc = DEVICE_CLASS(oc);
8932 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6f46dcb3 8933 CPUClass *cc = CPU_CLASS(oc);
706d6467
AK		 8934
8935 dc->fw_name = "PowerPC,POWER9";
8936 dc->desc = "POWER9";
8937 dc->props = powerpc_servercpu_properties;
8938 pcc->pvr_match = ppc_pvr_match_power9;
8939 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
216c944e
SJS		 8940 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8941 PCR_COMPAT_2_05;
706d6467
AK		 8942 pcc->init_proc = init_proc_POWER9;
8943 pcc->check_pow = check_pow_nocheck;
6f46dcb3 8944 cc->has_work = cpu_has_work_POWER9;
706d6467
AK		 8945 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8946 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8947 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8948 PPC_FLOAT_FRSQRTES |
8949 PPC_FLOAT_STFIWX |
8950 PPC_FLOAT_EXT |
8951 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8952 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8953 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8954 PPC_64B | PPC_64BX | PPC_ALTIVEC |
8955 PPC_SEGMENT_64B | PPC_SLBI |
8956 PPC_POPCNTB | PPC_POPCNTWD |
8957 PPC_CILDST;
8958 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8959 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8960 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8961 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8962 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8963 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
eb640b13 8964 PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300;
706d6467
AK		 8965 pcc->msr_mask = (1ull << MSR_SF) |
8966 (1ull << MSR_TM) |
8967 (1ull << MSR_VR) |
8968 (1ull << MSR_VSX) |
8969 (1ull << MSR_EE) |
8970 (1ull << MSR_PR) |
8971 (1ull << MSR_FP) |
8972 (1ull << MSR_ME) |
8973 (1ull << MSR_FE0) |
8974 (1ull << MSR_SE) |
8975 (1ull << MSR_DE) |
8976 (1ull << MSR_FE1) |
8977 (1ull << MSR_IR) |
8978 (1ull << MSR_DR) |
8979 (1ull << MSR_PMM) |
8980 (1ull << MSR_RI) |
8981 (1ull << MSR_LE);
86cf1e9f 8982 pcc->mmu_model = POWERPC_MMU_3_00;
706d6467 8983#if defined(CONFIG_SOFTMMU)
b2899495 8984 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
706d6467
AK		 8985 /* segment page size remain the same */
8986 pcc->sps = &POWER7_POWER8_sps;
ccd531b9 8987 pcc->radix_page_info = &POWER9_radix_page_info;
8d43ea1c 8988#endif
5c94b2a5 8989 pcc->excp_model = POWERPC_EXCP_POWER8;
8d43ea1c
PS		 8990 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8991 pcc->bfd_mach = bfd_mach_ppc64;
8992 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8993 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
74f23997 8994 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
3e28c5e3 8995 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8d43ea1c
PS		 8996 pcc->l1_dcache_size = 0x8000;
8997 pcc->l1_icache_size = 0x8000;
382d2db6 8998 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8d43ea1c 8999}
a750fc0b 9000
26a7f129 9001#if !defined(CONFIG_USER_ONLY)
b7b0b1f1 9002void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
26a7f129
BH		 9003{
9004 CPUPPCState *env = &cpu->env;
61687db2 9005 ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
6a9c4ef4 9006 ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
26a7f129 9007
b7b0b1f1
DG		 9008 cpu->vhyp = vhyp;
9009
26a7f129
BH		 9010 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
9011 * MSR[IP] should never be set.
9012 *
9013 * We also disallow setting of MSR_HV
9014 */
9015 env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
9016
61687db2
BH		 9017 /* Set emulated LPCR to not send interrupts to hypervisor. Note that
9018 * under KVM, the actual HW LPCR will be set differently by KVM itself,
9019 * the settings below ensure proper operations with TCG in absence of
912acdf4
BH		 9020 * a real hypervisor.
9021 *
9022 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
9023 * real mode accesses, which thankfully defaults to 0 and isn't
9024 * accessible in guest mode.
61687db2
BH		 9025 */
9026 lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
9027 lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
9028
912acdf4
BH		 9029 /* Set RMLS to the max (ie, 16G) */
9030 lpcr->default_value &= ~LPCR_RMLS;
9031 lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
9032
18aa49ec
SJS		 9033 switch (env->mmu_model) {
9034 case POWERPC_MMU_3_00:
9035 /* By default we choose legacy mode and switch to new hash or radix
9036 * when a register process table hcall is made. So disable process
9037 * tables and guest translation shootdown by default
9038 */
9039 lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
9040 lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
9041 LPCR_OEE;
9042 break;
9043 default:
9044 /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
9045 * bit 47 and 48 which are reserved on P7. Here we set them all, which
9046 * will work as expected for both implementations
9047 */
9048 lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
9049 LPCR_P8_PECE3 | LPCR_P8_PECE4;
9050 }
7778a575 9051
61687db2
BH		 9052 /* We should be followed by a CPU reset but update the active value
9053 * just in case...
9054 */
9055 env->spr[SPR_LPCR] = lpcr->default_value;
9056
6a9c4ef4
BH		 9057 /* Set a full AMOR so guest can use the AMR as it sees fit */
9058 env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
9059
912acdf4
BH		 9060 /* Update some env bits based on new LPCR value */
9061 ppc_hash64_update_rmls(env);
9062 ppc_hash64_update_vrma(env);
9063
26a7f129
BH		 9064 /* Tell KVM that we're in PAPR mode */
9065 if (kvm_enabled()) {
9066 kvmppc_set_papr(cpu);
9067 }
9068}
9069
9070#endif /* !defined(CONFIG_USER_ONLY) */
9071
9072#endif /* defined (TARGET_PPC64) */
fd5ed418 9073
a750fc0b 9074/*****************************************************************************/
60b14d95 9075/* Generic CPU instantiation routine */
cfe34f44 9076static void init_ppc_proc(PowerPCCPU *cpu)
a750fc0b 9077{
cfe34f44
AF		 9078 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9079 CPUPPCState *env = &cpu->env;
a750fc0b 9080#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 9081 int i;
9082
a750fc0b 9083 env->irq_inputs = NULL;
e1833e1f
JM		 9084 /* Set all exception vectors to an invalid address */
9085 for (i = 0; i < POWERPC_EXCP_NB; i++)
9086 env->excp_vectors[i] = (target_ulong)(-1ULL);
e1833e1f
JM		 9087 env->ivor_mask = 0x00000000;
9088 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 9089 /* Default MMU definitions */
9090 env->nb_BATs = 0;
9091 env->nb_tlb = 0;
9092 env->nb_ways = 0;
1c53accc 9093 env->tlb_type = TLB_NONE;
f2e63a42 9094#endif
a750fc0b
JM		 9095 /* Register SPR common to all PowerPC implementations */
9096 gen_spr_generic(env);
9097 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 9098 /* Linux permits userspace to read PVR */
9099#if defined(CONFIG_LINUX_USER)
9100 &spr_read_generic,
9101#else
9102 SPR_NOACCESS,
9103#endif
9104 SPR_NOACCESS,
a750fc0b 9105 &spr_read_generic, SPR_NOACCESS,
cfe34f44 9106 pcc->pvr);
80d11f44 9107 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
cfe34f44
AF		 9108 if (pcc->svr != POWERPC_SVR_NONE) {
9109 if (pcc->svr & POWERPC_SVR_E500) {
80d11f44
JM		 9110 spr_register(env, SPR_E500_SVR, "SVR",
9111 SPR_NOACCESS, SPR_NOACCESS,
9112 &spr_read_generic, SPR_NOACCESS,
cfe34f44 9113 pcc->svr & ~POWERPC_SVR_E500);
80d11f44
JM		 9114 } else {
9115 spr_register(env, SPR_SVR, "SVR",
9116 SPR_NOACCESS, SPR_NOACCESS,
9117 &spr_read_generic, SPR_NOACCESS,
cfe34f44 9118 pcc->svr);
80d11f44
JM		 9119 }
9120 }
a750fc0b 9121 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
cfe34f44 9122 (*pcc->init_proc)(env);
2cf3eb6d 9123
25ba3a68
JM		 9124 /* MSR bits & flags consistency checks */
9125 if (env->msr_mask & (1 << 25)) {
9126 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9127 case POWERPC_FLAG_SPE:
9128 case POWERPC_FLAG_VRE:
9129 break;
9130 default:
9131 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9132 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9133 exit(1);
9134 }
9135 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9136 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9137 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9138 exit(1);
9139 }
9140 if (env->msr_mask & (1 << 17)) {
9141 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9142 case POWERPC_FLAG_TGPR:
9143 case POWERPC_FLAG_CE:
9144 break;
9145 default:
9146 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9147 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9148 exit(1);
9149 }
9150 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9151 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9152 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9153 exit(1);
9154 }
9155 if (env->msr_mask & (1 << 10)) {
9156 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9157 POWERPC_FLAG_UBLE)) {
9158 case POWERPC_FLAG_SE:
9159 case POWERPC_FLAG_DWE:
9160 case POWERPC_FLAG_UBLE:
9161 break;
9162 default:
9163 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9164 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9165 "POWERPC_FLAG_UBLE\n");
9166 exit(1);
9167 }
9168 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9169 POWERPC_FLAG_UBLE)) {
9170 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9171 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9172 "POWERPC_FLAG_UBLE\n");
9173 exit(1);
9174 }
9175 if (env->msr_mask & (1 << 9)) {
9176 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9177 case POWERPC_FLAG_BE:
9178 case POWERPC_FLAG_DE:
9179 break;
9180 default:
9181 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9182 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9183 exit(1);
9184 }
9185 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9186 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9187 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9188 exit(1);
9189 }
9190 if (env->msr_mask & (1 << 2)) {
9191 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9192 case POWERPC_FLAG_PX:
9193 case POWERPC_FLAG_PMM:
9194 break;
9195 default:
9196 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9197 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9198 exit(1);
9199 }
9200 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9201 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9202 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9203 exit(1);
9204 }
4018bae9
JM		 9205 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9206 fprintf(stderr, "PowerPC flags inconsistency\n"
9207 "Should define the time-base and decrementer clock source\n");
9208 exit(1);
9209 }
a750fc0b 9210 /* Allocate TLBs buffer when needed */
f2e63a42 9211#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9212 if (env->nb_tlb != 0) {
9213 int nb_tlb = env->nb_tlb;
9214 if (env->id_tlbs != 0)
9215 nb_tlb *= 2;
1c53accc
AG		 9216 switch (env->tlb_type) {
9217 case TLB_6XX:
7267c094 9218 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
1c53accc
AG		 9219 break;
9220 case TLB_EMB:
7267c094 9221 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
1c53accc
AG		 9222 break;
9223 case TLB_MAS:
7267c094 9224 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
1c53accc
AG		 9225 break;
9226 }
a750fc0b
JM		 9227 /* Pre-compute some useful values */
9228 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9229 }
a750fc0b
JM		 9230 if (env->irq_inputs == NULL) {
9231 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5cbdb3a3 9232 " Attempt QEMU to crash very soon !\n");
a750fc0b
JM		 9233 }
9234#endif
2f462816
JM		 9235 if (env->check_pow == NULL) {
9236 fprintf(stderr, "WARNING: no power management check handler "
9237 "registered.\n"
5cbdb3a3 9238 " Attempt QEMU to crash very soon !\n");
2f462816 9239 }
a750fc0b
JM		 9240}
9241
9242#if defined(PPC_DUMP_CPU)
9243static void dump_ppc_sprs (CPUPPCState *env)
9244{
9245 ppc_spr_t *spr;
9246#if !defined(CONFIG_USER_ONLY)
9247 uint32_t sr, sw;
9248#endif
9249 uint32_t ur, uw;
9250 int i, j, n;
9251
9252 printf("Special purpose registers:\n");
9253 for (i = 0; i < 32; i++) {
9254 for (j = 0; j < 32; j++) {
9255 n = (i << 5) | j;
9256 spr = &env->spr_cb[n];
9257 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9258 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9259#if !defined(CONFIG_USER_ONLY)
9260 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9261 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9262 if (sw || sr || uw || ur) {
9263 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9264 (i << 5) | j, (i << 5) | j, spr->name,
9265 sw ? 'w' : '-', sr ? 'r' : '-',
9266 uw ? 'w' : '-', ur ? 'r' : '-');
9267 }
9268#else
9269 if (uw || ur) {
9270 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9271 (i << 5) | j, (i << 5) | j, spr->name,
9272 uw ? 'w' : '-', ur ? 'r' : '-');
9273 }
9274#endif
9275 }
9276 }
9277 fflush(stdout);
9278 fflush(stderr);
9279}
9280#endif
9281
9282/*****************************************************************************/
a750fc0b 9283
a750fc0b
JM		 9284/* Opcode types */
9285enum {
9286 PPC_DIRECT = 0, /* Opcode routine */
9287 PPC_INDIRECT = 1, /* Indirect opcode table */
9288};
9289
54ff58bb
BR		 9290#define PPC_OPCODE_MASK 0x3
9291
a750fc0b
JM		 9292static inline int is_indirect_opcode (void *handler)
9293{
54ff58bb 9294 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
a750fc0b
JM		 9295}
9296
c227f099 9297static inline opc_handler_t **ind_table(void *handler)
a750fc0b 9298{
54ff58bb 9299 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
a750fc0b
JM		 9300}
9301
9302/* Instruction table creation */
9303/* Opcodes tables creation */
c227f099 9304static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 9305{
9306 int i;
9307
9308 for (i = 0; i < len; i++)
9309 table[i] = &invalid_handler;
9310}
9311
c227f099 9312static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 9313{
c227f099 9314 opc_handler_t **tmp;
a750fc0b 9315
54ff58bb
BR		 9316 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
9317 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
5724753e 9318 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
a750fc0b
JM		 9319
9320 return 0;
9321}
9322
c227f099
AL		 9323static int insert_in_table (opc_handler_t **table, unsigned char idx,
9324 opc_handler_t *handler)
a750fc0b
JM		 9325{
9326 if (table[idx] != &invalid_handler)
9327 return -1;
9328 table[idx] = handler;
9329
9330 return 0;
9331}
9332
c227f099
AL		 9333static int register_direct_insn (opc_handler_t **ppc_opcodes,
9334 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 9335{
9336 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9337 printf("*** ERROR: opcode %02x already assigned in main "
9338 "opcode table\n", idx);
4c1b1bfe
JM		 9339#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9340 printf(" Registered handler '%s' - new handler '%s'\n",
9341 ppc_opcodes[idx]->oname, handler->oname);
9342#endif
a750fc0b
JM		 9343 return -1;
9344 }
9345
9346 return 0;
9347}
9348
c227f099 9349static int register_ind_in_table (opc_handler_t **table,
a750fc0b 9350 unsigned char idx1, unsigned char idx2,
c227f099 9351 opc_handler_t *handler)
a750fc0b
JM		 9352{
9353 if (table[idx1] == &invalid_handler) {
9354 if (create_new_table(table, idx1) < 0) {
9355 printf("*** ERROR: unable to create indirect table "
9356 "idx=%02x\n", idx1);
9357 return -1;
9358 }
9359 } else {
9360 if (!is_indirect_opcode(table[idx1])) {
9361 printf("*** ERROR: idx %02x already assigned to a direct "
9362 "opcode\n", idx1);
4c1b1bfe
JM		 9363#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9364 printf(" Registered handler '%s' - new handler '%s'\n",
9365 ind_table(table[idx1])[idx2]->oname, handler->oname);
9366#endif
a750fc0b
JM		 9367 return -1;
9368 }
3a607854 9369 }
a750fc0b
JM		 9370 if (handler != NULL &&
9371 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9372 printf("*** ERROR: opcode %02x already assigned in "
9373 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9374#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9375 printf(" Registered handler '%s' - new handler '%s'\n",
9376 ind_table(table[idx1])[idx2]->oname, handler->oname);
9377#endif
a750fc0b 9378 return -1;
3a607854 9379 }
a750fc0b
JM		 9380
9381 return 0;
9382}
9383
c227f099 9384static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9385 unsigned char idx1, unsigned char idx2,
c227f099 9386 opc_handler_t *handler)
a750fc0b 9387{
74c373e4 9388 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
a750fc0b
JM		 9389}
9390
c227f099 9391static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9392 unsigned char idx1, unsigned char idx2,
c227f099 9393 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 9394{
9395 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9396 printf("*** ERROR: unable to join indirect table idx "
9397 "[%02x-%02x]\n", idx1, idx2);
9398 return -1;
9399 }
9400 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9401 handler) < 0) {
9402 printf("*** ERROR: unable to insert opcode "
9403 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9404 return -1;
9405 }
9406
9407 return 0;
9408}
9409
323ad19b
ND		 9410static int register_trplind_insn(opc_handler_t **ppc_opcodes,
9411 unsigned char idx1, unsigned char idx2,
9412 unsigned char idx3, unsigned char idx4,
9413 opc_handler_t *handler)
9414{
9415 opc_handler_t **table;
9416
9417 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9418 printf("*** ERROR: unable to join indirect table idx "
9419 "[%02x-%02x]\n", idx1, idx2);
9420 return -1;
9421 }
9422 table = ind_table(ppc_opcodes[idx1]);
9423 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
9424 printf("*** ERROR: unable to join 2nd-level indirect table idx "
9425 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9426 return -1;
9427 }
9428 table = ind_table(table[idx2]);
9429 if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
9430 printf("*** ERROR: unable to insert opcode "
9431 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
9432 return -1;
9433 }
9434 return 0;
9435}
c227f099 9436static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 9437{
9438 if (insn->opc2 != 0xFF) {
9439 if (insn->opc3 != 0xFF) {
323ad19b
ND		 9440 if (insn->opc4 != 0xFF) {
9441 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9442 insn->opc3, insn->opc4,
9443 &insn->handler) < 0) {
9444 return -1;
9445 }
9446 } else {
9447 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9448 insn->opc3, &insn->handler) < 0)
9449 return -1;
9450 }
a750fc0b
JM		 9451 } else {
9452 if (register_ind_insn(ppc_opcodes, insn->opc1,
9453 insn->opc2, &insn->handler) < 0)
9454 return -1;
9455 }
9456 } else {
9457 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9458 return -1;
9459 }
9460
9461 return 0;
9462}
9463
c227f099 9464static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 9465{
9466 int i, count, tmp;
9467
9468 for (i = 0, count = 0; i < len; i++) {
9469 /* Consistency fixup */
9470 if (table[i] == NULL)
9471 table[i] = &invalid_handler;
9472 if (table[i] != &invalid_handler) {
9473 if (is_indirect_opcode(table[i])) {
54ff58bb
BR		 9474 tmp = test_opcode_table(ind_table(table[i]),
9475 PPC_CPU_INDIRECT_OPCODES_LEN);
a750fc0b
JM		 9476 if (tmp == 0) {
9477 free(table[i]);
9478 table[i] = &invalid_handler;
9479 } else {
9480 count++;
9481 }
9482 } else {
9483 count++;
9484 }
9485 }
9486 }
9487
9488 return count;
9489}
9490
c227f099 9491static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 9492{
54ff58bb 9493 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
a750fc0b
JM		 9494 printf("*** WARNING: no opcode defined !\n");
9495}
9496
9497/*****************************************************************************/
2985b86b 9498static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
a750fc0b 9499{
2985b86b
AF		 9500 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9501 CPUPPCState *env = &cpu->env;
c227f099 9502 opcode_t *opc;
a750fc0b 9503
54ff58bb 9504 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
5c55ff99 9505 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
cfe34f44
AF		 9506 if (((opc->handler.type & pcc->insns_flags) != 0) ||
9507 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
a750fc0b 9508 if (register_insn(env->opcodes, opc) < 0) {
2985b86b 9509 error_setg(errp, "ERROR initializing PowerPC instruction "
312fd5f2 9510 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
2985b86b
AF		 9511 opc->opc3);
9512 return;
a750fc0b
JM		 9513 }
9514 }
9515 }
c227f099 9516 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 9517 fflush(stdout);
9518 fflush(stderr);
a750fc0b
JM		 9519}
9520
9521#if defined(PPC_DUMP_CPU)
25ba3a68 9522static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 9523{
c227f099 9524 opc_handler_t **table, *handler;
b55266b5 9525 const char *p, *q;
323ad19b 9526 uint8_t opc1, opc2, opc3, opc4;
a750fc0b
JM		 9527
9528 printf("Instructions set:\n");
9529 /* opc1 is 6 bits long */
54ff58bb 9530 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
a750fc0b
JM		 9531 table = env->opcodes;
9532 handler = table[opc1];
9533 if (is_indirect_opcode(handler)) {
9534 /* opc2 is 5 bits long */
54ff58bb 9535 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
a750fc0b
JM		 9536 table = env->opcodes;
9537 handler = env->opcodes[opc1];
9538 table = ind_table(handler);
9539 handler = table[opc2];
9540 if (is_indirect_opcode(handler)) {
9541 table = ind_table(handler);
9542 /* opc3 is 5 bits long */
54ff58bb
BR		 9543 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
9544 opc3++) {
a750fc0b 9545 handler = table[opc3];
323ad19b
ND		 9546 if (is_indirect_opcode(handler)) {
9547 table = ind_table(handler);
9548 /* opc4 is 5 bits long */
9549 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
9550 opc4++) {
9551 handler = table[opc4];
9552 if (handler->handler != &gen_invalid) {
9553 printf("INSN: %02x %02x %02x %02x -- "
9554 "(%02d %04d %02d) : %s\n",
9555 opc1, opc2, opc3, opc4,
9556 opc1, (opc3 << 5) | opc2, opc4,
4c1b1bfe
JM		 9557 handler->oname);
9558 }
323ad19b
ND		 9559 }
9560 } else {
9561 if (handler->handler != &gen_invalid) {
9562 /* Special hack to properly dump SPE insns */
9563 p = strchr(handler->oname, '_');
9564 if (p == NULL) {
4c1b1bfe
JM		 9565 printf("INSN: %02x %02x %02x (%02d %04d) : "
9566 "%s\n",
323ad19b
ND		 9567 opc1, opc2, opc3, opc1,
9568 (opc3 << 5) | opc2,
9569 handler->oname);
9570 } else {
9571 q = "speundef";
9572 if ((p - handler->oname) != strlen(q)
9573 || (memcmp(handler->oname, q, strlen(q))
9574 != 0)) {
9575 /* First instruction */
9576 printf("INSN: %02x %02x %02x"
9577 "(%02d %04d) : %.*s\n",
9578 opc1, opc2 << 1, opc3, opc1,
9579 (opc3 << 6) | (opc2 << 1),
9580 (int)(p - handler->oname),
9581 handler->oname);
9582 }
9583 if (strcmp(p + 1, q) != 0) {
9584 /* Second instruction */
9585 printf("INSN: %02x %02x %02x "
9586 "(%02d %04d) : %s\n", opc1,
9587 (opc2 << 1) | 1, opc3, opc1,
9588 (opc3 << 6) | (opc2 << 1) | 1,
9589 p + 1);
9590 }
4c1b1bfe
JM		 9591 }
9592 }
a750fc0b
JM		 9593 }
9594 }
9595 } else {
9596 if (handler->handler != &gen_invalid) {
9597 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9598 opc1, opc2, opc1, opc2, handler->oname);
9599 }
9600 }
9601 }
9602 } else {
9603 if (handler->handler != &gen_invalid) {
9604 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9605 opc1, opc1, handler->oname);
9606 }
9607 }
9608 }
9609}
3a607854 9610#endif
a750fc0b 9611
87601e2d
GK		 9612static bool avr_need_swap(CPUPPCState *env)
9613{
9614#ifdef HOST_WORDS_BIGENDIAN
ea499e71 9615 return msr_le;
87601e2d 9616#else
ea499e71 9617 return !msr_le;
87601e2d
GK		 9618#endif
9619}
9620
1328c2bf 9621static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 9622{
9623 if (n < 32) {
9624 stfq_p(mem_buf, env->fpr[n]);
385abeb3 9625 ppc_maybe_bswap_register(env, mem_buf, 8);
24951522
AJ		 9626 return 8;
9627 }
9628 if (n == 32) {
5a576fb3 9629 stl_p(mem_buf, env->fpscr);
385abeb3 9630 ppc_maybe_bswap_register(env, mem_buf, 4);
24951522
AJ		 9631 return 4;
9632 }
9633 return 0;
9634}
9635
1328c2bf 9636static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 9637{
9638 if (n < 32) {
385abeb3 9639 ppc_maybe_bswap_register(env, mem_buf, 8);
24951522
AJ		 9640 env->fpr[n] = ldfq_p(mem_buf);
9641 return 8;
9642 }
9643 if (n == 32) {
385abeb3 9644 ppc_maybe_bswap_register(env, mem_buf, 4);
d6478bc7 9645 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
24951522
AJ		 9646 return 4;
9647 }
9648 return 0;
9649}
9650
1328c2bf 9651static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 9652{
9653 if (n < 32) {
87601e2d
GK		 9654 if (!avr_need_swap(env)) {
9655 stq_p(mem_buf, env->avr[n].u64[0]);
9656 stq_p(mem_buf+8, env->avr[n].u64[1]);
9657 } else {
9658 stq_p(mem_buf, env->avr[n].u64[1]);
9659 stq_p(mem_buf+8, env->avr[n].u64[0]);
9660 }
ea499e71
GK		 9661 ppc_maybe_bswap_register(env, mem_buf, 8);
9662 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
b4f8d821
AJ		 9663 return 16;
9664 }
70976a79 9665 if (n == 32) {
b4f8d821 9666 stl_p(mem_buf, env->vscr);
ea499e71 9667 ppc_maybe_bswap_register(env, mem_buf, 4);
b4f8d821
AJ		 9668 return 4;
9669 }
70976a79 9670 if (n == 33) {
b4f8d821 9671 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
ea499e71 9672 ppc_maybe_bswap_register(env, mem_buf, 4);
b4f8d821
AJ		 9673 return 4;
9674 }
9675 return 0;
9676}
9677
1328c2bf 9678static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 9679{
9680 if (n < 32) {
ea499e71
GK		 9681 ppc_maybe_bswap_register(env, mem_buf, 8);
9682 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
87601e2d
GK		 9683 if (!avr_need_swap(env)) {
9684 env->avr[n].u64[0] = ldq_p(mem_buf);
9685 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9686 } else {
9687 env->avr[n].u64[1] = ldq_p(mem_buf);
9688 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9689 }
b4f8d821
AJ		 9690 return 16;
9691 }
70976a79 9692 if (n == 32) {
ea499e71 9693 ppc_maybe_bswap_register(env, mem_buf, 4);
b4f8d821
AJ		 9694 env->vscr = ldl_p(mem_buf);
9695 return 4;
9696 }
70976a79 9697 if (n == 33) {
ea499e71 9698 ppc_maybe_bswap_register(env, mem_buf, 4);
b4f8d821
AJ		 9699 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9700 return 4;
9701 }
9702 return 0;
9703}
9704
1328c2bf 9705static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 9706{
9707 if (n < 32) {
9708#if defined(TARGET_PPC64)
9709 stl_p(mem_buf, env->gpr[n] >> 32);
95f5b540 9710 ppc_maybe_bswap_register(env, mem_buf, 4);
688890f7
AJ		 9711#else
9712 stl_p(mem_buf, env->gprh[n]);
9713#endif
9714 return 4;
9715 }
70976a79 9716 if (n == 32) {
688890f7 9717 stq_p(mem_buf, env->spe_acc);
95f5b540 9718 ppc_maybe_bswap_register(env, mem_buf, 8);
688890f7
AJ		 9719 return 8;
9720 }
70976a79 9721 if (n == 33) {
d34defbc 9722 stl_p(mem_buf, env->spe_fscr);
95f5b540 9723 ppc_maybe_bswap_register(env, mem_buf, 4);
688890f7
AJ		 9724 return 4;
9725 }
9726 return 0;
9727}
9728
1328c2bf 9729static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 9730{
9731 if (n < 32) {
9732#if defined(TARGET_PPC64)
9733 target_ulong lo = (uint32_t)env->gpr[n];
95f5b540
GK		 9734 target_ulong hi;
9735
9736 ppc_maybe_bswap_register(env, mem_buf, 4);
9737
9738 hi = (target_ulong)ldl_p(mem_buf) << 32;
688890f7
AJ		 9739 env->gpr[n] = lo | hi;
9740#else
9741 env->gprh[n] = ldl_p(mem_buf);
9742#endif
9743 return 4;
9744 }
70976a79 9745 if (n == 32) {
95f5b540 9746 ppc_maybe_bswap_register(env, mem_buf, 8);
688890f7
AJ		 9747 env->spe_acc = ldq_p(mem_buf);
9748 return 8;
9749 }
70976a79 9750 if (n == 33) {
95f5b540 9751 ppc_maybe_bswap_register(env, mem_buf, 4);
d34defbc 9752 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 9753 return 4;
9754 }
9755 return 0;
9756}
9757
1438eff3
AB		 9758static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9759{
9760 if (n < 32) {
9761 stq_p(mem_buf, env->vsr[n]);
9762 ppc_maybe_bswap_register(env, mem_buf, 8);
9763 return 8;
9764 }
9765 return 0;
9766}
9767
9768static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9769{
9770 if (n < 32) {
9771 ppc_maybe_bswap_register(env, mem_buf, 8);
9772 env->vsr[n] = ldq_p(mem_buf);
9773 return 8;
9774 }
9775 return 0;
9776}
9777
55e5c285 9778static int ppc_fixup_cpu(PowerPCCPU *cpu)
12b1143b 9779{
55e5c285
AF		 9780 CPUPPCState *env = &cpu->env;
9781
12b1143b
DG		 9782 /* TCG doesn't (yet) emulate some groups of instructions that
9783 * are implemented on some otherwise supported CPUs (e.g. VSX
9784 * and decimal floating point instructions on POWER7). We
9785 * remove unsupported instruction groups from the cpu state's
9786 * instruction masks and hope the guest can cope. For at
9787 * least the pseries machine, the unavailability of these
9788 * instructions can be advertised to the guest via the device
9789 * tree. */
9790 if ((env->insns_flags & ~PPC_TCG_INSNS)
9791 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9792 fprintf(stderr, "Warning: Disabling some instructions which are not "
9793 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9794 env->insns_flags & ~PPC_TCG_INSNS,
9795 env->insns_flags2 & ~PPC_TCG_INSNS2);
9796 }
9797 env->insns_flags &= PPC_TCG_INSNS;
9798 env->insns_flags2 &= PPC_TCG_INSNS2;
9799 return 0;
9800}
9801
292363e1
AF		 9802static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
9803{
9804#ifdef TARGET_PPCEMB
9805 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
9806 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
9807 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
9808#else
9809 return true;
9810#endif
9811}
9812
4776ce60 9813static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
a750fc0b 9814{
22169d41 9815 CPUState *cs = CPU(dev);
4776ce60 9816 PowerPCCPU *cpu = POWERPC_CPU(dev);
2985b86b 9817 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2985b86b 9818 Error *local_err = NULL;
fe828a4d 9819#if !defined(CONFIG_USER_ONLY)
c4e6c423 9820 int max_smt = kvmppc_smt_threads();
fe828a4d
MQ		 9821#endif
9822
9823#if !defined(CONFIG_USER_ONLY)
9824 if (smp_threads > max_smt) {
5e95acc8
AF		 9825 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
9826 max_smt, kvm_enabled() ? "KVM" : "TCG");
9827 return;
fe828a4d 9828 }
5ec83c73
BR		 9829 if (!is_power_of_2(smp_threads)) {
9830 error_setg(errp, "Cannot support %d threads on PPC with %s, "
9831 "threads count must be a power of 2.",
9832 smp_threads, kvm_enabled() ? "KVM" : "TCG");
9833 return;
9834 }
6dd0f834
BR		 9835#endif
9836
ce5b1bbf 9837 cpu_exec_realizefn(cs, &local_err);
6dd0f834
BR		 9838 if (local_err != NULL) {
9839 error_propagate(errp, local_err);
9840 return;
9841 }
0ce470cd 9842
6dd0f834 9843#if !defined(CONFIG_USER_ONLY)
0ce470cd
AK		 9844 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
9845 + (cs->cpu_index % smp_threads);
41264b38
GK		 9846
9847 if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->cpu_dt_id)) {
9848 error_setg(errp, "Can't create CPU with id %d in KVM", cpu->cpu_dt_id);
9849 error_append_hint(errp, "Adjust the number of cpus to %d "
9850 "or try to raise the number of threads per core\n",
9851 cpu->cpu_dt_id * smp_threads / max_smt);
9852 return;
9853 }
fe828a4d 9854#endif
4656e1f0 9855
0ce470cd 9856 if (tcg_enabled()) {
55e5c285 9857 if (ppc_fixup_cpu(cpu) != 0) {
2985b86b
AF		 9858 error_setg(errp, "Unable to emulate selected CPU with TCG");
9859 return;
12b1143b
DG		 9860 }
9861 }
9862
4d7fb187 9863#if defined(TARGET_PPCEMB)
292363e1
AF		 9864 if (!ppc_cpu_is_valid(pcc)) {
9865 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
4d7fb187
AF		 9866 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
9867 "or choose another CPU model.");
9868 return;
9869 }
9870#endif
9871
2985b86b
AF		 9872 create_ppc_opcodes(cpu, &local_err);
9873 if (local_err != NULL) {
9874 error_propagate(errp, local_err);
9875 return;
9876 }
cfe34f44 9877 init_ppc_proc(cpu);
24951522 9878
cfe34f44 9879 if (pcc->insns_flags & PPC_FLOAT) {
22169d41 9880 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
24951522
AJ		 9881 33, "power-fpu.xml", 0);
9882 }
cfe34f44 9883 if (pcc->insns_flags & PPC_ALTIVEC) {
22169d41 9884 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
b4f8d821
AJ		 9885 34, "power-altivec.xml", 0);
9886 }
cfe34f44 9887 if (pcc->insns_flags & PPC_SPE) {
22169d41 9888 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
688890f7
AJ		 9889 34, "power-spe.xml", 0);
9890 }
1438eff3
AB		 9891 if (pcc->insns_flags2 & PPC2_VSX) {
9892 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9893 32, "power-vsx.xml", 0);
9894 }
688890f7 9895
14a10fc3
AF		 9896 qemu_init_vcpu(cs);
9897
4776ce60
AF		 9898 pcc->parent_realize(dev, errp);
9899
a750fc0b 9900#if defined(PPC_DUMP_CPU)
3a607854 9901 {
22169d41 9902 CPUPPCState *env = &cpu->env;
b55266b5 9903 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9904 switch (env->mmu_model) {
9905 case POWERPC_MMU_32B:
9906 mmu_model = "PowerPC 32";
9907 break;
a750fc0b
JM		 9908 case POWERPC_MMU_SOFT_6xx:
9909 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9910 break;
9911 case POWERPC_MMU_SOFT_74xx:
9912 mmu_model = "PowerPC 74xx with software driven TLBs";
9913 break;
9914 case POWERPC_MMU_SOFT_4xx:
9915 mmu_model = "PowerPC 4xx with software driven TLBs";
9916 break;
9917 case POWERPC_MMU_SOFT_4xx_Z:
9918 mmu_model = "PowerPC 4xx with software driven TLBs "
9919 "and zones protections";
9920 break;
b4095fed
JM		 9921 case POWERPC_MMU_REAL:
9922 mmu_model = "PowerPC real mode only";
9923 break;
9924 case POWERPC_MMU_MPC8xx:
9925 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9926 break;
9927 case POWERPC_MMU_BOOKE:
9928 mmu_model = "PowerPC BookE";
9929 break;
01662f3e
AG		 9930 case POWERPC_MMU_BOOKE206:
9931 mmu_model = "PowerPC BookE 2.06";
a750fc0b 9932 break;
b4095fed
JM		 9933 case POWERPC_MMU_601:
9934 mmu_model = "PowerPC 601";
9935 break;
00af685f
JM		 9936#if defined (TARGET_PPC64)
9937 case POWERPC_MMU_64B:
9938 mmu_model = "PowerPC 64";
9939 break;
00af685f 9940#endif
a750fc0b
JM		 9941 default:
9942 mmu_model = "Unknown or invalid";
9943 break;
9944 }
9945 switch (env->excp_model) {
9946 case POWERPC_EXCP_STD:
9947 excp_model = "PowerPC";
9948 break;
9949 case POWERPC_EXCP_40x:
9950 excp_model = "PowerPC 40x";
9951 break;
9952 case POWERPC_EXCP_601:
9953 excp_model = "PowerPC 601";
9954 break;
9955 case POWERPC_EXCP_602:
9956 excp_model = "PowerPC 602";
9957 break;
9958 case POWERPC_EXCP_603:
9959 excp_model = "PowerPC 603";
9960 break;
9961 case POWERPC_EXCP_603E:
9962 excp_model = "PowerPC 603e";
9963 break;
9964 case POWERPC_EXCP_604:
9965 excp_model = "PowerPC 604";
9966 break;
9967 case POWERPC_EXCP_7x0:
9968 excp_model = "PowerPC 740/750";
9969 break;
9970 case POWERPC_EXCP_7x5:
9971 excp_model = "PowerPC 745/755";
9972 break;
9973 case POWERPC_EXCP_74xx:
9974 excp_model = "PowerPC 74xx";
9975 break;
a750fc0b
JM		 9976 case POWERPC_EXCP_BOOKE:
9977 excp_model = "PowerPC BookE";
9978 break;
00af685f
JM		 9979#if defined (TARGET_PPC64)
9980 case POWERPC_EXCP_970:
9981 excp_model = "PowerPC 970";
9982 break;
9983#endif
a750fc0b
JM		 9984 default:
9985 excp_model = "Unknown or invalid";
9986 break;
9987 }
9988 switch (env->bus_model) {
9989 case PPC_FLAGS_INPUT_6xx:
9990 bus_model = "PowerPC 6xx";
9991 break;
9992 case PPC_FLAGS_INPUT_BookE:
9993 bus_model = "PowerPC BookE";
9994 break;
9995 case PPC_FLAGS_INPUT_405:
9996 bus_model = "PowerPC 405";
9997 break;
a750fc0b
JM		 9998 case PPC_FLAGS_INPUT_401:
9999 bus_model = "PowerPC 401/403";
10000 break;
b4095fed
JM		 10001 case PPC_FLAGS_INPUT_RCPU:
10002 bus_model = "RCPU / MPC8xx";
10003 break;
00af685f
JM		 10004#if defined (TARGET_PPC64)
10005 case PPC_FLAGS_INPUT_970:
10006 bus_model = "PowerPC 970";
10007 break;
10008#endif
a750fc0b
JM		 10009 default:
10010 bus_model = "Unknown or invalid";
10011 break;
10012 }
10013 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10014 " MMU model : %s\n",
a5100e75
AK		 10015 object_class_get_name(OBJECT_CLASS(pcc)),
10016 pcc->pvr, pcc->msr_mask, mmu_model);
f2e63a42 10017#if !defined(CONFIG_USER_ONLY)
a5100e75 10018 if (env->tlb.tlb6) {
a750fc0b
JM		 10019 printf(" %d %s TLB in %d ways\n",
10020 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10021 env->nb_ways);
10022 }
f2e63a42 10023#endif
a750fc0b
JM		 10024 printf(" Exceptions model : %s\n"
10025 " Bus model : %s\n",
10026 excp_model, bus_model);
25ba3a68
JM		 10027 printf(" MSR features :\n");
10028 if (env->flags & POWERPC_FLAG_SPE)
10029 printf(" signal processing engine enable"
10030 "\n");
10031 else if (env->flags & POWERPC_FLAG_VRE)
10032 printf(" vector processor enable\n");
10033 if (env->flags & POWERPC_FLAG_TGPR)
10034 printf(" temporary GPRs\n");
10035 else if (env->flags & POWERPC_FLAG_CE)
10036 printf(" critical input enable\n");
10037 if (env->flags & POWERPC_FLAG_SE)
10038 printf(" single-step trace mode\n");
10039 else if (env->flags & POWERPC_FLAG_DWE)
10040 printf(" debug wait enable\n");
10041 else if (env->flags & POWERPC_FLAG_UBLE)
10042 printf(" user BTB lock enable\n");
10043 if (env->flags & POWERPC_FLAG_BE)
10044 printf(" branch-step trace mode\n");
10045 else if (env->flags & POWERPC_FLAG_DE)
10046 printf(" debug interrupt enable\n");
10047 if (env->flags & POWERPC_FLAG_PX)
10048 printf(" inclusive protection\n");
10049 else if (env->flags & POWERPC_FLAG_PMM)
10050 printf(" performance monitor mark\n");
10051 if (env->flags == POWERPC_FLAG_NONE)
10052 printf(" none\n");
4018bae9
JM		 10053 printf(" Time-base/decrementer clock source: %s\n",
10054 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
22169d41
AF		 10055 dump_ppc_insns(env);
10056 dump_ppc_sprs(env);
10057 fflush(stdout);
a750fc0b 10058 }
3a607854 10059#endif
a750fc0b 10060}
3fc6c082 10061
b048960f
AF		 10062static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
10063{
10064 PowerPCCPU *cpu = POWERPC_CPU(dev);
7bbc124e 10065 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
b048960f 10066 CPUPPCState *env = &cpu->env;
7bbc124e 10067 Error *local_err = NULL;
323ad19b
ND		 10068 opc_handler_t **table, **table_2;
10069 int i, j, k;
b048960f 10070
7bbc124e
LV		 10071 pcc->parent_unrealize(dev, &local_err);
10072 if (local_err != NULL) {
10073 error_propagate(errp, local_err);
10074 return;
10075 }
6dd0f834 10076
b048960f 10077 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
81f194dd
BR		 10078 if (env->opcodes[i] == &invalid_handler) {
10079 continue;
10080 }
10081 if (is_indirect_opcode(env->opcodes[i])) {
10082 table = ind_table(env->opcodes[i]);
10083 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
323ad19b
ND		 10084 if (table[j] == &invalid_handler) {
10085 continue;
10086 }
10087 if (is_indirect_opcode(table[j])) {
10088 table_2 = ind_table(table[j]);
10089 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
10090 if (table_2[k] != &invalid_handler &&
10091 is_indirect_opcode(table_2[k])) {
10092 g_free((opc_handler_t *)((uintptr_t)table_2[k] &
10093 ~PPC_INDIRECT));
10094 }
10095 }
81f194dd 10096 g_free((opc_handler_t *)((uintptr_t)table[j] &
323ad19b 10097 ~PPC_INDIRECT));
81f194dd
BR		 10098 }
10099 }
10100 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
10101 ~PPC_INDIRECT));
b048960f
AF		 10102 }
10103 }
10104}
10105
2985b86b 10106static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
f0ad8c34 10107{
2985b86b
AF		 10108 ObjectClass *oc = (ObjectClass *)a;
10109 uint32_t pvr = *(uint32_t *)b;
10110 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10111
10112 /* -cpu host does a PVR lookup during construction */
10113 if (unlikely(strcmp(object_class_get_name(oc),
10114 TYPE_HOST_POWERPC_CPU) == 0)) {
10115 return -1;
f0ad8c34 10116 }
f0ad8c34 10117
292363e1 10118 if (!ppc_cpu_is_valid(pcc)) {
4d7fb187
AF		 10119 return -1;
10120 }
4d7fb187 10121
cfe34f44 10122 return pcc->pvr == pvr ? 0 : -1;
f0ad8c34
AG		 10123}
10124
2985b86b 10125PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
3fc6c082 10126{
2985b86b
AF		 10127 GSList *list, *item;
10128 PowerPCCPUClass *pcc = NULL;
be40edcd 10129
2985b86b
AF		 10130 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10131 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10132 if (item != NULL) {
10133 pcc = POWERPC_CPU_CLASS(item->data);
3fc6c082 10134 }
2985b86b
AF		 10135 g_slist_free(list);
10136
10137 return pcc;
10138}
10139
3bc9ccc0
AK		 10140static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
10141{
10142 ObjectClass *oc = (ObjectClass *)a;
10143 uint32_t pvr = *(uint32_t *)b;
10144 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
3bc9ccc0
AK		 10145
10146 /* -cpu host does a PVR lookup during construction */
10147 if (unlikely(strcmp(object_class_get_name(oc),
10148 TYPE_HOST_POWERPC_CPU) == 0)) {
10149 return -1;
10150 }
10151
292363e1 10152 if (!ppc_cpu_is_valid(pcc)) {
3bc9ccc0
AK		 10153 return -1;
10154 }
292363e1 10155
03ae4133
AK		 10156 if (pcc->pvr_match(pcc, pvr)) {
10157 return 0;
10158 }
3bc9ccc0 10159
03ae4133 10160 return -1;
3bc9ccc0
AK		 10161}
10162
10163PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
10164{
10165 GSList *list, *item;
10166 PowerPCCPUClass *pcc = NULL;
10167
10168 list = object_class_get_list(TYPE_POWERPC_CPU, true);
10169 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
10170 if (item != NULL) {
10171 pcc = POWERPC_CPU_CLASS(item->data);
10172 }
10173 g_slist_free(list);
10174
10175 return pcc;
10176}
10177
2985b86b
AF		 10178static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
10179{
10180 ObjectClass *oc = (ObjectClass *)a;
10181 const char *name = b;
4d7fb187 10182 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
ee4e83ed 10183
2985b86b 10184 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
292363e1 10185 ppc_cpu_is_valid(pcc) &&
2985b86b
AF		 10186 strcmp(object_class_get_name(oc) + strlen(name),
10187 "-" TYPE_POWERPC_CPU) == 0) {
10188 return 0;
10189 }
10190 return -1;
3fc6c082
FB		 10191}
10192
3fc6c082 10193
9761ad75
AG		 10194static ObjectClass *ppc_cpu_class_by_name(const char *name);
10195
10196static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
10197{
10198 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
10199
10200 /* Cache target class lookups in the alias table */
10201 if (!alias->oc) {
10202 alias->oc = ppc_cpu_class_by_name(alias->model);
10203 if (!alias->oc) {
10204 /* Fast check for non-existing aliases */
10205 alias->oc = invalid_class;
10206 }
10207 }
10208
10209 if (alias->oc == invalid_class) {
10210 return NULL;
10211 } else {
10212 return alias->oc;
10213 }
10214}
10215
2985b86b 10216static ObjectClass *ppc_cpu_class_by_name(const char *name)
ee4e83ed 10217{
2985b86b
AF		 10218 GSList *list, *item;
10219 ObjectClass *ret = NULL;
b55266b5 10220 const char *p;
2985b86b 10221 int i, len;
ee4e83ed
JM		 10222
10223 /* Check if the given name is a PVR */
10224 len = strlen(name);
10225 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10226 p = name + 2;
10227 goto check_pvr;
10228 } else if (len == 8) {
10229 p = name;
10230 check_pvr:
10231 for (i = 0; i < 8; i++) {
cd390083 10232 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 10233 break;
10234 }
2985b86b 10235 if (i == 8) {
74c373e4 10236 return OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
f0ad8c34 10237 }
2985b86b 10238 }
f0ad8c34 10239
2985b86b
AF		 10240 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10241 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
10242 if (item != NULL) {
10243 ret = OBJECT_CLASS(item->data);
3fc6c082 10244 }
2985b86b 10245 g_slist_free(list);
ee4e83ed 10246
fdf8a960
AK		 10247 if (ret) {
10248 return ret;
10249 }
10250
10251 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10252 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
10253 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
10254 }
10255 }
10256
10257 return NULL;
3fc6c082
FB		 10258}
10259
caf6316d
TH		 10260const char *ppc_cpu_lookup_alias(const char *alias)
10261{
10262 int ai;
10263
10264 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
10265 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
10266 return ppc_cpu_aliases[ai].model;
10267 }
10268 }
10269
10270 return NULL;
10271}
10272
2985b86b 10273PowerPCCPU *cpu_ppc_init(const char *cpu_model)
3fc6c082 10274{
9262685b 10275 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
2985b86b
AF		 10276}
10277
10278/* Sort by PVR, ordering special case "host" last. */
10279static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10280{
10281 ObjectClass *oc_a = (ObjectClass *)a;
10282 ObjectClass *oc_b = (ObjectClass *)b;
10283 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10284 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10285 const char *name_a = object_class_get_name(oc_a);
10286 const char *name_b = object_class_get_name(oc_b);
10287
10288 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10289 return 1;
10290 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10291 return -1;
10292 } else {
10293 /* Avoid an integer overflow during subtraction */
cfe34f44 10294 if (pcc_a->pvr < pcc_b->pvr) {
2985b86b 10295 return -1;
cfe34f44 10296 } else if (pcc_a->pvr > pcc_b->pvr) {
2985b86b
AF		 10297 return 1;
10298 } else {
10299 return 0;
10300 }
10301 }
10302}
10303
10304static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10305{
10306 ObjectClass *oc = data;
10307 CPUListState *s = user_data;
10308 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
de400129
AF		 10309 const char *typename = object_class_get_name(oc);
10310 char *name;
55d3d1a4 10311 int i;
2985b86b 10312
292363e1 10313 if (!ppc_cpu_is_valid(pcc)) {
4d7fb187
AF		 10314 return;
10315 }
5ba4576b
AF		 10316 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
10317 return;
10318 }
4d7fb187 10319
de400129
AF		 10320 name = g_strndup(typename,
10321 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
2985b86b 10322 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
cfe34f44 10323 name, pcc->pvr);
e9a96075 10324 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9761ad75
AG		 10325 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10326 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
55d3d1a4
AF		 10327
10328 if (alias_oc != oc) {
10329 continue;
10330 }
10331 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
10332 alias->alias, name);
10333 }
de400129 10334 g_free(name);
2985b86b
AF		 10335}
10336
10337void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10338{
10339 CPUListState s = {
10340 .file = f,
10341 .cpu_fprintf = cpu_fprintf,
10342 };
10343 GSList *list;
10344
10345 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10346 list = g_slist_sort(list, ppc_cpu_list_compare);
10347 g_slist_foreach(list, ppc_cpu_list_entry, &s);
10348 g_slist_free(list);
fd5ed418 10349
5ba4576b
AF		 10350#ifdef CONFIG_KVM
10351 cpu_fprintf(f, "\n");
10352 cpu_fprintf(f, "PowerPC %-16s\n", "host");
10353#endif
2985b86b
AF		 10354}
10355
10356static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10357{
10358 ObjectClass *oc = data;
10359 CpuDefinitionInfoList **first = user_data;
de400129 10360 const char *typename;
2985b86b
AF		 10361 CpuDefinitionInfoList *entry;
10362 CpuDefinitionInfo *info;
4d7fb187
AF		 10363 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10364
292363e1 10365 if (!ppc_cpu_is_valid(pcc)) {
4d7fb187
AF		 10366 return;
10367 }
2985b86b 10368
de400129 10369 typename = object_class_get_name(oc);
2985b86b 10370 info = g_malloc0(sizeof(*info));
de400129
AF		 10371 info->name = g_strndup(typename,
10372 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
2985b86b
AF		 10373
10374 entry = g_malloc0(sizeof(*entry));
10375 entry->value = info;
10376 entry->next = *first;
10377 *first = entry;
3fc6c082 10378}
1d0cb67d 10379
76b64a7a 10380CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
70b7660a
AL		 10381{
10382 CpuDefinitionInfoList *cpu_list = NULL;
2985b86b 10383 GSList *list;
35e21d3f 10384 int i;
70b7660a 10385
2985b86b
AF		 10386 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10387 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10388 g_slist_free(list);
70b7660a 10389
e9a96075 10390 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9761ad75 10391 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
35e21d3f
AF		 10392 ObjectClass *oc;
10393 CpuDefinitionInfoList *entry;
10394 CpuDefinitionInfo *info;
10395
9761ad75 10396 oc = ppc_cpu_class_by_alias(alias);
35e21d3f
AF		 10397 if (oc == NULL) {
10398 continue;
10399 }
10400
10401 info = g_malloc0(sizeof(*info));
10402 info->name = g_strdup(alias->alias);
8ed877b7 10403 info->q_typename = g_strdup(object_class_get_name(oc));
35e21d3f
AF		 10404
10405 entry = g_malloc0(sizeof(*entry));
10406 entry->value = info;
10407 entry->next = cpu_list;
10408 cpu_list = entry;
10409 }
10410
2985b86b
AF		 10411 return cpu_list;
10412}
70b7660a 10413
f45748f1
AF		 10414static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
10415{
10416 PowerPCCPU *cpu = POWERPC_CPU(cs);
10417
10418 cpu->env.nip = value;
10419}
10420
8c2e1b00
AF		 10421static bool ppc_cpu_has_work(CPUState *cs)
10422{
10423 PowerPCCPU *cpu = POWERPC_CPU(cs);
10424 CPUPPCState *env = &cpu->env;
10425
10426 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
10427}
10428
774f0abe
RH		 10429static void ppc_cpu_exec_enter(CPUState *cs)
10430{
10431 PowerPCCPU *cpu = POWERPC_CPU(cs);
10432 CPUPPCState *env = &cpu->env;
10433
10434 env->reserve_addr = -1;
10435}
10436
1d0cb67d
AF		 10437/* CPUClass::reset() */
10438static void ppc_cpu_reset(CPUState *s)
10439{
10440 PowerPCCPU *cpu = POWERPC_CPU(s);
10441 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10442 CPUPPCState *env = &cpu->env;
a1389542 10443 target_ulong msr;
d197fdbc 10444 int i;
a1389542 10445
1d0cb67d
AF		 10446 pcc->parent_reset(s);
10447
a1389542 10448 msr = (target_ulong)0;
932ccbdd 10449 msr |= (target_ulong)MSR_HVB;
a1389542
AF		 10450 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10451 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10452 msr |= (target_ulong)1 << MSR_EP;
10453#if defined(DO_SINGLE_STEP) && 0
10454 /* Single step trace mode */
10455 msr |= (target_ulong)1 << MSR_SE;
10456 msr |= (target_ulong)1 << MSR_BE;
10457#endif
10458#if defined(CONFIG_USER_ONLY)
10459 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10460 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
5b274ed7 10461 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
a1389542
AF		 10462 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10463 msr |= (target_ulong)1 << MSR_PR;
cdcdda27
AK		 10464#if defined(TARGET_PPC64)
10465 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
10466#endif
e22c357b
DK		 10467#if !defined(TARGET_WORDS_BIGENDIAN)
10468 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
a74029f6
RH		 10469 if (!((env->msr_mask >> MSR_LE) & 1)) {
10470 fprintf(stderr, "Selected CPU does not support little-endian.\n");
10471 exit(1);
10472 }
e22c357b 10473#endif
a1389542 10474#endif
2cf3eb6d 10475
a1389542
AF		 10476#if defined(TARGET_PPC64)
10477 if (env->mmu_model & POWERPC_MMU_64) {
8b9f2118 10478 msr |= (1ULL << MSR_SF);
a1389542
AF		 10479 }
10480#endif
2cf3eb6d
FC		 10481
10482 hreg_store_msr(env, msr, 1);
10483
10484#if !defined(CONFIG_USER_ONLY)
10485 env->nip = env->hreset_vector | env->excp_prefix;
10486 if (env->mmu_model != POWERPC_MMU_REAL) {
10487 ppc_tlb_invalidate_all(env);
10488 }
10489#endif
10490
a1389542
AF		 10491 hreg_compute_hflags(env);
10492 env->reserve_addr = (target_ulong)-1ULL;
10493 /* Be sure no exception or interrupt is pending */
10494 env->pending_interrupts = 0;
27103424 10495 s->exception_index = POWERPC_EXCP_NONE;
a1389542 10496 env->error_code = 0;
2b15811c
DG		 10497
10498#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1bfb37d1
DG		 10499 env->vpa_addr = 0;
10500 env->slb_shadow_addr = 0;
10501 env->slb_shadow_size = 0;
10502 env->dtl_addr = 0;
2b15811c
DG		 10503 env->dtl_size = 0;
10504#endif /* TARGET_PPC64 */
10505
d197fdbc
AK		 10506 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
10507 ppc_spr_t *spr = &env->spr_cb[i];
10508
10509 if (!spr->name) {
10510 continue;
10511 }
10512 env->spr[i] = spr->default_value;
10513 }
1d0cb67d
AF		 10514}
10515
7826c2b2
GK		 10516#ifndef CONFIG_USER_ONLY
10517static bool ppc_cpu_is_big_endian(CPUState *cs)
10518{
10519 PowerPCCPU *cpu = POWERPC_CPU(cs);
10520 CPUPPCState *env = &cpu->env;
10521
10522 cpu_synchronize_state(cs);
10523
10524 return !msr_le;
10525}
10526#endif
10527
6cca7ad6
AF		 10528static void ppc_cpu_initfn(Object *obj)
10529{
c05efcb1 10530 CPUState *cs = CPU(obj);
6cca7ad6 10531 PowerPCCPU *cpu = POWERPC_CPU(obj);
2985b86b 10532 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6cca7ad6
AF		 10533 CPUPPCState *env = &cpu->env;
10534
c05efcb1 10535 cs->env_ptr = env;
2985b86b 10536
cfe34f44
AF		 10537 env->msr_mask = pcc->msr_mask;
10538 env->mmu_model = pcc->mmu_model;
10539 env->excp_model = pcc->excp_model;
10540 env->bus_model = pcc->bus_model;
10541 env->insns_flags = pcc->insns_flags;
10542 env->insns_flags2 = pcc->insns_flags2;
10543 env->flags = pcc->flags;
10544 env->bfd_mach = pcc->bfd_mach;
10545 env->check_pow = pcc->check_pow;
2985b86b 10546
932ccbdd
BH		 10547 /* Mark HV mode as supported if the CPU has an MSR_HV bit
10548 * in the msr_mask. The mask can later be cleared by PAPR
10549 * mode but the hv mode support will remain, thus enforcing
10550 * that we cannot use priv. instructions in guest in PAPR
10551 * mode. For 970 we currently simply don't set HV in msr_mask
10552 * thus simulating an "Apple mode" 970. If we ever want to
10553 * support 970 HV mode, we'll have to add a processor attribute
10554 * of some sort.
10555 */
10556#if !defined(CONFIG_USER_ONLY)
10557 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10558#endif
10559
2985b86b 10560#if defined(TARGET_PPC64)
cfe34f44
AF		 10561 if (pcc->sps) {
10562 env->sps = *pcc->sps;
2985b86b 10563 } else if (env->mmu_model & POWERPC_MMU_64) {
4322e8ce
BH		 10564 /* Use default sets of page sizes. We don't support MPSS */
10565 static const struct ppc_segment_page_sizes defsps_4k = {
2985b86b
AF		 10566 .sps = {
10567 { .page_shift = 12, /* 4K */
10568 .slb_enc = 0,
10569 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10570 },
10571 { .page_shift = 24, /* 16M */
10572 .slb_enc = 0x100,
10573 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10574 },
10575 },
10576 };
4322e8ce
BH		 10577 static const struct ppc_segment_page_sizes defsps_64k = {
10578 .sps = {
10579 { .page_shift = 12, /* 4K */
10580 .slb_enc = 0,
10581 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10582 },
10583 { .page_shift = 16, /* 64K */
10584 .slb_enc = 0x110,
10585 .enc = { { .page_shift = 16, .pte_enc = 1 } }
10586 },
10587 { .page_shift = 24, /* 16M */
10588 .slb_enc = 0x100,
10589 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10590 },
10591 },
10592 };
10593 env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
2985b86b
AF		 10594 }
10595#endif /* defined(TARGET_PPC64) */
60925d26
AF		 10596
10597 if (tcg_enabled()) {
10598 ppc_translate_init();
10599 }
6cca7ad6
AF		 10600}
10601
03ae4133
AK		 10602static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10603{
10604 return pcc->pvr == pvr;
10605}
10606
b3820e6c
DH		 10607static gchar *ppc_gdb_arch_name(CPUState *cs)
10608{
10609#if defined(TARGET_PPC64)
10610 return g_strdup("powerpc:common64");
10611#else
10612 return g_strdup("powerpc:common");
10613#endif
10614}
10615
146c11f1
DG		 10616static Property ppc_cpu_properties[] = {
10617 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
10618 DEFINE_PROP_END_OF_LIST(),
10619};
10620
1d0cb67d
AF		 10621static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10622{
10623 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10624 CPUClass *cc = CPU_CLASS(oc);
4776ce60
AF		 10625 DeviceClass *dc = DEVICE_CLASS(oc);
10626
10627 pcc->parent_realize = dc->realize;
7bbc124e 10628 pcc->parent_unrealize = dc->unrealize;
03ae4133 10629 pcc->pvr_match = ppc_pvr_match_default;
382d2db6 10630 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
4776ce60 10631 dc->realize = ppc_cpu_realizefn;
b048960f 10632 dc->unrealize = ppc_cpu_unrealizefn;
146c11f1 10633 dc->props = ppc_cpu_properties;
1d0cb67d
AF		 10634
10635 pcc->parent_reset = cc->reset;
10636 cc->reset = ppc_cpu_reset;
2b8c2754
AF		 10637
10638 cc->class_by_name = ppc_cpu_class_by_name;
8c2e1b00 10639 cc->has_work = ppc_cpu_has_work;
97a8ea5a 10640 cc->do_interrupt = ppc_cpu_do_interrupt;
458dd766 10641 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
878096ee
AF		 10642 cc->dump_state = ppc_cpu_dump_state;
10643 cc->dump_statistics = ppc_cpu_dump_statistics;
f45748f1 10644 cc->set_pc = ppc_cpu_set_pc;
5b50e790
AF		 10645 cc->gdb_read_register = ppc_cpu_gdb_read_register;
10646 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7510454e
AF		 10647#ifdef CONFIG_USER_ONLY
10648 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
10649#else
00b941e5 10650 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
a90db158 10651 cc->vmsd = &vmstate_ppc_cpu;
00b941e5 10652#endif
774f0abe 10653 cc->cpu_exec_enter = ppc_cpu_exec_enter;
356bb70e
MN		 10654#if defined(CONFIG_SOFTMMU)
10655 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10656 cc->write_elf32_note = ppc32_cpu_write_elf32_note;
10657#endif
a0e372f0
AF		 10658
10659 cc->gdb_num_core_regs = 71;
b3cad3ab
AG		 10660
10661#ifdef USE_APPLE_GDB
10662 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10663 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10664 cc->gdb_num_core_regs = 71 + 32;
10665#endif
10666
b3820e6c 10667 cc->gdb_arch_name = ppc_gdb_arch_name;
5b24c641
AF		 10668#if defined(TARGET_PPC64)
10669 cc->gdb_core_xml_file = "power64-core.xml";
10670#else
10671 cc->gdb_core_xml_file = "power-core.xml";
10672#endif
7826c2b2
GK		 10673#ifndef CONFIG_USER_ONLY
10674 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10675#endif
3bbf37f2
AF		 10676
10677 dc->fw_name = "PowerPC,UNKNOWN";
1d0cb67d
AF		 10678}
10679
10680static const TypeInfo ppc_cpu_type_info = {
10681 .name = TYPE_POWERPC_CPU,
10682 .parent = TYPE_CPU,
10683 .instance_size = sizeof(PowerPCCPU),
6cca7ad6 10684 .instance_init = ppc_cpu_initfn,
2985b86b 10685 .abstract = true,
1d0cb67d
AF		 10686 .class_size = sizeof(PowerPCCPUClass),
10687 .class_init = ppc_cpu_class_init,
10688};
10689
1d1be34d
DG		 10690static const TypeInfo ppc_vhyp_type_info = {
10691 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
10692 .parent = TYPE_INTERFACE,
10693 .class_size = sizeof(PPCVirtualHypervisorClass),
10694};
10695
1d0cb67d
AF		 10696static void ppc_cpu_register_types(void)
10697{
10698 type_register_static(&ppc_cpu_type_info);
1d1be34d 10699 type_register_static(&ppc_vhyp_type_info);
1d0cb67d
AF		 10700}
10701
10702type_init(ppc_cpu_register_types)
Empty description
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