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cpu: Move numa_node field to CPUState
[qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
f7aa5583 5 * Copyright 2011 Freescale Semiconductor, Inc.
3fc6c082
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
76cad711 26#include "disas/bfd.h"
022c62cb 27#include "exec/gdbstub.h"
9c17d615 28#include <sysemu/kvm.h>
a1e98583 29#include "kvm_ppc.h"
9c17d615 30#include "sysemu/arch_init.h"
237c0af0 31
3fc6c082
FB		 32//#define PPC_DUMP_CPU
33//#define PPC_DEBUG_SPR
80d11f44
JM		 34//#define PPC_DUMP_SPR_ACCESSES
35#if defined(CONFIG_USER_ONLY)
36#define TODO_USER_ONLY 1
37#endif
3fc6c082 38
e9df014c
JM		 39/* For user-mode emulation, we don't emulate any IRQ controller */
40#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 41#define PPC_IRQ_INIT_FN(name) \
42static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43{ \
e9df014c
JM		 44}
45#else
a750fc0b 46#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 47void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48#endif
a750fc0b 49
4e290a0b 50PPC_IRQ_INIT_FN(40x);
e9df014c 51PPC_IRQ_INIT_FN(6xx);
d0dfae6e 52PPC_IRQ_INIT_FN(970);
9d52e907 53PPC_IRQ_INIT_FN(POWER7);
9fdc60bf 54PPC_IRQ_INIT_FN(e500);
e9df014c 55
3fc6c082
FB		 56/* Generic callbacks:
57 * do nothing but store/retrieve spr value
58 */
91f477fd
AG		 59static void spr_load_dump_spr(int sprn)
60{
61#ifdef PPC_DUMP_SPR_ACCESSES
62 TCGv_i32 t0 = tcg_const_i32(sprn);
63 gen_helper_load_dump_spr(t0);
64 tcg_temp_free_i32(t0);
65#endif
66}
67
45d827d2 68static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 69{
45d827d2 70 gen_load_spr(cpu_gpr[gprn], sprn);
91f477fd
AG		 71 spr_load_dump_spr(sprn);
72}
73
74static void spr_store_dump_spr(int sprn)
75{
45d827d2 76#ifdef PPC_DUMP_SPR_ACCESSES
91f477fd
AG		 77 TCGv_i32 t0 = tcg_const_i32(sprn);
78 gen_helper_store_dump_spr(t0);
79 tcg_temp_free_i32(t0);
45d827d2 80#endif
a496775f
JM		 81}
82
45d827d2 83static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 84{
45d827d2 85 gen_store_spr(sprn, cpu_gpr[gprn]);
91f477fd 86 spr_store_dump_spr(sprn);
45d827d2 87}
a496775f
JM		 88
89#if !defined(CONFIG_USER_ONLY)
ba38ab8d
AG		 90static void spr_write_generic32(void *opaque, int sprn, int gprn)
91{
92#ifdef TARGET_PPC64
93 TCGv t0 = tcg_temp_new();
94 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
95 gen_store_spr(sprn, t0);
96 tcg_temp_free(t0);
97 spr_store_dump_spr(sprn);
98#else
99 spr_write_generic(opaque, sprn, gprn);
100#endif
101}
102
45d827d2 103static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 104{
45d827d2
AJ		 105 TCGv t0 = tcg_temp_new();
106 TCGv t1 = tcg_temp_new();
107 gen_load_spr(t0, sprn);
108 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
109 tcg_gen_and_tl(t0, t0, t1);
110 gen_store_spr(sprn, t0);
111 tcg_temp_free(t0);
112 tcg_temp_free(t1);
a496775f
JM		 113}
114#endif
115
76a66253 116/* SPR common to all PowerPC */
3fc6c082 117/* XER */
45d827d2 118static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 119{
45d827d2 120 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 121}
122
45d827d2 123static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 124{
45d827d2 125 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 126}
127
128/* LR */
45d827d2 129static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 130{
45d827d2 131 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 132}
133
45d827d2 134static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 135{
45d827d2 136 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 137}
138
697ab892
DG		 139/* CFAR */
140#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
141static void spr_read_cfar (void *opaque, int gprn, int sprn)
142{
143 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
144}
145
146static void spr_write_cfar (void *opaque, int sprn, int gprn)
147{
148 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
149}
150#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
151
3fc6c082 152/* CTR */
45d827d2 153static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 154{
45d827d2 155 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 156}
157
45d827d2 158static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 159{
45d827d2 160 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 161}
162
163/* User read access to SPR */
164/* USPRx */
165/* UMMCRx */
166/* UPMCx */
167/* USIA */
168/* UDECR */
45d827d2 169static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 170{
45d827d2 171 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 172}
173
76a66253 174/* SPR common to all non-embedded PowerPC */
3fc6c082 175/* DECR */
76a66253 176#if !defined(CONFIG_USER_ONLY)
45d827d2 177static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 178{
630ecca0
TG		 179 if (use_icount) {
180 gen_io_start();
181 }
d0f1562d 182 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 183 if (use_icount) {
184 gen_io_end();
185 gen_stop_exception(opaque);
186 }
3fc6c082
FB		 187}
188
45d827d2 189static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 190{
630ecca0
TG		 191 if (use_icount) {
192 gen_io_start();
193 }
d0f1562d 194 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 195 if (use_icount) {
196 gen_io_end();
197 gen_stop_exception(opaque);
198 }
3fc6c082 199}
76a66253 200#endif
3fc6c082 201
76a66253 202/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 203/* Time base */
45d827d2 204static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 205{
630ecca0
TG		 206 if (use_icount) {
207 gen_io_start();
208 }
d0f1562d 209 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 210 if (use_icount) {
211 gen_io_end();
212 gen_stop_exception(opaque);
213 }
3fc6c082
FB		 214}
215
45d827d2 216static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 217{
630ecca0
TG		 218 if (use_icount) {
219 gen_io_start();
220 }
d0f1562d 221 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 222 if (use_icount) {
223 gen_io_end();
224 gen_stop_exception(opaque);
225 }
3fc6c082
FB		 226}
227
a062e36c 228__attribute__ (( unused ))
45d827d2 229static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 230{
d0f1562d 231 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 232}
233
234__attribute__ (( unused ))
45d827d2 235static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 236{
d0f1562d 237 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 238}
239
76a66253 240#if !defined(CONFIG_USER_ONLY)
45d827d2 241static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 242{
630ecca0
TG		 243 if (use_icount) {
244 gen_io_start();
245 }
d0f1562d 246 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 247 if (use_icount) {
248 gen_io_end();
249 gen_stop_exception(opaque);
250 }
3fc6c082
FB		 251}
252
45d827d2 253static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 254{
630ecca0
TG		 255 if (use_icount) {
256 gen_io_start();
257 }
d0f1562d 258 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 259 if (use_icount) {
260 gen_io_end();
261 gen_stop_exception(opaque);
262 }
3fc6c082 263}
a062e36c
JM		 264
265__attribute__ (( unused ))
45d827d2 266static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 267{
d0f1562d 268 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
a062e36c
JM		 269}
270
271__attribute__ (( unused ))
45d827d2 272static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 273{
d0f1562d 274 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
a062e36c 275}
3a7f009a
DG		 276
277#if defined(TARGET_PPC64)
278__attribute__ (( unused ))
279static void spr_read_purr (void *opaque, int gprn, int sprn)
280{
d0f1562d 281 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
3a7f009a
DG		 282}
283#endif
76a66253 284#endif
3fc6c082 285
76a66253 286#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 287/* IBAT0U...IBAT0U */
288/* IBAT0L...IBAT7L */
45d827d2 289static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 290{
1328c2bf 291 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 292}
293
45d827d2 294static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 295{
1328c2bf 296 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 297}
298
45d827d2 299static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 300{
45d827d2 301 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 302 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 303 tcg_temp_free_i32(t0);
3fc6c082
FB		 304}
305
45d827d2 306static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 307{
8daf1781 308 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
c6c7cf05 309 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 310 tcg_temp_free_i32(t0);
3fc6c082
FB		 311}
312
45d827d2 313static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 314{
45d827d2 315 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
c6c7cf05 316 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 317 tcg_temp_free_i32(t0);
3fc6c082
FB		 318}
319
45d827d2 320static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 321{
8daf1781 322 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
c6c7cf05 323 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 324 tcg_temp_free_i32(t0);
3fc6c082
FB		 325}
326
327/* DBAT0U...DBAT7U */
328/* DBAT0L...DBAT7L */
45d827d2 329static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 330{
1328c2bf 331 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 332}
333
45d827d2 334static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 335{
1328c2bf 336 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 337}
338
45d827d2 339static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 340{
45d827d2 341 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
c6c7cf05 342 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 343 tcg_temp_free_i32(t0);
3fc6c082
FB		 344}
345
45d827d2 346static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 347{
45d827d2 348 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
c6c7cf05 349 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 350 tcg_temp_free_i32(t0);
3fc6c082
FB		 351}
352
45d827d2 353static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 354{
45d827d2 355 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
c6c7cf05 356 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 357 tcg_temp_free_i32(t0);
3fc6c082
FB		 358}
359
45d827d2 360static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 361{
45d827d2 362 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
c6c7cf05 363 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 364 tcg_temp_free_i32(t0);
3fc6c082
FB		 365}
366
367/* SDR1 */
45d827d2 368static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 369{
d523dd00 370 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
3fc6c082
FB		 371}
372
76a66253
JM		 373/* 64 bits PowerPC specific SPRs */
374/* ASR */
578bb252 375#if defined(TARGET_PPC64)
2adab7d6
BS		 376static void spr_read_hior (void *opaque, int gprn, int sprn)
377{
1328c2bf 378 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 379}
380
381static void spr_write_hior (void *opaque, int sprn, int gprn)
382{
383 TCGv t0 = tcg_temp_new();
384 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
1328c2bf 385 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 386 tcg_temp_free(t0);
387}
388
45d827d2 389static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 390{
1328c2bf 391 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
76a66253
JM		 392}
393
45d827d2 394static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 395{
d523dd00 396 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 397}
398#endif
a750fc0b 399#endif
76a66253
JM		 400
401/* PowerPC 601 specific registers */
402/* RTC */
45d827d2 403static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 404{
d0f1562d 405 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
76a66253
JM		 406}
407
45d827d2 408static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 409{
d0f1562d 410 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
76a66253
JM		 411}
412
413#if !defined(CONFIG_USER_ONLY)
45d827d2 414static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 415{
d0f1562d 416 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 417}
418
45d827d2 419static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 420{
d0f1562d 421 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
76a66253 422}
056401ea 423
45d827d2 424static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 425{
426 DisasContext *ctx = opaque;
427
d523dd00 428 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
056401ea 429 /* Must stop the translation as endianness may have changed */
e06fcd75 430 gen_stop_exception(ctx);
056401ea 431}
76a66253
JM		 432#endif
433
434/* Unified bats */
435#if !defined(CONFIG_USER_ONLY)
45d827d2 436static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 437{
1328c2bf 438 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 439}
440
45d827d2 441static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 442{
45d827d2 443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 444 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 445 tcg_temp_free_i32(t0);
76a66253
JM		 446}
447
45d827d2 448static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 449{
45d827d2 450 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 451 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 452 tcg_temp_free_i32(t0);
76a66253
JM		 453}
454#endif
455
456/* PowerPC 40x specific registers */
457#if !defined(CONFIG_USER_ONLY)
45d827d2 458static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 459{
d0f1562d 460 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
76a66253
JM		 461}
462
45d827d2 463static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 464{
d0f1562d 465 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 466}
467
45d827d2 468static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 469{
470 DisasContext *ctx = opaque;
471
d523dd00 472 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
8ecc7913 473 /* We must stop translation as we may have rebooted */
e06fcd75 474 gen_stop_exception(ctx);
8ecc7913
JM		 475}
476
45d827d2 477static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 478{
d523dd00 479 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
c294fc58
JM		 480}
481
45d827d2 482static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 483{
d0f1562d 484 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 485}
486
45d827d2 487static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 488{
d0f1562d 489 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 490}
491#endif
492
493/* PowerPC 403 specific registers */
494/* PBL1 / PBU1 / PBL2 / PBU2 */
495#if !defined(CONFIG_USER_ONLY)
45d827d2 496static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 497{
1328c2bf 498 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 499}
500
45d827d2 501static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 502{
45d827d2 503 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
d523dd00 504 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 505 tcg_temp_free_i32(t0);
76a66253
JM		 506}
507
45d827d2 508static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 509{
45d827d2
AJ		 510 TCGv t0 = tcg_temp_new();
511 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
512 gen_store_spr(SPR_PIR, t0);
513 tcg_temp_free(t0);
3fc6c082 514}
76a66253 515#endif
3fc6c082 516
d34defbc
AJ		 517/* SPE specific registers */
518static void spr_read_spefscr (void *opaque, int gprn, int sprn)
519{
520 TCGv_i32 t0 = tcg_temp_new_i32();
1328c2bf 521 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 522 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
523 tcg_temp_free_i32(t0);
524}
525
526static void spr_write_spefscr (void *opaque, int sprn, int gprn)
527{
528 TCGv_i32 t0 = tcg_temp_new_i32();
529 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1328c2bf 530 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 531 tcg_temp_free_i32(t0);
532}
533
6f5d427d
JM		 534#if !defined(CONFIG_USER_ONLY)
535/* Callback used to write the exception vector base */
45d827d2 536static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 537{
45d827d2 538 TCGv t0 = tcg_temp_new();
1328c2bf 539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
45d827d2 540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
45d827d2 542 gen_store_spr(sprn, t0);
69bd5820 543 tcg_temp_free(t0);
6f5d427d
JM		 544}
545
45d827d2 546static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 547{
548 DisasContext *ctx = opaque;
e9205258 549 int sprn_offs;
6f5d427d
JM		 550
551 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
e9205258 552 sprn_offs = sprn - SPR_BOOKE_IVOR0;
6f5d427d 553 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
e9205258
AG		 554 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
555 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
556 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
6f5d427d
JM		 557 } else {
558 printf("Trying to write an unknown exception vector %d %03x\n",
559 sprn, sprn);
e06fcd75 560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
e9205258 561 return;
6f5d427d 562 }
e9205258
AG		 563
564 TCGv t0 = tcg_temp_new();
1328c2bf 565 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
e9205258 566 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 567 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
e9205258
AG		 568 gen_store_spr(sprn, t0);
569 tcg_temp_free(t0);
6f5d427d
JM		 570}
571#endif
572
cf8358c8
AJ		 573static inline void vscr_init (CPUPPCState *env, uint32_t val)
574{
575 env->vscr = val;
576 /* Altivec always uses round-to-nearest */
577 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
578 set_flush_to_zero(vscr_nj, &env->vec_status);
579}
580
76a66253
JM		 581#if defined(CONFIG_USER_ONLY)
582#define spr_register(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, initial_value) \
584do { \
585 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
586} while (0)
587static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 588 const char *name,
45d827d2
AJ		 589 void (*uea_read)(void *opaque, int gprn, int sprn),
590 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 591 target_ulong initial_value)
592#else
3fc6c082 593static inline void spr_register (CPUPPCState *env, int num,
b55266b5 594 const char *name,
45d827d2
AJ		 595 void (*uea_read)(void *opaque, int gprn, int sprn),
596 void (*uea_write)(void *opaque, int sprn, int gprn),
597 void (*oea_read)(void *opaque, int gprn, int sprn),
598 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 599 target_ulong initial_value)
76a66253 600#endif
3fc6c082 601{
c227f099 602 ppc_spr_t *spr;
3fc6c082
FB		 603
604 spr = &env->spr_cb[num];
605 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 606#if !defined(CONFIG_USER_ONLY)
607 spr->oea_read != NULL || spr->oea_write != NULL ||
608#endif
609 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 610 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
611 exit(1);
612 }
613#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 614 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
615 name, initial_value);
3fc6c082
FB		 616#endif
617 spr->name = name;
618 spr->uea_read = uea_read;
619 spr->uea_write = uea_write;
76a66253 620#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 621 spr->oea_read = oea_read;
622 spr->oea_write = oea_write;
76a66253 623#endif
3fc6c082
FB		 624 env->spr[num] = initial_value;
625}
626
627/* Generic PowerPC SPRs */
628static void gen_spr_generic (CPUPPCState *env)
629{
630 /* Integer processing */
631 spr_register(env, SPR_XER, "XER",
632 &spr_read_xer, &spr_write_xer,
633 &spr_read_xer, &spr_write_xer,
634 0x00000000);
635 /* Branch contol */
636 spr_register(env, SPR_LR, "LR",
637 &spr_read_lr, &spr_write_lr,
638 &spr_read_lr, &spr_write_lr,
639 0x00000000);
640 spr_register(env, SPR_CTR, "CTR",
641 &spr_read_ctr, &spr_write_ctr,
642 &spr_read_ctr, &spr_write_ctr,
643 0x00000000);
644 /* Interrupt processing */
645 spr_register(env, SPR_SRR0, "SRR0",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649 spr_register(env, SPR_SRR1, "SRR1",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_generic, &spr_write_generic,
652 0x00000000);
653 /* Processor control */
654 spr_register(env, SPR_SPRG0, "SPRG0",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_generic, &spr_write_generic,
657 0x00000000);
658 spr_register(env, SPR_SPRG1, "SPRG1",
659 SPR_NOACCESS, SPR_NOACCESS,
660 &spr_read_generic, &spr_write_generic,
661 0x00000000);
662 spr_register(env, SPR_SPRG2, "SPRG2",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_generic, &spr_write_generic,
665 0x00000000);
666 spr_register(env, SPR_SPRG3, "SPRG3",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_generic, &spr_write_generic,
669 0x00000000);
670}
671
672/* SPR common to all non-embedded PowerPC, including 601 */
673static void gen_spr_ne_601 (CPUPPCState *env)
674{
675 /* Exception processing */
676 spr_register(env, SPR_DSISR, "DSISR",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 spr_register(env, SPR_DAR, "DAR",
681 SPR_NOACCESS, SPR_NOACCESS,
682 &spr_read_generic, &spr_write_generic,
683 0x00000000);
684 /* Timer */
685 spr_register(env, SPR_DECR, "DECR",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_decr, &spr_write_decr,
688 0x00000000);
689 /* Memory management */
690 spr_register(env, SPR_SDR1, "SDR1",
691 SPR_NOACCESS, SPR_NOACCESS,
bb593904 692 &spr_read_generic, &spr_write_sdr1,
3fc6c082
FB		 693 0x00000000);
694}
695
696/* BATs 0-3 */
697static void gen_low_BATs (CPUPPCState *env)
698{
f2e63a42 699#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 700 spr_register(env, SPR_IBAT0U, "IBAT0U",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_ibat, &spr_write_ibatu,
703 0x00000000);
704 spr_register(env, SPR_IBAT0L, "IBAT0L",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat, &spr_write_ibatl,
707 0x00000000);
708 spr_register(env, SPR_IBAT1U, "IBAT1U",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat, &spr_write_ibatu,
711 0x00000000);
712 spr_register(env, SPR_IBAT1L, "IBAT1L",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_ibat, &spr_write_ibatl,
715 0x00000000);
716 spr_register(env, SPR_IBAT2U, "IBAT2U",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_ibat, &spr_write_ibatu,
719 0x00000000);
720 spr_register(env, SPR_IBAT2L, "IBAT2L",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_ibat, &spr_write_ibatl,
723 0x00000000);
724 spr_register(env, SPR_IBAT3U, "IBAT3U",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_ibat, &spr_write_ibatu,
727 0x00000000);
728 spr_register(env, SPR_IBAT3L, "IBAT3L",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_ibat, &spr_write_ibatl,
731 0x00000000);
732 spr_register(env, SPR_DBAT0U, "DBAT0U",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_dbat, &spr_write_dbatu,
735 0x00000000);
736 spr_register(env, SPR_DBAT0L, "DBAT0L",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat, &spr_write_dbatl,
739 0x00000000);
740 spr_register(env, SPR_DBAT1U, "DBAT1U",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat, &spr_write_dbatu,
743 0x00000000);
744 spr_register(env, SPR_DBAT1L, "DBAT1L",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_dbat, &spr_write_dbatl,
747 0x00000000);
748 spr_register(env, SPR_DBAT2U, "DBAT2U",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_dbat, &spr_write_dbatu,
751 0x00000000);
752 spr_register(env, SPR_DBAT2L, "DBAT2L",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_dbat, &spr_write_dbatl,
755 0x00000000);
756 spr_register(env, SPR_DBAT3U, "DBAT3U",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_dbat, &spr_write_dbatu,
759 0x00000000);
760 spr_register(env, SPR_DBAT3L, "DBAT3L",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_dbat, &spr_write_dbatl,
763 0x00000000);
a750fc0b 764 env->nb_BATs += 4;
f2e63a42 765#endif
3fc6c082
FB		 766}
767
768/* BATs 4-7 */
769static void gen_high_BATs (CPUPPCState *env)
770{
f2e63a42 771#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 772 spr_register(env, SPR_IBAT4U, "IBAT4U",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_ibat_h, &spr_write_ibatu_h,
775 0x00000000);
776 spr_register(env, SPR_IBAT4L, "IBAT4L",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat_h, &spr_write_ibatl_h,
779 0x00000000);
780 spr_register(env, SPR_IBAT5U, "IBAT5U",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat_h, &spr_write_ibatu_h,
783 0x00000000);
784 spr_register(env, SPR_IBAT5L, "IBAT5L",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_ibat_h, &spr_write_ibatl_h,
787 0x00000000);
788 spr_register(env, SPR_IBAT6U, "IBAT6U",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_ibat_h, &spr_write_ibatu_h,
791 0x00000000);
792 spr_register(env, SPR_IBAT6L, "IBAT6L",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat_h, &spr_write_ibatl_h,
795 0x00000000);
796 spr_register(env, SPR_IBAT7U, "IBAT7U",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_ibat_h, &spr_write_ibatu_h,
799 0x00000000);
800 spr_register(env, SPR_IBAT7L, "IBAT7L",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_ibat_h, &spr_write_ibatl_h,
803 0x00000000);
804 spr_register(env, SPR_DBAT4U, "DBAT4U",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_dbat_h, &spr_write_dbatu_h,
807 0x00000000);
808 spr_register(env, SPR_DBAT4L, "DBAT4L",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat_h, &spr_write_dbatl_h,
811 0x00000000);
812 spr_register(env, SPR_DBAT5U, "DBAT5U",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat_h, &spr_write_dbatu_h,
815 0x00000000);
816 spr_register(env, SPR_DBAT5L, "DBAT5L",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_dbat_h, &spr_write_dbatl_h,
819 0x00000000);
820 spr_register(env, SPR_DBAT6U, "DBAT6U",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_dbat_h, &spr_write_dbatu_h,
823 0x00000000);
824 spr_register(env, SPR_DBAT6L, "DBAT6L",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat_h, &spr_write_dbatl_h,
827 0x00000000);
828 spr_register(env, SPR_DBAT7U, "DBAT7U",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_dbat_h, &spr_write_dbatu_h,
831 0x00000000);
832 spr_register(env, SPR_DBAT7L, "DBAT7L",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_dbat_h, &spr_write_dbatl_h,
835 0x00000000);
a750fc0b 836 env->nb_BATs += 4;
f2e63a42 837#endif
3fc6c082
FB		 838}
839
840/* Generic PowerPC time base */
841static void gen_tbl (CPUPPCState *env)
842{
843 spr_register(env, SPR_VTBL, "TBL",
844 &spr_read_tbl, SPR_NOACCESS,
845 &spr_read_tbl, SPR_NOACCESS,
846 0x00000000);
847 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 848 &spr_read_tbl, SPR_NOACCESS,
849 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 850 0x00000000);
851 spr_register(env, SPR_VTBU, "TBU",
852 &spr_read_tbu, SPR_NOACCESS,
853 &spr_read_tbu, SPR_NOACCESS,
854 0x00000000);
855 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 856 &spr_read_tbu, SPR_NOACCESS,
857 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 858 0x00000000);
859}
860
76a66253
JM		 861/* Softare table search registers */
862static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
863{
f2e63a42 864#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 865 env->nb_tlb = nb_tlbs;
866 env->nb_ways = nb_ways;
867 env->id_tlbs = 1;
1c53accc 868 env->tlb_type = TLB_6XX;
76a66253
JM		 869 spr_register(env, SPR_DMISS, "DMISS",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, SPR_NOACCESS,
872 0x00000000);
873 spr_register(env, SPR_DCMP, "DCMP",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, SPR_NOACCESS,
876 0x00000000);
877 spr_register(env, SPR_HASH1, "HASH1",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, SPR_NOACCESS,
880 0x00000000);
881 spr_register(env, SPR_HASH2, "HASH2",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, SPR_NOACCESS,
884 0x00000000);
885 spr_register(env, SPR_IMISS, "IMISS",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, SPR_NOACCESS,
888 0x00000000);
889 spr_register(env, SPR_ICMP, "ICMP",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 0x00000000);
893 spr_register(env, SPR_RPA, "RPA",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, &spr_write_generic,
896 0x00000000);
f2e63a42 897#endif
76a66253
JM		 898}
899
900/* SPR common to MPC755 and G2 */
901static void gen_spr_G2_755 (CPUPPCState *env)
902{
903 /* SGPRs */
904 spr_register(env, SPR_SPRG4, "SPRG4",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, &spr_write_generic,
907 0x00000000);
908 spr_register(env, SPR_SPRG5, "SPRG5",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, &spr_write_generic,
911 0x00000000);
912 spr_register(env, SPR_SPRG6, "SPRG6",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 spr_register(env, SPR_SPRG7, "SPRG7",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
76a66253
JM		 920}
921
3fc6c082
FB		 922/* SPR common to all 7xx PowerPC implementations */
923static void gen_spr_7xx (CPUPPCState *env)
924{
925 /* Breakpoints */
926 /* XXX : not implemented */
927 spr_register(env, SPR_DABR, "DABR",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 /* XXX : not implemented */
932 spr_register(env, SPR_IABR, "IABR",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* Cache management */
937 /* XXX : not implemented */
938 spr_register(env, SPR_ICTC, "ICTC",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* Performance monitors */
943 /* XXX : not implemented */
944 spr_register(env, SPR_MMCR0, "MMCR0",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948 /* XXX : not implemented */
949 spr_register(env, SPR_MMCR1, "MMCR1",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953 /* XXX : not implemented */
954 spr_register(env, SPR_PMC1, "PMC1",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_PMC2, "PMC2",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_PMC3, "PMC3",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_PMC4, "PMC4",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
a750fc0b 974 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, SPR_NOACCESS,
977 0x00000000);
578bb252 978 /* XXX : not implemented */
3fc6c082
FB		 979 spr_register(env, SPR_UMMCR0, "UMMCR0",
980 &spr_read_ureg, SPR_NOACCESS,
981 &spr_read_ureg, SPR_NOACCESS,
982 0x00000000);
578bb252 983 /* XXX : not implemented */
3fc6c082
FB		 984 spr_register(env, SPR_UMMCR1, "UMMCR1",
985 &spr_read_ureg, SPR_NOACCESS,
986 &spr_read_ureg, SPR_NOACCESS,
987 0x00000000);
578bb252 988 /* XXX : not implemented */
3fc6c082
FB		 989 spr_register(env, SPR_UPMC1, "UPMC1",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
578bb252 993 /* XXX : not implemented */
3fc6c082
FB		 994 spr_register(env, SPR_UPMC2, "UPMC2",
995 &spr_read_ureg, SPR_NOACCESS,
996 &spr_read_ureg, SPR_NOACCESS,
997 0x00000000);
578bb252 998 /* XXX : not implemented */
3fc6c082
FB		 999 spr_register(env, SPR_UPMC3, "UPMC3",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
578bb252 1003 /* XXX : not implemented */
3fc6c082
FB		 1004 spr_register(env, SPR_UPMC4, "UPMC4",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
578bb252 1008 /* XXX : not implemented */
a750fc0b 1009 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
a750fc0b 1013 /* External access control */
3fc6c082 1014 /* XXX : not implemented */
a750fc0b 1015 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
a750fc0b
JM		 1019}
1020
1021static void gen_spr_thrm (CPUPPCState *env)
1022{
1023 /* Thermal management */
3fc6c082 1024 /* XXX : not implemented */
a750fc0b 1025 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* XXX : not implemented */
a750fc0b 1030 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
3fc6c082 1034 /* XXX : not implemented */
a750fc0b 1035 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039}
1040
1041/* SPR specific to PowerPC 604 implementation */
1042static void gen_spr_604 (CPUPPCState *env)
1043{
1044 /* Processor identification */
1045 spr_register(env, SPR_PIR, "PIR",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_pir,
1048 0x00000000);
1049 /* Breakpoints */
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_IABR, "IABR",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* XXX : not implemented */
1056 spr_register(env, SPR_DABR, "DABR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060 /* Performance counters */
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_MMCR0, "MMCR0",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_generic,
1065 0x00000000);
1066 /* XXX : not implemented */
3fc6c082
FB		 1067 spr_register(env, SPR_PMC1, "PMC1",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071 /* XXX : not implemented */
1072 spr_register(env, SPR_PMC2, "PMC2",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076 /* XXX : not implemented */
a750fc0b 1077 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, SPR_NOACCESS,
1080 0x00000000);
1081 /* XXX : not implemented */
1082 spr_register(env, SPR_SDA, "SDA",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, SPR_NOACCESS,
1085 0x00000000);
1086 /* External access control */
1087 /* XXX : not implemented */
1088 spr_register(env, SPR_EAR, "EAR",
1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092}
1093
76a66253
JM		 1094/* SPR specific to PowerPC 603 implementation */
1095static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1096{
76a66253
JM		 1097 /* External access control */
1098 /* XXX : not implemented */
1099 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1100 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1101 &spr_read_generic, &spr_write_generic,
1102 0x00000000);
3fc6c082
FB		 1103}
1104
76a66253
JM		 1105/* SPR specific to PowerPC G2 implementation */
1106static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1107{
76a66253
JM		 1108 /* Memory base address */
1109 /* MBAR */
578bb252 1110 /* XXX : not implemented */
76a66253
JM		 1111 spr_register(env, SPR_MBAR, "MBAR",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
76a66253 1115 /* Exception processing */
363be49c 1116 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
363be49c 1120 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* Breakpoints */
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_DABR, "DABR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_DABR2, "DABR2",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, &spr_write_generic,
1134 0x00000000);
1135 /* XXX : not implemented */
1136 spr_register(env, SPR_IABR, "IABR",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_generic, &spr_write_generic,
1139 0x00000000);
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_IABR2, "IABR2",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_IBCR, "IBCR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
1151 spr_register(env, SPR_DBCR, "DBCR",
1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155}
1156
1157/* SPR specific to PowerPC 602 implementation */
1158static void gen_spr_602 (CPUPPCState *env)
1159{
1160 /* ESA registers */
1161 /* XXX : not implemented */
1162 spr_register(env, SPR_SER, "SER",
1163 SPR_NOACCESS, SPR_NOACCESS,
1164 &spr_read_generic, &spr_write_generic,
1165 0x00000000);
1166 /* XXX : not implemented */
1167 spr_register(env, SPR_SEBR, "SEBR",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* XXX : not implemented */
a750fc0b 1172 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
1176 /* Floating point status */
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_SP, "SP",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 /* XXX : not implemented */
1183 spr_register(env, SPR_LT, "LT",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187 /* Watchdog timer */
1188 /* XXX : not implemented */
1189 spr_register(env, SPR_TCR, "TCR",
1190 SPR_NOACCESS, SPR_NOACCESS,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193 /* Interrupt base */
1194 spr_register(env, SPR_IBR, "IBR",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
a750fc0b
JM		 1198 /* XXX : not implemented */
1199 spr_register(env, SPR_IABR, "IABR",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
76a66253
JM		 1203}
1204
1205/* SPR specific to PowerPC 601 implementation */
1206static void gen_spr_601 (CPUPPCState *env)
1207{
1208 /* Multiplication/division register */
1209 /* MQ */
1210 spr_register(env, SPR_MQ, "MQ",
1211 &spr_read_generic, &spr_write_generic,
1212 &spr_read_generic, &spr_write_generic,
1213 0x00000000);
1214 /* RTC registers */
1215 spr_register(env, SPR_601_RTCU, "RTCU",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 SPR_NOACCESS, &spr_write_601_rtcu,
1218 0x00000000);
1219 spr_register(env, SPR_601_VRTCU, "RTCU",
1220 &spr_read_601_rtcu, SPR_NOACCESS,
1221 &spr_read_601_rtcu, SPR_NOACCESS,
1222 0x00000000);
1223 spr_register(env, SPR_601_RTCL, "RTCL",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 SPR_NOACCESS, &spr_write_601_rtcl,
1226 0x00000000);
1227 spr_register(env, SPR_601_VRTCL, "RTCL",
1228 &spr_read_601_rtcl, SPR_NOACCESS,
1229 &spr_read_601_rtcl, SPR_NOACCESS,
1230 0x00000000);
1231 /* Timer */
1232#if 0 /* ? */
1233 spr_register(env, SPR_601_UDECR, "UDECR",
1234 &spr_read_decr, SPR_NOACCESS,
1235 &spr_read_decr, SPR_NOACCESS,
1236 0x00000000);
1237#endif
1238 /* External access control */
1239 /* XXX : not implemented */
1240 spr_register(env, SPR_EAR, "EAR",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, &spr_write_generic,
1243 0x00000000);
1244 /* Memory management */
f2e63a42 1245#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1246 spr_register(env, SPR_IBAT0U, "IBAT0U",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_601_ubat, &spr_write_601_ubatu,
1249 0x00000000);
1250 spr_register(env, SPR_IBAT0L, "IBAT0L",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_601_ubat, &spr_write_601_ubatl,
1253 0x00000000);
1254 spr_register(env, SPR_IBAT1U, "IBAT1U",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_601_ubat, &spr_write_601_ubatu,
1257 0x00000000);
1258 spr_register(env, SPR_IBAT1L, "IBAT1L",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_601_ubat, &spr_write_601_ubatl,
1261 0x00000000);
1262 spr_register(env, SPR_IBAT2U, "IBAT2U",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_601_ubat, &spr_write_601_ubatu,
1265 0x00000000);
1266 spr_register(env, SPR_IBAT2L, "IBAT2L",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_601_ubat, &spr_write_601_ubatl,
1269 0x00000000);
1270 spr_register(env, SPR_IBAT3U, "IBAT3U",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_601_ubat, &spr_write_601_ubatu,
1273 0x00000000);
1274 spr_register(env, SPR_IBAT3L, "IBAT3L",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_601_ubat, &spr_write_601_ubatl,
1277 0x00000000);
a750fc0b 1278 env->nb_BATs = 4;
f2e63a42 1279#endif
a750fc0b
JM		 1280}
1281
1282static void gen_spr_74xx (CPUPPCState *env)
1283{
1284 /* Processor identification */
1285 spr_register(env, SPR_PIR, "PIR",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_pir,
1288 0x00000000);
1289 /* XXX : not implemented */
1290 spr_register(env, SPR_MMCR2, "MMCR2",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
578bb252 1294 /* XXX : not implemented */
a750fc0b
JM		 1295 spr_register(env, SPR_UMMCR2, "UMMCR2",
1296 &spr_read_ureg, SPR_NOACCESS,
1297 &spr_read_ureg, SPR_NOACCESS,
1298 0x00000000);
1299 /* XXX: not implemented */
1300 spr_register(env, SPR_BAMR, "BAMR",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
578bb252 1304 /* XXX : not implemented */
a750fc0b
JM		 1305 spr_register(env, SPR_MSSCR0, "MSSCR0",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Hardware implementation registers */
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_HID0, "HID0",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_HID1, "HID1",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 /* Altivec */
1321 spr_register(env, SPR_VRSAVE, "VRSAVE",
1322 &spr_read_generic, &spr_write_generic,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
bd928eba
JM		 1325 /* XXX : not implemented */
1326 spr_register(env, SPR_L2CR, "L2CR",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
cf8358c8
AJ		 1330 /* Not strictly an SPR */
1331 vscr_init(env, 0x00010000);
a750fc0b
JM		 1332}
1333
a750fc0b
JM		 1334static void gen_l3_ctrl (CPUPPCState *env)
1335{
1336 /* L3CR */
1337 /* XXX : not implemented */
1338 spr_register(env, SPR_L3CR, "L3CR",
1339 SPR_NOACCESS, SPR_NOACCESS,
1340 &spr_read_generic, &spr_write_generic,
1341 0x00000000);
1342 /* L3ITCR0 */
578bb252 1343 /* XXX : not implemented */
a750fc0b
JM		 1344 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
a750fc0b 1348 /* L3PM */
578bb252 1349 /* XXX : not implemented */
a750fc0b
JM		 1350 spr_register(env, SPR_L3PM, "L3PM",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354}
a750fc0b 1355
578bb252 1356static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1357{
f2e63a42 1358#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1359 env->nb_tlb = nb_tlbs;
1360 env->nb_ways = nb_ways;
1361 env->id_tlbs = 1;
1c53accc 1362 env->tlb_type = TLB_6XX;
578bb252 1363 /* XXX : not implemented */
a750fc0b
JM		 1364 spr_register(env, SPR_PTEHI, "PTEHI",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
578bb252 1368 /* XXX : not implemented */
a750fc0b
JM		 1369 spr_register(env, SPR_PTELO, "PTELO",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
578bb252 1373 /* XXX : not implemented */
a750fc0b
JM		 1374 spr_register(env, SPR_TLBMISS, "TLBMISS",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
f2e63a42 1378#endif
76a66253
JM		 1379}
1380
01662f3e
AG		 1381#if !defined(CONFIG_USER_ONLY)
1382static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1383{
1384 TCGv t0 = tcg_temp_new();
1385
1386 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1387 gen_store_spr(sprn, t0);
1388 tcg_temp_free(t0);
1389}
1390
1391static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1392{
1ff7854e 1393 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1394 gen_helper_booke206_tlbflush(cpu_env, t0);
1ff7854e 1395 tcg_temp_free_i32(t0);
01662f3e
AG		 1396}
1397
1398static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1399{
1ff7854e 1400 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1401 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1ff7854e 1402 tcg_temp_free_i32(t0);
01662f3e
AG		 1403}
1404#endif
1405
80d11f44 1406static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1407{
80d11f44
JM		 1408 spr_register(env, SPR_USPRG4, "USPRG4",
1409 &spr_read_ureg, SPR_NOACCESS,
1410 &spr_read_ureg, SPR_NOACCESS,
1411 0x00000000);
1412 spr_register(env, SPR_USPRG5, "USPRG5",
1413 &spr_read_ureg, SPR_NOACCESS,
1414 &spr_read_ureg, SPR_NOACCESS,
1415 0x00000000);
1416 spr_register(env, SPR_USPRG6, "USPRG6",
1417 &spr_read_ureg, SPR_NOACCESS,
1418 &spr_read_ureg, SPR_NOACCESS,
1419 0x00000000);
1420 spr_register(env, SPR_USPRG7, "USPRG7",
1421 &spr_read_ureg, SPR_NOACCESS,
1422 &spr_read_ureg, SPR_NOACCESS,
76a66253 1423 0x00000000);
80d11f44
JM		 1424}
1425
1426/* PowerPC BookE SPR */
1427static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1428{
b55266b5 1429 const char *ivor_names[64] = {
80d11f44
JM		 1430 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1431 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1432 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1433 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1434 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1435 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1436 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1437 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1438 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1439 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1440 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1441 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1442 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1443 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1444 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1445 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1446 };
1447#define SPR_BOOKE_IVORxx (-1)
1448 int ivor_sprn[64] = {
1449 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1450 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1451 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1452 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1453 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
e9205258
AG		 1458 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1459 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
80d11f44
JM		 1460 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1461 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1462 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1463 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1464 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1465 };
1466 int i;
1467
76a66253 1468 /* Interrupt processing */
363be49c 1469 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
363be49c
JM		 1473 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
76a66253
JM		 1477 /* Debug */
1478 /* XXX : not implemented */
1479 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* XXX : not implemented */
76a66253
JM		 1489 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* XXX : not implemented */
76a66253
JM		 1499 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1500 SPR_NOACCESS, SPR_NOACCESS,
e598a9c5 1501 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1502 0x00000000);
1503 /* XXX : not implemented */
1504 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_generic, &spr_write_generic,
1507 0x00000000);
1508 /* XXX : not implemented */
1509 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1510 SPR_NOACCESS, SPR_NOACCESS,
1511 &spr_read_generic, &spr_write_generic,
1512 0x00000000);
1513 /* XXX : not implemented */
1514 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1515 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1516 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1517 0x00000000);
1518 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522 spr_register(env, SPR_BOOKE_ESR, "ESR",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
363be49c
JM		 1526 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1527 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1528 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1529 0x00000000);
1530 /* Exception vectors */
80d11f44
JM		 1531 for (i = 0; i < 64; i++) {
1532 if (ivor_mask & (1ULL << i)) {
1533 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1534 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1535 exit(1);
1536 }
1537 spr_register(env, ivor_sprn[i], ivor_names[i],
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_excp_vector,
1540 0x00000000);
1541 }
1542 }
76a66253
JM		 1543 spr_register(env, SPR_BOOKE_PID, "PID",
1544 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1545 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 1546 0x00000000);
1547 spr_register(env, SPR_BOOKE_TCR, "TCR",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_booke_tcr,
1550 0x00000000);
1551 spr_register(env, SPR_BOOKE_TSR, "TSR",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_booke_tsr,
1554 0x00000000);
1555 /* Timer */
1556 spr_register(env, SPR_DECR, "DECR",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_decr, &spr_write_decr,
1559 0x00000000);
1560 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 SPR_NOACCESS, &spr_write_generic,
1563 0x00000000);
1564 /* SPRGs */
1565 spr_register(env, SPR_USPRG0, "USPRG0",
1566 &spr_read_generic, &spr_write_generic,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 spr_register(env, SPR_SPRG4, "SPRG4",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
76a66253
JM		 1573 spr_register(env, SPR_SPRG5, "SPRG5",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
76a66253
JM		 1577 spr_register(env, SPR_SPRG6, "SPRG6",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, &spr_write_generic,
1580 0x00000000);
76a66253
JM		 1581 spr_register(env, SPR_SPRG7, "SPRG7",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
76a66253
JM		 1585}
1586
01662f3e
AG		 1587static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1588 uint32_t maxsize, uint32_t flags,
1589 uint32_t nentries)
1590{
1591 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1592 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1593 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1594 flags | nentries;
1595}
1596
1597/* BookE 2.06 storage control registers */
1598static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1599 uint32_t *tlbncfg)
363be49c 1600{
f2e63a42 1601#if !defined(CONFIG_USER_ONLY)
b55266b5 1602 const char *mas_names[8] = {
80d11f44
JM		 1603 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1604 };
1605 int mas_sprn[8] = {
1606 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1607 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1608 };
1609 int i;
1610
363be49c 1611 /* TLB assist registers */
578bb252 1612 /* XXX : not implemented */
80d11f44 1613 for (i = 0; i < 8; i++) {
ba38ab8d
AG		 1614 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1615 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1616 uea_write = &spr_write_generic;
1617 }
80d11f44
JM		 1618 if (mas_mask & (1 << i)) {
1619 spr_register(env, mas_sprn[i], mas_names[i],
1620 SPR_NOACCESS, SPR_NOACCESS,
ba38ab8d 1621 &spr_read_generic, uea_write,
80d11f44
JM		 1622 0x00000000);
1623 }
1624 }
363be49c 1625 if (env->nb_pids > 1) {
578bb252 1626 /* XXX : not implemented */
363be49c
JM		 1627 spr_register(env, SPR_BOOKE_PID1, "PID1",
1628 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1629 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1630 0x00000000);
1631 }
1632 if (env->nb_pids > 2) {
578bb252 1633 /* XXX : not implemented */
363be49c
JM		 1634 spr_register(env, SPR_BOOKE_PID2, "PID2",
1635 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1636 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1637 0x00000000);
1638 }
578bb252 1639 /* XXX : not implemented */
65f9ee8d 1640 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 0x00000000); /* TOFIX */
363be49c
JM		 1644 switch (env->nb_ways) {
1645 case 4:
1646 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, SPR_NOACCESS,
01662f3e 1649 tlbncfg[3]);
363be49c
JM		 1650 /* Fallthru */
1651 case 3:
1652 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, SPR_NOACCESS,
01662f3e 1655 tlbncfg[2]);
363be49c
JM		 1656 /* Fallthru */
1657 case 2:
1658 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, SPR_NOACCESS,
01662f3e 1661 tlbncfg[1]);
363be49c
JM		 1662 /* Fallthru */
1663 case 1:
1664 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, SPR_NOACCESS,
01662f3e 1667 tlbncfg[0]);
363be49c
JM		 1668 /* Fallthru */
1669 case 0:
1670 default:
1671 break;
1672 }
f2e63a42 1673#endif
01662f3e
AG		 1674
1675 gen_spr_usprgh(env);
363be49c
JM		 1676}
1677
76a66253
JM		 1678/* SPR specific to PowerPC 440 implementation */
1679static void gen_spr_440 (CPUPPCState *env)
1680{
1681 /* Cache control */
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_440_DNV0, "DNV0",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_440_DNV1, "DNV1",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_440_DNV2, "DNV2",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DNV3, "DNV3",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
2662a059 1703 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
2662a059 1708 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
2662a059 1713 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
2662a059 1718 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_440_DVLIM, "DVLIM",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_440_INV0, "INV0",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_440_INV1, "INV1",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_440_INV2, "INV2",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_INV3, "INV3",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* XXX : not implemented */
2662a059 1748 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
2662a059 1753 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
2662a059 1758 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
2662a059 1763 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_440_IVLIM, "IVLIM",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* Cache debug */
1773 /* XXX : not implemented */
2662a059 1774 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, SPR_NOACCESS,
1777 0x00000000);
1778 /* XXX : not implemented */
2662a059 1779 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, SPR_NOACCESS,
1782 0x00000000);
1783 /* XXX : not implemented */
2662a059 1784 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, SPR_NOACCESS,
1787 0x00000000);
1788 /* XXX : not implemented */
2662a059 1789 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, SPR_NOACCESS,
1792 0x00000000);
1793 /* XXX : not implemented */
2662a059 1794 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1795 SPR_NOACCESS, SPR_NOACCESS,
1796 &spr_read_generic, SPR_NOACCESS,
1797 0x00000000);
1798 /* XXX : not implemented */
1799 spr_register(env, SPR_440_DBDR, "DBDR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
1803 /* Processor control */
1804 spr_register(env, SPR_4xx_CCR0, "CCR0",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
1808 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, SPR_NOACCESS,
1811 0x00000000);
1812 /* Storage control */
1813 spr_register(env, SPR_440_MMUCR, "MMUCR",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817}
1818
1819/* SPR shared between PowerPC 40x implementations */
1820static void gen_spr_40x (CPUPPCState *env)
1821{
1822 /* Cache */
5cbdb3a3 1823 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1824 spr_register(env, SPR_40x_DCCR, "DCCR",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
5cbdb3a3 1828 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1829 spr_register(env, SPR_40x_ICCR, "ICCR",
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, &spr_write_generic,
1832 0x00000000);
5cbdb3a3 1833 /* not emulated, as QEMU do not emulate caches */
2662a059 1834 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1835 SPR_NOACCESS, SPR_NOACCESS,
1836 &spr_read_generic, SPR_NOACCESS,
1837 0x00000000);
76a66253
JM		 1838 /* Exception */
1839 spr_register(env, SPR_40x_DEAR, "DEAR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_generic,
1842 0x00000000);
1843 spr_register(env, SPR_40x_ESR, "ESR",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, &spr_write_generic,
1846 0x00000000);
1847 spr_register(env, SPR_40x_EVPR, "EVPR",
1848 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1849 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1850 0x00000000);
1851 spr_register(env, SPR_40x_SRR2, "SRR2",
1852 &spr_read_generic, &spr_write_generic,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
1855 spr_register(env, SPR_40x_SRR3, "SRR3",
1856 &spr_read_generic, &spr_write_generic,
1857 &spr_read_generic, &spr_write_generic,
1858 0x00000000);
1859 /* Timers */
1860 spr_register(env, SPR_40x_PIT, "PIT",
1861 SPR_NOACCESS, SPR_NOACCESS,
1862 &spr_read_40x_pit, &spr_write_40x_pit,
1863 0x00000000);
1864 spr_register(env, SPR_40x_TCR, "TCR",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_booke_tcr,
1867 0x00000000);
1868 spr_register(env, SPR_40x_TSR, "TSR",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_booke_tsr,
1871 0x00000000);
2662a059
JM		 1872}
1873
1874/* SPR specific to PowerPC 405 implementation */
1875static void gen_spr_405 (CPUPPCState *env)
1876{
1877 /* MMU */
1878 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
2662a059 1882 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1885 0x00700000);
1886 /* Debug interface */
76a66253
JM		 1887 /* XXX : not implemented */
1888 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1889 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1890 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1891 0x00000000);
1892 /* XXX : not implemented */
2662a059
JM		 1893 spr_register(env, SPR_405_DBCR1, "DBCR1",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
76a66253
JM		 1898 spr_register(env, SPR_40x_DBSR, "DBSR",
1899 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1900 &spr_read_generic, &spr_write_clear,
1901 /* Last reset was system reset */
76a66253
JM		 1902 0x00000300);
1903 /* XXX : not implemented */
2662a059 1904 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
2662a059 1908 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
2662a059
JM		 1912 /* XXX : not implemented */
1913 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
2662a059 1916 0x00000000);
76a66253 1917 /* XXX : not implemented */
2662a059 1918 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1921 0x00000000);
1922 /* XXX : not implemented */
2662a059 1923 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
2662a059 1927 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 /* XXX : not implemented */
1932 spr_register(env, SPR_405_IAC3, "IAC3",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 &spr_read_generic, &spr_write_generic,
1935 0x00000000);
1936 /* XXX : not implemented */
1937 spr_register(env, SPR_405_IAC4, "IAC4",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 /* Storage control */
035feb88 1942 /* XXX: TODO: not implemented */
76a66253
JM		 1943 spr_register(env, SPR_405_SLER, "SLER",
1944 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1945 &spr_read_generic, &spr_write_40x_sler,
76a66253 1946 0x00000000);
2662a059
JM		 1947 spr_register(env, SPR_40x_ZPR, "ZPR",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
76a66253
JM		 1951 /* XXX : not implemented */
1952 spr_register(env, SPR_405_SU0R, "SU0R",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956 /* SPRG */
1957 spr_register(env, SPR_USPRG0, "USPRG0",
1958 &spr_read_ureg, SPR_NOACCESS,
1959 &spr_read_ureg, SPR_NOACCESS,
1960 0x00000000);
1961 spr_register(env, SPR_SPRG4, "SPRG4",
1962 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1963 &spr_read_generic, &spr_write_generic,
76a66253 1964 0x00000000);
76a66253
JM		 1965 spr_register(env, SPR_SPRG5, "SPRG5",
1966 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1967 spr_read_generic, &spr_write_generic,
76a66253 1968 0x00000000);
76a66253
JM		 1969 spr_register(env, SPR_SPRG6, "SPRG6",
1970 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1971 spr_read_generic, &spr_write_generic,
76a66253 1972 0x00000000);
76a66253
JM		 1973 spr_register(env, SPR_SPRG7, "SPRG7",
1974 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1975 spr_read_generic, &spr_write_generic,
76a66253 1976 0x00000000);
80d11f44 1977 gen_spr_usprgh(env);
76a66253
JM		 1978}
1979
1980/* SPR shared between PowerPC 401 & 403 implementations */
1981static void gen_spr_401_403 (CPUPPCState *env)
1982{
1983 /* Time base */
1984 spr_register(env, SPR_403_VTBL, "TBL",
1985 &spr_read_tbl, SPR_NOACCESS,
1986 &spr_read_tbl, SPR_NOACCESS,
1987 0x00000000);
1988 spr_register(env, SPR_403_TBL, "TBL",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 SPR_NOACCESS, &spr_write_tbl,
1991 0x00000000);
1992 spr_register(env, SPR_403_VTBU, "TBU",
1993 &spr_read_tbu, SPR_NOACCESS,
1994 &spr_read_tbu, SPR_NOACCESS,
1995 0x00000000);
1996 spr_register(env, SPR_403_TBU, "TBU",
1997 SPR_NOACCESS, SPR_NOACCESS,
1998 SPR_NOACCESS, &spr_write_tbu,
1999 0x00000000);
2000 /* Debug */
5cbdb3a3 2001 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 2002 spr_register(env, SPR_403_CDBCR, "CDBCR",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006}
2007
2662a059
JM		 2008/* SPR specific to PowerPC 401 implementation */
2009static void gen_spr_401 (CPUPPCState *env)
2010{
2011 /* Debug interface */
2012 /* XXX : not implemented */
2013 spr_register(env, SPR_40x_DBCR0, "DBCR",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_40x_dbcr0,
2016 0x00000000);
2017 /* XXX : not implemented */
2018 spr_register(env, SPR_40x_DBSR, "DBSR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_clear,
2021 /* Last reset was system reset */
2022 0x00000300);
2023 /* XXX : not implemented */
2024 spr_register(env, SPR_40x_DAC1, "DAC",
2025 SPR_NOACCESS, SPR_NOACCESS,
2026 &spr_read_generic, &spr_write_generic,
2027 0x00000000);
2028 /* XXX : not implemented */
2029 spr_register(env, SPR_40x_IAC1, "IAC",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 /* Storage control */
035feb88 2034 /* XXX: TODO: not implemented */
2662a059
JM		 2035 spr_register(env, SPR_405_SLER, "SLER",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_40x_sler,
2038 0x00000000);
5cbdb3a3 2039 /* not emulated, as QEMU never does speculative access */
035feb88
JM		 2040 spr_register(env, SPR_40x_SGR, "SGR",
2041 SPR_NOACCESS, SPR_NOACCESS,
2042 &spr_read_generic, &spr_write_generic,
2043 0xFFFFFFFF);
5cbdb3a3 2044 /* not emulated, as QEMU do not emulate caches */
035feb88
JM		 2045 spr_register(env, SPR_40x_DCWR, "DCWR",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_generic,
2048 0x00000000);
2662a059
JM		 2049}
2050
a750fc0b
JM		 2051static void gen_spr_401x2 (CPUPPCState *env)
2052{
2053 gen_spr_401(env);
2054 spr_register(env, SPR_40x_PID, "PID",
2055 SPR_NOACCESS, SPR_NOACCESS,
2056 &spr_read_generic, &spr_write_generic,
2057 0x00000000);
2058 spr_register(env, SPR_40x_ZPR, "ZPR",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062}
2063
76a66253
JM		 2064/* SPR specific to PowerPC 403 implementation */
2065static void gen_spr_403 (CPUPPCState *env)
2066{
2662a059
JM		 2067 /* Debug interface */
2068 /* XXX : not implemented */
2069 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, &spr_write_40x_dbcr0,
2072 0x00000000);
2073 /* XXX : not implemented */
2074 spr_register(env, SPR_40x_DBSR, "DBSR",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_clear,
2077 /* Last reset was system reset */
2078 0x00000300);
2079 /* XXX : not implemented */
2080 spr_register(env, SPR_40x_DAC1, "DAC1",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
578bb252 2084 /* XXX : not implemented */
2662a059
JM		 2085 spr_register(env, SPR_40x_DAC2, "DAC2",
2086 SPR_NOACCESS, SPR_NOACCESS,
2087 &spr_read_generic, &spr_write_generic,
2088 0x00000000);
2089 /* XXX : not implemented */
2090 spr_register(env, SPR_40x_IAC1, "IAC1",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_generic, &spr_write_generic,
2093 0x00000000);
578bb252 2094 /* XXX : not implemented */
2662a059
JM		 2095 spr_register(env, SPR_40x_IAC2, "IAC2",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
a750fc0b
JM		 2099}
2100
2101static void gen_spr_403_real (CPUPPCState *env)
2102{
76a66253
JM		 2103 spr_register(env, SPR_403_PBL1, "PBL1",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_403_pbr, &spr_write_403_pbr,
2106 0x00000000);
2107 spr_register(env, SPR_403_PBU1, "PBU1",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_403_pbr, &spr_write_403_pbr,
2110 0x00000000);
2111 spr_register(env, SPR_403_PBL2, "PBL2",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_403_pbr, &spr_write_403_pbr,
2114 0x00000000);
2115 spr_register(env, SPR_403_PBU2, "PBU2",
2116 SPR_NOACCESS, SPR_NOACCESS,
2117 &spr_read_403_pbr, &spr_write_403_pbr,
2118 0x00000000);
a750fc0b
JM		 2119}
2120
2121static void gen_spr_403_mmu (CPUPPCState *env)
2122{
2123 /* MMU */
2124 spr_register(env, SPR_40x_PID, "PID",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_generic,
2127 0x00000000);
2662a059 2128 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132}
2133
2134/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2135static void gen_spr_compress (CPUPPCState *env)
2136{
578bb252 2137 /* XXX : not implemented */
76a66253
JM		 2138 spr_register(env, SPR_401_SKR, "SKR",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142}
a750fc0b
JM		 2143
2144#if defined (TARGET_PPC64)
a750fc0b
JM		 2145/* SPR specific to PowerPC 620 */
2146static void gen_spr_620 (CPUPPCState *env)
2147{
082c6681
JM		 2148 /* Processor identification */
2149 spr_register(env, SPR_PIR, "PIR",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, &spr_write_pir,
2152 0x00000000);
2153 spr_register(env, SPR_ASR, "ASR",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_asr, &spr_write_asr,
2156 0x00000000);
2157 /* Breakpoints */
2158 /* XXX : not implemented */
2159 spr_register(env, SPR_IABR, "IABR",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_DABR, "DABR",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_SIAR, "SIAR",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, SPR_NOACCESS,
2172 0x00000000);
2173 /* XXX : not implemented */
2174 spr_register(env, SPR_SDA, "SDA",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 &spr_read_generic, SPR_NOACCESS,
2177 0x00000000);
2178 /* XXX : not implemented */
2179 spr_register(env, SPR_620_PMC1R, "PMC1",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, SPR_NOACCESS,
2182 0x00000000);
2183 spr_register(env, SPR_620_PMC1W, "PMC1",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 SPR_NOACCESS, &spr_write_generic,
2186 0x00000000);
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_620_PMC2R, "PMC2",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, SPR_NOACCESS,
2191 0x00000000);
2192 spr_register(env, SPR_620_PMC2W, "PMC2",
2193 SPR_NOACCESS, SPR_NOACCESS,
2194 SPR_NOACCESS, &spr_write_generic,
2195 0x00000000);
2196 /* XXX : not implemented */
2197 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2198 SPR_NOACCESS, SPR_NOACCESS,
2199 &spr_read_generic, SPR_NOACCESS,
2200 0x00000000);
2201 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 SPR_NOACCESS, &spr_write_generic,
2204 0x00000000);
2205 /* External access control */
2206 /* XXX : not implemented */
2207 spr_register(env, SPR_EAR, "EAR",
2208 SPR_NOACCESS, SPR_NOACCESS,
2209 &spr_read_generic, &spr_write_generic,
2210 0x00000000);
2211#if 0 // XXX: check this
578bb252 2212 /* XXX : not implemented */
a750fc0b
JM		 2213 spr_register(env, SPR_620_PMR0, "PMR0",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
578bb252 2217 /* XXX : not implemented */
a750fc0b
JM		 2218 spr_register(env, SPR_620_PMR1, "PMR1",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
578bb252 2222 /* XXX : not implemented */
a750fc0b
JM		 2223 spr_register(env, SPR_620_PMR2, "PMR2",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
578bb252 2227 /* XXX : not implemented */
a750fc0b
JM		 2228 spr_register(env, SPR_620_PMR3, "PMR3",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
578bb252 2232 /* XXX : not implemented */
a750fc0b
JM		 2233 spr_register(env, SPR_620_PMR4, "PMR4",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
578bb252 2237 /* XXX : not implemented */
a750fc0b
JM		 2238 spr_register(env, SPR_620_PMR5, "PMR5",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
578bb252 2242 /* XXX : not implemented */
a750fc0b
JM		 2243 spr_register(env, SPR_620_PMR6, "PMR6",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
578bb252 2247 /* XXX : not implemented */
a750fc0b
JM		 2248 spr_register(env, SPR_620_PMR7, "PMR7",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
578bb252 2252 /* XXX : not implemented */
a750fc0b
JM		 2253 spr_register(env, SPR_620_PMR8, "PMR8",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
578bb252 2257 /* XXX : not implemented */
a750fc0b
JM		 2258 spr_register(env, SPR_620_PMR9, "PMR9",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
578bb252 2262 /* XXX : not implemented */
a750fc0b
JM		 2263 spr_register(env, SPR_620_PMRA, "PMR10",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
578bb252 2267 /* XXX : not implemented */
a750fc0b
JM		 2268 spr_register(env, SPR_620_PMRB, "PMR11",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
578bb252 2272 /* XXX : not implemented */
a750fc0b
JM		 2273 spr_register(env, SPR_620_PMRC, "PMR12",
2274 SPR_NOACCESS, SPR_NOACCESS,
2275 &spr_read_generic, &spr_write_generic,
2276 0x00000000);
578bb252 2277 /* XXX : not implemented */
a750fc0b
JM		 2278 spr_register(env, SPR_620_PMRD, "PMR13",
2279 SPR_NOACCESS, SPR_NOACCESS,
2280 &spr_read_generic, &spr_write_generic,
2281 0x00000000);
578bb252 2282 /* XXX : not implemented */
a750fc0b
JM		 2283 spr_register(env, SPR_620_PMRE, "PMR14",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
578bb252 2287 /* XXX : not implemented */
a750fc0b
JM		 2288 spr_register(env, SPR_620_PMRF, "PMR15",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
082c6681 2292#endif
578bb252 2293 /* XXX : not implemented */
082c6681 2294 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
578bb252 2298 /* XXX : not implemented */
082c6681
JM		 2299 spr_register(env, SPR_620_L2CR, "L2CR",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308}
a750fc0b 2309#endif /* defined (TARGET_PPC64) */
76a66253 2310
80d11f44 2311static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2312{
80d11f44
JM		 2313 /* Exception processing */
2314 spr_register(env, SPR_DSISR, "DSISR",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 spr_register(env, SPR_DAR, "DAR",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* Timer */
2323 spr_register(env, SPR_DECR, "DECR",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_decr, &spr_write_decr,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_MPC_EIE, "EIE",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_MPC_EID, "EID",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_NRI, "NRI",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_CMPA, "CMPA",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_CMPB, "CMPB",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_CMPC, "CMPC",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_CMPD, "CMPD",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_ECR, "ECR",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_DER, "DER",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_CMPE, "CMPE",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_CMPF, "CMPF",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_CMPG, "CMPG",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_CMPH, "CMPH",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402 /* XXX : not implemented */
2403 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2404 SPR_NOACCESS, SPR_NOACCESS,
2405 &spr_read_generic, &spr_write_generic,
2406 0x00000000);
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_MPC_BAR, "BAR",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_MPC_DPDR, "DPDR",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_MPC_IMMR, "IMMR",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427}
2428
2429static void gen_spr_5xx (CPUPPCState *env)
2430{
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511 /* XXX : not implemented */
2512 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2513 SPR_NOACCESS, SPR_NOACCESS,
2514 &spr_read_generic, &spr_write_generic,
2515 0x00000000);
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536}
2537
2538static void gen_spr_8xx (CPUPPCState *env)
2539{
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640 /* XXX : not implemented */
2641 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645 /* XXX : not implemented */
2646 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 /* XXX : not implemented */
2651 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
2655 /* XXX : not implemented */
2656 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2657 SPR_NOACCESS, SPR_NOACCESS,
2658 &spr_read_generic, &spr_write_generic,
2659 0x00000000);
2660 /* XXX : not implemented */
2661 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
2665}
2666
2667// XXX: TODO
2668/*
2669 * AMR => SPR 29 (Power 2.04)
2670 * CTRL => SPR 136 (Power 2.04)
2671 * CTRL => SPR 152 (Power 2.04)
2672 * SCOMC => SPR 276 (64 bits ?)
2673 * SCOMD => SPR 277 (64 bits ?)
2674 * TBU40 => SPR 286 (Power 2.04 hypv)
2675 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2676 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2677 * HDSISR => SPR 306 (Power 2.04 hypv)
2678 * HDAR => SPR 307 (Power 2.04 hypv)
2679 * PURR => SPR 309 (Power 2.04 hypv)
2680 * HDEC => SPR 310 (Power 2.04 hypv)
2681 * HIOR => SPR 311 (hypv)
2682 * RMOR => SPR 312 (970)
2683 * HRMOR => SPR 313 (Power 2.04 hypv)
2684 * HSRR0 => SPR 314 (Power 2.04 hypv)
2685 * HSRR1 => SPR 315 (Power 2.04 hypv)
2686 * LPCR => SPR 316 (970)
2687 * LPIDR => SPR 317 (970)
80d11f44
JM		 2688 * EPR => SPR 702 (Power 2.04 emb)
2689 * perf => 768-783 (Power 2.04)
2690 * perf => 784-799 (Power 2.04)
2691 * PPR => SPR 896 (Power 2.04)
2692 * EPLC => SPR 947 (Power 2.04 emb)
2693 * EPSC => SPR 948 (Power 2.04 emb)
2694 * DABRX => 1015 (Power 2.04 hypv)
2695 * FPECR => SPR 1022 (?)
2696 * ... and more (thermal management, performance counters, ...)
2697 */
2698
2699/*****************************************************************************/
2700/* Exception vectors models */
2701static void init_excp_4xx_real (CPUPPCState *env)
2702{
2703#if !defined(CONFIG_USER_ONLY)
2704 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2705 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2706 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2707 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2708 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2709 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2710 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2711 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2712 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2713 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2714 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2715 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2716 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2717 /* Hardware reset vector */
2718 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2719#endif
2720}
2721
80d11f44
JM		 2722static void init_excp_4xx_softmmu (CPUPPCState *env)
2723{
2724#if !defined(CONFIG_USER_ONLY)
2725 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2726 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2727 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2728 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2729 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2730 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2731 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2732 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2733 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2734 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2735 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2736 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2737 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2738 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2739 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2740 env->ivor_mask = 0x0000FFF0UL;
2741 env->ivpr_mask = 0xFFFF0000UL;
2742 /* Hardware reset vector */
2743 env->hreset_vector = 0xFFFFFFFCUL;
2744#endif
2745}
2746
2747static void init_excp_MPC5xx (CPUPPCState *env)
2748{
2749#if !defined(CONFIG_USER_ONLY)
2750 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2751 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2752 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2753 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2754 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2755 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2756 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2757 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2758 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2759 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2760 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2761 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2762 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2763 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2764 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2765 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2766 env->ivor_mask = 0x0000FFF0UL;
2767 env->ivpr_mask = 0xFFFF0000UL;
2768 /* Hardware reset vector */
2769 env->hreset_vector = 0xFFFFFFFCUL;
2770#endif
2771}
2772
2773static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2774{
2775#if !defined(CONFIG_USER_ONLY)
2776 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2777 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2778 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2779 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2780 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2781 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2782 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2783 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2784 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2785 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2786 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2787 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2788 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2789 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2790 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2791 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2792 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2793 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2794 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2795 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2796 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2797 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2798 env->ivor_mask = 0x0000FFF0UL;
2799 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2800 /* Hardware reset vector */
80d11f44 2801 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2802#endif
2803}
2804
80d11f44 2805static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2806{
2807#if !defined(CONFIG_USER_ONLY)
2808 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2809 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2810 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2811 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2812 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2813 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2814 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2815 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2816 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2817 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2818 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2819 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2820 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2821 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2822 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2823 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2824 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2825 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2826 /* Hardware reset vector */
2827 env->hreset_vector = 0xFFFFFFFCUL;
2828#endif
2829}
2830
e9cd84b9 2831static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
80d11f44
JM		 2832{
2833#if !defined(CONFIG_USER_ONLY)
2834 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2835 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2836 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
fc1c67bc 2854 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2855 env->ivor_mask = 0x0000FFF7UL;
e9cd84b9 2856 env->ivpr_mask = ivpr_mask;
80d11f44
JM		 2857 /* Hardware reset vector */
2858 env->hreset_vector = 0xFFFFFFFCUL;
2859#endif
2860}
2861
2862static void init_excp_BookE (CPUPPCState *env)
2863{
2864#if !defined(CONFIG_USER_ONLY)
2865 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2866 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2872 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2875 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
fc1c67bc 2881 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2882 env->ivor_mask = 0x0000FFE0UL;
2883 env->ivpr_mask = 0xFFFF0000UL;
2884 /* Hardware reset vector */
2885 env->hreset_vector = 0xFFFFFFFCUL;
2886#endif
2887}
2888
2889static void init_excp_601 (CPUPPCState *env)
2890{
2891#if !defined(CONFIG_USER_ONLY)
2892 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2893 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2894 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2895 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2896 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2897 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2898 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2899 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2900 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2901 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2902 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2903 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
fc1c67bc 2904 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2905 /* Hardware reset vector */
80d11f44 2906 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2907#endif
2908}
2909
80d11f44 2910static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2911{
2912#if !defined(CONFIG_USER_ONLY)
082c6681 2913 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2914 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2915 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2916 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2917 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2918 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2919 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2920 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2921 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2922 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2923 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2924 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2925 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2926 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2927 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2928 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2929 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2930 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2931 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
fc1c67bc 2932 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2933 /* Hardware reset vector */
2934 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2935#endif
2936}
2937
80d11f44 2938static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2939{
2940#if !defined(CONFIG_USER_ONLY)
2941 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2942 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2943 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2946 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2947 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2948 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2949 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2950 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2951 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2952 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2953 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2954 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2955 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2956 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2957 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2958 /* Hardware reset vector */
2959 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2960#endif
2961}
2962
2963static void init_excp_604 (CPUPPCState *env)
2964{
2965#if !defined(CONFIG_USER_ONLY)
2966 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2967 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2968 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2969 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2970 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2971 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2972 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2973 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2974 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2975 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2976 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2977 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2978 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2979 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2d3eb7bf 2980 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2981 /* Hardware reset vector */
2d3eb7bf 2982 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2983#endif
2984}
2985
578bb252 2986#if defined(TARGET_PPC64)
e1833e1f
JM		 2987static void init_excp_620 (CPUPPCState *env)
2988{
2989#if !defined(CONFIG_USER_ONLY)
2990 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2991 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2992 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2993 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2994 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2995 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2996 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2997 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2998 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2999 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3000 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 3001 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3002 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3003 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3004 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 3005 /* Hardware reset vector */
faadf50e 3006 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3007#endif
3008}
578bb252 3009#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 3010
3011static void init_excp_7x0 (CPUPPCState *env)
3012{
3013#if !defined(CONFIG_USER_ONLY)
3014 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3015 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3016 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3017 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3018 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3019 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3020 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3021 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3022 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3023 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3024 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3025 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3026 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 3027 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 3028 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3029 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3030 /* Hardware reset vector */
3031 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3032#endif
3033}
3034
bd928eba 3035static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 3036{
3037#if !defined(CONFIG_USER_ONLY)
3038 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3039 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3040 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3041 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3042 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3043 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3044 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3045 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3046 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3049 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3050 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3051 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3052 env->hreset_excp_prefix = 0x00000000UL;
bd928eba
JM		 3053 /* Hardware reset vector */
3054 env->hreset_vector = 0xFFFFFFFCUL;
3055#endif
3056}
3057
3058static void init_excp_750cx (CPUPPCState *env)
3059{
3060#if !defined(CONFIG_USER_ONLY)
3061 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3062 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3063 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3064 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3065 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3066 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3067 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3068 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3069 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3070 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3071 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3072 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3073 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 3074 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3075 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3076 /* Hardware reset vector */
3077 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3078#endif
3079}
3080
7a3a6927
JM		 3081/* XXX: Check if this is correct */
3082static void init_excp_7x5 (CPUPPCState *env)
3083{
3084#if !defined(CONFIG_USER_ONLY)
3085 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3086 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3087 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3088 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3089 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3090 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3091 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3092 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3093 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3094 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3095 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 3096 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 3097 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3098 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3099 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 3100 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3101 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3102 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3103 env->hreset_excp_prefix = 0x00000000UL;
7a3a6927
JM		 3104 /* Hardware reset vector */
3105 env->hreset_vector = 0xFFFFFFFCUL;
3106#endif
3107}
3108
e1833e1f
JM		 3109static void init_excp_7400 (CPUPPCState *env)
3110{
3111#if !defined(CONFIG_USER_ONLY)
3112 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3113 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3114 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3115 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3116 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3117 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3118 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3119 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3120 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3121 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3122 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3123 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3124 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3125 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3126 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3127 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3128 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3129 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3130 /* Hardware reset vector */
3131 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3132#endif
3133}
3134
e1833e1f
JM		 3135static void init_excp_7450 (CPUPPCState *env)
3136{
3137#if !defined(CONFIG_USER_ONLY)
3138 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3139 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3140 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3141 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3142 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3143 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3144 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3145 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3146 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3147 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3148 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3149 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3150 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3151 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3152 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3153 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3154 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3155 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3156 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
fc1c67bc 3157 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3158 /* Hardware reset vector */
3159 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3160#endif
3161}
e1833e1f
JM		 3162
3163#if defined (TARGET_PPC64)
3164static void init_excp_970 (CPUPPCState *env)
3165{
3166#if !defined(CONFIG_USER_ONLY)
3167 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3168 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3169 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3170 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3171 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3172 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3173 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3174 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3175 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3176 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3177 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3178 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3179 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3180 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3181 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3182 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3183 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3184 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3185 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3186 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
fc1c67bc 3187 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3188 /* Hardware reset vector */
3189 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3190#endif
3191}
9d52e907
DG		 3192
3193static void init_excp_POWER7 (CPUPPCState *env)
3194{
3195#if !defined(CONFIG_USER_ONLY)
3196 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3197 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3198 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3199 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3200 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3201 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3202 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3203 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3204 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3205 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3206 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3207 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3208 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3209 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3210 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3211 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3212 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3213 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3214 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3215 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3216 env->hreset_excp_prefix = 0;
3217 /* Hardware reset vector */
3218 env->hreset_vector = 0x0000000000000100ULL;
3219#endif
3220}
e1833e1f
JM		 3221#endif
3222
2f462816
JM		 3223/*****************************************************************************/
3224/* Power management enable checks */
3225static int check_pow_none (CPUPPCState *env)
3226{
3227 return 0;
3228}
3229
3230static int check_pow_nocheck (CPUPPCState *env)
3231{
3232 return 1;
3233}
3234
3235static int check_pow_hid0 (CPUPPCState *env)
3236{
3237 if (env->spr[SPR_HID0] & 0x00E00000)
3238 return 1;
3239
3240 return 0;
3241}
3242
4e777442
JM		 3243static int check_pow_hid0_74xx (CPUPPCState *env)
3244{
3245 if (env->spr[SPR_HID0] & 0x00600000)
3246 return 1;
3247
3248 return 0;
3249}
3250
a750fc0b
JM		 3251/*****************************************************************************/
3252/* PowerPC implementations definitions */
76a66253 3253
a750fc0b 3254/* PowerPC 401 */
082c6681
JM		 3255#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3256 PPC_WRTEE | PPC_DCR | \
3257 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3258 PPC_CACHE_DCBZ | \
a750fc0b 3259 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3260 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3261#define POWERPC_INSNS2_401 (PPC_NONE)
a750fc0b 3262#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3263#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3264#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3265#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3266#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3267#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3268 POWERPC_FLAG_BUS_CLK)
2f462816 3269#define check_pow_401 check_pow_nocheck
76a66253 3270
a750fc0b
JM		 3271static void init_proc_401 (CPUPPCState *env)
3272{
3273 gen_spr_40x(env);
3274 gen_spr_401_403(env);
3275 gen_spr_401(env);
e1833e1f 3276 init_excp_4xx_real(env);
d63001d1
JM		 3277 env->dcache_line_size = 32;
3278 env->icache_line_size = 32;
4e290a0b
JM		 3279 /* Allocate hardware IRQ controller */
3280 ppc40x_irq_init(env);
ddd1055b
FC		 3281
3282 SET_FIT_PERIOD(12, 16, 20, 24);
3283 SET_WDT_PERIOD(16, 20, 24, 28);
a750fc0b 3284}
76a66253 3285
a750fc0b 3286/* PowerPC 401x2 */
082c6681
JM		 3287#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3288 PPC_DCR | PPC_WRTEE | \
3289 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3290 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3291 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3292 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3293 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3294#define POWERPC_INSNS2_401x2 (PPC_NONE)
a750fc0b
JM		 3295#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3296#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3297#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3298#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3299#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3300#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3301 POWERPC_FLAG_BUS_CLK)
2f462816 3302#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3303
3304static void init_proc_401x2 (CPUPPCState *env)
3305{
3306 gen_spr_40x(env);
3307 gen_spr_401_403(env);
3308 gen_spr_401x2(env);
3309 gen_spr_compress(env);
a750fc0b 3310 /* Memory management */
f2e63a42 3311#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3312 env->nb_tlb = 64;
3313 env->nb_ways = 1;
3314 env->id_tlbs = 0;
1c53accc 3315 env->tlb_type = TLB_EMB;
f2e63a42 3316#endif
e1833e1f 3317 init_excp_4xx_softmmu(env);
d63001d1
JM		 3318 env->dcache_line_size = 32;
3319 env->icache_line_size = 32;
4e290a0b
JM		 3320 /* Allocate hardware IRQ controller */
3321 ppc40x_irq_init(env);
ddd1055b
FC		 3322
3323 SET_FIT_PERIOD(12, 16, 20, 24);
3324 SET_WDT_PERIOD(16, 20, 24, 28);
76a66253
JM		 3325}
3326
a750fc0b 3327/* PowerPC 401x3 */
082c6681
JM		 3328#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3329 PPC_DCR | PPC_WRTEE | \
3330 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3331 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3332 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3333 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3334 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3335#define POWERPC_INSNS2_401x3 (PPC_NONE)
a750fc0b
JM		 3336#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3337#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3338#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3339#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3340#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3341#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3342 POWERPC_FLAG_BUS_CLK)
2f462816 3343#define check_pow_401x3 check_pow_nocheck
a750fc0b 3344
578bb252 3345__attribute__ (( unused ))
e1833e1f 3346static void init_proc_401x3 (CPUPPCState *env)
76a66253 3347{
4e290a0b
JM		 3348 gen_spr_40x(env);
3349 gen_spr_401_403(env);
3350 gen_spr_401(env);
3351 gen_spr_401x2(env);
3352 gen_spr_compress(env);
e1833e1f 3353 init_excp_4xx_softmmu(env);
d63001d1
JM		 3354 env->dcache_line_size = 32;
3355 env->icache_line_size = 32;
4e290a0b
JM		 3356 /* Allocate hardware IRQ controller */
3357 ppc40x_irq_init(env);
ddd1055b
FC		 3358
3359 SET_FIT_PERIOD(12, 16, 20, 24);
3360 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082 3361}
a750fc0b
JM		 3362
3363/* IOP480 */
082c6681
JM		 3364#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3365 PPC_DCR | PPC_WRTEE | \
3366 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3367 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3368 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3369 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3370 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3371#define POWERPC_INSNS2_IOP480 (PPC_NONE)
a750fc0b
JM		 3372#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3373#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3374#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3375#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3376#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3377#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3378 POWERPC_FLAG_BUS_CLK)
2f462816 3379#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3380
3381static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3382{
a750fc0b
JM		 3383 gen_spr_40x(env);
3384 gen_spr_401_403(env);
3385 gen_spr_401x2(env);
3386 gen_spr_compress(env);
a750fc0b 3387 /* Memory management */
f2e63a42 3388#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3389 env->nb_tlb = 64;
3390 env->nb_ways = 1;
3391 env->id_tlbs = 0;
1c53accc 3392 env->tlb_type = TLB_EMB;
f2e63a42 3393#endif
e1833e1f 3394 init_excp_4xx_softmmu(env);
d63001d1
JM		 3395 env->dcache_line_size = 32;
3396 env->icache_line_size = 32;
4e290a0b
JM		 3397 /* Allocate hardware IRQ controller */
3398 ppc40x_irq_init(env);
ddd1055b
FC		 3399
3400 SET_FIT_PERIOD(8, 12, 16, 20);
3401 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3402}
3403
a750fc0b 3404/* PowerPC 403 */
082c6681
JM		 3405#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3406 PPC_DCR | PPC_WRTEE | \
3407 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3408 PPC_CACHE_DCBZ | \
a750fc0b 3409 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3410 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3411#define POWERPC_INSNS2_403 (PPC_NONE)
a750fc0b 3412#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3413#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3414#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3415#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3416#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3417#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3418 POWERPC_FLAG_BUS_CLK)
2f462816 3419#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3420
3421static void init_proc_403 (CPUPPCState *env)
3fc6c082 3422{
a750fc0b
JM		 3423 gen_spr_40x(env);
3424 gen_spr_401_403(env);
3425 gen_spr_403(env);
3426 gen_spr_403_real(env);
e1833e1f 3427 init_excp_4xx_real(env);
d63001d1
JM		 3428 env->dcache_line_size = 32;
3429 env->icache_line_size = 32;
4e290a0b
JM		 3430 /* Allocate hardware IRQ controller */
3431 ppc40x_irq_init(env);
ddd1055b
FC		 3432
3433 SET_FIT_PERIOD(8, 12, 16, 20);
3434 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3435}
3436
a750fc0b 3437/* PowerPC 403 GCX */
082c6681
JM		 3438#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3439 PPC_DCR | PPC_WRTEE | \
3440 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3441 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3442 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3443 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3444 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3445#define POWERPC_INSNS2_403GCX (PPC_NONE)
a750fc0b
JM		 3446#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3447#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3448#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3449#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3450#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3451#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3452 POWERPC_FLAG_BUS_CLK)
2f462816 3453#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3454
3455static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3456{
a750fc0b
JM		 3457 gen_spr_40x(env);
3458 gen_spr_401_403(env);
3459 gen_spr_403(env);
3460 gen_spr_403_real(env);
3461 gen_spr_403_mmu(env);
3462 /* Bus access control */
5cbdb3a3 3463 /* not emulated, as QEMU never does speculative access */
a750fc0b
JM		 3464 spr_register(env, SPR_40x_SGR, "SGR",
3465 SPR_NOACCESS, SPR_NOACCESS,
3466 &spr_read_generic, &spr_write_generic,
3467 0xFFFFFFFF);
5cbdb3a3 3468 /* not emulated, as QEMU do not emulate caches */
a750fc0b
JM		 3469 spr_register(env, SPR_40x_DCWR, "DCWR",
3470 SPR_NOACCESS, SPR_NOACCESS,
3471 &spr_read_generic, &spr_write_generic,
3472 0x00000000);
3473 /* Memory management */
f2e63a42 3474#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3475 env->nb_tlb = 64;
3476 env->nb_ways = 1;
3477 env->id_tlbs = 0;
1c53accc 3478 env->tlb_type = TLB_EMB;
f2e63a42 3479#endif
80d11f44
JM		 3480 init_excp_4xx_softmmu(env);
3481 env->dcache_line_size = 32;
3482 env->icache_line_size = 32;
3483 /* Allocate hardware IRQ controller */
3484 ppc40x_irq_init(env);
ddd1055b
FC		 3485
3486 SET_FIT_PERIOD(8, 12, 16, 20);
3487 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3488}
3489
3490/* PowerPC 405 */
082c6681
JM		 3491#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3492 PPC_DCR | PPC_WRTEE | \
3493 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3494 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3495 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3496 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3497 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
a5858d7a 3498#define POWERPC_INSNS2_405 (PPC_NONE)
80d11f44
JM		 3499#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3500#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3501#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3502#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3503#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3504#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3505 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3506#define check_pow_405 check_pow_nocheck
3507
3508static void init_proc_405 (CPUPPCState *env)
3509{
3510 /* Time base */
3511 gen_tbl(env);
3512 gen_spr_40x(env);
3513 gen_spr_405(env);
3514 /* Bus access control */
5cbdb3a3 3515 /* not emulated, as QEMU never does speculative access */
80d11f44
JM		 3516 spr_register(env, SPR_40x_SGR, "SGR",
3517 SPR_NOACCESS, SPR_NOACCESS,
3518 &spr_read_generic, &spr_write_generic,
3519 0xFFFFFFFF);
5cbdb3a3 3520 /* not emulated, as QEMU do not emulate caches */
80d11f44
JM		 3521 spr_register(env, SPR_40x_DCWR, "DCWR",
3522 SPR_NOACCESS, SPR_NOACCESS,
3523 &spr_read_generic, &spr_write_generic,
3524 0x00000000);
3525 /* Memory management */
3526#if !defined(CONFIG_USER_ONLY)
3527 env->nb_tlb = 64;
3528 env->nb_ways = 1;
3529 env->id_tlbs = 0;
1c53accc 3530 env->tlb_type = TLB_EMB;
80d11f44
JM		 3531#endif
3532 init_excp_4xx_softmmu(env);
3533 env->dcache_line_size = 32;
3534 env->icache_line_size = 32;
3535 /* Allocate hardware IRQ controller */
3536 ppc40x_irq_init(env);
ddd1055b
FC		 3537
3538 SET_FIT_PERIOD(8, 12, 16, 20);
3539 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3540}
3541
3542/* PowerPC 440 EP */
082c6681 3543#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
c0a7e81a
AG		 3544 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3545 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3546 PPC_FLOAT_STFIWX | \
082c6681
JM		 3547 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3548 PPC_CACHE | PPC_CACHE_ICBI | \
3549 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3550 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3551 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3552 PPC_440_SPEC)
a5858d7a 3553#define POWERPC_INSNS2_440EP (PPC_NONE)
c0a7e81a 3554#define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
80d11f44
JM		 3555#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3556#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3557#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3558#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3559#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3560 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3561#define check_pow_440EP check_pow_nocheck
3562
80d11f44
JM		 3563static void init_proc_440EP (CPUPPCState *env)
3564{
3565 /* Time base */
3566 gen_tbl(env);
3567 gen_spr_BookE(env, 0x000000000000FFFFULL);
3568 gen_spr_440(env);
3569 gen_spr_usprgh(env);
3570 /* Processor identification */
3571 spr_register(env, SPR_BOOKE_PIR, "PIR",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_pir,
3574 0x00000000);
3575 /* XXX : not implemented */
3576 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 /* XXX : not implemented */
3581 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3582 SPR_NOACCESS, SPR_NOACCESS,
3583 &spr_read_generic, &spr_write_generic,
3584 0x00000000);
3585 /* XXX : not implemented */
3586 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3587 SPR_NOACCESS, SPR_NOACCESS,
3588 &spr_read_generic, &spr_write_generic,
3589 0x00000000);
3590 /* XXX : not implemented */
3591 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3592 SPR_NOACCESS, SPR_NOACCESS,
3593 &spr_read_generic, &spr_write_generic,
3594 0x00000000);
3595 /* XXX : not implemented */
3596 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3597 SPR_NOACCESS, SPR_NOACCESS,
3598 &spr_read_generic, &spr_write_generic,
3599 0x00000000);
3600 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3601 SPR_NOACCESS, SPR_NOACCESS,
3602 &spr_read_generic, &spr_write_generic,
3603 0x00000000);
3604 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3605 SPR_NOACCESS, SPR_NOACCESS,
3606 &spr_read_generic, &spr_write_generic,
3607 0x00000000);
3608 /* XXX : not implemented */
3609 spr_register(env, SPR_440_CCR1, "CCR1",
3610 SPR_NOACCESS, SPR_NOACCESS,
3611 &spr_read_generic, &spr_write_generic,
3612 0x00000000);
3613 /* Memory management */
3614#if !defined(CONFIG_USER_ONLY)
3615 env->nb_tlb = 64;
3616 env->nb_ways = 1;
3617 env->id_tlbs = 0;
1c53accc 3618 env->tlb_type = TLB_EMB;
80d11f44
JM		 3619#endif
3620 init_excp_BookE(env);
3621 env->dcache_line_size = 32;
3622 env->icache_line_size = 32;
c0a7e81a 3623 ppc40x_irq_init(env);
ddd1055b
FC		 3624
3625 SET_FIT_PERIOD(12, 16, 20, 24);
3626 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3627}
3628
3629/* PowerPC 440 GP */
082c6681
JM		 3630#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3631 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3632 PPC_CACHE | PPC_CACHE_ICBI | \
3633 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3634 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
082c6681
JM		 3635 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3636 PPC_440_SPEC)
a5858d7a 3637#define POWERPC_INSNS2_440GP (PPC_NONE)
80d11f44
JM		 3638#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3639#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3640#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3641#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3642#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3643#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3644 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3645#define check_pow_440GP check_pow_nocheck
3646
3647__attribute__ (( unused ))
3648static void init_proc_440GP (CPUPPCState *env)
3649{
3650 /* Time base */
3651 gen_tbl(env);
3652 gen_spr_BookE(env, 0x000000000000FFFFULL);
3653 gen_spr_440(env);
3654 gen_spr_usprgh(env);
3655 /* Processor identification */
3656 spr_register(env, SPR_BOOKE_PIR, "PIR",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_pir,
3659 0x00000000);
3660 /* XXX : not implemented */
3661 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_generic,
3664 0x00000000);
3665 /* XXX : not implemented */
3666 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
3670 /* XXX : not implemented */
3671 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675 /* XXX : not implemented */
3676 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
3680 /* Memory management */
3681#if !defined(CONFIG_USER_ONLY)
3682 env->nb_tlb = 64;
3683 env->nb_ways = 1;
3684 env->id_tlbs = 0;
1c53accc 3685 env->tlb_type = TLB_EMB;
80d11f44
JM		 3686#endif
3687 init_excp_BookE(env);
3688 env->dcache_line_size = 32;
3689 env->icache_line_size = 32;
3690 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3691
3692 SET_FIT_PERIOD(12, 16, 20, 24);
3693 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3694}
3695
3696/* PowerPC 440x4 */
082c6681
JM		 3697#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3698 PPC_DCR | PPC_WRTEE | \
3699 PPC_CACHE | PPC_CACHE_ICBI | \
3700 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3701 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44
JM		 3702 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3703 PPC_440_SPEC)
a5858d7a 3704#define POWERPC_INSNS2_440x4 (PPC_NONE)
80d11f44
JM		 3705#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3706#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3707#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3708#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3709#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3710#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3711 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3712#define check_pow_440x4 check_pow_nocheck
3713
3714__attribute__ (( unused ))
3715static void init_proc_440x4 (CPUPPCState *env)
3716{
3717 /* Time base */
3718 gen_tbl(env);
3719 gen_spr_BookE(env, 0x000000000000FFFFULL);
3720 gen_spr_440(env);
3721 gen_spr_usprgh(env);
3722 /* Processor identification */
3723 spr_register(env, SPR_BOOKE_PIR, "PIR",
3724 SPR_NOACCESS, SPR_NOACCESS,
3725 &spr_read_generic, &spr_write_pir,
3726 0x00000000);
3727 /* XXX : not implemented */
3728 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3729 SPR_NOACCESS, SPR_NOACCESS,
3730 &spr_read_generic, &spr_write_generic,
3731 0x00000000);
3732 /* XXX : not implemented */
3733 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3736 0x00000000);
3737 /* XXX : not implemented */
3738 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3739 SPR_NOACCESS, SPR_NOACCESS,
3740 &spr_read_generic, &spr_write_generic,
3741 0x00000000);
3742 /* XXX : not implemented */
3743 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3744 SPR_NOACCESS, SPR_NOACCESS,
3745 &spr_read_generic, &spr_write_generic,
3746 0x00000000);
3747 /* Memory management */
3748#if !defined(CONFIG_USER_ONLY)
3749 env->nb_tlb = 64;
3750 env->nb_ways = 1;
3751 env->id_tlbs = 0;
1c53accc 3752 env->tlb_type = TLB_EMB;
80d11f44
JM		 3753#endif
3754 init_excp_BookE(env);
d63001d1
JM		 3755 env->dcache_line_size = 32;
3756 env->icache_line_size = 32;
80d11f44 3757 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3758
3759 SET_FIT_PERIOD(12, 16, 20, 24);
3760 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3761}
3762
80d11f44 3763/* PowerPC 440x5 */
082c6681
JM		 3764#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3765 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3766 PPC_CACHE | PPC_CACHE_ICBI | \
3767 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3768 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3769 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3770 PPC_440_SPEC)
a5858d7a 3771#define POWERPC_INSNS2_440x5 (PPC_NONE)
80d11f44
JM		 3772#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3773#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3774#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3775#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3776#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3777#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3778 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3779#define check_pow_440x5 check_pow_nocheck
a750fc0b 3780
80d11f44 3781static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3782{
a750fc0b
JM		 3783 /* Time base */
3784 gen_tbl(env);
80d11f44
JM		 3785 gen_spr_BookE(env, 0x000000000000FFFFULL);
3786 gen_spr_440(env);
3787 gen_spr_usprgh(env);
3788 /* Processor identification */
3789 spr_register(env, SPR_BOOKE_PIR, "PIR",
3790 SPR_NOACCESS, SPR_NOACCESS,
3791 &spr_read_generic, &spr_write_pir,
3792 0x00000000);
3793 /* XXX : not implemented */
3794 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3795 SPR_NOACCESS, SPR_NOACCESS,
3796 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3797 0x00000000);
3798 /* XXX : not implemented */
3799 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3800 SPR_NOACCESS, SPR_NOACCESS,
3801 &spr_read_generic, &spr_write_generic,
3802 0x00000000);
3803 /* XXX : not implemented */
3804 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3805 SPR_NOACCESS, SPR_NOACCESS,
3806 &spr_read_generic, &spr_write_generic,
3807 0x00000000);
3808 /* XXX : not implemented */
3809 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3810 SPR_NOACCESS, SPR_NOACCESS,
3811 &spr_read_generic, &spr_write_generic,
3812 0x00000000);
3813 /* XXX : not implemented */
3814 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3815 SPR_NOACCESS, SPR_NOACCESS,
3816 &spr_read_generic, &spr_write_generic,
3817 0x00000000);
3818 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3819 SPR_NOACCESS, SPR_NOACCESS,
3820 &spr_read_generic, &spr_write_generic,
3821 0x00000000);
3822 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3823 SPR_NOACCESS, SPR_NOACCESS,
3824 &spr_read_generic, &spr_write_generic,
3825 0x00000000);
3826 /* XXX : not implemented */
3827 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_generic,
3830 0x00000000);
3831 /* Memory management */
f2e63a42 3832#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3833 env->nb_tlb = 64;
3834 env->nb_ways = 1;
3835 env->id_tlbs = 0;
1c53accc 3836 env->tlb_type = TLB_EMB;
f2e63a42 3837#endif
80d11f44 3838 init_excp_BookE(env);
d63001d1
JM		 3839 env->dcache_line_size = 32;
3840 env->icache_line_size = 32;
95070372 3841 ppc40x_irq_init(env);
ddd1055b
FC		 3842
3843 SET_FIT_PERIOD(12, 16, 20, 24);
3844 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3845}
3846
80d11f44 3847/* PowerPC 460 (guessed) */
082c6681 3848#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3849 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
f4078236 3850 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
082c6681
JM		 3851 PPC_CACHE | PPC_CACHE_ICBI | \
3852 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3853 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3854 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3855 PPC_440_SPEC)
a5858d7a 3856#define POWERPC_INSNS2_460 (PPC_NONE)
80d11f44
JM		 3857#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3858#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3859#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3860#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3861#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3862#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3863 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3864#define check_pow_460 check_pow_nocheck
a750fc0b 3865
80d11f44
JM		 3866__attribute__ (( unused ))
3867static void init_proc_460 (CPUPPCState *env)
3fc6c082 3868{
a750fc0b
JM		 3869 /* Time base */
3870 gen_tbl(env);
80d11f44 3871 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3872 gen_spr_440(env);
80d11f44
JM		 3873 gen_spr_usprgh(env);
3874 /* Processor identification */
3875 spr_register(env, SPR_BOOKE_PIR, "PIR",
3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_pir,
3878 0x00000000);
3879 /* XXX : not implemented */
3880 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 /* XXX : not implemented */
3885 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3886 SPR_NOACCESS, SPR_NOACCESS,
3887 &spr_read_generic, &spr_write_generic,
3888 0x00000000);
3889 /* XXX : not implemented */
3890 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
578bb252 3899 /* XXX : not implemented */
a750fc0b
JM		 3900 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3905 SPR_NOACCESS, SPR_NOACCESS,
3906 &spr_read_generic, &spr_write_generic,
3907 0x00000000);
3908 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3909 SPR_NOACCESS, SPR_NOACCESS,
3910 &spr_read_generic, &spr_write_generic,
3911 0x00000000);
578bb252 3912 /* XXX : not implemented */
a750fc0b
JM		 3913 spr_register(env, SPR_440_CCR1, "CCR1",
3914 SPR_NOACCESS, SPR_NOACCESS,
3915 &spr_read_generic, &spr_write_generic,
3916 0x00000000);
80d11f44
JM		 3917 /* XXX : not implemented */
3918 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3919 &spr_read_generic, &spr_write_generic,
3920 &spr_read_generic, &spr_write_generic,
3921 0x00000000);
a750fc0b 3922 /* Memory management */
f2e63a42 3923#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3924 env->nb_tlb = 64;
3925 env->nb_ways = 1;
3926 env->id_tlbs = 0;
1c53accc 3927 env->tlb_type = TLB_EMB;
f2e63a42 3928#endif
e1833e1f 3929 init_excp_BookE(env);
d63001d1
JM		 3930 env->dcache_line_size = 32;
3931 env->icache_line_size = 32;
a750fc0b 3932 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3933
3934 SET_FIT_PERIOD(12, 16, 20, 24);
3935 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3936}
3937
80d11f44 3938/* PowerPC 460F (guessed) */
082c6681
JM		 3939#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3940 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3941 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
f4078236 3942 PPC_FLOAT_STFIWX | PPC_MFTB | \
082c6681
JM		 3943 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3944 PPC_WRTEE | PPC_MFAPIDI | \
3945 PPC_CACHE | PPC_CACHE_ICBI | \
3946 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3947 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3948 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3949 PPC_440_SPEC)
a5858d7a 3950#define POWERPC_INSNS2_460F (PPC_NONE)
80d11f44
JM		 3951#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3952#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3953#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3954#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3955#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3956#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3957 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3958#define check_pow_460F check_pow_nocheck
a750fc0b 3959
80d11f44
JM		 3960__attribute__ (( unused ))
3961static void init_proc_460F (CPUPPCState *env)
3fc6c082 3962{
a750fc0b
JM		 3963 /* Time base */
3964 gen_tbl(env);
80d11f44 3965 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3966 gen_spr_440(env);
80d11f44
JM		 3967 gen_spr_usprgh(env);
3968 /* Processor identification */
3969 spr_register(env, SPR_BOOKE_PIR, "PIR",
3970 SPR_NOACCESS, SPR_NOACCESS,
3971 &spr_read_generic, &spr_write_pir,
3972 0x00000000);
3973 /* XXX : not implemented */
3974 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 /* XXX : not implemented */
3979 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3980 SPR_NOACCESS, SPR_NOACCESS,
3981 &spr_read_generic, &spr_write_generic,
3982 0x00000000);
3983 /* XXX : not implemented */
3984 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3985 SPR_NOACCESS, SPR_NOACCESS,
3986 &spr_read_generic, &spr_write_generic,
3987 0x00000000);
3988 /* XXX : not implemented */
3989 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3990 SPR_NOACCESS, SPR_NOACCESS,
3991 &spr_read_generic, &spr_write_generic,
3992 0x00000000);
3993 /* XXX : not implemented */
3994 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3995 SPR_NOACCESS, SPR_NOACCESS,
3996 &spr_read_generic, &spr_write_generic,
3997 0x00000000);
3998 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3999 SPR_NOACCESS, SPR_NOACCESS,
4000 &spr_read_generic, &spr_write_generic,
4001 0x00000000);
4002 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4003 SPR_NOACCESS, SPR_NOACCESS,
4004 &spr_read_generic, &spr_write_generic,
4005 0x00000000);
4006 /* XXX : not implemented */
4007 spr_register(env, SPR_440_CCR1, "CCR1",
4008 SPR_NOACCESS, SPR_NOACCESS,
4009 &spr_read_generic, &spr_write_generic,
4010 0x00000000);
4011 /* XXX : not implemented */
4012 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4013 &spr_read_generic, &spr_write_generic,
4014 &spr_read_generic, &spr_write_generic,
4015 0x00000000);
a750fc0b 4016 /* Memory management */
f2e63a42 4017#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4018 env->nb_tlb = 64;
4019 env->nb_ways = 1;
4020 env->id_tlbs = 0;
1c53accc 4021 env->tlb_type = TLB_EMB;
f2e63a42 4022#endif
e1833e1f 4023 init_excp_BookE(env);
d63001d1
JM		 4024 env->dcache_line_size = 32;
4025 env->icache_line_size = 32;
a750fc0b 4026 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 4027
4028 SET_FIT_PERIOD(12, 16, 20, 24);
4029 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4030}
4031
80d11f44
JM		 4032/* Freescale 5xx cores (aka RCPU) */
4033#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4034 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4035 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4036 PPC_MFTB)
a5858d7a 4037#define POWERPC_INSNS2_MPC5xx (PPC_NONE)
80d11f44
JM		 4038#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4039#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4040#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4041#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4042#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 4043#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4044 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4045#define check_pow_MPC5xx check_pow_none
4046
4047__attribute__ (( unused ))
4048static void init_proc_MPC5xx (CPUPPCState *env)
4049{
4050 /* Time base */
4051 gen_tbl(env);
4052 gen_spr_5xx_8xx(env);
4053 gen_spr_5xx(env);
4054 init_excp_MPC5xx(env);
4055 env->dcache_line_size = 32;
4056 env->icache_line_size = 32;
4057 /* XXX: TODO: allocate internal IRQ controller */
4058}
4059
4060/* Freescale 8xx cores (aka PowerQUICC) */
4061#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4062 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4063 PPC_CACHE_ICBI | PPC_MFTB)
a5858d7a 4064#define POWERPC_INSNS2_MPC8xx (PPC_NONE)
80d11f44
JM		 4065#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4066#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4067#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4068#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4069#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 4070#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4071 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4072#define check_pow_MPC8xx check_pow_none
4073
4074__attribute__ (( unused ))
4075static void init_proc_MPC8xx (CPUPPCState *env)
4076{
4077 /* Time base */
4078 gen_tbl(env);
4079 gen_spr_5xx_8xx(env);
4080 gen_spr_8xx(env);
4081 init_excp_MPC8xx(env);
4082 env->dcache_line_size = 32;
4083 env->icache_line_size = 32;
4084 /* XXX: TODO: allocate internal IRQ controller */
4085}
4086
4087/* Freescale 82xx cores (aka PowerQUICC-II) */
4088/* PowerPC G2 */
082c6681
JM		 4089#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4090 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4091 PPC_FLOAT_STFIWX | \
4092 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4093 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4094 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4095 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4096#define POWERPC_INSNS2_G2 (PPC_NONE)
80d11f44
JM		 4097#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4098#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4099//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4100#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4101#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4102#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4103 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4104#define check_pow_G2 check_pow_hid0
a750fc0b 4105
80d11f44 4106static void init_proc_G2 (CPUPPCState *env)
3fc6c082 4107{
80d11f44
JM		 4108 gen_spr_ne_601(env);
4109 gen_spr_G2_755(env);
4110 gen_spr_G2(env);
a750fc0b
JM		 4111 /* Time base */
4112 gen_tbl(env);
bd928eba
JM		 4113 /* External access control */
4114 /* XXX : not implemented */
4115 spr_register(env, SPR_EAR, "EAR",
4116 SPR_NOACCESS, SPR_NOACCESS,
4117 &spr_read_generic, &spr_write_generic,
4118 0x00000000);
80d11f44
JM		 4119 /* Hardware implementation register */
4120 /* XXX : not implemented */
4121 spr_register(env, SPR_HID0, "HID0",
4122 SPR_NOACCESS, SPR_NOACCESS,
4123 &spr_read_generic, &spr_write_generic,
4124 0x00000000);
4125 /* XXX : not implemented */
4126 spr_register(env, SPR_HID1, "HID1",
4127 SPR_NOACCESS, SPR_NOACCESS,
4128 &spr_read_generic, &spr_write_generic,
4129 0x00000000);
4130 /* XXX : not implemented */
4131 spr_register(env, SPR_HID2, "HID2",
4132 SPR_NOACCESS, SPR_NOACCESS,
4133 &spr_read_generic, &spr_write_generic,
4134 0x00000000);
a750fc0b 4135 /* Memory management */
80d11f44
JM		 4136 gen_low_BATs(env);
4137 gen_high_BATs(env);
4138 gen_6xx_7xx_soft_tlb(env, 64, 2);
4139 init_excp_G2(env);
d63001d1
JM		 4140 env->dcache_line_size = 32;
4141 env->icache_line_size = 32;
80d11f44
JM		 4142 /* Allocate hardware IRQ controller */
4143 ppc6xx_irq_init(env);
3fc6c082 4144}
a750fc0b 4145
80d11f44 4146/* PowerPC G2LE */
082c6681
JM		 4147#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4148 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4149 PPC_FLOAT_STFIWX | \
4150 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4151 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4152 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4153 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4154#define POWERPC_INSNS2_G2LE (PPC_NONE)
80d11f44
JM		 4155#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4156#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4157#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4158#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4159#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4160#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4161 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4162#define check_pow_G2LE check_pow_hid0
a750fc0b 4163
80d11f44 4164static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4165{
80d11f44
JM		 4166 gen_spr_ne_601(env);
4167 gen_spr_G2_755(env);
4168 gen_spr_G2(env);
a750fc0b
JM		 4169 /* Time base */
4170 gen_tbl(env);
bd928eba
JM		 4171 /* External access control */
4172 /* XXX : not implemented */
4173 spr_register(env, SPR_EAR, "EAR",
4174 SPR_NOACCESS, SPR_NOACCESS,
4175 &spr_read_generic, &spr_write_generic,
4176 0x00000000);
80d11f44 4177 /* Hardware implementation register */
578bb252 4178 /* XXX : not implemented */
80d11f44 4179 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4180 SPR_NOACCESS, SPR_NOACCESS,
4181 &spr_read_generic, &spr_write_generic,
4182 0x00000000);
80d11f44
JM		 4183 /* XXX : not implemented */
4184 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4185 SPR_NOACCESS, SPR_NOACCESS,
4186 &spr_read_generic, &spr_write_generic,
4187 0x00000000);
578bb252 4188 /* XXX : not implemented */
80d11f44 4189 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4190 SPR_NOACCESS, SPR_NOACCESS,
4191 &spr_read_generic, &spr_write_generic,
4192 0x00000000);
4193 /* Memory management */
80d11f44
JM		 4194 gen_low_BATs(env);
4195 gen_high_BATs(env);
4196 gen_6xx_7xx_soft_tlb(env, 64, 2);
4197 init_excp_G2(env);
d63001d1
JM		 4198 env->dcache_line_size = 32;
4199 env->icache_line_size = 32;
80d11f44
JM		 4200 /* Allocate hardware IRQ controller */
4201 ppc6xx_irq_init(env);
3fc6c082
FB		 4202}
4203
80d11f44
JM		 4204/* e200 core */
4205/* XXX: unimplemented instructions:
4206 * dcblc
4207 * dcbtlst
4208 * dcbtstls
4209 * icblc
4210 * icbtls
4211 * tlbivax
4212 * all SPE multiply-accumulate instructions
4213 */
082c6681 4214#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
40569b7e 4215 PPC_SPE | PPC_SPE_SINGLE | \
082c6681
JM		 4216 PPC_WRTEE | PPC_RFDI | \
4217 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4218 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4219 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4220 PPC_BOOKE)
a5858d7a 4221#define POWERPC_INSNS2_e200 (PPC_NONE)
80d11f44 4222#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
01662f3e 4223#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
80d11f44
JM		 4224#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4225#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4226#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4227#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4228 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4229 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4230#define check_pow_e200 check_pow_hid0
4231
578bb252 4232__attribute__ (( unused ))
80d11f44 4233static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4234{
e1833e1f
JM		 4235 /* Time base */
4236 gen_tbl(env);
80d11f44 4237 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4238 /* XXX : not implemented */
80d11f44 4239 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4240 &spr_read_spefscr, &spr_write_spefscr,
4241 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4242 0x00000000);
80d11f44 4243 /* Memory management */
01662f3e 4244 gen_spr_BookE206(env, 0x0000005D, NULL);
80d11f44
JM		 4245 /* XXX : not implemented */
4246 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
80d11f44
JM		 4250 /* XXX : not implemented */
4251 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4252 SPR_NOACCESS, SPR_NOACCESS,
4253 &spr_read_generic, &spr_write_generic,
4254 0x00000000);
578bb252 4255 /* XXX : not implemented */
80d11f44 4256 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4257 SPR_NOACCESS, SPR_NOACCESS,
4258 &spr_read_generic, &spr_write_generic,
4259 0x00000000);
578bb252 4260 /* XXX : not implemented */
80d11f44
JM		 4261 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4262 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4263 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4264 0x00000000);
4265 /* XXX : not implemented */
4266 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4267 SPR_NOACCESS, SPR_NOACCESS,
4268 &spr_read_generic, &spr_write_generic,
4269 0x00000000);
4270 /* XXX : not implemented */
4271 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4272 SPR_NOACCESS, SPR_NOACCESS,
4273 &spr_read_generic, &spr_write_generic,
4274 0x00000000);
4275 /* XXX : not implemented */
4276 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4277 SPR_NOACCESS, SPR_NOACCESS,
4278 &spr_read_generic, &spr_write_generic,
4279 0x00000000);
4280 /* XXX : not implemented */
4281 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4282 SPR_NOACCESS, SPR_NOACCESS,
4283 &spr_read_generic, &spr_write_generic,
4284 0x00000000);
4285 /* XXX : not implemented */
4286 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4287 SPR_NOACCESS, SPR_NOACCESS,
4288 &spr_read_generic, &spr_write_generic,
4289 0x00000000);
4290 /* XXX : not implemented */
4291 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4292 SPR_NOACCESS, SPR_NOACCESS,
4293 &spr_read_generic, &spr_write_generic,
4294 0x00000000);
4295 /* XXX : not implemented */
4296 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4297 SPR_NOACCESS, SPR_NOACCESS,
4298 &spr_read_generic, &spr_write_generic,
4299 0x00000000);
4300 /* XXX : not implemented */
4301 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4302 SPR_NOACCESS, SPR_NOACCESS,
4303 &spr_read_generic, &spr_write_generic,
4304 0x00000000);
4305 /* XXX : not implemented */
4306 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4307 SPR_NOACCESS, SPR_NOACCESS,
4308 &spr_read_generic, &spr_write_generic,
4309 0x00000000);
4310 /* XXX : not implemented */
4311 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4312 SPR_NOACCESS, SPR_NOACCESS,
4313 &spr_read_generic, &spr_write_generic,
4314 0x00000000);
01662f3e
AG		 4315 /* XXX : not implemented */
4316 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4317 SPR_NOACCESS, SPR_NOACCESS,
4318 &spr_read_generic, &spr_write_generic,
4319 0x00000000); /* TOFIX */
80d11f44
JM		 4320 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4321 SPR_NOACCESS, SPR_NOACCESS,
4322 &spr_read_generic, &spr_write_generic,
4323 0x00000000);
4324 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4325 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
f2e63a42 4328#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4329 env->nb_tlb = 64;
4330 env->nb_ways = 1;
4331 env->id_tlbs = 0;
1c53accc 4332 env->tlb_type = TLB_EMB;
f2e63a42 4333#endif
e9cd84b9 4334 init_excp_e200(env, 0xFFFF0000UL);
d63001d1
JM		 4335 env->dcache_line_size = 32;
4336 env->icache_line_size = 32;
e1833e1f 4337 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4338}
a750fc0b 4339
80d11f44 4340/* e300 core */
082c6681
JM		 4341#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4342 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4343 PPC_FLOAT_STFIWX | \
4344 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4345 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4346 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4347 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4348#define POWERPC_INSNS2_e300 (PPC_NONE)
80d11f44
JM		 4349#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4350#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4351#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4352#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4353#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4354#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4355 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4356#define check_pow_e300 check_pow_hid0
a750fc0b 4357
578bb252 4358__attribute__ (( unused ))
80d11f44 4359static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4360{
80d11f44
JM		 4361 gen_spr_ne_601(env);
4362 gen_spr_603(env);
a750fc0b
JM		 4363 /* Time base */
4364 gen_tbl(env);
80d11f44
JM		 4365 /* hardware implementation registers */
4366 /* XXX : not implemented */
4367 spr_register(env, SPR_HID0, "HID0",
4368 SPR_NOACCESS, SPR_NOACCESS,
4369 &spr_read_generic, &spr_write_generic,
4370 0x00000000);
4371 /* XXX : not implemented */
4372 spr_register(env, SPR_HID1, "HID1",
4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
8daf1781
TM		 4376 /* XXX : not implemented */
4377 spr_register(env, SPR_HID2, "HID2",
4378 SPR_NOACCESS, SPR_NOACCESS,
4379 &spr_read_generic, &spr_write_generic,
4380 0x00000000);
80d11f44
JM		 4381 /* Memory management */
4382 gen_low_BATs(env);
8daf1781 4383 gen_high_BATs(env);
80d11f44
JM		 4384 gen_6xx_7xx_soft_tlb(env, 64, 2);
4385 init_excp_603(env);
4386 env->dcache_line_size = 32;
4387 env->icache_line_size = 32;
4388 /* Allocate hardware IRQ controller */
4389 ppc6xx_irq_init(env);
4390}
4391
bd5ea513
AJ		 4392/* e500v1 core */
4393#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4394 PPC_SPE | PPC_SPE_SINGLE | \
4395 PPC_WRTEE | PPC_RFDI | \
4396 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4397 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
53319166 4398 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
01662f3e 4399#define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
bd5ea513 4400#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
01662f3e 4401#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4402#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4403#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4404#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4405#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4406 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4407 POWERPC_FLAG_BUS_CLK)
4408#define check_pow_e500v1 check_pow_hid0
01662f3e 4409#define init_proc_e500v1 init_proc_e500v1
bd5ea513
AJ		 4410
4411/* e500v2 core */
4412#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4413 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4414 PPC_WRTEE | PPC_RFDI | \
4415 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4416 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
53319166 4417 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
01662f3e 4418#define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
bd5ea513 4419#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
01662f3e 4420#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4421#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4422#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4423#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4424#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4425 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4426 POWERPC_FLAG_BUS_CLK)
4427#define check_pow_e500v2 check_pow_hid0
01662f3e 4428#define init_proc_e500v2 init_proc_e500v2
80d11f44 4429
f7aa5583
VS		 4430/* e500mc core */
4431#define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4432 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4433 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4434 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4435 PPC_FLOAT | PPC_FLOAT_FRES | \
4436 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4437 PPC_FLOAT_STFIWX | PPC_WAIT | \
53319166 4438 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
8917f4dc 4439#define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
f7aa5583
VS		 4440#define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4441#define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4442#define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4443#define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4444/* Fixme: figure out the correct flag for e500mc */
4445#define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4446#define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4447 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4448#define check_pow_e500mc check_pow_none
4449#define init_proc_e500mc init_proc_e500mc
4450
b81ccf8a
AG		 4451/* e5500 core */
4452#define POWERPC_INSNS_e5500 (PPC_INSNS_BASE | PPC_ISEL | \
4453 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4454 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4455 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4456 PPC_FLOAT | PPC_FLOAT_FRES | \
4457 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4458 PPC_FLOAT_STFIWX | PPC_WAIT | \
4459 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | \
4460 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD)
4461#define POWERPC_INSNS2_e5500 (PPC2_BOOKE206 | PPC2_PRCNTL)
4462#define POWERPC_MSRM_e5500 (0x000000009402FB36ULL)
4463#define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
4464#define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
4465#define POWERPC_INPUT_e5500 (PPC_FLAGS_INPUT_BookE)
4466/* Fixme: figure out the correct flag for e5500 */
4467#define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
4468#define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4469 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4470#define check_pow_e5500 check_pow_none
4471#define init_proc_e5500 init_proc_e5500
4472
4473#if !defined(CONFIG_USER_ONLY)
4474static void spr_write_mas73(void *opaque, int sprn, int gprn)
4475{
4476 TCGv val = tcg_temp_new();
4477 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4478 gen_store_spr(SPR_BOOKE_MAS3, val);
cfee0218 4479 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
b81ccf8a
AG		 4480 gen_store_spr(SPR_BOOKE_MAS7, val);
4481 tcg_temp_free(val);
4482}
4483
4484static void spr_read_mas73(void *opaque, int gprn, int sprn)
4485{
4486 TCGv mas7 = tcg_temp_new();
4487 TCGv mas3 = tcg_temp_new();
4488 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4489 tcg_gen_shli_tl(mas7, mas7, 32);
4490 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4491 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4492 tcg_temp_free(mas3);
4493 tcg_temp_free(mas7);
4494}
4495
b81ccf8a
AG		 4496#endif
4497
f7aa5583
VS		 4498enum fsl_e500_version {
4499 fsl_e500v1,
4500 fsl_e500v2,
4501 fsl_e500mc,
b81ccf8a 4502 fsl_e5500,
f7aa5583
VS		 4503};
4504
01662f3e 4505static void init_proc_e500 (CPUPPCState *env, int version)
80d11f44 4506{
01662f3e 4507 uint32_t tlbncfg[2];
b81ccf8a 4508 uint64_t ivor_mask;
e9cd84b9 4509 uint64_t ivpr_mask = 0xFFFF0000ULL;
a496e8ee
AG		 4510 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4511 | 0x0020; /* 32 kb */
01662f3e
AG		 4512#if !defined(CONFIG_USER_ONLY)
4513 int i;
4514#endif
4515
80d11f44
JM		 4516 /* Time base */
4517 gen_tbl(env);
01662f3e
AG		 4518 /*
4519 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4520 * complain when accessing them.
4521 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4522 */
b81ccf8a
AG		 4523 switch (version) {
4524 case fsl_e500v1:
4525 case fsl_e500v2:
4526 default:
4527 ivor_mask = 0x0000000F0000FFFFULL;
4528 break;
4529 case fsl_e500mc:
4530 case fsl_e5500:
4531 ivor_mask = 0x000003FE0000FFFFULL;
4532 break;
2c9732db
AG		 4533 }
4534 gen_spr_BookE(env, ivor_mask);
80d11f44
JM		 4535 /* Processor identification */
4536 spr_register(env, SPR_BOOKE_PIR, "PIR",
4537 SPR_NOACCESS, SPR_NOACCESS,
4538 &spr_read_generic, &spr_write_pir,
4539 0x00000000);
4540 /* XXX : not implemented */
4541 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4542 &spr_read_spefscr, &spr_write_spefscr,
4543 &spr_read_spefscr, &spr_write_spefscr,
80d11f44 4544 0x00000000);
892c587f 4545#if !defined(CONFIG_USER_ONLY)
80d11f44 4546 /* Memory management */
80d11f44 4547 env->nb_pids = 3;
01662f3e
AG		 4548 env->nb_ways = 2;
4549 env->id_tlbs = 0;
4550 switch (version) {
f7aa5583 4551 case fsl_e500v1:
01662f3e
AG		 4552 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4553 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4554 break;
f7aa5583 4555 case fsl_e500v2:
01662f3e
AG		 4556 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4557 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
f7aa5583
VS		 4558 break;
4559 case fsl_e500mc:
b81ccf8a 4560 case fsl_e5500:
f7aa5583
VS		 4561 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4562 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
892c587f
AG		 4563 break;
4564 default:
4565 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4566 }
4567#endif
4568 /* Cache sizes */
4569 switch (version) {
4570 case fsl_e500v1:
4571 case fsl_e500v2:
4572 env->dcache_line_size = 32;
4573 env->icache_line_size = 32;
4574 break;
4575 case fsl_e500mc:
b81ccf8a 4576 case fsl_e5500:
f7aa5583
VS		 4577 env->dcache_line_size = 64;
4578 env->icache_line_size = 64;
a496e8ee 4579 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
01662f3e
AG		 4580 break;
4581 default:
4582 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4583 }
01662f3e 4584 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
80d11f44
JM		 4585 /* XXX : not implemented */
4586 spr_register(env, SPR_HID0, "HID0",
4587 SPR_NOACCESS, SPR_NOACCESS,
4588 &spr_read_generic, &spr_write_generic,
4589 0x00000000);
4590 /* XXX : not implemented */
4591 spr_register(env, SPR_HID1, "HID1",
4592 SPR_NOACCESS, SPR_NOACCESS,
4593 &spr_read_generic, &spr_write_generic,
4594 0x00000000);
4595 /* XXX : not implemented */
4596 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_generic,
4599 0x00000000);
4600 /* XXX : not implemented */
4601 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4602 SPR_NOACCESS, SPR_NOACCESS,
4603 &spr_read_generic, &spr_write_generic,
4604 0x00000000);
4605 /* XXX : not implemented */
4606 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4607 SPR_NOACCESS, SPR_NOACCESS,
4608 &spr_read_generic, &spr_write_generic,
4609 0x00000000);
578bb252 4610 /* XXX : not implemented */
a750fc0b
JM		 4611 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4612 SPR_NOACCESS, SPR_NOACCESS,
4613 &spr_read_generic, &spr_write_generic,
4614 0x00000000);
80d11f44
JM		 4615 /* XXX : not implemented */
4616 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4617 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_generic,
4619 0x00000000);
80d11f44
JM		 4620 /* XXX : not implemented */
4621 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000);
578bb252 4625 /* XXX : not implemented */
80d11f44 4626 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4627 SPR_NOACCESS, SPR_NOACCESS,
4628 &spr_read_generic, &spr_write_generic,
a496e8ee 4629 l1cfg0);
578bb252 4630 /* XXX : not implemented */
80d11f44
JM		 4631 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4632 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 4633 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44
JM		 4634 0x00000000);
4635 /* XXX : not implemented */
4636 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4637 SPR_NOACCESS, SPR_NOACCESS,
4638 &spr_read_generic, &spr_write_generic,
4639 0x00000000);
80d11f44
JM		 4640 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4641 SPR_NOACCESS, SPR_NOACCESS,
4642 &spr_read_generic, &spr_write_generic,
4643 0x00000000);
4644 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4645 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4646 &spr_read_generic, &spr_write_generic,
4647 0x00000000);
01662f3e
AG		 4648 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4649 SPR_NOACCESS, SPR_NOACCESS,
4650 &spr_read_generic, &spr_write_booke206_mmucsr0,
4651 0x00000000);
b81ccf8a
AG		 4652 spr_register(env, SPR_BOOKE_EPR, "EPR",
4653 SPR_NOACCESS, SPR_NOACCESS,
68c2dd70 4654 &spr_read_generic, SPR_NOACCESS,
b81ccf8a
AG		 4655 0x00000000);
4656 /* XXX better abstract into Emb.xxx features */
4657 if (version == fsl_e5500) {
4658 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4659 SPR_NOACCESS, SPR_NOACCESS,
4660 &spr_read_generic, &spr_write_generic,
4661 0x00000000);
4662 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4663 SPR_NOACCESS, SPR_NOACCESS,
4664 &spr_read_mas73, &spr_write_mas73,
4665 0x00000000);
4666 ivpr_mask = (target_ulong)~0xFFFFULL;
4667 }
01662f3e 4668
f2e63a42 4669#if !defined(CONFIG_USER_ONLY)
01662f3e 4670 env->nb_tlb = 0;
1c53accc 4671 env->tlb_type = TLB_MAS;
01662f3e
AG		 4672 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4673 env->nb_tlb += booke206_tlb_size(env, i);
4674 }
f2e63a42 4675#endif
01662f3e 4676
e9cd84b9 4677 init_excp_e200(env, ivpr_mask);
9fdc60bf
AJ		 4678 /* Allocate hardware IRQ controller */
4679 ppce500_irq_init(env);
3fc6c082 4680}
a750fc0b 4681
01662f3e
AG		 4682static void init_proc_e500v1(CPUPPCState *env)
4683{
f7aa5583 4684 init_proc_e500(env, fsl_e500v1);
01662f3e
AG		 4685}
4686
4687static void init_proc_e500v2(CPUPPCState *env)
4688{
f7aa5583
VS		 4689 init_proc_e500(env, fsl_e500v2);
4690}
4691
4692static void init_proc_e500mc(CPUPPCState *env)
4693{
4694 init_proc_e500(env, fsl_e500mc);
01662f3e
AG		 4695}
4696
b81ccf8a
AG		 4697#ifdef TARGET_PPC64
4698static void init_proc_e5500(CPUPPCState *env)
4699{
4700 init_proc_e500(env, fsl_e5500);
4701}
4702#endif
4703
a750fc0b 4704/* Non-embedded PowerPC */
a750fc0b
JM		 4705
4706/* POWER : same as 601, without mfmsr, mfsr */
4707#if defined(TODO)
4708#define POWERPC_INSNS_POWER (XXX_TODO)
4709/* POWER RSC (from RAD6000) */
4710#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4711#endif /* TODO */
4712
4713/* PowerPC 601 */
082c6681
JM		 4714#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4715 PPC_FLOAT | \
4716 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4717 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4718 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4719#define POWERPC_INSNS2_601 (PPC_NONE)
25ba3a68 4720#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4721#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4722//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4723//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4724#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4725#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4726#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4727#define check_pow_601 check_pow_none
a750fc0b
JM		 4728
4729static void init_proc_601 (CPUPPCState *env)
3fc6c082 4730{
a750fc0b
JM		 4731 gen_spr_ne_601(env);
4732 gen_spr_601(env);
4733 /* Hardware implementation registers */
4734 /* XXX : not implemented */
4735 spr_register(env, SPR_HID0, "HID0",
4736 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4737 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4738 0x80010080);
a750fc0b
JM		 4739 /* XXX : not implemented */
4740 spr_register(env, SPR_HID1, "HID1",
4741 SPR_NOACCESS, SPR_NOACCESS,
4742 &spr_read_generic, &spr_write_generic,
4743 0x00000000);
4744 /* XXX : not implemented */
4745 spr_register(env, SPR_601_HID2, "HID2",
4746 SPR_NOACCESS, SPR_NOACCESS,
4747 &spr_read_generic, &spr_write_generic,
4748 0x00000000);
4749 /* XXX : not implemented */
4750 spr_register(env, SPR_601_HID5, "HID5",
4751 SPR_NOACCESS, SPR_NOACCESS,
4752 &spr_read_generic, &spr_write_generic,
4753 0x00000000);
a750fc0b 4754 /* Memory management */
e1833e1f 4755 init_excp_601(env);
082c6681
JM		 4756 /* XXX: beware that dcache line size is 64
4757 * but dcbz uses 32 bytes "sectors"
4758 * XXX: this breaks clcs instruction !
4759 */
4760 env->dcache_line_size = 32;
d63001d1 4761 env->icache_line_size = 64;
faadf50e
JM		 4762 /* Allocate hardware IRQ controller */
4763 ppc6xx_irq_init(env);
3fc6c082
FB		 4764}
4765
082c6681
JM		 4766/* PowerPC 601v */
4767#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4768 PPC_FLOAT | \
4769 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4770 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4771 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4772#define POWERPC_INSNS2_601v (PPC_NONE)
082c6681
JM		 4773#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4774#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4775#define POWERPC_MMU_601v (POWERPC_MMU_601)
4776#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4777#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4778#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4779#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4780#define check_pow_601v check_pow_none
4781
4782static void init_proc_601v (CPUPPCState *env)
4783{
4784 init_proc_601(env);
4785 /* XXX : not implemented */
4786 spr_register(env, SPR_601_HID15, "HID15",
4787 SPR_NOACCESS, SPR_NOACCESS,
4788 &spr_read_generic, &spr_write_generic,
4789 0x00000000);
4790}
4791
a750fc0b 4792/* PowerPC 602 */
082c6681
JM		 4793#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4794 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4795 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4796 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4797 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4798 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4799 PPC_SEGMENT | PPC_602_SPEC)
a5858d7a 4800#define POWERPC_INSNS2_602 (PPC_NONE)
082c6681
JM		 4801#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4802/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4803#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4804//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4805#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4806#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4807#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4808 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4809#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4810
4811static void init_proc_602 (CPUPPCState *env)
3fc6c082 4812{
a750fc0b
JM		 4813 gen_spr_ne_601(env);
4814 gen_spr_602(env);
4815 /* Time base */
4816 gen_tbl(env);
4817 /* hardware implementation registers */
4818 /* XXX : not implemented */
4819 spr_register(env, SPR_HID0, "HID0",
4820 SPR_NOACCESS, SPR_NOACCESS,
4821 &spr_read_generic, &spr_write_generic,
4822 0x00000000);
4823 /* XXX : not implemented */
4824 spr_register(env, SPR_HID1, "HID1",
4825 SPR_NOACCESS, SPR_NOACCESS,
4826 &spr_read_generic, &spr_write_generic,
4827 0x00000000);
4828 /* Memory management */
4829 gen_low_BATs(env);
4830 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4831 init_excp_602(env);
d63001d1
JM		 4832 env->dcache_line_size = 32;
4833 env->icache_line_size = 32;
a750fc0b
JM		 4834 /* Allocate hardware IRQ controller */
4835 ppc6xx_irq_init(env);
4836}
3fc6c082 4837
a750fc0b 4838/* PowerPC 603 */
082c6681
JM		 4839#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4840 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4841 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4842 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4843 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4844 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4845 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4846#define POWERPC_INSNS2_603 (PPC_NONE)
25ba3a68 4847#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4848#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4849//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4850#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4851#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4852#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4853 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4854#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4855
4856static void init_proc_603 (CPUPPCState *env)
4857{
4858 gen_spr_ne_601(env);
4859 gen_spr_603(env);
4860 /* Time base */
4861 gen_tbl(env);
4862 /* hardware implementation registers */
4863 /* XXX : not implemented */
4864 spr_register(env, SPR_HID0, "HID0",
4865 SPR_NOACCESS, SPR_NOACCESS,
4866 &spr_read_generic, &spr_write_generic,
4867 0x00000000);
4868 /* XXX : not implemented */
4869 spr_register(env, SPR_HID1, "HID1",
4870 SPR_NOACCESS, SPR_NOACCESS,
4871 &spr_read_generic, &spr_write_generic,
4872 0x00000000);
4873 /* Memory management */
4874 gen_low_BATs(env);
4875 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4876 init_excp_603(env);
d63001d1
JM		 4877 env->dcache_line_size = 32;
4878 env->icache_line_size = 32;
a750fc0b
JM		 4879 /* Allocate hardware IRQ controller */
4880 ppc6xx_irq_init(env);
3fc6c082
FB		 4881}
4882
a750fc0b 4883/* PowerPC 603e */
082c6681
JM		 4884#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4885 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4886 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4887 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4888 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4889 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4890 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4891#define POWERPC_INSNS2_603E (PPC_NONE)
a750fc0b
JM		 4892#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4893#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4894//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4895#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4896#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4897#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4898 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4899#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4900
4901static void init_proc_603E (CPUPPCState *env)
4902{
4903 gen_spr_ne_601(env);
4904 gen_spr_603(env);
4905 /* Time base */
4906 gen_tbl(env);
4907 /* hardware implementation registers */
4908 /* XXX : not implemented */
4909 spr_register(env, SPR_HID0, "HID0",
4910 SPR_NOACCESS, SPR_NOACCESS,
4911 &spr_read_generic, &spr_write_generic,
4912 0x00000000);
4913 /* XXX : not implemented */
4914 spr_register(env, SPR_HID1, "HID1",
4915 SPR_NOACCESS, SPR_NOACCESS,
4916 &spr_read_generic, &spr_write_generic,
4917 0x00000000);
4918 /* XXX : not implemented */
4919 spr_register(env, SPR_IABR, "IABR",
4920 SPR_NOACCESS, SPR_NOACCESS,
4921 &spr_read_generic, &spr_write_generic,
4922 0x00000000);
4923 /* Memory management */
4924 gen_low_BATs(env);
4925 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4926 init_excp_603(env);
d63001d1
JM		 4927 env->dcache_line_size = 32;
4928 env->icache_line_size = 32;
a750fc0b
JM		 4929 /* Allocate hardware IRQ controller */
4930 ppc6xx_irq_init(env);
4931}
4932
a750fc0b 4933/* PowerPC 604 */
082c6681
JM		 4934#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4935 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4936 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4937 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4938 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4939 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4940 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4941#define POWERPC_INSNS2_604 (PPC_NONE)
a750fc0b
JM		 4942#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4943#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4944//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4945#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4946#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4947#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4948 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4949#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4950
4951static void init_proc_604 (CPUPPCState *env)
4952{
4953 gen_spr_ne_601(env);
4954 gen_spr_604(env);
4955 /* Time base */
4956 gen_tbl(env);
4957 /* Hardware implementation registers */
4958 /* XXX : not implemented */
082c6681
JM		 4959 spr_register(env, SPR_HID0, "HID0",
4960 SPR_NOACCESS, SPR_NOACCESS,
4961 &spr_read_generic, &spr_write_generic,
4962 0x00000000);
4963 /* Memory management */
4964 gen_low_BATs(env);
4965 init_excp_604(env);
4966 env->dcache_line_size = 32;
4967 env->icache_line_size = 32;
4968 /* Allocate hardware IRQ controller */
4969 ppc6xx_irq_init(env);
4970}
4971
4972/* PowerPC 604E */
4973#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4974 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4975 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4976 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4977 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4978 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4979 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4980#define POWERPC_INSNS2_604E (PPC_NONE)
082c6681
JM		 4981#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4982#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4983#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4984#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4985#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4986#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4987 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4988#define check_pow_604E check_pow_nocheck
4989
4990static void init_proc_604E (CPUPPCState *env)
4991{
4992 gen_spr_ne_601(env);
4993 gen_spr_604(env);
4994 /* XXX : not implemented */
4995 spr_register(env, SPR_MMCR1, "MMCR1",
4996 SPR_NOACCESS, SPR_NOACCESS,
4997 &spr_read_generic, &spr_write_generic,
4998 0x00000000);
4999 /* XXX : not implemented */
5000 spr_register(env, SPR_PMC3, "PMC3",
5001 SPR_NOACCESS, SPR_NOACCESS,
5002 &spr_read_generic, &spr_write_generic,
5003 0x00000000);
5004 /* XXX : not implemented */
5005 spr_register(env, SPR_PMC4, "PMC4",
5006 SPR_NOACCESS, SPR_NOACCESS,
5007 &spr_read_generic, &spr_write_generic,
5008 0x00000000);
5009 /* Time base */
5010 gen_tbl(env);
5011 /* Hardware implementation registers */
5012 /* XXX : not implemented */
a750fc0b
JM		 5013 spr_register(env, SPR_HID0, "HID0",
5014 SPR_NOACCESS, SPR_NOACCESS,
5015 &spr_read_generic, &spr_write_generic,
5016 0x00000000);
5017 /* XXX : not implemented */
5018 spr_register(env, SPR_HID1, "HID1",
5019 SPR_NOACCESS, SPR_NOACCESS,
5020 &spr_read_generic, &spr_write_generic,
5021 0x00000000);
5022 /* Memory management */
5023 gen_low_BATs(env);
e1833e1f 5024 init_excp_604(env);
d63001d1
JM		 5025 env->dcache_line_size = 32;
5026 env->icache_line_size = 32;
a750fc0b
JM		 5027 /* Allocate hardware IRQ controller */
5028 ppc6xx_irq_init(env);
5029}
5030
bd928eba
JM		 5031/* PowerPC 740 */
5032#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5033 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 5034 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5035 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5036 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5037 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5038 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5039#define POWERPC_INSNS2_740 (PPC_NONE)
bd928eba
JM		 5040#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
5041#define POWERPC_MMU_740 (POWERPC_MMU_32B)
5042#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
5043#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
5044#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
5045#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5046 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5047#define check_pow_740 check_pow_hid0
a750fc0b 5048
bd928eba 5049static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 5050{
5051 gen_spr_ne_601(env);
5052 gen_spr_7xx(env);
5053 /* Time base */
5054 gen_tbl(env);
5055 /* Thermal management */
5056 gen_spr_thrm(env);
5057 /* Hardware implementation registers */
5058 /* XXX : not implemented */
5059 spr_register(env, SPR_HID0, "HID0",
5060 SPR_NOACCESS, SPR_NOACCESS,
5061 &spr_read_generic, &spr_write_generic,
5062 0x00000000);
5063 /* XXX : not implemented */
5064 spr_register(env, SPR_HID1, "HID1",
5065 SPR_NOACCESS, SPR_NOACCESS,
5066 &spr_read_generic, &spr_write_generic,
5067 0x00000000);
5068 /* Memory management */
5069 gen_low_BATs(env);
e1833e1f 5070 init_excp_7x0(env);
d63001d1
JM		 5071 env->dcache_line_size = 32;
5072 env->icache_line_size = 32;
a750fc0b
JM		 5073 /* Allocate hardware IRQ controller */
5074 ppc6xx_irq_init(env);
5075}
5076
bd928eba
JM		 5077/* PowerPC 750 */
5078#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5079 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5080 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5081 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5082 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5083 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5084 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5085#define POWERPC_INSNS2_750 (PPC_NONE)
bd928eba
JM		 5086#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
5087#define POWERPC_MMU_750 (POWERPC_MMU_32B)
5088#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
5089#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
5090#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
5091#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5092 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5093#define check_pow_750 check_pow_hid0
5094
5095static void init_proc_750 (CPUPPCState *env)
5096{
5097 gen_spr_ne_601(env);
5098 gen_spr_7xx(env);
5099 /* XXX : not implemented */
5100 spr_register(env, SPR_L2CR, "L2CR",
5101 SPR_NOACCESS, SPR_NOACCESS,
5102 &spr_read_generic, &spr_write_generic,
5103 0x00000000);
5104 /* Time base */
5105 gen_tbl(env);
5106 /* Thermal management */
5107 gen_spr_thrm(env);
5108 /* Hardware implementation registers */
5109 /* XXX : not implemented */
5110 spr_register(env, SPR_HID0, "HID0",
5111 SPR_NOACCESS, SPR_NOACCESS,
5112 &spr_read_generic, &spr_write_generic,
5113 0x00000000);
5114 /* XXX : not implemented */
5115 spr_register(env, SPR_HID1, "HID1",
5116 SPR_NOACCESS, SPR_NOACCESS,
5117 &spr_read_generic, &spr_write_generic,
5118 0x00000000);
5119 /* Memory management */
5120 gen_low_BATs(env);
5121 /* XXX: high BATs are also present but are known to be bugged on
5122 * die version 1.x
5123 */
5124 init_excp_7x0(env);
5125 env->dcache_line_size = 32;
5126 env->icache_line_size = 32;
5127 /* Allocate hardware IRQ controller */
5128 ppc6xx_irq_init(env);
5129}
5130
5131/* PowerPC 750 CL */
5132/* XXX: not implemented:
5133 * cache lock instructions:
5134 * dcbz_l
5135 * floating point paired instructions
5136 * psq_lux
5137 * psq_lx
5138 * psq_stux
5139 * psq_stx
5140 * ps_abs
5141 * ps_add
5142 * ps_cmpo0
5143 * ps_cmpo1
5144 * ps_cmpu0
5145 * ps_cmpu1
5146 * ps_div
5147 * ps_madd
5148 * ps_madds0
5149 * ps_madds1
5150 * ps_merge00
5151 * ps_merge01
5152 * ps_merge10
5153 * ps_merge11
5154 * ps_mr
5155 * ps_msub
5156 * ps_mul
5157 * ps_muls0
5158 * ps_muls1
5159 * ps_nabs
5160 * ps_neg
5161 * ps_nmadd
5162 * ps_nmsub
5163 * ps_res
5164 * ps_rsqrte
5165 * ps_sel
5166 * ps_sub
5167 * ps_sum0
5168 * ps_sum1
5169 */
5170#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5171 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5172 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5173 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5174 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5175 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5176 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5177#define POWERPC_INSNS2_750cl (PPC_NONE)
bd928eba
JM		 5178#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5179#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5180#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5181#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5182#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5183#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5184 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5185#define check_pow_750cl check_pow_hid0
5186
5187static void init_proc_750cl (CPUPPCState *env)
5188{
5189 gen_spr_ne_601(env);
5190 gen_spr_7xx(env);
5191 /* XXX : not implemented */
5192 spr_register(env, SPR_L2CR, "L2CR",
5193 SPR_NOACCESS, SPR_NOACCESS,
5194 &spr_read_generic, &spr_write_generic,
5195 0x00000000);
5196 /* Time base */
5197 gen_tbl(env);
5198 /* Thermal management */
5199 /* Those registers are fake on 750CL */
5200 spr_register(env, SPR_THRM1, "THRM1",
5201 SPR_NOACCESS, SPR_NOACCESS,
5202 &spr_read_generic, &spr_write_generic,
5203 0x00000000);
5204 spr_register(env, SPR_THRM2, "THRM2",
5205 SPR_NOACCESS, SPR_NOACCESS,
5206 &spr_read_generic, &spr_write_generic,
5207 0x00000000);
5208 spr_register(env, SPR_THRM3, "THRM3",
5209 SPR_NOACCESS, SPR_NOACCESS,
5210 &spr_read_generic, &spr_write_generic,
5211 0x00000000);
5212 /* XXX: not implemented */
5213 spr_register(env, SPR_750_TDCL, "TDCL",
5214 SPR_NOACCESS, SPR_NOACCESS,
5215 &spr_read_generic, &spr_write_generic,
5216 0x00000000);
5217 spr_register(env, SPR_750_TDCH, "TDCH",
5218 SPR_NOACCESS, SPR_NOACCESS,
5219 &spr_read_generic, &spr_write_generic,
5220 0x00000000);
5221 /* DMA */
5222 /* XXX : not implemented */
5223 spr_register(env, SPR_750_WPAR, "WPAR",
5224 SPR_NOACCESS, SPR_NOACCESS,
5225 &spr_read_generic, &spr_write_generic,
5226 0x00000000);
5227 spr_register(env, SPR_750_DMAL, "DMAL",
5228 SPR_NOACCESS, SPR_NOACCESS,
5229 &spr_read_generic, &spr_write_generic,
5230 0x00000000);
5231 spr_register(env, SPR_750_DMAU, "DMAU",
5232 SPR_NOACCESS, SPR_NOACCESS,
5233 &spr_read_generic, &spr_write_generic,
5234 0x00000000);
5235 /* Hardware implementation registers */
5236 /* XXX : not implemented */
5237 spr_register(env, SPR_HID0, "HID0",
5238 SPR_NOACCESS, SPR_NOACCESS,
5239 &spr_read_generic, &spr_write_generic,
5240 0x00000000);
5241 /* XXX : not implemented */
5242 spr_register(env, SPR_HID1, "HID1",
5243 SPR_NOACCESS, SPR_NOACCESS,
5244 &spr_read_generic, &spr_write_generic,
5245 0x00000000);
5246 /* XXX : not implemented */
5247 spr_register(env, SPR_750CL_HID2, "HID2",
5248 SPR_NOACCESS, SPR_NOACCESS,
5249 &spr_read_generic, &spr_write_generic,
5250 0x00000000);
5251 /* XXX : not implemented */
5252 spr_register(env, SPR_750CL_HID4, "HID4",
5253 SPR_NOACCESS, SPR_NOACCESS,
5254 &spr_read_generic, &spr_write_generic,
5255 0x00000000);
5256 /* Quantization registers */
5257 /* XXX : not implemented */
5258 spr_register(env, SPR_750_GQR0, "GQR0",
5259 SPR_NOACCESS, SPR_NOACCESS,
5260 &spr_read_generic, &spr_write_generic,
5261 0x00000000);
5262 /* XXX : not implemented */
5263 spr_register(env, SPR_750_GQR1, "GQR1",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 /* XXX : not implemented */
5268 spr_register(env, SPR_750_GQR2, "GQR2",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 0x00000000);
5272 /* XXX : not implemented */
5273 spr_register(env, SPR_750_GQR3, "GQR3",
5274 SPR_NOACCESS, SPR_NOACCESS,
5275 &spr_read_generic, &spr_write_generic,
5276 0x00000000);
5277 /* XXX : not implemented */
5278 spr_register(env, SPR_750_GQR4, "GQR4",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 0x00000000);
5282 /* XXX : not implemented */
5283 spr_register(env, SPR_750_GQR5, "GQR5",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 0x00000000);
5287 /* XXX : not implemented */
5288 spr_register(env, SPR_750_GQR6, "GQR6",
5289 SPR_NOACCESS, SPR_NOACCESS,
5290 &spr_read_generic, &spr_write_generic,
5291 0x00000000);
5292 /* XXX : not implemented */
5293 spr_register(env, SPR_750_GQR7, "GQR7",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 0x00000000);
5297 /* Memory management */
5298 gen_low_BATs(env);
5299 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5300 gen_high_BATs(env);
5301 init_excp_750cl(env);
5302 env->dcache_line_size = 32;
5303 env->icache_line_size = 32;
5304 /* Allocate hardware IRQ controller */
5305 ppc6xx_irq_init(env);
5306}
5307
4e777442 5308/* PowerPC 750CX */
bd928eba
JM		 5309#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5310 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5311 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5312 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5313 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5314 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5315 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5316#define POWERPC_INSNS2_750cx (PPC_NONE)
bd928eba
JM		 5317#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5318#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5319#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5320#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5321#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5322#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5323 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5324#define check_pow_750cx check_pow_hid0
5325
5326static void init_proc_750cx (CPUPPCState *env)
5327{
5328 gen_spr_ne_601(env);
5329 gen_spr_7xx(env);
5330 /* XXX : not implemented */
5331 spr_register(env, SPR_L2CR, "L2CR",
5332 SPR_NOACCESS, SPR_NOACCESS,
5333 &spr_read_generic, &spr_write_generic,
5334 0x00000000);
5335 /* Time base */
5336 gen_tbl(env);
5337 /* Thermal management */
5338 gen_spr_thrm(env);
5339 /* This register is not implemented but is present for compatibility */
5340 spr_register(env, SPR_SDA, "SDA",
5341 SPR_NOACCESS, SPR_NOACCESS,
5342 &spr_read_generic, &spr_write_generic,
5343 0x00000000);
5344 /* Hardware implementation registers */
5345 /* XXX : not implemented */
5346 spr_register(env, SPR_HID0, "HID0",
5347 SPR_NOACCESS, SPR_NOACCESS,
5348 &spr_read_generic, &spr_write_generic,
5349 0x00000000);
5350 /* XXX : not implemented */
5351 spr_register(env, SPR_HID1, "HID1",
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 &spr_read_generic, &spr_write_generic,
5354 0x00000000);
5355 /* Memory management */
5356 gen_low_BATs(env);
4e777442
JM		 5357 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5358 gen_high_BATs(env);
bd928eba
JM		 5359 init_excp_750cx(env);
5360 env->dcache_line_size = 32;
5361 env->icache_line_size = 32;
5362 /* Allocate hardware IRQ controller */
5363 ppc6xx_irq_init(env);
5364}
5365
5366/* PowerPC 750FX */
082c6681
JM		 5367#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5368 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 5369 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5370 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5371 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5372 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5373 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5374#define POWERPC_INSNS2_750fx (PPC_NONE)
25ba3a68 5375#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 5376#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5377#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5378#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 5379#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 5380#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5381 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 5382#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 5383
5384static void init_proc_750fx (CPUPPCState *env)
5385{
5386 gen_spr_ne_601(env);
5387 gen_spr_7xx(env);
bd928eba
JM		 5388 /* XXX : not implemented */
5389 spr_register(env, SPR_L2CR, "L2CR",
5390 SPR_NOACCESS, SPR_NOACCESS,
5391 &spr_read_generic, &spr_write_generic,
5392 0x00000000);
a750fc0b
JM		 5393 /* Time base */
5394 gen_tbl(env);
5395 /* Thermal management */
5396 gen_spr_thrm(env);
bd928eba
JM		 5397 /* XXX : not implemented */
5398 spr_register(env, SPR_750_THRM4, "THRM4",
5399 SPR_NOACCESS, SPR_NOACCESS,
5400 &spr_read_generic, &spr_write_generic,
5401 0x00000000);
a750fc0b
JM		 5402 /* Hardware implementation registers */
5403 /* XXX : not implemented */
5404 spr_register(env, SPR_HID0, "HID0",
5405 SPR_NOACCESS, SPR_NOACCESS,
5406 &spr_read_generic, &spr_write_generic,
5407 0x00000000);
5408 /* XXX : not implemented */
5409 spr_register(env, SPR_HID1, "HID1",
5410 SPR_NOACCESS, SPR_NOACCESS,
5411 &spr_read_generic, &spr_write_generic,
5412 0x00000000);
5413 /* XXX : not implemented */
bd928eba 5414 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5415 SPR_NOACCESS, SPR_NOACCESS,
5416 &spr_read_generic, &spr_write_generic,
5417 0x00000000);
5418 /* Memory management */
5419 gen_low_BATs(env);
5420 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5421 gen_high_BATs(env);
bd928eba 5422 init_excp_7x0(env);
d63001d1
JM		 5423 env->dcache_line_size = 32;
5424 env->icache_line_size = 32;
a750fc0b
JM		 5425 /* Allocate hardware IRQ controller */
5426 ppc6xx_irq_init(env);
5427}
5428
bd928eba
JM		 5429/* PowerPC 750GX */
5430#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5431 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 5432 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5433 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5434 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5435 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5436 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5437#define POWERPC_INSNS2_750gx (PPC_NONE)
bd928eba
JM		 5438#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5439#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5440#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5441#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5442#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5443#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5444 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5445#define check_pow_750gx check_pow_hid0
5446
5447static void init_proc_750gx (CPUPPCState *env)
5448{
5449 gen_spr_ne_601(env);
5450 gen_spr_7xx(env);
5451 /* XXX : not implemented (XXX: different from 750fx) */
5452 spr_register(env, SPR_L2CR, "L2CR",
5453 SPR_NOACCESS, SPR_NOACCESS,
5454 &spr_read_generic, &spr_write_generic,
5455 0x00000000);
5456 /* Time base */
5457 gen_tbl(env);
5458 /* Thermal management */
5459 gen_spr_thrm(env);
5460 /* XXX : not implemented */
5461 spr_register(env, SPR_750_THRM4, "THRM4",
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 &spr_read_generic, &spr_write_generic,
5464 0x00000000);
5465 /* Hardware implementation registers */
5466 /* XXX : not implemented (XXX: different from 750fx) */
5467 spr_register(env, SPR_HID0, "HID0",
5468 SPR_NOACCESS, SPR_NOACCESS,
5469 &spr_read_generic, &spr_write_generic,
5470 0x00000000);
5471 /* XXX : not implemented */
5472 spr_register(env, SPR_HID1, "HID1",
5473 SPR_NOACCESS, SPR_NOACCESS,
5474 &spr_read_generic, &spr_write_generic,
5475 0x00000000);
5476 /* XXX : not implemented (XXX: different from 750fx) */
5477 spr_register(env, SPR_750FX_HID2, "HID2",
5478 SPR_NOACCESS, SPR_NOACCESS,
5479 &spr_read_generic, &spr_write_generic,
5480 0x00000000);
5481 /* Memory management */
5482 gen_low_BATs(env);
5483 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5484 gen_high_BATs(env);
5485 init_excp_7x0(env);
5486 env->dcache_line_size = 32;
5487 env->icache_line_size = 32;
5488 /* Allocate hardware IRQ controller */
5489 ppc6xx_irq_init(env);
5490}
5491
5492/* PowerPC 745 */
5493#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5494 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5495 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5496 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5497 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5498 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5499 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5500#define POWERPC_INSNS2_745 (PPC_NONE)
bd928eba
JM		 5501#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5502#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5503#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5504#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5505#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5506#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5507 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5508#define check_pow_745 check_pow_hid0
5509
5510static void init_proc_745 (CPUPPCState *env)
5511{
5512 gen_spr_ne_601(env);
5513 gen_spr_7xx(env);
5514 gen_spr_G2_755(env);
5515 /* Time base */
5516 gen_tbl(env);
5517 /* Thermal management */
5518 gen_spr_thrm(env);
5519 /* Hardware implementation registers */
5520 /* XXX : not implemented */
5521 spr_register(env, SPR_HID0, "HID0",
5522 SPR_NOACCESS, SPR_NOACCESS,
5523 &spr_read_generic, &spr_write_generic,
5524 0x00000000);
5525 /* XXX : not implemented */
5526 spr_register(env, SPR_HID1, "HID1",
5527 SPR_NOACCESS, SPR_NOACCESS,
5528 &spr_read_generic, &spr_write_generic,
5529 0x00000000);
5530 /* XXX : not implemented */
5531 spr_register(env, SPR_HID2, "HID2",
5532 SPR_NOACCESS, SPR_NOACCESS,
5533 &spr_read_generic, &spr_write_generic,
5534 0x00000000);
5535 /* Memory management */
5536 gen_low_BATs(env);
5537 gen_high_BATs(env);
5538 gen_6xx_7xx_soft_tlb(env, 64, 2);
5539 init_excp_7x5(env);
5540 env->dcache_line_size = 32;
5541 env->icache_line_size = 32;
5542 /* Allocate hardware IRQ controller */
5543 ppc6xx_irq_init(env);
5544}
5545
5546/* PowerPC 755 */
5547#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5548 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5549 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5550 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5551 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5552 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5553 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5554#define POWERPC_INSNS2_755 (PPC_NONE)
bd928eba
JM		 5555#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5556#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5557#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5558#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5559#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5560#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5561 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5562#define check_pow_755 check_pow_hid0
a750fc0b 5563
bd928eba 5564static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5565{
5566 gen_spr_ne_601(env);
bd928eba 5567 gen_spr_7xx(env);
a750fc0b
JM		 5568 gen_spr_G2_755(env);
5569 /* Time base */
5570 gen_tbl(env);
5571 /* L2 cache control */
5572 /* XXX : not implemented */
bd928eba 5573 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5574 SPR_NOACCESS, SPR_NOACCESS,
5575 &spr_read_generic, &spr_write_generic,
5576 0x00000000);
5577 /* XXX : not implemented */
5578 spr_register(env, SPR_L2PMCR, "L2PMCR",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic,
5581 0x00000000);
bd928eba
JM		 5582 /* Thermal management */
5583 gen_spr_thrm(env);
a750fc0b
JM		 5584 /* Hardware implementation registers */
5585 /* XXX : not implemented */
5586 spr_register(env, SPR_HID0, "HID0",
5587 SPR_NOACCESS, SPR_NOACCESS,
5588 &spr_read_generic, &spr_write_generic,
5589 0x00000000);
5590 /* XXX : not implemented */
5591 spr_register(env, SPR_HID1, "HID1",
5592 SPR_NOACCESS, SPR_NOACCESS,
5593 &spr_read_generic, &spr_write_generic,
5594 0x00000000);
5595 /* XXX : not implemented */
5596 spr_register(env, SPR_HID2, "HID2",
5597 SPR_NOACCESS, SPR_NOACCESS,
5598 &spr_read_generic, &spr_write_generic,
5599 0x00000000);
5600 /* Memory management */
5601 gen_low_BATs(env);
5602 gen_high_BATs(env);
5603 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5604 init_excp_7x5(env);
d63001d1
JM		 5605 env->dcache_line_size = 32;
5606 env->icache_line_size = 32;
a750fc0b
JM		 5607 /* Allocate hardware IRQ controller */
5608 ppc6xx_irq_init(env);
5609}
5610
5611/* PowerPC 7400 (aka G4) */
082c6681
JM		 5612#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5613 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5614 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5615 PPC_FLOAT_STFIWX | \
5616 PPC_CACHE | PPC_CACHE_ICBI | \
5617 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5618 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5620 PPC_MEM_TLBIA | \
5621 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5622 PPC_ALTIVEC)
a5858d7a 5623#define POWERPC_INSNS2_7400 (PPC_NONE)
a750fc0b
JM		 5624#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5625#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5626#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5627#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5628#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5629#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5630 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5631 POWERPC_FLAG_BUS_CLK)
488243b0 5632#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 5633
5634static void init_proc_7400 (CPUPPCState *env)
5635{
5636 gen_spr_ne_601(env);
5637 gen_spr_7xx(env);
5638 /* Time base */
5639 gen_tbl(env);
5640 /* 74xx specific SPR */
5641 gen_spr_74xx(env);
4e777442
JM		 5642 /* XXX : not implemented */
5643 spr_register(env, SPR_UBAMR, "UBAMR",
5644 &spr_read_ureg, SPR_NOACCESS,
5645 &spr_read_ureg, SPR_NOACCESS,
5646 0x00000000);
5647 /* XXX: this seems not implemented on all revisions. */
5648 /* XXX : not implemented */
5649 spr_register(env, SPR_MSSCR1, "MSSCR1",
5650 SPR_NOACCESS, SPR_NOACCESS,
5651 &spr_read_generic, &spr_write_generic,
5652 0x00000000);
a750fc0b
JM		 5653 /* Thermal management */
5654 gen_spr_thrm(env);
5655 /* Memory management */
5656 gen_low_BATs(env);
e1833e1f 5657 init_excp_7400(env);
d63001d1
JM		 5658 env->dcache_line_size = 32;
5659 env->icache_line_size = 32;
a750fc0b
JM		 5660 /* Allocate hardware IRQ controller */
5661 ppc6xx_irq_init(env);
5662}
5663
5664/* PowerPC 7410 (aka G4) */
082c6681
JM		 5665#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5666 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5667 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5668 PPC_FLOAT_STFIWX | \
5669 PPC_CACHE | PPC_CACHE_ICBI | \
5670 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5671 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5672 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5673 PPC_MEM_TLBIA | \
5674 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5675 PPC_ALTIVEC)
a5858d7a 5676#define POWERPC_INSNS2_7410 (PPC_NONE)
a750fc0b
JM		 5677#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5678#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5679#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5680#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5681#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5682#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5683 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5684 POWERPC_FLAG_BUS_CLK)
488243b0 5685#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 5686
5687static void init_proc_7410 (CPUPPCState *env)
5688{
5689 gen_spr_ne_601(env);
5690 gen_spr_7xx(env);
5691 /* Time base */
5692 gen_tbl(env);
5693 /* 74xx specific SPR */
5694 gen_spr_74xx(env);
4e777442
JM		 5695 /* XXX : not implemented */
5696 spr_register(env, SPR_UBAMR, "UBAMR",
5697 &spr_read_ureg, SPR_NOACCESS,
5698 &spr_read_ureg, SPR_NOACCESS,
5699 0x00000000);
a750fc0b
JM		 5700 /* Thermal management */
5701 gen_spr_thrm(env);
5702 /* L2PMCR */
5703 /* XXX : not implemented */
5704 spr_register(env, SPR_L2PMCR, "L2PMCR",
5705 SPR_NOACCESS, SPR_NOACCESS,
5706 &spr_read_generic, &spr_write_generic,
5707 0x00000000);
5708 /* LDSTDB */
5709 /* XXX : not implemented */
5710 spr_register(env, SPR_LDSTDB, "LDSTDB",
5711 SPR_NOACCESS, SPR_NOACCESS,
5712 &spr_read_generic, &spr_write_generic,
5713 0x00000000);
5714 /* Memory management */
5715 gen_low_BATs(env);
e1833e1f 5716 init_excp_7400(env);
d63001d1
JM		 5717 env->dcache_line_size = 32;
5718 env->icache_line_size = 32;
a750fc0b
JM		 5719 /* Allocate hardware IRQ controller */
5720 ppc6xx_irq_init(env);
5721}
5722
5723/* PowerPC 7440 (aka G4) */
082c6681
JM		 5724#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5725 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5726 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5727 PPC_FLOAT_STFIWX | \
5728 PPC_CACHE | PPC_CACHE_ICBI | \
5729 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5730 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5731 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5732 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5733 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5734 PPC_ALTIVEC)
a5858d7a 5735#define POWERPC_INSNS2_7440 (PPC_NONE)
a750fc0b
JM		 5736#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5737#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5738#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5739#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5740#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5741#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5742 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5743 POWERPC_FLAG_BUS_CLK)
4e777442 5744#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5745
578bb252 5746__attribute__ (( unused ))
a750fc0b
JM		 5747static void init_proc_7440 (CPUPPCState *env)
5748{
5749 gen_spr_ne_601(env);
5750 gen_spr_7xx(env);
5751 /* Time base */
5752 gen_tbl(env);
5753 /* 74xx specific SPR */
5754 gen_spr_74xx(env);
4e777442
JM		 5755 /* XXX : not implemented */
5756 spr_register(env, SPR_UBAMR, "UBAMR",
5757 &spr_read_ureg, SPR_NOACCESS,
5758 &spr_read_ureg, SPR_NOACCESS,
5759 0x00000000);
a750fc0b
JM		 5760 /* LDSTCR */
5761 /* XXX : not implemented */
5762 spr_register(env, SPR_LDSTCR, "LDSTCR",
5763 SPR_NOACCESS, SPR_NOACCESS,
5764 &spr_read_generic, &spr_write_generic,
5765 0x00000000);
5766 /* ICTRL */
5767 /* XXX : not implemented */
5768 spr_register(env, SPR_ICTRL, "ICTRL",
5769 SPR_NOACCESS, SPR_NOACCESS,
5770 &spr_read_generic, &spr_write_generic,
5771 0x00000000);
5772 /* MSSSR0 */
578bb252 5773 /* XXX : not implemented */
a750fc0b
JM		 5774 spr_register(env, SPR_MSSSR0, "MSSSR0",
5775 SPR_NOACCESS, SPR_NOACCESS,
5776 &spr_read_generic, &spr_write_generic,
5777 0x00000000);
5778 /* PMC */
5779 /* XXX : not implemented */
5780 spr_register(env, SPR_PMC5, "PMC5",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x00000000);
578bb252 5784 /* XXX : not implemented */
a750fc0b
JM		 5785 spr_register(env, SPR_UPMC5, "UPMC5",
5786 &spr_read_ureg, SPR_NOACCESS,
5787 &spr_read_ureg, SPR_NOACCESS,
5788 0x00000000);
578bb252 5789 /* XXX : not implemented */
a750fc0b
JM		 5790 spr_register(env, SPR_PMC6, "PMC6",
5791 SPR_NOACCESS, SPR_NOACCESS,
5792 &spr_read_generic, &spr_write_generic,
5793 0x00000000);
578bb252 5794 /* XXX : not implemented */
a750fc0b
JM		 5795 spr_register(env, SPR_UPMC6, "UPMC6",
5796 &spr_read_ureg, SPR_NOACCESS,
5797 &spr_read_ureg, SPR_NOACCESS,
5798 0x00000000);
5799 /* Memory management */
5800 gen_low_BATs(env);
578bb252 5801 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5802 init_excp_7450(env);
d63001d1
JM		 5803 env->dcache_line_size = 32;
5804 env->icache_line_size = 32;
a750fc0b
JM		 5805 /* Allocate hardware IRQ controller */
5806 ppc6xx_irq_init(env);
5807}
a750fc0b
JM		 5808
5809/* PowerPC 7450 (aka G4) */
082c6681
JM		 5810#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5811 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5812 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5813 PPC_FLOAT_STFIWX | \
5814 PPC_CACHE | PPC_CACHE_ICBI | \
5815 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5816 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5817 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5818 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5819 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5820 PPC_ALTIVEC)
a5858d7a 5821#define POWERPC_INSNS2_7450 (PPC_NONE)
a750fc0b
JM		 5822#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5823#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5824#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5825#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5826#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5827#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5828 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5829 POWERPC_FLAG_BUS_CLK)
4e777442 5830#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5831
578bb252 5832__attribute__ (( unused ))
a750fc0b
JM		 5833static void init_proc_7450 (CPUPPCState *env)
5834{
5835 gen_spr_ne_601(env);
5836 gen_spr_7xx(env);
5837 /* Time base */
5838 gen_tbl(env);
5839 /* 74xx specific SPR */
5840 gen_spr_74xx(env);
5841 /* Level 3 cache control */
5842 gen_l3_ctrl(env);
4e777442
JM		 5843 /* L3ITCR1 */
5844 /* XXX : not implemented */
5845 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5846 SPR_NOACCESS, SPR_NOACCESS,
5847 &spr_read_generic, &spr_write_generic,
5848 0x00000000);
5849 /* L3ITCR2 */
5850 /* XXX : not implemented */
5851 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5852 SPR_NOACCESS, SPR_NOACCESS,
5853 &spr_read_generic, &spr_write_generic,
5854 0x00000000);
5855 /* L3ITCR3 */
5856 /* XXX : not implemented */
5857 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5858 SPR_NOACCESS, SPR_NOACCESS,
5859 &spr_read_generic, &spr_write_generic,
5860 0x00000000);
5861 /* L3OHCR */
5862 /* XXX : not implemented */
5863 spr_register(env, SPR_L3OHCR, "L3OHCR",
5864 SPR_NOACCESS, SPR_NOACCESS,
5865 &spr_read_generic, &spr_write_generic,
5866 0x00000000);
5867 /* XXX : not implemented */
5868 spr_register(env, SPR_UBAMR, "UBAMR",
5869 &spr_read_ureg, SPR_NOACCESS,
5870 &spr_read_ureg, SPR_NOACCESS,
5871 0x00000000);
a750fc0b
JM		 5872 /* LDSTCR */
5873 /* XXX : not implemented */
5874 spr_register(env, SPR_LDSTCR, "LDSTCR",
5875 SPR_NOACCESS, SPR_NOACCESS,
5876 &spr_read_generic, &spr_write_generic,
5877 0x00000000);
5878 /* ICTRL */
5879 /* XXX : not implemented */
5880 spr_register(env, SPR_ICTRL, "ICTRL",
5881 SPR_NOACCESS, SPR_NOACCESS,
5882 &spr_read_generic, &spr_write_generic,
5883 0x00000000);
5884 /* MSSSR0 */
578bb252 5885 /* XXX : not implemented */
a750fc0b
JM		 5886 spr_register(env, SPR_MSSSR0, "MSSSR0",
5887 SPR_NOACCESS, SPR_NOACCESS,
5888 &spr_read_generic, &spr_write_generic,
5889 0x00000000);
5890 /* PMC */
5891 /* XXX : not implemented */
5892 spr_register(env, SPR_PMC5, "PMC5",
5893 SPR_NOACCESS, SPR_NOACCESS,
5894 &spr_read_generic, &spr_write_generic,
5895 0x00000000);
578bb252 5896 /* XXX : not implemented */
a750fc0b
JM		 5897 spr_register(env, SPR_UPMC5, "UPMC5",
5898 &spr_read_ureg, SPR_NOACCESS,
5899 &spr_read_ureg, SPR_NOACCESS,
5900 0x00000000);
578bb252 5901 /* XXX : not implemented */
a750fc0b
JM		 5902 spr_register(env, SPR_PMC6, "PMC6",
5903 SPR_NOACCESS, SPR_NOACCESS,
5904 &spr_read_generic, &spr_write_generic,
5905 0x00000000);
578bb252 5906 /* XXX : not implemented */
a750fc0b
JM		 5907 spr_register(env, SPR_UPMC6, "UPMC6",
5908 &spr_read_ureg, SPR_NOACCESS,
5909 &spr_read_ureg, SPR_NOACCESS,
5910 0x00000000);
5911 /* Memory management */
5912 gen_low_BATs(env);
578bb252 5913 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5914 init_excp_7450(env);
d63001d1
JM		 5915 env->dcache_line_size = 32;
5916 env->icache_line_size = 32;
a750fc0b
JM		 5917 /* Allocate hardware IRQ controller */
5918 ppc6xx_irq_init(env);
5919}
a750fc0b
JM		 5920
5921/* PowerPC 7445 (aka G4) */
082c6681
JM		 5922#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5923 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5924 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5925 PPC_FLOAT_STFIWX | \
5926 PPC_CACHE | PPC_CACHE_ICBI | \
5927 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5928 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5929 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5930 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5931 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5932 PPC_ALTIVEC)
a5858d7a 5933#define POWERPC_INSNS2_7445 (PPC_NONE)
a750fc0b
JM		 5934#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5935#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5936#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5937#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5938#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5939#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5940 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5941 POWERPC_FLAG_BUS_CLK)
4e777442 5942#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5943
578bb252 5944__attribute__ (( unused ))
a750fc0b
JM		 5945static void init_proc_7445 (CPUPPCState *env)
5946{
5947 gen_spr_ne_601(env);
5948 gen_spr_7xx(env);
5949 /* Time base */
5950 gen_tbl(env);
5951 /* 74xx specific SPR */
5952 gen_spr_74xx(env);
5953 /* LDSTCR */
5954 /* XXX : not implemented */
5955 spr_register(env, SPR_LDSTCR, "LDSTCR",
5956 SPR_NOACCESS, SPR_NOACCESS,
5957 &spr_read_generic, &spr_write_generic,
5958 0x00000000);
5959 /* ICTRL */
5960 /* XXX : not implemented */
5961 spr_register(env, SPR_ICTRL, "ICTRL",
5962 SPR_NOACCESS, SPR_NOACCESS,
5963 &spr_read_generic, &spr_write_generic,
5964 0x00000000);
5965 /* MSSSR0 */
578bb252 5966 /* XXX : not implemented */
a750fc0b
JM		 5967 spr_register(env, SPR_MSSSR0, "MSSSR0",
5968 SPR_NOACCESS, SPR_NOACCESS,
5969 &spr_read_generic, &spr_write_generic,
5970 0x00000000);
5971 /* PMC */
5972 /* XXX : not implemented */
5973 spr_register(env, SPR_PMC5, "PMC5",
5974 SPR_NOACCESS, SPR_NOACCESS,
5975 &spr_read_generic, &spr_write_generic,
5976 0x00000000);
578bb252 5977 /* XXX : not implemented */
a750fc0b
JM		 5978 spr_register(env, SPR_UPMC5, "UPMC5",
5979 &spr_read_ureg, SPR_NOACCESS,
5980 &spr_read_ureg, SPR_NOACCESS,
5981 0x00000000);
578bb252 5982 /* XXX : not implemented */
a750fc0b
JM		 5983 spr_register(env, SPR_PMC6, "PMC6",
5984 SPR_NOACCESS, SPR_NOACCESS,
5985 &spr_read_generic, &spr_write_generic,
5986 0x00000000);
578bb252 5987 /* XXX : not implemented */
a750fc0b
JM		 5988 spr_register(env, SPR_UPMC6, "UPMC6",
5989 &spr_read_ureg, SPR_NOACCESS,
5990 &spr_read_ureg, SPR_NOACCESS,
5991 0x00000000);
5992 /* SPRGs */
5993 spr_register(env, SPR_SPRG4, "SPRG4",
5994 SPR_NOACCESS, SPR_NOACCESS,
5995 &spr_read_generic, &spr_write_generic,
5996 0x00000000);
5997 spr_register(env, SPR_USPRG4, "USPRG4",
5998 &spr_read_ureg, SPR_NOACCESS,
5999 &spr_read_ureg, SPR_NOACCESS,
6000 0x00000000);
6001 spr_register(env, SPR_SPRG5, "SPRG5",
6002 SPR_NOACCESS, SPR_NOACCESS,
6003 &spr_read_generic, &spr_write_generic,
6004 0x00000000);
6005 spr_register(env, SPR_USPRG5, "USPRG5",
6006 &spr_read_ureg, SPR_NOACCESS,
6007 &spr_read_ureg, SPR_NOACCESS,
6008 0x00000000);
6009 spr_register(env, SPR_SPRG6, "SPRG6",
6010 SPR_NOACCESS, SPR_NOACCESS,
6011 &spr_read_generic, &spr_write_generic,
6012 0x00000000);
6013 spr_register(env, SPR_USPRG6, "USPRG6",
6014 &spr_read_ureg, SPR_NOACCESS,
6015 &spr_read_ureg, SPR_NOACCESS,
6016 0x00000000);
6017 spr_register(env, SPR_SPRG7, "SPRG7",
6018 SPR_NOACCESS, SPR_NOACCESS,
6019 &spr_read_generic, &spr_write_generic,
6020 0x00000000);
6021 spr_register(env, SPR_USPRG7, "USPRG7",
6022 &spr_read_ureg, SPR_NOACCESS,
6023 &spr_read_ureg, SPR_NOACCESS,
6024 0x00000000);
6025 /* Memory management */
6026 gen_low_BATs(env);
6027 gen_high_BATs(env);
578bb252 6028 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6029 init_excp_7450(env);
d63001d1
JM		 6030 env->dcache_line_size = 32;
6031 env->icache_line_size = 32;
a750fc0b
JM		 6032 /* Allocate hardware IRQ controller */
6033 ppc6xx_irq_init(env);
6034}
a750fc0b
JM		 6035
6036/* PowerPC 7455 (aka G4) */
082c6681
JM		 6037#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6038 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6039 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6040 PPC_FLOAT_STFIWX | \
6041 PPC_CACHE | PPC_CACHE_ICBI | \
6042 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6043 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6044 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6045 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6046 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6047 PPC_ALTIVEC)
a5858d7a 6048#define POWERPC_INSNS2_7455 (PPC_NONE)
a750fc0b
JM		 6049#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
6050#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
6051#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
6052#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 6053#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 6054#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6055 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6056 POWERPC_FLAG_BUS_CLK)
4e777442 6057#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 6058
578bb252 6059__attribute__ (( unused ))
a750fc0b
JM		 6060static void init_proc_7455 (CPUPPCState *env)
6061{
6062 gen_spr_ne_601(env);
6063 gen_spr_7xx(env);
6064 /* Time base */
6065 gen_tbl(env);
6066 /* 74xx specific SPR */
6067 gen_spr_74xx(env);
6068 /* Level 3 cache control */
6069 gen_l3_ctrl(env);
6070 /* LDSTCR */
6071 /* XXX : not implemented */
6072 spr_register(env, SPR_LDSTCR, "LDSTCR",
6073 SPR_NOACCESS, SPR_NOACCESS,
6074 &spr_read_generic, &spr_write_generic,
6075 0x00000000);
6076 /* ICTRL */
6077 /* XXX : not implemented */
6078 spr_register(env, SPR_ICTRL, "ICTRL",
6079 SPR_NOACCESS, SPR_NOACCESS,
6080 &spr_read_generic, &spr_write_generic,
6081 0x00000000);
6082 /* MSSSR0 */
578bb252 6083 /* XXX : not implemented */
a750fc0b
JM		 6084 spr_register(env, SPR_MSSSR0, "MSSSR0",
6085 SPR_NOACCESS, SPR_NOACCESS,
6086 &spr_read_generic, &spr_write_generic,
6087 0x00000000);
6088 /* PMC */
6089 /* XXX : not implemented */
6090 spr_register(env, SPR_PMC5, "PMC5",
6091 SPR_NOACCESS, SPR_NOACCESS,
6092 &spr_read_generic, &spr_write_generic,
6093 0x00000000);
578bb252 6094 /* XXX : not implemented */
a750fc0b
JM		 6095 spr_register(env, SPR_UPMC5, "UPMC5",
6096 &spr_read_ureg, SPR_NOACCESS,
6097 &spr_read_ureg, SPR_NOACCESS,
6098 0x00000000);
578bb252 6099 /* XXX : not implemented */
a750fc0b
JM		 6100 spr_register(env, SPR_PMC6, "PMC6",
6101 SPR_NOACCESS, SPR_NOACCESS,
6102 &spr_read_generic, &spr_write_generic,
6103 0x00000000);
578bb252 6104 /* XXX : not implemented */
a750fc0b
JM		 6105 spr_register(env, SPR_UPMC6, "UPMC6",
6106 &spr_read_ureg, SPR_NOACCESS,
6107 &spr_read_ureg, SPR_NOACCESS,
6108 0x00000000);
6109 /* SPRGs */
6110 spr_register(env, SPR_SPRG4, "SPRG4",
6111 SPR_NOACCESS, SPR_NOACCESS,
6112 &spr_read_generic, &spr_write_generic,
6113 0x00000000);
6114 spr_register(env, SPR_USPRG4, "USPRG4",
6115 &spr_read_ureg, SPR_NOACCESS,
6116 &spr_read_ureg, SPR_NOACCESS,
6117 0x00000000);
6118 spr_register(env, SPR_SPRG5, "SPRG5",
6119 SPR_NOACCESS, SPR_NOACCESS,
6120 &spr_read_generic, &spr_write_generic,
6121 0x00000000);
6122 spr_register(env, SPR_USPRG5, "USPRG5",
6123 &spr_read_ureg, SPR_NOACCESS,
6124 &spr_read_ureg, SPR_NOACCESS,
6125 0x00000000);
6126 spr_register(env, SPR_SPRG6, "SPRG6",
6127 SPR_NOACCESS, SPR_NOACCESS,
6128 &spr_read_generic, &spr_write_generic,
6129 0x00000000);
6130 spr_register(env, SPR_USPRG6, "USPRG6",
6131 &spr_read_ureg, SPR_NOACCESS,
6132 &spr_read_ureg, SPR_NOACCESS,
6133 0x00000000);
6134 spr_register(env, SPR_SPRG7, "SPRG7",
6135 SPR_NOACCESS, SPR_NOACCESS,
6136 &spr_read_generic, &spr_write_generic,
6137 0x00000000);
6138 spr_register(env, SPR_USPRG7, "USPRG7",
6139 &spr_read_ureg, SPR_NOACCESS,
6140 &spr_read_ureg, SPR_NOACCESS,
6141 0x00000000);
6142 /* Memory management */
6143 gen_low_BATs(env);
6144 gen_high_BATs(env);
578bb252 6145 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6146 init_excp_7450(env);
d63001d1
JM		 6147 env->dcache_line_size = 32;
6148 env->icache_line_size = 32;
a750fc0b
JM		 6149 /* Allocate hardware IRQ controller */
6150 ppc6xx_irq_init(env);
6151}
a750fc0b 6152
4e777442
JM		 6153/* PowerPC 7457 (aka G4) */
6154#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6155 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6156 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6157 PPC_FLOAT_STFIWX | \
6158 PPC_CACHE | PPC_CACHE_ICBI | \
6159 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6160 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6161 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6162 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6163 PPC_SEGMENT | PPC_EXTERN | \
6164 PPC_ALTIVEC)
a5858d7a 6165#define POWERPC_INSNS2_7457 (PPC_NONE)
4e777442
JM		 6166#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6167#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6168#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6169#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6170#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6171#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6172 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6173 POWERPC_FLAG_BUS_CLK)
6174#define check_pow_7457 check_pow_hid0_74xx
6175
6176__attribute__ (( unused ))
6177static void init_proc_7457 (CPUPPCState *env)
6178{
6179 gen_spr_ne_601(env);
6180 gen_spr_7xx(env);
6181 /* Time base */
6182 gen_tbl(env);
6183 /* 74xx specific SPR */
6184 gen_spr_74xx(env);
6185 /* Level 3 cache control */
6186 gen_l3_ctrl(env);
6187 /* L3ITCR1 */
6188 /* XXX : not implemented */
6189 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6190 SPR_NOACCESS, SPR_NOACCESS,
6191 &spr_read_generic, &spr_write_generic,
6192 0x00000000);
6193 /* L3ITCR2 */
6194 /* XXX : not implemented */
6195 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6196 SPR_NOACCESS, SPR_NOACCESS,
6197 &spr_read_generic, &spr_write_generic,
6198 0x00000000);
6199 /* L3ITCR3 */
6200 /* XXX : not implemented */
6201 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6202 SPR_NOACCESS, SPR_NOACCESS,
6203 &spr_read_generic, &spr_write_generic,
6204 0x00000000);
6205 /* L3OHCR */
6206 /* XXX : not implemented */
6207 spr_register(env, SPR_L3OHCR, "L3OHCR",
6208 SPR_NOACCESS, SPR_NOACCESS,
6209 &spr_read_generic, &spr_write_generic,
6210 0x00000000);
6211 /* LDSTCR */
6212 /* XXX : not implemented */
6213 spr_register(env, SPR_LDSTCR, "LDSTCR",
6214 SPR_NOACCESS, SPR_NOACCESS,
6215 &spr_read_generic, &spr_write_generic,
6216 0x00000000);
6217 /* ICTRL */
6218 /* XXX : not implemented */
6219 spr_register(env, SPR_ICTRL, "ICTRL",
6220 SPR_NOACCESS, SPR_NOACCESS,
6221 &spr_read_generic, &spr_write_generic,
6222 0x00000000);
6223 /* MSSSR0 */
6224 /* XXX : not implemented */
6225 spr_register(env, SPR_MSSSR0, "MSSSR0",
6226 SPR_NOACCESS, SPR_NOACCESS,
6227 &spr_read_generic, &spr_write_generic,
6228 0x00000000);
6229 /* PMC */
6230 /* XXX : not implemented */
6231 spr_register(env, SPR_PMC5, "PMC5",
6232 SPR_NOACCESS, SPR_NOACCESS,
6233 &spr_read_generic, &spr_write_generic,
6234 0x00000000);
6235 /* XXX : not implemented */
6236 spr_register(env, SPR_UPMC5, "UPMC5",
6237 &spr_read_ureg, SPR_NOACCESS,
6238 &spr_read_ureg, SPR_NOACCESS,
6239 0x00000000);
6240 /* XXX : not implemented */
6241 spr_register(env, SPR_PMC6, "PMC6",
6242 SPR_NOACCESS, SPR_NOACCESS,
6243 &spr_read_generic, &spr_write_generic,
6244 0x00000000);
6245 /* XXX : not implemented */
6246 spr_register(env, SPR_UPMC6, "UPMC6",
6247 &spr_read_ureg, SPR_NOACCESS,
6248 &spr_read_ureg, SPR_NOACCESS,
6249 0x00000000);
6250 /* SPRGs */
6251 spr_register(env, SPR_SPRG4, "SPRG4",
6252 SPR_NOACCESS, SPR_NOACCESS,
6253 &spr_read_generic, &spr_write_generic,
6254 0x00000000);
6255 spr_register(env, SPR_USPRG4, "USPRG4",
6256 &spr_read_ureg, SPR_NOACCESS,
6257 &spr_read_ureg, SPR_NOACCESS,
6258 0x00000000);
6259 spr_register(env, SPR_SPRG5, "SPRG5",
6260 SPR_NOACCESS, SPR_NOACCESS,
6261 &spr_read_generic, &spr_write_generic,
6262 0x00000000);
6263 spr_register(env, SPR_USPRG5, "USPRG5",
6264 &spr_read_ureg, SPR_NOACCESS,
6265 &spr_read_ureg, SPR_NOACCESS,
6266 0x00000000);
6267 spr_register(env, SPR_SPRG6, "SPRG6",
6268 SPR_NOACCESS, SPR_NOACCESS,
6269 &spr_read_generic, &spr_write_generic,
6270 0x00000000);
6271 spr_register(env, SPR_USPRG6, "USPRG6",
6272 &spr_read_ureg, SPR_NOACCESS,
6273 &spr_read_ureg, SPR_NOACCESS,
6274 0x00000000);
6275 spr_register(env, SPR_SPRG7, "SPRG7",
6276 SPR_NOACCESS, SPR_NOACCESS,
6277 &spr_read_generic, &spr_write_generic,
6278 0x00000000);
6279 spr_register(env, SPR_USPRG7, "USPRG7",
6280 &spr_read_ureg, SPR_NOACCESS,
6281 &spr_read_ureg, SPR_NOACCESS,
6282 0x00000000);
6283 /* Memory management */
6284 gen_low_BATs(env);
6285 gen_high_BATs(env);
6286 gen_74xx_soft_tlb(env, 128, 2);
6287 init_excp_7450(env);
6288 env->dcache_line_size = 32;
6289 env->icache_line_size = 32;
6290 /* Allocate hardware IRQ controller */
6291 ppc6xx_irq_init(env);
6292}
6293
a750fc0b
JM		 6294#if defined (TARGET_PPC64)
6295/* PowerPC 970 */
082c6681
JM		 6296#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6297 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6298 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6299 PPC_FLOAT_STFIWX | \
6300 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6301 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6302 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6303 PPC_64B | PPC_ALTIVEC | \
12de9a39 6304 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6305#define POWERPC_INSNS2_970 (PPC_NONE)
a750fc0b 6306#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 6307#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 6308//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6309#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 6310#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 6311#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6312 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6313 POWERPC_FLAG_BUS_CLK)
a750fc0b 6314
417bf010
JM		 6315#if defined(CONFIG_USER_ONLY)
6316#define POWERPC970_HID5_INIT 0x00000080
6317#else
6318#define POWERPC970_HID5_INIT 0x00000000
6319#endif
6320
2f462816
JM		 6321static int check_pow_970 (CPUPPCState *env)
6322{
6323 if (env->spr[SPR_HID0] & 0x00600000)
6324 return 1;
6325
6326 return 0;
6327}
6328
a750fc0b
JM		 6329static void init_proc_970 (CPUPPCState *env)
6330{
6331 gen_spr_ne_601(env);
6332 gen_spr_7xx(env);
6333 /* Time base */
6334 gen_tbl(env);
6335 /* Hardware implementation registers */
6336 /* XXX : not implemented */
6337 spr_register(env, SPR_HID0, "HID0",
6338 SPR_NOACCESS, SPR_NOACCESS,
06403421 6339 &spr_read_generic, &spr_write_clear,
d63001d1 6340 0x60000000);
a750fc0b
JM		 6341 /* XXX : not implemented */
6342 spr_register(env, SPR_HID1, "HID1",
6343 SPR_NOACCESS, SPR_NOACCESS,
6344 &spr_read_generic, &spr_write_generic,
6345 0x00000000);
6346 /* XXX : not implemented */
bd928eba 6347 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, &spr_write_generic,
6350 0x00000000);
e57448f1
JM		 6351 /* XXX : not implemented */
6352 spr_register(env, SPR_970_HID5, "HID5",
6353 SPR_NOACCESS, SPR_NOACCESS,
6354 &spr_read_generic, &spr_write_generic,
417bf010 6355 POWERPC970_HID5_INIT);
bd928eba
JM		 6356 /* XXX : not implemented */
6357 spr_register(env, SPR_L2CR, "L2CR",
6358 SPR_NOACCESS, SPR_NOACCESS,
6359 &spr_read_generic, &spr_write_generic,
6360 0x00000000);
a750fc0b
JM		 6361 /* Memory management */
6362 /* XXX: not correct */
6363 gen_low_BATs(env);
12de9a39
JM		 6364 /* XXX : not implemented */
6365 spr_register(env, SPR_MMUCFG, "MMUCFG",
6366 SPR_NOACCESS, SPR_NOACCESS,
6367 &spr_read_generic, SPR_NOACCESS,
6368 0x00000000); /* TOFIX */
6369 /* XXX : not implemented */
6370 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6371 SPR_NOACCESS, SPR_NOACCESS,
6372 &spr_read_generic, &spr_write_generic,
6373 0x00000000); /* TOFIX */
6374 spr_register(env, SPR_HIOR, "SPR_HIOR",
6375 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6376 &spr_read_hior, &spr_write_hior,
6377 0x00000000);
f2e63a42 6378#if !defined(CONFIG_USER_ONLY)
12de9a39 6379 env->slb_nr = 32;
f2e63a42 6380#endif
e1833e1f 6381 init_excp_970(env);
d63001d1
JM		 6382 env->dcache_line_size = 128;
6383 env->icache_line_size = 128;
a750fc0b
JM		 6384 /* Allocate hardware IRQ controller */
6385 ppc970_irq_init(env);
cf8358c8
AJ		 6386 /* Can't find information on what this should be on reset. This
6387 * value is the one used by 74xx processors. */
6388 vscr_init(env, 0x00010000);
a750fc0b 6389}
a750fc0b
JM		 6390
6391/* PowerPC 970FX (aka G5) */
082c6681
JM		 6392#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6393 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6394 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6395 PPC_FLOAT_STFIWX | \
6396 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6397 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6398 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6399 PPC_64B | PPC_ALTIVEC | \
12de9a39 6400 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6401#define POWERPC_INSNS2_970FX (PPC_NONE)
a750fc0b 6402#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 6403#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 6404#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6405#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 6406#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 6407#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6408 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6409 POWERPC_FLAG_BUS_CLK)
a750fc0b 6410
2f462816
JM		 6411static int check_pow_970FX (CPUPPCState *env)
6412{
6413 if (env->spr[SPR_HID0] & 0x00600000)
6414 return 1;
6415
6416 return 0;
6417}
6418
a750fc0b
JM		 6419static void init_proc_970FX (CPUPPCState *env)
6420{
6421 gen_spr_ne_601(env);
6422 gen_spr_7xx(env);
6423 /* Time base */
6424 gen_tbl(env);
6425 /* Hardware implementation registers */
6426 /* XXX : not implemented */
6427 spr_register(env, SPR_HID0, "HID0",
6428 SPR_NOACCESS, SPR_NOACCESS,
06403421 6429 &spr_read_generic, &spr_write_clear,
d63001d1 6430 0x60000000);
a750fc0b
JM		 6431 /* XXX : not implemented */
6432 spr_register(env, SPR_HID1, "HID1",
6433 SPR_NOACCESS, SPR_NOACCESS,
6434 &spr_read_generic, &spr_write_generic,
6435 0x00000000);
6436 /* XXX : not implemented */
bd928eba 6437 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6438 SPR_NOACCESS, SPR_NOACCESS,
6439 &spr_read_generic, &spr_write_generic,
6440 0x00000000);
d63001d1
JM		 6441 /* XXX : not implemented */
6442 spr_register(env, SPR_970_HID5, "HID5",
6443 SPR_NOACCESS, SPR_NOACCESS,
6444 &spr_read_generic, &spr_write_generic,
417bf010 6445 POWERPC970_HID5_INIT);
bd928eba
JM		 6446 /* XXX : not implemented */
6447 spr_register(env, SPR_L2CR, "L2CR",
6448 SPR_NOACCESS, SPR_NOACCESS,
6449 &spr_read_generic, &spr_write_generic,
6450 0x00000000);
a750fc0b
JM		 6451 /* Memory management */
6452 /* XXX: not correct */
6453 gen_low_BATs(env);
12de9a39
JM		 6454 /* XXX : not implemented */
6455 spr_register(env, SPR_MMUCFG, "MMUCFG",
6456 SPR_NOACCESS, SPR_NOACCESS,
6457 &spr_read_generic, SPR_NOACCESS,
6458 0x00000000); /* TOFIX */
6459 /* XXX : not implemented */
6460 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6461 SPR_NOACCESS, SPR_NOACCESS,
6462 &spr_read_generic, &spr_write_generic,
6463 0x00000000); /* TOFIX */
6464 spr_register(env, SPR_HIOR, "SPR_HIOR",
6465 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6466 &spr_read_hior, &spr_write_hior,
6467 0x00000000);
4e98d8cf
BS		 6468 spr_register(env, SPR_CTRL, "SPR_CTRL",
6469 SPR_NOACCESS, SPR_NOACCESS,
6470 &spr_read_generic, &spr_write_generic,
6471 0x00000000);
6472 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6473 SPR_NOACCESS, SPR_NOACCESS,
6474 &spr_read_generic, &spr_write_generic,
6475 0x00000000);
6476 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6477 &spr_read_generic, &spr_write_generic,
6478 &spr_read_generic, &spr_write_generic,
6479 0x00000000);
f2e63a42 6480#if !defined(CONFIG_USER_ONLY)
8eee0af9 6481 env->slb_nr = 64;
f2e63a42 6482#endif
e1833e1f 6483 init_excp_970(env);
d63001d1
JM		 6484 env->dcache_line_size = 128;
6485 env->icache_line_size = 128;
a750fc0b
JM		 6486 /* Allocate hardware IRQ controller */
6487 ppc970_irq_init(env);
cf8358c8
AJ		 6488 /* Can't find information on what this should be on reset. This
6489 * value is the one used by 74xx processors. */
6490 vscr_init(env, 0x00010000);
a750fc0b 6491}
a750fc0b
JM		 6492
6493/* PowerPC 970 GX */
082c6681
JM		 6494#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6495 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6496 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6497 PPC_FLOAT_STFIWX | \
6498 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6499 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6500 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6501 PPC_64B | PPC_ALTIVEC | \
12de9a39 6502 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6503#define POWERPC_INSNS2_970GX (PPC_NONE)
a750fc0b 6504#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6505#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6506#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6507#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6508#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6509#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6510 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6511 POWERPC_FLAG_BUS_CLK)
a750fc0b 6512
2f462816
JM		 6513static int check_pow_970GX (CPUPPCState *env)
6514{
6515 if (env->spr[SPR_HID0] & 0x00600000)
6516 return 1;
6517
6518 return 0;
6519}
6520
a750fc0b
JM		 6521static void init_proc_970GX (CPUPPCState *env)
6522{
6523 gen_spr_ne_601(env);
6524 gen_spr_7xx(env);
6525 /* Time base */
6526 gen_tbl(env);
6527 /* Hardware implementation registers */
6528 /* XXX : not implemented */
6529 spr_register(env, SPR_HID0, "HID0",
6530 SPR_NOACCESS, SPR_NOACCESS,
06403421 6531 &spr_read_generic, &spr_write_clear,
d63001d1 6532 0x60000000);
a750fc0b
JM		 6533 /* XXX : not implemented */
6534 spr_register(env, SPR_HID1, "HID1",
6535 SPR_NOACCESS, SPR_NOACCESS,
6536 &spr_read_generic, &spr_write_generic,
6537 0x00000000);
6538 /* XXX : not implemented */
bd928eba 6539 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6540 SPR_NOACCESS, SPR_NOACCESS,
6541 &spr_read_generic, &spr_write_generic,
6542 0x00000000);
d63001d1
JM		 6543 /* XXX : not implemented */
6544 spr_register(env, SPR_970_HID5, "HID5",
6545 SPR_NOACCESS, SPR_NOACCESS,
6546 &spr_read_generic, &spr_write_generic,
417bf010 6547 POWERPC970_HID5_INIT);
bd928eba
JM		 6548 /* XXX : not implemented */
6549 spr_register(env, SPR_L2CR, "L2CR",
6550 SPR_NOACCESS, SPR_NOACCESS,
6551 &spr_read_generic, &spr_write_generic,
6552 0x00000000);
a750fc0b
JM		 6553 /* Memory management */
6554 /* XXX: not correct */
6555 gen_low_BATs(env);
12de9a39
JM		 6556 /* XXX : not implemented */
6557 spr_register(env, SPR_MMUCFG, "MMUCFG",
6558 SPR_NOACCESS, SPR_NOACCESS,
6559 &spr_read_generic, SPR_NOACCESS,
6560 0x00000000); /* TOFIX */
6561 /* XXX : not implemented */
6562 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6563 SPR_NOACCESS, SPR_NOACCESS,
6564 &spr_read_generic, &spr_write_generic,
6565 0x00000000); /* TOFIX */
6566 spr_register(env, SPR_HIOR, "SPR_HIOR",
6567 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6568 &spr_read_hior, &spr_write_hior,
6569 0x00000000);
f2e63a42 6570#if !defined(CONFIG_USER_ONLY)
12de9a39 6571 env->slb_nr = 32;
f2e63a42 6572#endif
e1833e1f 6573 init_excp_970(env);
d63001d1
JM		 6574 env->dcache_line_size = 128;
6575 env->icache_line_size = 128;
a750fc0b
JM		 6576 /* Allocate hardware IRQ controller */
6577 ppc970_irq_init(env);
cf8358c8
AJ		 6578 /* Can't find information on what this should be on reset. This
6579 * value is the one used by 74xx processors. */
6580 vscr_init(env, 0x00010000);
a750fc0b 6581}
a750fc0b 6582
2f462816 6583/* PowerPC 970 MP */
082c6681
JM		 6584#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6585 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6586 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6587 PPC_FLOAT_STFIWX | \
6588 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6589 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6590 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6591 PPC_64B | PPC_ALTIVEC | \
6592 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6593#define POWERPC_INSNS2_970MP (PPC_NONE)
2f462816
JM		 6594#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6595#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6596#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6597#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6598#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6599#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6600 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6601 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6602
6603static int check_pow_970MP (CPUPPCState *env)
6604{
6605 if (env->spr[SPR_HID0] & 0x01C00000)
6606 return 1;
6607
6608 return 0;
6609}
6610
6611static void init_proc_970MP (CPUPPCState *env)
6612{
6613 gen_spr_ne_601(env);
6614 gen_spr_7xx(env);
6615 /* Time base */
6616 gen_tbl(env);
6617 /* Hardware implementation registers */
6618 /* XXX : not implemented */
6619 spr_register(env, SPR_HID0, "HID0",
6620 SPR_NOACCESS, SPR_NOACCESS,
6621 &spr_read_generic, &spr_write_clear,
6622 0x60000000);
6623 /* XXX : not implemented */
6624 spr_register(env, SPR_HID1, "HID1",
6625 SPR_NOACCESS, SPR_NOACCESS,
6626 &spr_read_generic, &spr_write_generic,
6627 0x00000000);
6628 /* XXX : not implemented */
bd928eba 6629 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6630 SPR_NOACCESS, SPR_NOACCESS,
6631 &spr_read_generic, &spr_write_generic,
6632 0x00000000);
6633 /* XXX : not implemented */
6634 spr_register(env, SPR_970_HID5, "HID5",
6635 SPR_NOACCESS, SPR_NOACCESS,
6636 &spr_read_generic, &spr_write_generic,
6637 POWERPC970_HID5_INIT);
bd928eba
JM		 6638 /* XXX : not implemented */
6639 spr_register(env, SPR_L2CR, "L2CR",
6640 SPR_NOACCESS, SPR_NOACCESS,
6641 &spr_read_generic, &spr_write_generic,
6642 0x00000000);
2f462816
JM		 6643 /* Memory management */
6644 /* XXX: not correct */
6645 gen_low_BATs(env);
6646 /* XXX : not implemented */
6647 spr_register(env, SPR_MMUCFG, "MMUCFG",
6648 SPR_NOACCESS, SPR_NOACCESS,
6649 &spr_read_generic, SPR_NOACCESS,
6650 0x00000000); /* TOFIX */
6651 /* XXX : not implemented */
6652 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6653 SPR_NOACCESS, SPR_NOACCESS,
6654 &spr_read_generic, &spr_write_generic,
6655 0x00000000); /* TOFIX */
6656 spr_register(env, SPR_HIOR, "SPR_HIOR",
6657 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6658 &spr_read_hior, &spr_write_hior,
6659 0x00000000);
2f462816
JM		 6660#if !defined(CONFIG_USER_ONLY)
6661 env->slb_nr = 32;
6662#endif
6663 init_excp_970(env);
6664 env->dcache_line_size = 128;
6665 env->icache_line_size = 128;
6666 /* Allocate hardware IRQ controller */
6667 ppc970_irq_init(env);
cf8358c8
AJ		 6668 /* Can't find information on what this should be on reset. This
6669 * value is the one used by 74xx processors. */
6670 vscr_init(env, 0x00010000);
2f462816
JM		 6671}
6672
9d52e907
DG		 6673#if defined(TARGET_PPC64)
6674/* POWER7 */
6675#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6676 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6677 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6678 PPC_FLOAT_STFIWX | \
6679 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6680 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6681 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6682 PPC_64B | PPC_ALTIVEC | \
6683 PPC_SEGMENT_64B | PPC_SLBI | \
6684 PPC_POPCNTB | PPC_POPCNTWD)
cd6e9320 6685#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
9d52e907
DG		 6686#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6687#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6688#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6689#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6690#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6691#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6692 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
697ab892 6693 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
9d52e907
DG		 6694#define check_pow_POWER7 check_pow_nocheck
6695
6696static void init_proc_POWER7 (CPUPPCState *env)
6697{
6698 gen_spr_ne_601(env);
6699 gen_spr_7xx(env);
6700 /* Time base */
6701 gen_tbl(env);
2e06214f
NW		 6702 /* Processor identification */
6703 spr_register(env, SPR_PIR, "PIR",
6704 SPR_NOACCESS, SPR_NOACCESS,
6705 &spr_read_generic, &spr_write_pir,
6706 0x00000000);
9d52e907
DG		 6707#if !defined(CONFIG_USER_ONLY)
6708 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6709 spr_register(env, SPR_PURR, "PURR",
6710 &spr_read_purr, SPR_NOACCESS,
6711 &spr_read_purr, SPR_NOACCESS,
6712 0x00000000);
6713 spr_register(env, SPR_SPURR, "SPURR",
6714 &spr_read_purr, SPR_NOACCESS,
6715 &spr_read_purr, SPR_NOACCESS,
6716 0x00000000);
697ab892
DG		 6717 spr_register(env, SPR_CFAR, "SPR_CFAR",
6718 SPR_NOACCESS, SPR_NOACCESS,
6719 &spr_read_cfar, &spr_write_cfar,
6720 0x00000000);
6721 spr_register(env, SPR_DSCR, "SPR_DSCR",
6722 SPR_NOACCESS, SPR_NOACCESS,
6723 &spr_read_generic, &spr_write_generic,
6724 0x00000000);
9d52e907
DG		 6725#endif /* !CONFIG_USER_ONLY */
6726 /* Memory management */
6727 /* XXX : not implemented */
6728 spr_register(env, SPR_MMUCFG, "MMUCFG",
6729 SPR_NOACCESS, SPR_NOACCESS,
6730 &spr_read_generic, SPR_NOACCESS,
6731 0x00000000); /* TOFIX */
6732 /* XXX : not implemented */
6733 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6734 SPR_NOACCESS, SPR_NOACCESS,
6735 &spr_read_generic, &spr_write_generic,
6736 0x80800000);
6737 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6738 SPR_NOACCESS, SPR_NOACCESS,
6739 &spr_read_generic, &spr_write_generic,
6740 0x80800000);
6741 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6742 &spr_read_generic, &spr_write_generic,
6743 &spr_read_generic, &spr_write_generic,
6744 0x00000000);
6745#if !defined(CONFIG_USER_ONLY)
6746 env->slb_nr = 32;
6747#endif
6748 init_excp_POWER7(env);
6749 env->dcache_line_size = 128;
6750 env->icache_line_size = 128;
6751 /* Allocate hardware IRQ controller */
6752 ppcPOWER7_irq_init(env);
6753 /* Can't find information on what this should be on reset. This
6754 * value is the one used by 74xx processors. */
6755 vscr_init(env, 0x00010000);
6756}
6757#endif /* TARGET_PPC64 */
6758
a750fc0b 6759/* PowerPC 620 */
082c6681
JM		 6760#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6761 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6762 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6763 PPC_FLOAT_STFIWX | \
6764 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6765 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6766 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6767 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6768 PPC_64B | PPC_SLBI)
a5858d7a 6769#define POWERPC_INSNS2_620 (PPC_NONE)
add78955
JM		 6770#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6771//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6772#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6773#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6774#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6775#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6776 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6777#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6778
578bb252 6779__attribute__ (( unused ))
a750fc0b
JM		 6780static void init_proc_620 (CPUPPCState *env)
6781{
6782 gen_spr_ne_601(env);
6783 gen_spr_620(env);
6784 /* Time base */
6785 gen_tbl(env);
6786 /* Hardware implementation registers */
6787 /* XXX : not implemented */
6788 spr_register(env, SPR_HID0, "HID0",
6789 SPR_NOACCESS, SPR_NOACCESS,
6790 &spr_read_generic, &spr_write_generic,
6791 0x00000000);
6792 /* Memory management */
6793 gen_low_BATs(env);
e1833e1f 6794 init_excp_620(env);
d63001d1
JM		 6795 env->dcache_line_size = 64;
6796 env->icache_line_size = 64;
faadf50e
JM		 6797 /* Allocate hardware IRQ controller */
6798 ppc6xx_irq_init(env);
a750fc0b 6799}
a750fc0b
JM		 6800#endif /* defined (TARGET_PPC64) */
6801
6802/* Default 32 bits PowerPC target will be 604 */
6803#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6804#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
a5858d7a 6805#define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
a750fc0b
JM		 6806#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6807#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6808#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6809#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6810#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6811#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6812#define check_pow_PPC32 check_pow_604
6813#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6814
6815/* Default 64 bits PowerPC target will be 970 FX */
6816#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6817#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
a5858d7a 6818#define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
a750fc0b
JM		 6819#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6820#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6821#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6822#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6823#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6824#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6825#define check_pow_PPC64 check_pow_970FX
6826#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6827
6828/* Default PowerPC target will be PowerPC 32 */
6829#if defined (TARGET_PPC64) && 0 // XXX: TODO
a5858d7a
AG		 6830#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6831#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6bbc5ed1 6832#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC64
a5858d7a
AG		 6833#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6834#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6835#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6836#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6837#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6838#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6839#define check_pow_DEFAULT check_pow_PPC64
6840#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6841#else
a5858d7a
AG		 6842#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6843#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6bbc5ed1 6844#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC32
a5858d7a
AG		 6845#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6846#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6847#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6848#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6849#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6850#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6851#define check_pow_DEFAULT check_pow_PPC32
6852#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6853#endif
6854
6855/*****************************************************************************/
6856/* PVR definitions for most known PowerPC */
6857enum {
6858 /* PowerPC 401 family */
6859 /* Generic PowerPC 401 */
80d11f44 6860#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6861 /* PowerPC 401 cores */
80d11f44
JM		 6862 CPU_POWERPC_401A1 = 0x00210000,
6863 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6864#if 0
80d11f44 6865 CPU_POWERPC_401B3 = xxx,
a750fc0b 6866#endif
80d11f44
JM		 6867 CPU_POWERPC_401C2 = 0x00230000,
6868 CPU_POWERPC_401D2 = 0x00240000,
6869 CPU_POWERPC_401E2 = 0x00250000,
6870 CPU_POWERPC_401F2 = 0x00260000,
6871 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6872 /* PowerPC 401 microcontrolers */
6873#if 0
80d11f44 6874 CPU_POWERPC_401GF = xxx,
a750fc0b 6875#endif
80d11f44 6876#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6877 /* IBM Processor for Network Resources */
80d11f44 6878 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6879#if 0
80d11f44 6880 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6881#endif
6882 /* PowerPC 403 family */
6883 /* Generic PowerPC 403 */
80d11f44 6884#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6885 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6886 CPU_POWERPC_403GA = 0x00200011,
6887 CPU_POWERPC_403GB = 0x00200100,
6888 CPU_POWERPC_403GC = 0x00200200,
6889 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6890#if 0
80d11f44 6891 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6892#endif
6893 /* PowerPC 405 family */
6894 /* Generic PowerPC 405 */
80d11f44 6895#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6896 /* PowerPC 405 cores */
6897#if 0
80d11f44 6898 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6899#endif
6900#if 0
80d11f44 6901 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6902#endif
6903#if 0
80d11f44 6904 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6905#endif
6906#if 0
80d11f44 6907 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6908#endif
6909#if 0
80d11f44 6910 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6911#endif
6912#if 0
80d11f44 6913 CPU_POWERPC_405C4 = xxx,
a750fc0b 6914#endif
80d11f44 6915 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6916#if 0
80d11f44 6917 CPU_POWERPC_405D3 = xxx,
a750fc0b 6918#endif
80d11f44 6919 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6920#if 0
80d11f44 6921 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6922#endif
6923#if 0
80d11f44 6924 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6925#endif
6926#if 0
80d11f44 6927 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6928#endif
6929#if 0
80d11f44 6930 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6931#endif
6932#if 0
80d11f44 6933 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6934#endif
6935 /* PowerPC 405 microcontrolers */
6936 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6937#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6938 CPU_POWERPC_405CRa = 0x40110041,
6939 CPU_POWERPC_405CRb = 0x401100C5,
6940 CPU_POWERPC_405CRc = 0x40110145,
6941 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6942#if 0
80d11f44 6943 CPU_POWERPC_405EXr = xxx,
a750fc0b 6944#endif
80d11f44 6945 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6946#if 0
80d11f44
JM		 6947 CPU_POWERPC_405FX = xxx,
6948#endif
6949#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6950 CPU_POWERPC_405GPa = 0x40110000,
6951 CPU_POWERPC_405GPb = 0x40110040,
6952 CPU_POWERPC_405GPc = 0x40110082,
6953 CPU_POWERPC_405GPd = 0x401100C4,
6954#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6955 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6956#if 0
80d11f44 6957 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6958#endif
6959#if 0
80d11f44 6960 CPU_POWERPC_405L = xxx,
a750fc0b 6961#endif
80d11f44 6962 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6963#if 0
80d11f44 6964 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6965#endif
6966#if 0
80d11f44 6967 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6968#endif
6969#if 0
80d11f44 6970 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6971#endif
6972 /* IBM network processors */
80d11f44
JM		 6973 CPU_POWERPC_NPE405H = 0x414100C0,
6974 CPU_POWERPC_NPE405H2 = 0x41410140,
6975 CPU_POWERPC_NPE405L = 0x416100C0,
6976 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6977#if 0
80d11f44 6978 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6979#endif
6980#if 0
80d11f44 6981 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6982#endif
6983#if 0
80d11f44 6984 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6985#endif
6986 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6987#if 0
80d11f44 6988 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6989#endif
6990#if 0
80d11f44 6991 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6992#endif
6993#if 0
80d11f44 6994 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6995#endif
80d11f44 6996 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6997#if 0
80d11f44 6998 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6999#endif
7000#if 0
80d11f44 7001 CPU_POWERPC_STB045 = xxx,
a750fc0b 7002#endif
80d11f44
JM		 7003 CPU_POWERPC_STB04 = 0x41810000,
7004 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 7005#if 0
80d11f44 7006 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 7007#endif
7008 /* Xilinx cores */
80d11f44
JM		 7009 CPU_POWERPC_X2VP4 = 0x20010820,
7010#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
7011 CPU_POWERPC_X2VP20 = 0x20010860,
7012#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 7013#if 0
80d11f44 7014 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 7015#endif
7016#if 0
80d11f44 7017 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 7018#endif
7019#if 0
80d11f44 7020 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 7021#endif
7022#if 0
80d11f44 7023 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 7024#endif
7025 /* PowerPC 440 family */
7026 /* Generic PowerPC 440 */
80d11f44 7027#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 7028 /* PowerPC 440 cores */
7029#if 0
80d11f44 7030 CPU_POWERPC_440A4 = xxx,
a750fc0b 7031#endif
95070372 7032 CPU_POWERPC_440_XILINX = 0x7ff21910,
a750fc0b 7033#if 0
80d11f44 7034 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 7035#endif
7036#if 0
80d11f44 7037 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 7038#endif
7039#if 0
80d11f44 7040 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 7041#endif
7042#if 0
80d11f44 7043 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 7044#endif
7045#if 0
80d11f44 7046 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 7047#endif
7048#if 0
80d11f44 7049 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 7050#endif
7051 /* PowerPC 440 microcontrolers */
80d11f44
JM		 7052#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
7053 CPU_POWERPC_440EPa = 0x42221850,
7054 CPU_POWERPC_440EPb = 0x422218D3,
7055#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
7056 CPU_POWERPC_440GPb = 0x40120440,
7057 CPU_POWERPC_440GPc = 0x40120481,
7058#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
7059#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
7060 CPU_POWERPC_440GRX = 0x200008D0,
7061#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
7062#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
7063 CPU_POWERPC_440GXa = 0x51B21850,
7064 CPU_POWERPC_440GXb = 0x51B21851,
7065 CPU_POWERPC_440GXc = 0x51B21892,
7066 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 7067#if 0
80d11f44 7068 CPU_POWERPC_440S = xxx,
a750fc0b 7069#endif
80d11f44
JM		 7070 CPU_POWERPC_440SP = 0x53221850,
7071 CPU_POWERPC_440SP2 = 0x53221891,
7072 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 7073 /* PowerPC 460 family */
7074#if 0
7075 /* Generic PowerPC 464 */
80d11f44 7076#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 7077#endif
7078 /* PowerPC 464 microcontrolers */
7079#if 0
80d11f44 7080 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 7081#endif
7082#if 0
80d11f44 7083 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 7084#endif
7085 /* Freescale embedded PowerPC cores */
c3e36823 7086 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 7087 CPU_POWERPC_MPC5xx = 0x00020020,
7088#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
7089#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
7090#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
7091#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
7092#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
7093#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
7094#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
7095#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
7096#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
7097#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
7098#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
7099#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
7100#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 7101 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 7102 CPU_POWERPC_MPC8xx = 0x00500000,
7103#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
7104#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
7105#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
7106#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
7107#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
7108#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
7109#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
7110#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
7111#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
7112#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
7113#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
7114#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
7115#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
7116#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
7117#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 7118 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 7119 CPU_POWERPC_G2 = 0x00810011,
7120 CPU_POWERPC_G2H4 = 0x80811010,
7121 CPU_POWERPC_G2gp = 0x80821010,
7122 CPU_POWERPC_G2ls = 0x90810010,
7123 CPU_POWERPC_MPC603 = 0x00810100,
7124 CPU_POWERPC_G2_HIP3 = 0x00810101,
7125 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 7126 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 7127 CPU_POWERPC_G2LE = 0x80820010,
7128 CPU_POWERPC_G2LEgp = 0x80822010,
7129 CPU_POWERPC_G2LEls = 0xA0822010,
7130 CPU_POWERPC_G2LEgp1 = 0x80822011,
7131 CPU_POWERPC_G2LEgp3 = 0x80822013,
7132 /* MPC52xx microcontrollers */
c3e36823 7133 /* XXX: MPC 5121 ? */
80d11f44
JM		 7134#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7135#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7136#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7137#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7138#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7139#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7140#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7141#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7142 /* MPC82xx microcontrollers */
7143#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7144#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7145#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7146#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7147#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7148#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7149#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7150#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7151#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7152#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7153#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7154#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7155#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7156#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7157#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7158#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7159#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7160#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7161#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7162#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7163#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7164#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7165#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7166#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7167#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7168#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7169#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7170#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7171#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 7172 /* e200 family */
80d11f44
JM		 7173 /* e200 cores */
7174#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 7175#if 0
80d11f44 7176 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 7177#endif
7178#if 0
80d11f44 7179 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 7180#endif
7181#if 0 /* ? */
80d11f44
JM		 7182 CPU_POWERPC_e200z3 = 0x81120000,
7183#endif
7184 CPU_POWERPC_e200z5 = 0x81000000,
7185 CPU_POWERPC_e200z6 = 0x81120000,
7186 /* MPC55xx microcontrollers */
7187#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7188#if 0
7189#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7190#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7191#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7192#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7193#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7194#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7195#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7196#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7197#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7198#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7199#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7200#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7201#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7202#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7203#endif
7204#if 0
7205#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7206#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7207#endif
7208#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7209#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7210#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7211#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7212#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7213#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 7214 /* e300 family */
80d11f44
JM		 7215 /* e300 cores */
7216#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7217 CPU_POWERPC_e300c1 = 0x00830010,
7218 CPU_POWERPC_e300c2 = 0x00840010,
7219 CPU_POWERPC_e300c3 = 0x00850010,
7220 CPU_POWERPC_e300c4 = 0x00860010,
7221 /* MPC83xx microcontrollers */
74d77cae
TM		 7222#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7223#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7224#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7225#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7226#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7227#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
a750fc0b 7228 /* e500 family */
80d11f44
JM		 7229 /* e500 cores */
7230#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513 7231#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
80d11f44 7232#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 7233 CPU_POWERPC_e500v1_v10 = 0x80200010,
7234 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 7235 CPU_POWERPC_e500v2_v10 = 0x80210010,
7236 CPU_POWERPC_e500v2_v11 = 0x80210011,
7237 CPU_POWERPC_e500v2_v20 = 0x80210020,
7238 CPU_POWERPC_e500v2_v21 = 0x80210021,
7239 CPU_POWERPC_e500v2_v22 = 0x80210022,
7240 CPU_POWERPC_e500v2_v30 = 0x80210030,
f7aa5583 7241 CPU_POWERPC_e500mc = 0x80230020,
b81ccf8a 7242 CPU_POWERPC_e5500 = 0x80240020,
80d11f44
JM		 7243 /* MPC85xx microcontrollers */
7244#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7245#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7246#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7247#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7248#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7249#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7250#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
bd5ea513
AJ		 7251#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7252#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7253#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
80d11f44 7254#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
bd5ea513
AJ		 7255#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7256#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
80d11f44 7257#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
bd5ea513
AJ		 7258#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7259#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 7260#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7261#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7262#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7263#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7264#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7265#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7266#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7267#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7268#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7269#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7270#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7271#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7272#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7273#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7274#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7275#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7276#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7277#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7278#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7279#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7280#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7281#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7282#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7283#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7284#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7285#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7286#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7287#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7288#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7289#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7290#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7291#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7292#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7293#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7294#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7295#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7296#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7297#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7298#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7299#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7300#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7301#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7302#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7303#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7304#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7305#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7306#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7307#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7308#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7309#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7310#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7311#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7312#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7313#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 7314 /* e600 family */
80d11f44
JM		 7315 /* e600 cores */
7316 CPU_POWERPC_e600 = 0x80040010,
7317 /* MPC86xx microcontrollers */
7318#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7319#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7320#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 7321 /* PowerPC 6xx cores */
80d11f44
JM		 7322#define CPU_POWERPC_601 CPU_POWERPC_601_v2
7323 CPU_POWERPC_601_v0 = 0x00010001,
7324 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 7325#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 7326 CPU_POWERPC_601_v2 = 0x00010002,
7327 CPU_POWERPC_602 = 0x00050100,
7328 CPU_POWERPC_603 = 0x00030100,
7329#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7330 CPU_POWERPC_603E_v11 = 0x00060101,
7331 CPU_POWERPC_603E_v12 = 0x00060102,
7332 CPU_POWERPC_603E_v13 = 0x00060103,
7333 CPU_POWERPC_603E_v14 = 0x00060104,
7334 CPU_POWERPC_603E_v22 = 0x00060202,
7335 CPU_POWERPC_603E_v3 = 0x00060300,
7336 CPU_POWERPC_603E_v4 = 0x00060400,
7337 CPU_POWERPC_603E_v41 = 0x00060401,
7338 CPU_POWERPC_603E7t = 0x00071201,
7339 CPU_POWERPC_603E7v = 0x00070100,
7340 CPU_POWERPC_603E7v1 = 0x00070101,
7341 CPU_POWERPC_603E7v2 = 0x00070201,
7342 CPU_POWERPC_603E7 = 0x00070200,
7343 CPU_POWERPC_603P = 0x00070000,
7344#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 7345 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 7346 CPU_POWERPC_604 = 0x00040103,
7347#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 7348 /* XXX: missing 0x00091203 */
7349 /* XXX: missing 0x00092110 */
7350 /* XXX: missing 0x00092120 */
80d11f44
JM		 7351 CPU_POWERPC_604E_v10 = 0x00090100,
7352 CPU_POWERPC_604E_v22 = 0x00090202,
7353 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 7354 /* XXX: missing 0x000a0100 */
7355 /* XXX: missing 0x00093102 */
80d11f44 7356 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 7357#if 0
80d11f44 7358 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 7359#endif
7360 /* PowerPC 740/750 cores (aka G3) */
7361 /* XXX: missing 0x00084202 */
80d11f44 7362#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 7363 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 7364 CPU_POWERPC_7x0_v20 = 0x00080200,
7365 CPU_POWERPC_7x0_v21 = 0x00080201,
7366 CPU_POWERPC_7x0_v22 = 0x00080202,
7367 CPU_POWERPC_7x0_v30 = 0x00080300,
7368 CPU_POWERPC_7x0_v31 = 0x00080301,
7369 CPU_POWERPC_740E = 0x00080100,
bd928eba 7370 CPU_POWERPC_750E = 0x00080200,
80d11f44 7371 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 7372 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 7373#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7374 CPU_POWERPC_750CL_v10 = 0x00087200,
7375 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 7376#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 7377 CPU_POWERPC_750CX_v10 = 0x00082100,
7378 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 7379 CPU_POWERPC_750CX_v21 = 0x00082201,
7380 CPU_POWERPC_750CX_v22 = 0x00082202,
7381#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7382 CPU_POWERPC_750CXE_v21 = 0x00082211,
7383 CPU_POWERPC_750CXE_v22 = 0x00082212,
7384 CPU_POWERPC_750CXE_v23 = 0x00082213,
7385 CPU_POWERPC_750CXE_v24 = 0x00082214,
7386 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 7387 CPU_POWERPC_750CXE_v30 = 0x00082310,
7388 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 7389 CPU_POWERPC_750CXE_v31b = 0x00083311,
7390 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 7391 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 7392#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7393 CPU_POWERPC_750FX_v10 = 0x70000100,
7394 CPU_POWERPC_750FX_v20 = 0x70000200,
7395 CPU_POWERPC_750FX_v21 = 0x70000201,
7396 CPU_POWERPC_750FX_v22 = 0x70000202,
7397 CPU_POWERPC_750FX_v23 = 0x70000203,
7398 CPU_POWERPC_750GL = 0x70020102,
7399#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7400 CPU_POWERPC_750GX_v10 = 0x70020100,
7401 CPU_POWERPC_750GX_v11 = 0x70020101,
7402 CPU_POWERPC_750GX_v12 = 0x70020102,
7403#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 7404 CPU_POWERPC_750L_v20 = 0x00088200,
7405 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 7406 CPU_POWERPC_750L_v22 = 0x00088202,
7407 CPU_POWERPC_750L_v30 = 0x00088300,
7408 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 7409 /* PowerPC 745/755 cores */
80d11f44
JM		 7410#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7411 CPU_POWERPC_7x5_v10 = 0x00083100,
7412 CPU_POWERPC_7x5_v11 = 0x00083101,
7413 CPU_POWERPC_7x5_v20 = 0x00083200,
7414 CPU_POWERPC_7x5_v21 = 0x00083201,
7415 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7416 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7417 CPU_POWERPC_7x5_v24 = 0x00083204,
7418 CPU_POWERPC_7x5_v25 = 0x00083205,
7419 CPU_POWERPC_7x5_v26 = 0x00083206,
7420 CPU_POWERPC_7x5_v27 = 0x00083207,
7421 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 7422#if 0
80d11f44 7423 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 7424#endif
7425 /* PowerPC 74xx cores (aka G4) */
7426 /* XXX: missing 0x000C1101 */
80d11f44
JM		 7427#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7428 CPU_POWERPC_7400_v10 = 0x000C0100,
7429 CPU_POWERPC_7400_v11 = 0x000C0101,
7430 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 7431 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 7432 CPU_POWERPC_7400_v22 = 0x000C0202,
7433 CPU_POWERPC_7400_v26 = 0x000C0206,
7434 CPU_POWERPC_7400_v27 = 0x000C0207,
7435 CPU_POWERPC_7400_v28 = 0x000C0208,
7436 CPU_POWERPC_7400_v29 = 0x000C0209,
7437#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7438 CPU_POWERPC_7410_v10 = 0x800C1100,
7439 CPU_POWERPC_7410_v11 = 0x800C1101,
7440 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7441 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7442 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7443#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7444 CPU_POWERPC_7448_v10 = 0x80040100,
7445 CPU_POWERPC_7448_v11 = 0x80040101,
7446 CPU_POWERPC_7448_v20 = 0x80040200,
7447 CPU_POWERPC_7448_v21 = 0x80040201,
7448#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7449 CPU_POWERPC_7450_v10 = 0x80000100,
7450 CPU_POWERPC_7450_v11 = 0x80000101,
7451 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 7452 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 7453 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 7454#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7455 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7456 /* XXX: this entry might be a bug in some documentation */
7457 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 7458#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7459 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 7460 /* XXX: missing 0x80010200 */
80d11f44
JM		 7461 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7462 CPU_POWERPC_74x5_v32 = 0x80010302,
7463 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7464 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7465#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 7466 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 7467 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 7468 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 7469#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7470 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7471 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7472 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 7473 /* 64 bits PowerPC */
00af685f 7474#if defined(TARGET_PPC64)
80d11f44
JM		 7475 CPU_POWERPC_620 = 0x00140000,
7476 CPU_POWERPC_630 = 0x00400000,
7477 CPU_POWERPC_631 = 0x00410104,
7478 CPU_POWERPC_POWER4 = 0x00350000,
7479 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 7480 /* XXX: missing 0x003A0201 */
80d11f44
JM		 7481 CPU_POWERPC_POWER5 = 0x003A0203,
7482#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7483 CPU_POWERPC_POWER5P = 0x003B0000,
7484#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7485 CPU_POWERPC_POWER6 = 0x003E0000,
7486 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7487 CPU_POWERPC_POWER6A = 0x0F000002,
9d52e907
DG		 7488#define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7489 CPU_POWERPC_POWER7_v20 = 0x003F0200,
37e305ce
DG		 7490 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7491 CPU_POWERPC_POWER7_v23 = 0x003F0203,
80d11f44
JM		 7492 CPU_POWERPC_970 = 0x00390202,
7493#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7494 CPU_POWERPC_970FX_v10 = 0x00391100,
7495 CPU_POWERPC_970FX_v20 = 0x003C0200,
7496 CPU_POWERPC_970FX_v21 = 0x003C0201,
7497 CPU_POWERPC_970FX_v30 = 0x003C0300,
7498 CPU_POWERPC_970FX_v31 = 0x003C0301,
7499 CPU_POWERPC_970GX = 0x00450000,
7500#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7501 CPU_POWERPC_970MP_v10 = 0x00440100,
7502 CPU_POWERPC_970MP_v11 = 0x00440101,
7503#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7504 CPU_POWERPC_CELL_v10 = 0x00700100,
7505 CPU_POWERPC_CELL_v20 = 0x00700400,
7506 CPU_POWERPC_CELL_v30 = 0x00700500,
7507 CPU_POWERPC_CELL_v31 = 0x00700501,
7508#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7509 CPU_POWERPC_RS64 = 0x00330000,
7510 CPU_POWERPC_RS64II = 0x00340000,
7511 CPU_POWERPC_RS64III = 0x00360000,
7512 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 7513#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 7514 /* Original POWER */
7515 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7516 * POWER2 (RIOS2) & RSC2 (P2SC) here
7517 */
7518#if 0
80d11f44 7519 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 7520#endif
7521#if 0
80d11f44 7522 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7523#endif
7524 /* PA Semi core */
80d11f44 7525 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7526};
7527
7528/* System version register (used on MPC 8xxx) */
7529enum {
80d11f44
JM		 7530 POWERPC_SVR_NONE = 0x00000000,
7531#define POWERPC_SVR_52xx POWERPC_SVR_5200
7532#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7533 POWERPC_SVR_5200_v10 = 0x80110010,
7534 POWERPC_SVR_5200_v11 = 0x80110011,
7535 POWERPC_SVR_5200_v12 = 0x80110012,
7536#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7537 POWERPC_SVR_5200B_v20 = 0x80110020,
7538 POWERPC_SVR_5200B_v21 = 0x80110021,
7539#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7540#if 0
80d11f44 7541 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7542#endif
7543#if 0
80d11f44 7544 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7545#endif
7546#if 0
80d11f44 7547 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7548#endif
7549#if 0
80d11f44 7550 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7551#endif
7552#if 0
80d11f44 7553 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7554#endif
7555#if 0
80d11f44 7556 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7557#endif
7558#if 0
80d11f44 7559 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7560#endif
7561#if 0
80d11f44 7562 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7563#endif
7564#if 0
80d11f44 7565 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7566#endif
7567#if 0
80d11f44 7568 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7569#endif
7570#if 0
80d11f44 7571 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7572#endif
7573#if 0
80d11f44 7574 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7575#endif
7576#if 0
80d11f44 7577 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7578#endif
7579#if 0
80d11f44 7580 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7581#endif
7582#if 0
80d11f44 7583 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7584#endif
7585#if 0
80d11f44 7586 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7587#endif
7588#if 0
80d11f44 7589 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7590#endif
7591#if 0
80d11f44
JM		 7592 POWERPC_SVR_8323E = xxx,
7593#endif
492d7bf5 7594 POWERPC_SVR_8343 = 0x80570010,
80d11f44 7595 POWERPC_SVR_8343A = 0x80570030,
492d7bf5 7596 POWERPC_SVR_8343E = 0x80560010,
80d11f44 7597 POWERPC_SVR_8343EA = 0x80560030,
492d7bf5
TM		 7598#define POWERPC_SVR_8347 POWERPC_SVR_8347T
7599 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7600 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
80d11f44
JM		 7601#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7602 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7603 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
492d7bf5
TM		 7604#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7605 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7606 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
80d11f44
JM		 7607#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7608 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7609 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7610 POWERPC_SVR_8349 = 0x80510010,
7611 POWERPC_SVR_8349A = 0x80510030,
7612 POWERPC_SVR_8349E = 0x80500010,
7613 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7614#if 0
80d11f44 7615 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7616#endif
7617#if 0
80d11f44
JM		 7618 POWERPC_SVR_8360E = xxx,
7619#endif
7620#define POWERPC_SVR_E500 0x40000000
7621 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7622 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7623 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7624 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7625 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7626 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7627#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7628 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7629 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7630#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7631 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7632 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7633#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7634 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7635 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7636 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7637#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7638 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7639 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7640#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7641 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7642 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7643#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7644 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7645 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7646 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7647 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7648#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7649 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7650 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7651 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7652 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7653#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7654 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7655 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7656#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7657 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7658 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7659#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7660 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7661 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7662#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7663 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7664 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7665#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7666 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7667 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7668#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7669 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7670 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7671 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7672 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7673#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7674 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7675 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7676 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7677 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7678#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7679 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7680 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7681#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7682 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7683 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7684#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7685 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7686 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7687 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7688 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7689 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7690 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7691 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7692 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7693 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7694#if 0
80d11f44 7695 POWERPC_SVR_8610 = xxx,
c3e36823 7696#endif
80d11f44
JM		 7697 POWERPC_SVR_8641 = 0x80900021,
7698 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7699};
7700
3fc6c082 7701/*****************************************************************************/
a750fc0b 7702/* PowerPC CPU definitions */
80d11f44 7703#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b 7704 { \
a5858d7a
AG		 7705 .name = _name, \
7706 .pvr = _pvr, \
7707 .svr = _svr, \
7708 .insns_flags = glue(POWERPC_INSNS_,_type), \
7709 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7710 .msr_mask = glue(POWERPC_MSRM_,_type), \
7711 .mmu_model = glue(POWERPC_MMU_,_type), \
7712 .excp_model = glue(POWERPC_EXCP_,_type), \
7713 .bus_model = glue(POWERPC_INPUT_,_type), \
7714 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7715 .flags = glue(POWERPC_FLAG_,_type), \
7716 .init_proc = &glue(init_proc_,_type), \
7717 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7718 }
80d11f44
JM		 7719#define POWERPC_DEF(_name, _pvr, _type) \
7720POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7721
c227f099 7722static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7723 /* Embedded PowerPC */
7724 /* PowerPC 401 family */
2662a059 7725 /* Generic PowerPC 401 */
80d11f44 7726 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7727 /* PowerPC 401 cores */
2662a059 7728 /* PowerPC 401A1 */
80d11f44 7729 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7730 /* PowerPC 401B2 */
80d11f44 7731 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7732#if defined (TODO)
a750fc0b 7733 /* PowerPC 401B3 */
80d11f44 7734 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7735#endif
7736 /* PowerPC 401C2 */
80d11f44 7737 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7738 /* PowerPC 401D2 */
80d11f44 7739 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7740 /* PowerPC 401E2 */
80d11f44 7741 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7742 /* PowerPC 401F2 */
80d11f44 7743 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7744 /* PowerPC 401G2 */
7745 /* XXX: to be checked */
80d11f44 7746 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7747 /* PowerPC 401 microcontrolers */
2662a059 7748#if defined (TODO)
a750fc0b 7749 /* PowerPC 401GF */
80d11f44 7750 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7751#endif
a750fc0b 7752 /* IOP480 (401 microcontroler) */
80d11f44 7753 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7754 /* IBM Processor for Network Resources */
80d11f44 7755 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7756#if defined (TODO)
80d11f44 7757 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7758#endif
a750fc0b
JM		 7759 /* PowerPC 403 family */
7760 /* Generic PowerPC 403 */
80d11f44 7761 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7762 /* PowerPC 403 microcontrolers */
7763 /* PowerPC 403 GA */
80d11f44 7764 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7765 /* PowerPC 403 GB */
80d11f44 7766 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7767 /* PowerPC 403 GC */
80d11f44 7768 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7769 /* PowerPC 403 GCX */
80d11f44 7770 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7771#if defined (TODO)
a750fc0b 7772 /* PowerPC 403 GP */
80d11f44 7773 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7774#endif
a750fc0b
JM		 7775 /* PowerPC 405 family */
7776 /* Generic PowerPC 405 */
80d11f44 7777 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7778 /* PowerPC 405 cores */
2662a059 7779#if defined (TODO)
a750fc0b 7780 /* PowerPC 405 A3 */
80d11f44 7781 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7782#endif
3a607854 7783#if defined (TODO)
a750fc0b 7784 /* PowerPC 405 A4 */
80d11f44 7785 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7786#endif
3a607854 7787#if defined (TODO)
a750fc0b 7788 /* PowerPC 405 B3 */
80d11f44 7789 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7790#endif
7791#if defined (TODO)
a750fc0b 7792 /* PowerPC 405 B4 */
80d11f44 7793 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7794#endif
7795#if defined (TODO)
7796 /* PowerPC 405 C3 */
80d11f44 7797 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7798#endif
7799#if defined (TODO)
7800 /* PowerPC 405 C4 */
80d11f44 7801 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7802#endif
7803 /* PowerPC 405 D2 */
80d11f44 7804 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7805#if defined (TODO)
7806 /* PowerPC 405 D3 */
80d11f44 7807 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7808#endif
7809 /* PowerPC 405 D4 */
80d11f44 7810 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7811#if defined (TODO)
7812 /* PowerPC 405 D5 */
80d11f44 7813 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7814#endif
7815#if defined (TODO)
7816 /* PowerPC 405 E4 */
80d11f44 7817 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7818#endif
7819#if defined (TODO)
7820 /* PowerPC 405 F4 */
80d11f44 7821 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7822#endif
7823#if defined (TODO)
7824 /* PowerPC 405 F5 */
80d11f44 7825 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7826#endif
7827#if defined (TODO)
7828 /* PowerPC 405 F6 */
80d11f44 7829 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7830#endif
7831 /* PowerPC 405 microcontrolers */
7832 /* PowerPC 405 CR */
80d11f44 7833 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7834 /* PowerPC 405 CRa */
80d11f44 7835 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7836 /* PowerPC 405 CRb */
80d11f44 7837 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7838 /* PowerPC 405 CRc */
80d11f44 7839 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7840 /* PowerPC 405 EP */
80d11f44 7841 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7842#if defined(TODO)
7843 /* PowerPC 405 EXr */
80d11f44 7844 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7845#endif
7846 /* PowerPC 405 EZ */
80d11f44 7847 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7848#if defined(TODO)
7849 /* PowerPC 405 FX */
80d11f44 7850 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7851#endif
7852 /* PowerPC 405 GP */
80d11f44 7853 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7854 /* PowerPC 405 GPa */
80d11f44 7855 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7856 /* PowerPC 405 GPb */
80d11f44 7857 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7858 /* PowerPC 405 GPc */
80d11f44 7859 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7860 /* PowerPC 405 GPd */
80d11f44 7861 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7862 /* PowerPC 405 GPe */
80d11f44 7863 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7864 /* PowerPC 405 GPR */
80d11f44 7865 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7866#if defined(TODO)
7867 /* PowerPC 405 H */
80d11f44 7868 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7869#endif
7870#if defined(TODO)
7871 /* PowerPC 405 L */
80d11f44 7872 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7873#endif
7874 /* PowerPC 405 LP */
80d11f44 7875 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7876#if defined(TODO)
7877 /* PowerPC 405 PM */
80d11f44 7878 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7879#endif
7880#if defined(TODO)
7881 /* PowerPC 405 PS */
80d11f44 7882 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7883#endif
7884#if defined(TODO)
7885 /* PowerPC 405 S */
80d11f44 7886 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7887#endif
7888 /* Npe405 H */
80d11f44 7889 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7890 /* Npe405 H2 */
80d11f44 7891 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7892 /* Npe405 L */
80d11f44 7893 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7894 /* Npe4GS3 */
80d11f44 7895 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7896#if defined (TODO)
80d11f44 7897 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7898#endif
7899#if defined (TODO)
80d11f44 7900 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7901#endif
7902#if defined (TODO)
7903 /* PowerPC LC77700 (Sanyo) */
80d11f44 7904 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7905#endif
7906 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7907#if defined (TODO)
7908 /* STB010000 */
80d11f44 7909 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7910#endif
7911#if defined (TODO)
7912 /* STB01010 */
80d11f44 7913 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7914#endif
7915#if defined (TODO)
7916 /* STB0210 */
80d11f44 7917 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7918#endif
7919 /* STB03xx */
80d11f44 7920 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7921#if defined (TODO)
7922 /* STB043x */
80d11f44 7923 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7924#endif
7925#if defined (TODO)
7926 /* STB045x */
80d11f44 7927 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7928#endif
7929 /* STB04xx */
80d11f44 7930 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7931 /* STB25xx */
80d11f44 7932 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7933#if defined (TODO)
7934 /* STB130 */
80d11f44 7935 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7936#endif
7937 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7938 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7939 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7940 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7941 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7942#if defined (TODO)
7943 /* Zarlink ZL10310 */
80d11f44 7944 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7945#endif
7946#if defined (TODO)
7947 /* Zarlink ZL10311 */
80d11f44 7948 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7949#endif
7950#if defined (TODO)
7951 /* Zarlink ZL10320 */
80d11f44 7952 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7953#endif
7954#if defined (TODO)
7955 /* Zarlink ZL10321 */
80d11f44 7956 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7957#endif
7958 /* PowerPC 440 family */
80d11f44 7959#if defined(TODO_USER_ONLY)
a750fc0b 7960 /* Generic PowerPC 440 */
80d11f44
JM		 7961 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7962#endif
a750fc0b
JM		 7963 /* PowerPC 440 cores */
7964#if defined (TODO)
7965 /* PowerPC 440 A4 */
80d11f44 7966 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b 7967#endif
95070372
EI		 7968 /* PowerPC 440 Xilinx 5 */
7969 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
a750fc0b
JM		 7970#if defined (TODO)
7971 /* PowerPC 440 A5 */
80d11f44 7972 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7973#endif
7974#if defined (TODO)
7975 /* PowerPC 440 B4 */
80d11f44 7976 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7977#endif
7978#if defined (TODO)
7979 /* PowerPC 440 G4 */
80d11f44 7980 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7981#endif
7982#if defined (TODO)
7983 /* PowerPC 440 F5 */
80d11f44 7984 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7985#endif
7986#if defined (TODO)
7987 /* PowerPC 440 G5 */
80d11f44 7988 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7989#endif
7990#if defined (TODO)
7991 /* PowerPC 440H4 */
80d11f44 7992 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7993#endif
7994#if defined (TODO)
7995 /* PowerPC 440H6 */
80d11f44 7996 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7997#endif
7998 /* PowerPC 440 microcontrolers */
7999 /* PowerPC 440 EP */
80d11f44 8000 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
a750fc0b 8001 /* PowerPC 440 EPa */
80d11f44 8002 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
a750fc0b 8003 /* PowerPC 440 EPb */
80d11f44 8004 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
a750fc0b 8005 /* PowerPC 440 EPX */
80d11f44 8006 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
80d11f44 8007#if defined(TODO_USER_ONLY)
a750fc0b 8008 /* PowerPC 440 GP */
80d11f44
JM		 8009 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
8010#endif
8011#if defined(TODO_USER_ONLY)
a750fc0b 8012 /* PowerPC 440 GPb */
80d11f44
JM		 8013 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
8014#endif
8015#if defined(TODO_USER_ONLY)
a750fc0b 8016 /* PowerPC 440 GPc */
80d11f44
JM		 8017 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
8018#endif
8019#if defined(TODO_USER_ONLY)
a750fc0b 8020 /* PowerPC 440 GR */
80d11f44
JM		 8021 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
8022#endif
8023#if defined(TODO_USER_ONLY)
a750fc0b 8024 /* PowerPC 440 GRa */
80d11f44
JM		 8025 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
8026#endif
8027#if defined(TODO_USER_ONLY)
a750fc0b 8028 /* PowerPC 440 GRX */
80d11f44
JM		 8029 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
8030#endif
8031#if defined(TODO_USER_ONLY)
a750fc0b 8032 /* PowerPC 440 GX */
80d11f44
JM		 8033 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
8034#endif
8035#if defined(TODO_USER_ONLY)
a750fc0b 8036 /* PowerPC 440 GXa */
80d11f44
JM		 8037 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
8038#endif
8039#if defined(TODO_USER_ONLY)
a750fc0b 8040 /* PowerPC 440 GXb */
80d11f44
JM		 8041 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
8042#endif
8043#if defined(TODO_USER_ONLY)
a750fc0b 8044 /* PowerPC 440 GXc */
80d11f44
JM		 8045 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
8046#endif
8047#if defined(TODO_USER_ONLY)
a750fc0b 8048 /* PowerPC 440 GXf */
80d11f44
JM		 8049 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
8050#endif
a750fc0b
JM		 8051#if defined(TODO)
8052 /* PowerPC 440 S */
80d11f44 8053 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 8054#endif
80d11f44 8055#if defined(TODO_USER_ONLY)
a750fc0b 8056 /* PowerPC 440 SP */
80d11f44
JM		 8057 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
8058#endif
8059#if defined(TODO_USER_ONLY)
a750fc0b 8060 /* PowerPC 440 SP2 */
80d11f44
JM		 8061 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
8062#endif
8063#if defined(TODO_USER_ONLY)
a750fc0b 8064 /* PowerPC 440 SPE */
80d11f44
JM		 8065 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
8066#endif
a750fc0b
JM		 8067 /* PowerPC 460 family */
8068#if defined (TODO)
8069 /* Generic PowerPC 464 */
80d11f44 8070 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 8071#endif
8072 /* PowerPC 464 microcontrolers */
8073#if defined (TODO)
8074 /* PowerPC 464H90 */
80d11f44 8075 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 8076#endif
8077#if defined (TODO)
8078 /* PowerPC 464H90F */
80d11f44 8079 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 8080#endif
8081 /* Freescale embedded PowerPC cores */
80d11f44
JM		 8082 /* MPC5xx family (aka RCPU) */
8083#if defined(TODO_USER_ONLY)
8084 /* Generic MPC5xx core */
8085 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
8086#endif
8087#if defined(TODO_USER_ONLY)
8088 /* Codename for MPC5xx core */
8089 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
8090#endif
8091 /* MPC5xx microcontrollers */
8092#if defined(TODO_USER_ONLY)
8093 /* MGT560 */
8094 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
8095#endif
8096#if defined(TODO_USER_ONLY)
8097 /* MPC509 */
8098 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
8099#endif
8100#if defined(TODO_USER_ONLY)
8101 /* MPC533 */
8102 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
8103#endif
8104#if defined(TODO_USER_ONLY)
8105 /* MPC534 */
8106 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
8107#endif
8108#if defined(TODO_USER_ONLY)
8109 /* MPC555 */
8110 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
8111#endif
8112#if defined(TODO_USER_ONLY)
8113 /* MPC556 */
8114 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
8115#endif
8116#if defined(TODO_USER_ONLY)
8117 /* MPC560 */
8118 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
8119#endif
8120#if defined(TODO_USER_ONLY)
8121 /* MPC561 */
8122 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
8123#endif
8124#if defined(TODO_USER_ONLY)
8125 /* MPC562 */
8126 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
8127#endif
8128#if defined(TODO_USER_ONLY)
8129 /* MPC563 */
8130 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
8131#endif
8132#if defined(TODO_USER_ONLY)
8133 /* MPC564 */
8134 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
8135#endif
8136#if defined(TODO_USER_ONLY)
8137 /* MPC565 */
8138 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
8139#endif
8140#if defined(TODO_USER_ONLY)
8141 /* MPC566 */
8142 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
8143#endif
8144 /* MPC8xx family (aka PowerQUICC) */
8145#if defined(TODO_USER_ONLY)
8146 /* Generic MPC8xx core */
8147 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8148#endif
8149#if defined(TODO_USER_ONLY)
8150 /* Codename for MPC8xx core */
8151 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8152#endif
8153 /* MPC8xx microcontrollers */
8154#if defined(TODO_USER_ONLY)
8155 /* MGT823 */
8156 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8157#endif
8158#if defined(TODO_USER_ONLY)
8159 /* MPC821 */
8160 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8161#endif
8162#if defined(TODO_USER_ONLY)
8163 /* MPC823 */
8164 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8165#endif
8166#if defined(TODO_USER_ONLY)
8167 /* MPC850 */
8168 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8169#endif
8170#if defined(TODO_USER_ONLY)
8171 /* MPC852T */
8172 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8173#endif
8174#if defined(TODO_USER_ONLY)
8175 /* MPC855T */
8176 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8177#endif
8178#if defined(TODO_USER_ONLY)
8179 /* MPC857 */
8180 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8181#endif
8182#if defined(TODO_USER_ONLY)
8183 /* MPC859 */
8184 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8185#endif
8186#if defined(TODO_USER_ONLY)
8187 /* MPC860 */
8188 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8189#endif
8190#if defined(TODO_USER_ONLY)
8191 /* MPC862 */
8192 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8193#endif
8194#if defined(TODO_USER_ONLY)
8195 /* MPC866 */
8196 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8197#endif
8198#if defined(TODO_USER_ONLY)
8199 /* MPC870 */
8200 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8201#endif
8202#if defined(TODO_USER_ONLY)
8203 /* MPC875 */
8204 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8205#endif
8206#if defined(TODO_USER_ONLY)
8207 /* MPC880 */
8208 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8209#endif
8210#if defined(TODO_USER_ONLY)
8211 /* MPC885 */
8212 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8213#endif
8214 /* MPC82xx family (aka PowerQUICC-II) */
8215 /* Generic MPC52xx core */
8216 POWERPC_DEF_SVR("MPC52xx",
8217 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8218 /* Generic MPC82xx core */
8219 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8220 /* Codename for MPC82xx */
8221 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8222 /* PowerPC G2 core */
8223 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8224 /* PowerPC G2 H4 core */
8225 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8226 /* PowerPC G2 GP core */
8227 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8228 /* PowerPC G2 LS core */
8229 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8230 /* PowerPC G2 HiP3 core */
8231 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8232 /* PowerPC G2 HiP4 core */
8233 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8234 /* PowerPC MPC603 core */
8235 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8236 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8237 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8238 /* PowerPC G2LE GP core */
8239 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8240 /* PowerPC G2LE LS core */
8241 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8242 /* PowerPC G2LE GP1 core */
8243 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8244 /* PowerPC G2LE GP3 core */
8245 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8246 /* PowerPC MPC603 microcontrollers */
8247 /* MPC8240 */
8248 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8249 /* PowerPC G2 microcontrollers */
082c6681 8250#if defined(TODO)
80d11f44
JM		 8251 /* MPC5121 */
8252 POWERPC_DEF_SVR("MPC5121",
8253 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8254#endif
8255 /* MPC5200 */
8256 POWERPC_DEF_SVR("MPC5200",
8257 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8258 /* MPC5200 v1.0 */
8259 POWERPC_DEF_SVR("MPC5200_v10",
8260 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8261 /* MPC5200 v1.1 */
8262 POWERPC_DEF_SVR("MPC5200_v11",
8263 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8264 /* MPC5200 v1.2 */
8265 POWERPC_DEF_SVR("MPC5200_v12",
8266 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8267 /* MPC5200B */
8268 POWERPC_DEF_SVR("MPC5200B",
8269 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8270 /* MPC5200B v2.0 */
8271 POWERPC_DEF_SVR("MPC5200B_v20",
8272 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8273 /* MPC5200B v2.1 */
8274 POWERPC_DEF_SVR("MPC5200B_v21",
8275 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8276 /* MPC8241 */
8277 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8278 /* MPC8245 */
8279 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8280 /* MPC8247 */
8281 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8282 /* MPC8248 */
8283 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8284 /* MPC8250 */
8285 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8286 /* MPC8250 HiP3 */
8287 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8288 /* MPC8250 HiP4 */
8289 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8290 /* MPC8255 */
8291 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8292 /* MPC8255 HiP3 */
8293 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8294 /* MPC8255 HiP4 */
8295 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8296 /* MPC8260 */
8297 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8298 /* MPC8260 HiP3 */
8299 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8300 /* MPC8260 HiP4 */
8301 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8302 /* MPC8264 */
8303 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8304 /* MPC8264 HiP3 */
8305 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8306 /* MPC8264 HiP4 */
8307 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8308 /* MPC8265 */
8309 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8310 /* MPC8265 HiP3 */
8311 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8312 /* MPC8265 HiP4 */
8313 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8314 /* MPC8266 */
8315 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8316 /* MPC8266 HiP3 */
8317 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8318 /* MPC8266 HiP4 */
8319 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8320 /* MPC8270 */
8321 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8322 /* MPC8271 */
8323 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8324 /* MPC8272 */
8325 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8326 /* MPC8275 */
8327 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8328 /* MPC8280 */
8329 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 8330 /* e200 family */
a750fc0b 8331 /* Generic PowerPC e200 core */
80d11f44
JM		 8332 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8333 /* Generic MPC55xx core */
8334#if defined (TODO)
8335 POWERPC_DEF_SVR("MPC55xx",
8336 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 8337#endif
8338#if defined (TODO)
80d11f44
JM		 8339 /* PowerPC e200z0 core */
8340 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 8341#endif
8342#if defined (TODO)
80d11f44
JM		 8343 /* PowerPC e200z1 core */
8344 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8345#endif
8346#if defined (TODO)
8347 /* PowerPC e200z3 core */
8348 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8349#endif
8350 /* PowerPC e200z5 core */
8351 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 8352 /* PowerPC e200z6 core */
80d11f44
JM		 8353 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8354 /* PowerPC e200 microcontrollers */
8355#if defined (TODO)
8356 /* MPC5514E */
8357 POWERPC_DEF_SVR("MPC5514E",
8358 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 8359#endif
a750fc0b 8360#if defined (TODO)
80d11f44
JM		 8361 /* MPC5514E v0 */
8362 POWERPC_DEF_SVR("MPC5514E_v0",
8363 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 8364#endif
8365#if defined (TODO)
80d11f44
JM		 8366 /* MPC5514E v1 */
8367 POWERPC_DEF_SVR("MPC5514E_v1",
8368 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 8369#endif
8370#if defined (TODO)
80d11f44
JM		 8371 /* MPC5514G */
8372 POWERPC_DEF_SVR("MPC5514G",
8373 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 8374#endif
8375#if defined (TODO)
80d11f44
JM		 8376 /* MPC5514G v0 */
8377 POWERPC_DEF_SVR("MPC5514G_v0",
8378 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 8379#endif
a750fc0b 8380#if defined (TODO)
80d11f44
JM		 8381 /* MPC5514G v1 */
8382 POWERPC_DEF_SVR("MPC5514G_v1",
8383 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 8384#endif
8385#if defined (TODO)
80d11f44
JM		 8386 /* MPC5515S */
8387 POWERPC_DEF_SVR("MPC5515S",
8388 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 8389#endif
8390#if defined (TODO)
80d11f44
JM		 8391 /* MPC5516E */
8392 POWERPC_DEF_SVR("MPC5516E",
8393 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 8394#endif
8395#if defined (TODO)
80d11f44
JM		 8396 /* MPC5516E v0 */
8397 POWERPC_DEF_SVR("MPC5516E_v0",
8398 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 8399#endif
8400#if defined (TODO)
80d11f44
JM		 8401 /* MPC5516E v1 */
8402 POWERPC_DEF_SVR("MPC5516E_v1",
8403 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 8404#endif
a750fc0b 8405#if defined (TODO)
80d11f44
JM		 8406 /* MPC5516G */
8407 POWERPC_DEF_SVR("MPC5516G",
8408 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 8409#endif
a750fc0b 8410#if defined (TODO)
80d11f44
JM		 8411 /* MPC5516G v0 */
8412 POWERPC_DEF_SVR("MPC5516G_v0",
8413 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 8414#endif
a750fc0b 8415#if defined (TODO)
80d11f44
JM		 8416 /* MPC5516G v1 */
8417 POWERPC_DEF_SVR("MPC5516G_v1",
8418 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 8419#endif
a750fc0b 8420#if defined (TODO)
80d11f44
JM		 8421 /* MPC5516S */
8422 POWERPC_DEF_SVR("MPC5516S",
8423 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 8424#endif
8425#if defined (TODO)
80d11f44
JM		 8426 /* MPC5533 */
8427 POWERPC_DEF_SVR("MPC5533",
8428 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 8429#endif
8430#if defined (TODO)
80d11f44
JM		 8431 /* MPC5534 */
8432 POWERPC_DEF_SVR("MPC5534",
8433 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 8434#endif
80d11f44
JM		 8435#if defined (TODO)
8436 /* MPC5553 */
8437 POWERPC_DEF_SVR("MPC5553",
8438 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8439#endif
8440#if defined (TODO)
8441 /* MPC5554 */
8442 POWERPC_DEF_SVR("MPC5554",
8443 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8444#endif
8445#if defined (TODO)
8446 /* MPC5561 */
8447 POWERPC_DEF_SVR("MPC5561",
8448 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8449#endif
8450#if defined (TODO)
8451 /* MPC5565 */
8452 POWERPC_DEF_SVR("MPC5565",
8453 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8454#endif
8455#if defined (TODO)
8456 /* MPC5566 */
8457 POWERPC_DEF_SVR("MPC5566",
8458 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8459#endif
8460#if defined (TODO)
8461 /* MPC5567 */
8462 POWERPC_DEF_SVR("MPC5567",
8463 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8464#endif
8465 /* e300 family */
8466 /* Generic PowerPC e300 core */
8467 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8468 /* PowerPC e300c1 core */
8469 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8470 /* PowerPC e300c2 core */
8471 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8472 /* PowerPC e300c3 core */
8473 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8474 /* PowerPC e300c4 core */
8475 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8476 /* PowerPC e300 microcontrollers */
8477#if defined (TODO)
8478 /* MPC8313 */
8479 POWERPC_DEF_SVR("MPC8313",
74d77cae 8480 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
80d11f44
JM		 8481#endif
8482#if defined (TODO)
8483 /* MPC8313E */
8484 POWERPC_DEF_SVR("MPC8313E",
74d77cae 8485 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
80d11f44
JM		 8486#endif
8487#if defined (TODO)
8488 /* MPC8314 */
8489 POWERPC_DEF_SVR("MPC8314",
74d77cae 8490 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
80d11f44
JM		 8491#endif
8492#if defined (TODO)
8493 /* MPC8314E */
8494 POWERPC_DEF_SVR("MPC8314E",
74d77cae 8495 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
80d11f44
JM		 8496#endif
8497#if defined (TODO)
8498 /* MPC8315 */
8499 POWERPC_DEF_SVR("MPC8315",
74d77cae 8500 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
80d11f44
JM		 8501#endif
8502#if defined (TODO)
8503 /* MPC8315E */
8504 POWERPC_DEF_SVR("MPC8315E",
74d77cae 8505 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
80d11f44
JM		 8506#endif
8507#if defined (TODO)
8508 /* MPC8321 */
8509 POWERPC_DEF_SVR("MPC8321",
74d77cae 8510 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
80d11f44
JM		 8511#endif
8512#if defined (TODO)
8513 /* MPC8321E */
8514 POWERPC_DEF_SVR("MPC8321E",
74d77cae 8515 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
80d11f44
JM		 8516#endif
8517#if defined (TODO)
8518 /* MPC8323 */
8519 POWERPC_DEF_SVR("MPC8323",
74d77cae 8520 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
80d11f44
JM		 8521#endif
8522#if defined (TODO)
8523 /* MPC8323E */
8524 POWERPC_DEF_SVR("MPC8323E",
74d77cae 8525 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
80d11f44 8526#endif
492d7bf5
TM		 8527 /* MPC8343 */
8528 POWERPC_DEF_SVR("MPC8343",
74d77cae 8529 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
80d11f44
JM		 8530 /* MPC8343A */
8531 POWERPC_DEF_SVR("MPC8343A",
74d77cae 8532 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
492d7bf5
TM		 8533 /* MPC8343E */
8534 POWERPC_DEF_SVR("MPC8343E",
74d77cae 8535 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
80d11f44
JM		 8536 /* MPC8343EA */
8537 POWERPC_DEF_SVR("MPC8343EA",
74d77cae 8538 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
492d7bf5
TM		 8539 /* MPC8347 */
8540 POWERPC_DEF_SVR("MPC8347",
74d77cae 8541 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
492d7bf5
TM		 8542 /* MPC8347T */
8543 POWERPC_DEF_SVR("MPC8347T",
74d77cae 8544 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
492d7bf5
TM		 8545 /* MPC8347P */
8546 POWERPC_DEF_SVR("MPC8347P",
74d77cae 8547 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
80d11f44
JM		 8548 /* MPC8347A */
8549 POWERPC_DEF_SVR("MPC8347A",
74d77cae 8550 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
80d11f44
JM		 8551 /* MPC8347AT */
8552 POWERPC_DEF_SVR("MPC8347AT",
74d77cae 8553 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
80d11f44
JM		 8554 /* MPC8347AP */
8555 POWERPC_DEF_SVR("MPC8347AP",
74d77cae 8556 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
492d7bf5
TM		 8557 /* MPC8347E */
8558 POWERPC_DEF_SVR("MPC8347E",
74d77cae 8559 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
492d7bf5
TM		 8560 /* MPC8347ET */
8561 POWERPC_DEF_SVR("MPC8347ET",
74d77cae 8562 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
492d7bf5
TM		 8563 /* MPC8343EP */
8564 POWERPC_DEF_SVR("MPC8347EP",
74d77cae 8565 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
80d11f44
JM		 8566 /* MPC8347EA */
8567 POWERPC_DEF_SVR("MPC8347EA",
74d77cae 8568 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
80d11f44
JM		 8569 /* MPC8347EAT */
8570 POWERPC_DEF_SVR("MPC8347EAT",
74d77cae 8571 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
80d11f44
JM		 8572 /* MPC8343EAP */
8573 POWERPC_DEF_SVR("MPC8347EAP",
74d77cae 8574 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
80d11f44
JM		 8575 /* MPC8349 */
8576 POWERPC_DEF_SVR("MPC8349",
74d77cae 8577 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
80d11f44
JM		 8578 /* MPC8349A */
8579 POWERPC_DEF_SVR("MPC8349A",
74d77cae 8580 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
80d11f44
JM		 8581 /* MPC8349E */
8582 POWERPC_DEF_SVR("MPC8349E",
74d77cae 8583 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
80d11f44
JM		 8584 /* MPC8349EA */
8585 POWERPC_DEF_SVR("MPC8349EA",
74d77cae 8586 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
80d11f44
JM		 8587#if defined (TODO)
8588 /* MPC8358E */
8589 POWERPC_DEF_SVR("MPC8358E",
74d77cae 8590 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
80d11f44
JM		 8591#endif
8592#if defined (TODO)
8593 /* MPC8360E */
8594 POWERPC_DEF_SVR("MPC8360E",
74d77cae 8595 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
80d11f44
JM		 8596#endif
8597 /* MPC8377 */
8598 POWERPC_DEF_SVR("MPC8377",
74d77cae 8599 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
80d11f44
JM		 8600 /* MPC8377E */
8601 POWERPC_DEF_SVR("MPC8377E",
74d77cae 8602 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
80d11f44
JM		 8603 /* MPC8378 */
8604 POWERPC_DEF_SVR("MPC8378",
74d77cae 8605 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
80d11f44
JM		 8606 /* MPC8378E */
8607 POWERPC_DEF_SVR("MPC8378E",
74d77cae 8608 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
80d11f44
JM		 8609 /* MPC8379 */
8610 POWERPC_DEF_SVR("MPC8379",
74d77cae 8611 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
80d11f44
JM		 8612 /* MPC8379E */
8613 POWERPC_DEF_SVR("MPC8379E",
74d77cae 8614 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
80d11f44
JM		 8615 /* e500 family */
8616 /* PowerPC e500 core */
bd5ea513
AJ		 8617 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8618 /* PowerPC e500v1 core */
8619 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
80d11f44 8620 /* PowerPC e500 v1.0 core */
bd5ea513 8621 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
80d11f44 8622 /* PowerPC e500 v2.0 core */
bd5ea513 8623 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
80d11f44 8624 /* PowerPC e500v2 core */
bd5ea513 8625 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
80d11f44 8626 /* PowerPC e500v2 v1.0 core */
bd5ea513 8627 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
80d11f44 8628 /* PowerPC e500v2 v2.0 core */
bd5ea513 8629 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
80d11f44 8630 /* PowerPC e500v2 v2.1 core */
bd5ea513 8631 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
80d11f44 8632 /* PowerPC e500v2 v2.2 core */
bd5ea513 8633 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
80d11f44 8634 /* PowerPC e500v2 v3.0 core */
bd5ea513 8635 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
f7aa5583 8636 POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
b81ccf8a
AG		 8637#ifdef TARGET_PPC64
8638 POWERPC_DEF("e5500", CPU_POWERPC_e5500, e5500),
8639#endif
80d11f44
JM		 8640 /* PowerPC e500 microcontrollers */
8641 /* MPC8533 */
8642 POWERPC_DEF_SVR("MPC8533",
bd5ea513 8643 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
80d11f44
JM		 8644 /* MPC8533 v1.0 */
8645 POWERPC_DEF_SVR("MPC8533_v10",
bd5ea513 8646 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
80d11f44
JM		 8647 /* MPC8533 v1.1 */
8648 POWERPC_DEF_SVR("MPC8533_v11",
bd5ea513 8649 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
80d11f44
JM		 8650 /* MPC8533E */
8651 POWERPC_DEF_SVR("MPC8533E",
bd5ea513 8652 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
80d11f44
JM		 8653 /* MPC8533E v1.0 */
8654 POWERPC_DEF_SVR("MPC8533E_v10",
bd5ea513 8655 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
80d11f44 8656 POWERPC_DEF_SVR("MPC8533E_v11",
bd5ea513 8657 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
80d11f44
JM		 8658 /* MPC8540 */
8659 POWERPC_DEF_SVR("MPC8540",
bd5ea513 8660 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
80d11f44
JM		 8661 /* MPC8540 v1.0 */
8662 POWERPC_DEF_SVR("MPC8540_v10",
bd5ea513 8663 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
80d11f44
JM		 8664 /* MPC8540 v2.0 */
8665 POWERPC_DEF_SVR("MPC8540_v20",
bd5ea513 8666 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
80d11f44
JM		 8667 /* MPC8540 v2.1 */
8668 POWERPC_DEF_SVR("MPC8540_v21",
bd5ea513 8669 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
80d11f44
JM		 8670 /* MPC8541 */
8671 POWERPC_DEF_SVR("MPC8541",
bd5ea513 8672 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
80d11f44
JM		 8673 /* MPC8541 v1.0 */
8674 POWERPC_DEF_SVR("MPC8541_v10",
bd5ea513 8675 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
80d11f44
JM		 8676 /* MPC8541 v1.1 */
8677 POWERPC_DEF_SVR("MPC8541_v11",
bd5ea513 8678 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
80d11f44
JM		 8679 /* MPC8541E */
8680 POWERPC_DEF_SVR("MPC8541E",
bd5ea513 8681 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
80d11f44
JM		 8682 /* MPC8541E v1.0 */
8683 POWERPC_DEF_SVR("MPC8541E_v10",
bd5ea513 8684 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
80d11f44
JM		 8685 /* MPC8541E v1.1 */
8686 POWERPC_DEF_SVR("MPC8541E_v11",
bd5ea513 8687 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
80d11f44
JM		 8688 /* MPC8543 */
8689 POWERPC_DEF_SVR("MPC8543",
bd5ea513 8690 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
80d11f44
JM		 8691 /* MPC8543 v1.0 */
8692 POWERPC_DEF_SVR("MPC8543_v10",
bd5ea513 8693 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
80d11f44
JM		 8694 /* MPC8543 v1.1 */
8695 POWERPC_DEF_SVR("MPC8543_v11",
bd5ea513 8696 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
80d11f44
JM		 8697 /* MPC8543 v2.0 */
8698 POWERPC_DEF_SVR("MPC8543_v20",
bd5ea513 8699 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
80d11f44
JM		 8700 /* MPC8543 v2.1 */
8701 POWERPC_DEF_SVR("MPC8543_v21",
bd5ea513 8702 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
80d11f44
JM		 8703 /* MPC8543E */
8704 POWERPC_DEF_SVR("MPC8543E",
bd5ea513 8705 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
80d11f44
JM		 8706 /* MPC8543E v1.0 */
8707 POWERPC_DEF_SVR("MPC8543E_v10",
bd5ea513 8708 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
80d11f44
JM		 8709 /* MPC8543E v1.1 */
8710 POWERPC_DEF_SVR("MPC8543E_v11",
bd5ea513 8711 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
80d11f44
JM		 8712 /* MPC8543E v2.0 */
8713 POWERPC_DEF_SVR("MPC8543E_v20",
bd5ea513 8714 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
80d11f44
JM		 8715 /* MPC8543E v2.1 */
8716 POWERPC_DEF_SVR("MPC8543E_v21",
bd5ea513 8717 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
80d11f44
JM		 8718 /* MPC8544 */
8719 POWERPC_DEF_SVR("MPC8544",
bd5ea513 8720 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
80d11f44
JM		 8721 /* MPC8544 v1.0 */
8722 POWERPC_DEF_SVR("MPC8544_v10",
bd5ea513 8723 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
80d11f44
JM		 8724 /* MPC8544 v1.1 */
8725 POWERPC_DEF_SVR("MPC8544_v11",
bd5ea513 8726 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
80d11f44
JM		 8727 /* MPC8544E */
8728 POWERPC_DEF_SVR("MPC8544E",
bd5ea513 8729 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
80d11f44
JM		 8730 /* MPC8544E v1.0 */
8731 POWERPC_DEF_SVR("MPC8544E_v10",
bd5ea513 8732 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
80d11f44
JM		 8733 /* MPC8544E v1.1 */
8734 POWERPC_DEF_SVR("MPC8544E_v11",
bd5ea513 8735 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
80d11f44
JM		 8736 /* MPC8545 */
8737 POWERPC_DEF_SVR("MPC8545",
bd5ea513 8738 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
80d11f44
JM		 8739 /* MPC8545 v2.0 */
8740 POWERPC_DEF_SVR("MPC8545_v20",
bd5ea513 8741 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
80d11f44
JM		 8742 /* MPC8545 v2.1 */
8743 POWERPC_DEF_SVR("MPC8545_v21",
bd5ea513 8744 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
80d11f44
JM		 8745 /* MPC8545E */
8746 POWERPC_DEF_SVR("MPC8545E",
bd5ea513 8747 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
80d11f44
JM		 8748 /* MPC8545E v2.0 */
8749 POWERPC_DEF_SVR("MPC8545E_v20",
bd5ea513 8750 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
80d11f44
JM		 8751 /* MPC8545E v2.1 */
8752 POWERPC_DEF_SVR("MPC8545E_v21",
bd5ea513 8753 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
80d11f44
JM		 8754 /* MPC8547E */
8755 POWERPC_DEF_SVR("MPC8547E",
bd5ea513 8756 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
80d11f44
JM		 8757 /* MPC8547E v2.0 */
8758 POWERPC_DEF_SVR("MPC8547E_v20",
bd5ea513 8759 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
80d11f44
JM		 8760 /* MPC8547E v2.1 */
8761 POWERPC_DEF_SVR("MPC8547E_v21",
bd5ea513 8762 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
80d11f44
JM		 8763 /* MPC8548 */
8764 POWERPC_DEF_SVR("MPC8548",
bd5ea513 8765 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
80d11f44
JM		 8766 /* MPC8548 v1.0 */
8767 POWERPC_DEF_SVR("MPC8548_v10",
bd5ea513 8768 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
80d11f44
JM		 8769 /* MPC8548 v1.1 */
8770 POWERPC_DEF_SVR("MPC8548_v11",
bd5ea513 8771 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
80d11f44
JM		 8772 /* MPC8548 v2.0 */
8773 POWERPC_DEF_SVR("MPC8548_v20",
bd5ea513 8774 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
80d11f44
JM		 8775 /* MPC8548 v2.1 */
8776 POWERPC_DEF_SVR("MPC8548_v21",
bd5ea513 8777 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
80d11f44
JM		 8778 /* MPC8548E */
8779 POWERPC_DEF_SVR("MPC8548E",
bd5ea513 8780 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
80d11f44
JM		 8781 /* MPC8548E v1.0 */
8782 POWERPC_DEF_SVR("MPC8548E_v10",
bd5ea513 8783 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
80d11f44
JM		 8784 /* MPC8548E v1.1 */
8785 POWERPC_DEF_SVR("MPC8548E_v11",
bd5ea513 8786 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
80d11f44
JM		 8787 /* MPC8548E v2.0 */
8788 POWERPC_DEF_SVR("MPC8548E_v20",
bd5ea513 8789 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
80d11f44
JM		 8790 /* MPC8548E v2.1 */
8791 POWERPC_DEF_SVR("MPC8548E_v21",
bd5ea513 8792 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
80d11f44
JM		 8793 /* MPC8555 */
8794 POWERPC_DEF_SVR("MPC8555",
bd5ea513 8795 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
80d11f44
JM		 8796 /* MPC8555 v1.0 */
8797 POWERPC_DEF_SVR("MPC8555_v10",
bd5ea513 8798 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
80d11f44
JM		 8799 /* MPC8555 v1.1 */
8800 POWERPC_DEF_SVR("MPC8555_v11",
bd5ea513 8801 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
80d11f44
JM		 8802 /* MPC8555E */
8803 POWERPC_DEF_SVR("MPC8555E",
bd5ea513 8804 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
80d11f44
JM		 8805 /* MPC8555E v1.0 */
8806 POWERPC_DEF_SVR("MPC8555E_v10",
bd5ea513 8807 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
80d11f44
JM		 8808 /* MPC8555E v1.1 */
8809 POWERPC_DEF_SVR("MPC8555E_v11",
bd5ea513 8810 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
80d11f44
JM		 8811 /* MPC8560 */
8812 POWERPC_DEF_SVR("MPC8560",
bd5ea513 8813 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
80d11f44
JM		 8814 /* MPC8560 v1.0 */
8815 POWERPC_DEF_SVR("MPC8560_v10",
bd5ea513 8816 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
80d11f44
JM		 8817 /* MPC8560 v2.0 */
8818 POWERPC_DEF_SVR("MPC8560_v20",
bd5ea513 8819 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
80d11f44
JM		 8820 /* MPC8560 v2.1 */
8821 POWERPC_DEF_SVR("MPC8560_v21",
bd5ea513 8822 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
80d11f44
JM		 8823 /* MPC8567 */
8824 POWERPC_DEF_SVR("MPC8567",
bd5ea513 8825 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
80d11f44
JM		 8826 /* MPC8567E */
8827 POWERPC_DEF_SVR("MPC8567E",
bd5ea513 8828 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
80d11f44
JM		 8829 /* MPC8568 */
8830 POWERPC_DEF_SVR("MPC8568",
bd5ea513 8831 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
80d11f44
JM		 8832 /* MPC8568E */
8833 POWERPC_DEF_SVR("MPC8568E",
bd5ea513 8834 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
80d11f44
JM		 8835 /* MPC8572 */
8836 POWERPC_DEF_SVR("MPC8572",
bd5ea513 8837 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
80d11f44
JM		 8838 /* MPC8572E */
8839 POWERPC_DEF_SVR("MPC8572E",
bd5ea513 8840 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
80d11f44
JM		 8841 /* e600 family */
8842 /* PowerPC e600 core */
8843 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8844 /* PowerPC e600 microcontrollers */
8845#if defined (TODO)
8846 /* MPC8610 */
8847 POWERPC_DEF_SVR("MPC8610",
8848 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8849#endif
8850 /* MPC8641 */
8851 POWERPC_DEF_SVR("MPC8641",
8852 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8853 /* MPC8641D */
8854 POWERPC_DEF_SVR("MPC8641D",
8855 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8856 /* 32 bits "classic" PowerPC */
8857 /* PowerPC 6xx family */
8858 /* PowerPC 601 */
bd928eba 8859 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8860 /* PowerPC 601v0 */
082c6681 8861 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8862 /* PowerPC 601v1 */
082c6681
JM		 8863 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8864 /* PowerPC 601v */
bd928eba 8865 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8866 /* PowerPC 601v2 */
082c6681 8867 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8868 /* PowerPC 602 */
80d11f44 8869 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8870 /* PowerPC 603 */
80d11f44 8871 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8872 /* Code name for PowerPC 603 */
80d11f44 8873 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8874 /* PowerPC 603e (aka PID6) */
80d11f44 8875 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8876 /* Code name for PowerPC 603e */
80d11f44 8877 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8878 /* PowerPC 603e v1.1 */
80d11f44 8879 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8880 /* PowerPC 603e v1.2 */
80d11f44 8881 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8882 /* PowerPC 603e v1.3 */
80d11f44 8883 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8884 /* PowerPC 603e v1.4 */
80d11f44 8885 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8886 /* PowerPC 603e v2.2 */
80d11f44 8887 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8888 /* PowerPC 603e v3 */
80d11f44 8889 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8890 /* PowerPC 603e v4 */
80d11f44 8891 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8892 /* PowerPC 603e v4.1 */
80d11f44 8893 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8894 /* PowerPC 603e (aka PID7) */
80d11f44 8895 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8896 /* PowerPC 603e7t */
80d11f44 8897 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8898 /* PowerPC 603e7v */
80d11f44 8899 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8900 /* Code name for PowerPC 603ev */
80d11f44 8901 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8902 /* PowerPC 603e7v1 */
80d11f44 8903 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8904 /* PowerPC 603e7v2 */
80d11f44 8905 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8906 /* PowerPC 603p (aka PID7v) */
8907 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8908 /* PowerPC 603r (aka PID7t) */
80d11f44 8909 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8910 /* Code name for PowerPC 603r */
80d11f44 8911 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8912 /* PowerPC 604 */
80d11f44 8913 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8914 /* PowerPC 604e (aka PID9) */
8915 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8916 /* Code name for PowerPC 604e */
8917 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8918 /* PowerPC 604e v1.0 */
082c6681 8919 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8920 /* PowerPC 604e v2.2 */
082c6681 8921 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8922 /* PowerPC 604e v2.4 */
082c6681
JM		 8923 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8924 /* PowerPC 604r (aka PIDA) */
8925 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8926 /* Code name for PowerPC 604r */
8927 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8928#if defined(TODO)
8929 /* PowerPC 604ev */
082c6681 8930 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8931#endif
8932 /* PowerPC 7xx family */
8933 /* Generic PowerPC 740 (G3) */
bd928eba 8934 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8935 /* Code name for PowerPC 740 */
bd928eba 8936 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8937 /* Generic PowerPC 750 (G3) */
bd928eba 8938 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8939 /* Code name for PowerPC 750 */
bd928eba 8940 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8941 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8942 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8943 /* PowerPC 740 v1.0 (G3) */
8944 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8945 /* PowerPC 750 v1.0 (G3) */
8946 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8947 /* PowerPC 740 v2.0 (G3) */
bd928eba 8948 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8949 /* PowerPC 750 v2.0 (G3) */
bd928eba 8950 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8951 /* PowerPC 740 v2.1 (G3) */
bd928eba 8952 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8953 /* PowerPC 750 v2.1 (G3) */
bd928eba 8954 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8955 /* PowerPC 740 v2.2 (G3) */
bd928eba 8956 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8957 /* PowerPC 750 v2.2 (G3) */
bd928eba 8958 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8959 /* PowerPC 740 v3.0 (G3) */
bd928eba 8960 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8961 /* PowerPC 750 v3.0 (G3) */
bd928eba 8962 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8963 /* PowerPC 740 v3.1 (G3) */
bd928eba 8964 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8965 /* PowerPC 750 v3.1 (G3) */
bd928eba 8966 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8967 /* PowerPC 740E (G3) */
bd928eba
JM		 8968 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8969 /* PowerPC 750E (G3) */
8970 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8971 /* PowerPC 740P (G3) */
bd928eba 8972 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8973 /* PowerPC 750P (G3) */
bd928eba 8974 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8975 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8976 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8977 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8978 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8979 /* PowerPC 750CL v1.0 */
8980 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8981 /* PowerPC 750CL v2.0 */
8982 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8983 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8984 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8985 /* PowerPC 750CX v1.0 (G3 embedded) */
8986 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8987 /* PowerPC 750CX v2.1 (G3 embedded) */
8988 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8989 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8990 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8991 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8992 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8993 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8994 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8995 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8996 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8997 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8998 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8999 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 9000 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 9001 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 9002 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 9003 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 9004 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
9005 /* PowerPC 750CXe v3.0 (G3 embedded) */
9006 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 9007 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 9008 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 9009 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 9010 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 9011 /* PowerPC 750CXr (G3 embedded) */
bd928eba 9012 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 9013 /* PowerPC 750FL (G3 embedded) */
80d11f44 9014 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 9015 /* PowerPC 750FX (G3 embedded) */
80d11f44 9016 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 9017 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 9018 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 9019 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 9020 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 9021 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 9022 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 9023 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 9024 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 9025 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 9026 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 9027 /* PowerPC 750GL (G3 embedded) */
bd928eba 9028 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 9029 /* PowerPC 750GX (G3 embedded) */
bd928eba 9030 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 9031 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 9032 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 9033 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 9034 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 9035 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 9036 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 9037 /* PowerPC 750L (G3 embedded) */
bd928eba 9038 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 9039 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 9040 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
9041 /* PowerPC 750L v2.0 (G3 embedded) */
9042 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
9043 /* PowerPC 750L v2.1 (G3 embedded) */
9044 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 9045 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 9046 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 9047 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 9048 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 9049 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 9050 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 9051 /* Generic PowerPC 745 */
bd928eba 9052 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 9053 /* Generic PowerPC 755 */
bd928eba 9054 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 9055 /* Code name for PowerPC 745/755 */
bd928eba 9056 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 9057 /* PowerPC 745 v1.0 */
bd928eba 9058 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 9059 /* PowerPC 755 v1.0 */
bd928eba 9060 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 9061 /* PowerPC 745 v1.1 */
bd928eba 9062 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 9063 /* PowerPC 755 v1.1 */
bd928eba 9064 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 9065 /* PowerPC 745 v2.0 */
bd928eba 9066 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 9067 /* PowerPC 755 v2.0 */
bd928eba 9068 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 9069 /* PowerPC 745 v2.1 */
bd928eba 9070 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 9071 /* PowerPC 755 v2.1 */
bd928eba 9072 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 9073 /* PowerPC 745 v2.2 */
bd928eba 9074 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 9075 /* PowerPC 755 v2.2 */
bd928eba 9076 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 9077 /* PowerPC 745 v2.3 */
bd928eba 9078 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 9079 /* PowerPC 755 v2.3 */
bd928eba 9080 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 9081 /* PowerPC 745 v2.4 */
bd928eba 9082 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 9083 /* PowerPC 755 v2.4 */
bd928eba 9084 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 9085 /* PowerPC 745 v2.5 */
bd928eba 9086 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 9087 /* PowerPC 755 v2.5 */
bd928eba 9088 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 9089 /* PowerPC 745 v2.6 */
bd928eba 9090 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 9091 /* PowerPC 755 v2.6 */
bd928eba 9092 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 9093 /* PowerPC 745 v2.7 */
bd928eba 9094 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 9095 /* PowerPC 755 v2.7 */
bd928eba 9096 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 9097 /* PowerPC 745 v2.8 */
bd928eba 9098 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 9099 /* PowerPC 755 v2.8 */
bd928eba 9100 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 9101#if defined (TODO)
9102 /* PowerPC 745P (G3) */
bd928eba 9103 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 9104 /* PowerPC 755P (G3) */
bd928eba 9105 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 9106#endif
9107 /* PowerPC 74xx family */
9108 /* PowerPC 7400 (G4) */
80d11f44 9109 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 9110 /* Code name for PowerPC 7400 */
80d11f44 9111 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 9112 /* PowerPC 74xx is also well known as G4 */
80d11f44 9113 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 9114 /* PowerPC 7400 v1.0 (G4) */
80d11f44 9115 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 9116 /* PowerPC 7400 v1.1 (G4) */
80d11f44 9117 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 9118 /* PowerPC 7400 v2.0 (G4) */
80d11f44 9119 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 9120 /* PowerPC 7400 v2.1 (G4) */
9121 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 9122 /* PowerPC 7400 v2.2 (G4) */
80d11f44 9123 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 9124 /* PowerPC 7400 v2.6 (G4) */
80d11f44 9125 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 9126 /* PowerPC 7400 v2.7 (G4) */
80d11f44 9127 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 9128 /* PowerPC 7400 v2.8 (G4) */
80d11f44 9129 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 9130 /* PowerPC 7400 v2.9 (G4) */
80d11f44 9131 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 9132 /* PowerPC 7410 (G4) */
80d11f44 9133 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 9134 /* Code name for PowerPC 7410 */
80d11f44 9135 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 9136 /* PowerPC 7410 v1.0 (G4) */
80d11f44 9137 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 9138 /* PowerPC 7410 v1.1 (G4) */
80d11f44 9139 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 9140 /* PowerPC 7410 v1.2 (G4) */
80d11f44 9141 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 9142 /* PowerPC 7410 v1.3 (G4) */
80d11f44 9143 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 9144 /* PowerPC 7410 v1.4 (G4) */
80d11f44 9145 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 9146 /* PowerPC 7448 (G4) */
80d11f44 9147 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 9148 /* PowerPC 7448 v1.0 (G4) */
80d11f44 9149 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 9150 /* PowerPC 7448 v1.1 (G4) */
80d11f44 9151 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 9152 /* PowerPC 7448 v2.0 (G4) */
80d11f44 9153 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 9154 /* PowerPC 7448 v2.1 (G4) */
80d11f44 9155 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 9156 /* PowerPC 7450 (G4) */
80d11f44 9157 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 9158 /* Code name for PowerPC 7450 */
80d11f44 9159 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 9160 /* PowerPC 7450 v1.0 (G4) */
80d11f44 9161 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 9162 /* PowerPC 7450 v1.1 (G4) */
80d11f44 9163 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 9164 /* PowerPC 7450 v1.2 (G4) */
80d11f44 9165 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 9166 /* PowerPC 7450 v2.0 (G4) */
80d11f44 9167 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 9168 /* PowerPC 7450 v2.1 (G4) */
80d11f44 9169 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 9170 /* PowerPC 7441 (G4) */
80d11f44 9171 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 9172 /* PowerPC 7451 (G4) */
80d11f44 9173 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 9174 /* PowerPC 7441 v2.1 (G4) */
9175 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9176 /* PowerPC 7441 v2.3 (G4) */
9177 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9178 /* PowerPC 7451 v2.3 (G4) */
9179 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9180 /* PowerPC 7441 v2.10 (G4) */
9181 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9182 /* PowerPC 7451 v2.10 (G4) */
9183 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 9184 /* PowerPC 7445 (G4) */
80d11f44 9185 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 9186 /* PowerPC 7455 (G4) */
80d11f44 9187 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 9188 /* Code name for PowerPC 7445/7455 */
80d11f44 9189 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 9190 /* PowerPC 7445 v1.0 (G4) */
80d11f44 9191 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 9192 /* PowerPC 7455 v1.0 (G4) */
80d11f44 9193 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 9194 /* PowerPC 7445 v2.1 (G4) */
80d11f44 9195 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 9196 /* PowerPC 7455 v2.1 (G4) */
80d11f44 9197 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 9198 /* PowerPC 7445 v3.2 (G4) */
80d11f44 9199 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 9200 /* PowerPC 7455 v3.2 (G4) */
80d11f44 9201 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 9202 /* PowerPC 7445 v3.3 (G4) */
80d11f44 9203 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 9204 /* PowerPC 7455 v3.3 (G4) */
80d11f44 9205 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 9206 /* PowerPC 7445 v3.4 (G4) */
80d11f44 9207 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 9208 /* PowerPC 7455 v3.4 (G4) */
80d11f44 9209 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 9210 /* PowerPC 7447 (G4) */
80d11f44 9211 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 9212 /* PowerPC 7457 (G4) */
80d11f44 9213 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 9214 /* Code name for PowerPC 7447/7457 */
80d11f44 9215 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 9216 /* PowerPC 7447 v1.0 (G4) */
80d11f44 9217 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 9218 /* PowerPC 7457 v1.0 (G4) */
80d11f44 9219 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 9220 /* PowerPC 7447 v1.1 (G4) */
80d11f44 9221 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 9222 /* PowerPC 7457 v1.1 (G4) */
80d11f44 9223 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 9224 /* PowerPC 7457 v1.2 (G4) */
80d11f44 9225 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 9226 /* PowerPC 7447A (G4) */
9227 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9228 /* PowerPC 7457A (G4) */
9229 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9230 /* PowerPC 7447A v1.0 (G4) */
9231 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9232 /* PowerPC 7457A v1.0 (G4) */
9233 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9234 /* Code name for PowerPC 7447A/7457A */
9235 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9236 /* PowerPC 7447A v1.1 (G4) */
9237 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9238 /* PowerPC 7457A v1.1 (G4) */
9239 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9240 /* PowerPC 7447A v1.2 (G4) */
9241 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9242 /* PowerPC 7457A v1.2 (G4) */
9243 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 9244 /* 64 bits PowerPC */
9245#if defined (TARGET_PPC64)
a750fc0b 9246 /* PowerPC 620 */
80d11f44 9247 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 9248 /* Code name for PowerPC 620 */
9249 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 9250#if defined (TODO)
a750fc0b 9251 /* PowerPC 630 (POWER3) */
80d11f44
JM		 9252 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9253 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 9254 /* Code names for POWER3 */
9255 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9256 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 9257#endif
3a607854 9258#if defined (TODO)
a750fc0b 9259 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 9260 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9261 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 9262#endif
9263#if defined (TODO)
a750fc0b 9264 /* POWER4 */
80d11f44 9265 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 9266#endif
3a607854 9267#if defined (TODO)
a750fc0b 9268 /* POWER4p */
80d11f44 9269 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 9270#endif
2662a059 9271#if defined (TODO)
a750fc0b 9272 /* POWER5 */
80d11f44 9273 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 9274 /* POWER5GR */
80d11f44 9275 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 9276#endif
3a607854 9277#if defined (TODO)
a750fc0b 9278 /* POWER5+ */
80d11f44 9279 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 9280 /* POWER5GS */
80d11f44 9281 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 9282#endif
2662a059 9283#if defined (TODO)
a750fc0b 9284 /* POWER6 */
80d11f44 9285 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 9286 /* POWER6 running in POWER5 mode */
80d11f44 9287 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 9288 /* POWER6A */
80d11f44 9289 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 9290#endif
9d52e907
DG		 9291 /* POWER7 */
9292 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9293 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
37e305ce
DG		 9294 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
9295 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
a750fc0b 9296 /* PowerPC 970 */
80d11f44 9297 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 9298 /* PowerPC 970FX (G5) */
80d11f44 9299 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 9300 /* PowerPC 970FX v1.0 (G5) */
80d11f44 9301 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 9302 /* PowerPC 970FX v2.0 (G5) */
80d11f44 9303 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 9304 /* PowerPC 970FX v2.1 (G5) */
80d11f44 9305 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 9306 /* PowerPC 970FX v3.0 (G5) */
80d11f44 9307 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 9308 /* PowerPC 970FX v3.1 (G5) */
80d11f44 9309 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 9310 /* PowerPC 970GX (G5) */
80d11f44 9311 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 9312 /* PowerPC 970MP */
80d11f44 9313 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 9314 /* PowerPC 970MP v1.0 */
80d11f44 9315 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 9316 /* PowerPC 970MP v1.1 */
80d11f44 9317 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 9318#if defined (TODO)
a750fc0b 9319 /* PowerPC Cell */
80d11f44 9320 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 9321#endif
9322#if defined (TODO)
a750fc0b 9323 /* PowerPC Cell v1.0 */
80d11f44 9324 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 9325#endif
9326#if defined (TODO)
a750fc0b 9327 /* PowerPC Cell v2.0 */
80d11f44 9328 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 9329#endif
9330#if defined (TODO)
a750fc0b 9331 /* PowerPC Cell v3.0 */
80d11f44 9332 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 9333#endif
3a607854 9334#if defined (TODO)
a750fc0b 9335 /* PowerPC Cell v3.1 */
80d11f44 9336 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 9337#endif
9338#if defined (TODO)
a750fc0b 9339 /* PowerPC Cell v3.2 */
80d11f44 9340 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 9341#endif
9342#if defined (TODO)
a750fc0b
JM		 9343 /* RS64 (Apache/A35) */
9344 /* This one seems to support the whole POWER2 instruction set
9345 * and the PowerPC 64 one.
9346 */
9347 /* What about A10 & A30 ? */
80d11f44
JM		 9348 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9349 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9350 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 9351#endif
9352#if defined (TODO)
a750fc0b 9353 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 9354 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9355 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9356 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 9357#endif
9358#if defined (TODO)
a750fc0b 9359 /* RS64-III (Pulsar) */
80d11f44
JM		 9360 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9361 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 9362#endif
9363#if defined (TODO)
a750fc0b 9364 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 9365 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9366 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9367 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9368 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 9369#endif
a750fc0b
JM		 9370#endif /* defined (TARGET_PPC64) */
9371 /* POWER */
3fc6c082 9372#if defined (TODO)
a750fc0b 9373 /* Original POWER */
80d11f44
JM		 9374 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9375 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9376 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9377 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9378 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 9379#endif
9380#if defined (TODO)
a750fc0b 9381 /* POWER2 */
80d11f44
JM		 9382 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9383 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9384 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 9385#endif
9386 /* PA semi cores */
9387#if defined (TODO)
9388 /* PA PA6T */
80d11f44 9389 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 9390#endif
9391 /* Generic PowerPCs */
9392#if defined (TARGET_PPC64)
80d11f44 9393 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 9394#endif
80d11f44
JM		 9395 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9396 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 9397 /* Fallback */
80d11f44 9398 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 9399};
9400
9401/*****************************************************************************/
60b14d95 9402/* Generic CPU instantiation routine */
c227f099 9403static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9404{
9405#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 9406 int i;
9407
a750fc0b 9408 env->irq_inputs = NULL;
e1833e1f
JM		 9409 /* Set all exception vectors to an invalid address */
9410 for (i = 0; i < POWERPC_EXCP_NB; i++)
9411 env->excp_vectors[i] = (target_ulong)(-1ULL);
fc1c67bc 9412 env->hreset_excp_prefix = 0x00000000;
e1833e1f
JM		 9413 env->ivor_mask = 0x00000000;
9414 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 9415 /* Default MMU definitions */
9416 env->nb_BATs = 0;
9417 env->nb_tlb = 0;
9418 env->nb_ways = 0;
1c53accc 9419 env->tlb_type = TLB_NONE;
f2e63a42 9420#endif
a750fc0b
JM		 9421 /* Register SPR common to all PowerPC implementations */
9422 gen_spr_generic(env);
9423 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 9424 /* Linux permits userspace to read PVR */
9425#if defined(CONFIG_LINUX_USER)
9426 &spr_read_generic,
9427#else
9428 SPR_NOACCESS,
9429#endif
9430 SPR_NOACCESS,
a750fc0b
JM		 9431 &spr_read_generic, SPR_NOACCESS,
9432 def->pvr);
80d11f44
JM		 9433 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9434 if (def->svr != POWERPC_SVR_NONE) {
9435 if (def->svr & POWERPC_SVR_E500) {
9436 spr_register(env, SPR_E500_SVR, "SVR",
9437 SPR_NOACCESS, SPR_NOACCESS,
9438 &spr_read_generic, SPR_NOACCESS,
9439 def->svr & ~POWERPC_SVR_E500);
9440 } else {
9441 spr_register(env, SPR_SVR, "SVR",
9442 SPR_NOACCESS, SPR_NOACCESS,
9443 &spr_read_generic, SPR_NOACCESS,
9444 def->svr);
9445 }
9446 }
a750fc0b
JM		 9447 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9448 (*def->init_proc)(env);
fc1c67bc
BS		 9449#if !defined(CONFIG_USER_ONLY)
9450 env->excp_prefix = env->hreset_excp_prefix;
9451#endif
25ba3a68
JM		 9452 /* MSR bits & flags consistency checks */
9453 if (env->msr_mask & (1 << 25)) {
9454 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9455 case POWERPC_FLAG_SPE:
9456 case POWERPC_FLAG_VRE:
9457 break;
9458 default:
9459 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9460 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9461 exit(1);
9462 }
9463 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9464 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9465 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9466 exit(1);
9467 }
9468 if (env->msr_mask & (1 << 17)) {
9469 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9470 case POWERPC_FLAG_TGPR:
9471 case POWERPC_FLAG_CE:
9472 break;
9473 default:
9474 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9475 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9476 exit(1);
9477 }
9478 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9479 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9480 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9481 exit(1);
9482 }
9483 if (env->msr_mask & (1 << 10)) {
9484 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9485 POWERPC_FLAG_UBLE)) {
9486 case POWERPC_FLAG_SE:
9487 case POWERPC_FLAG_DWE:
9488 case POWERPC_FLAG_UBLE:
9489 break;
9490 default:
9491 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9492 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9493 "POWERPC_FLAG_UBLE\n");
9494 exit(1);
9495 }
9496 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9497 POWERPC_FLAG_UBLE)) {
9498 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9499 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9500 "POWERPC_FLAG_UBLE\n");
9501 exit(1);
9502 }
9503 if (env->msr_mask & (1 << 9)) {
9504 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9505 case POWERPC_FLAG_BE:
9506 case POWERPC_FLAG_DE:
9507 break;
9508 default:
9509 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9510 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9511 exit(1);
9512 }
9513 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9514 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9515 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9516 exit(1);
9517 }
9518 if (env->msr_mask & (1 << 2)) {
9519 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9520 case POWERPC_FLAG_PX:
9521 case POWERPC_FLAG_PMM:
9522 break;
9523 default:
9524 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9525 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9526 exit(1);
9527 }
9528 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9529 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9530 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9531 exit(1);
9532 }
4018bae9
JM		 9533 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9534 fprintf(stderr, "PowerPC flags inconsistency\n"
9535 "Should define the time-base and decrementer clock source\n");
9536 exit(1);
9537 }
a750fc0b 9538 /* Allocate TLBs buffer when needed */
f2e63a42 9539#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9540 if (env->nb_tlb != 0) {
9541 int nb_tlb = env->nb_tlb;
9542 if (env->id_tlbs != 0)
9543 nb_tlb *= 2;
1c53accc
AG		 9544 switch (env->tlb_type) {
9545 case TLB_6XX:
7267c094 9546 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
1c53accc
AG		 9547 break;
9548 case TLB_EMB:
7267c094 9549 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
1c53accc
AG		 9550 break;
9551 case TLB_MAS:
7267c094 9552 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
1c53accc
AG		 9553 break;
9554 }
a750fc0b
JM		 9555 /* Pre-compute some useful values */
9556 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9557 }
a750fc0b
JM		 9558 if (env->irq_inputs == NULL) {
9559 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5cbdb3a3 9560 " Attempt QEMU to crash very soon !\n");
a750fc0b
JM		 9561 }
9562#endif
2f462816
JM		 9563 if (env->check_pow == NULL) {
9564 fprintf(stderr, "WARNING: no power management check handler "
9565 "registered.\n"
5cbdb3a3 9566 " Attempt QEMU to crash very soon !\n");
2f462816 9567 }
a750fc0b
JM		 9568}
9569
9570#if defined(PPC_DUMP_CPU)
9571static void dump_ppc_sprs (CPUPPCState *env)
9572{
9573 ppc_spr_t *spr;
9574#if !defined(CONFIG_USER_ONLY)
9575 uint32_t sr, sw;
9576#endif
9577 uint32_t ur, uw;
9578 int i, j, n;
9579
9580 printf("Special purpose registers:\n");
9581 for (i = 0; i < 32; i++) {
9582 for (j = 0; j < 32; j++) {
9583 n = (i << 5) | j;
9584 spr = &env->spr_cb[n];
9585 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9586 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9587#if !defined(CONFIG_USER_ONLY)
9588 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9589 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9590 if (sw || sr || uw || ur) {
9591 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9592 (i << 5) | j, (i << 5) | j, spr->name,
9593 sw ? 'w' : '-', sr ? 'r' : '-',
9594 uw ? 'w' : '-', ur ? 'r' : '-');
9595 }
9596#else
9597 if (uw || ur) {
9598 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9599 (i << 5) | j, (i << 5) | j, spr->name,
9600 uw ? 'w' : '-', ur ? 'r' : '-');
9601 }
9602#endif
9603 }
9604 }
9605 fflush(stdout);
9606 fflush(stderr);
9607}
9608#endif
9609
9610/*****************************************************************************/
9611#include <stdlib.h>
9612#include <string.h>
9613
a750fc0b
JM		 9614/* Opcode types */
9615enum {
9616 PPC_DIRECT = 0, /* Opcode routine */
9617 PPC_INDIRECT = 1, /* Indirect opcode table */
9618};
9619
9620static inline int is_indirect_opcode (void *handler)
9621{
5724753e 9622 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
a750fc0b
JM		 9623}
9624
c227f099 9625static inline opc_handler_t **ind_table(void *handler)
a750fc0b 9626{
5724753e 9627 return (opc_handler_t **)((uintptr_t)handler & ~3);
a750fc0b
JM		 9628}
9629
9630/* Instruction table creation */
9631/* Opcodes tables creation */
c227f099 9632static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 9633{
9634 int i;
9635
9636 for (i = 0; i < len; i++)
9637 table[i] = &invalid_handler;
9638}
9639
c227f099 9640static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 9641{
c227f099 9642 opc_handler_t **tmp;
a750fc0b 9643
c227f099 9644 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 9645 fill_new_table(tmp, 0x20);
5724753e 9646 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
a750fc0b
JM		 9647
9648 return 0;
9649}
9650
c227f099
AL		 9651static int insert_in_table (opc_handler_t **table, unsigned char idx,
9652 opc_handler_t *handler)
a750fc0b
JM		 9653{
9654 if (table[idx] != &invalid_handler)
9655 return -1;
9656 table[idx] = handler;
9657
9658 return 0;
9659}
9660
c227f099
AL		 9661static int register_direct_insn (opc_handler_t **ppc_opcodes,
9662 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 9663{
9664 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9665 printf("*** ERROR: opcode %02x already assigned in main "
9666 "opcode table\n", idx);
4c1b1bfe
JM		 9667#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9668 printf(" Registered handler '%s' - new handler '%s'\n",
9669 ppc_opcodes[idx]->oname, handler->oname);
9670#endif
a750fc0b
JM		 9671 return -1;
9672 }
9673
9674 return 0;
9675}
9676
c227f099 9677static int register_ind_in_table (opc_handler_t **table,
a750fc0b 9678 unsigned char idx1, unsigned char idx2,
c227f099 9679 opc_handler_t *handler)
a750fc0b
JM		 9680{
9681 if (table[idx1] == &invalid_handler) {
9682 if (create_new_table(table, idx1) < 0) {
9683 printf("*** ERROR: unable to create indirect table "
9684 "idx=%02x\n", idx1);
9685 return -1;
9686 }
9687 } else {
9688 if (!is_indirect_opcode(table[idx1])) {
9689 printf("*** ERROR: idx %02x already assigned to a direct "
9690 "opcode\n", idx1);
4c1b1bfe
JM		 9691#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9692 printf(" Registered handler '%s' - new handler '%s'\n",
9693 ind_table(table[idx1])[idx2]->oname, handler->oname);
9694#endif
a750fc0b
JM		 9695 return -1;
9696 }
3a607854 9697 }
a750fc0b
JM		 9698 if (handler != NULL &&
9699 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9700 printf("*** ERROR: opcode %02x already assigned in "
9701 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9702#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9703 printf(" Registered handler '%s' - new handler '%s'\n",
9704 ind_table(table[idx1])[idx2]->oname, handler->oname);
9705#endif
a750fc0b 9706 return -1;
3a607854 9707 }
a750fc0b
JM		 9708
9709 return 0;
9710}
9711
c227f099 9712static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9713 unsigned char idx1, unsigned char idx2,
c227f099 9714 opc_handler_t *handler)
a750fc0b
JM		 9715{
9716 int ret;
9717
9718 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9719
9720 return ret;
9721}
9722
c227f099 9723static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9724 unsigned char idx1, unsigned char idx2,
c227f099 9725 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 9726{
9727 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9728 printf("*** ERROR: unable to join indirect table idx "
9729 "[%02x-%02x]\n", idx1, idx2);
9730 return -1;
9731 }
9732 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9733 handler) < 0) {
9734 printf("*** ERROR: unable to insert opcode "
9735 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9736 return -1;
9737 }
9738
9739 return 0;
9740}
9741
c227f099 9742static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 9743{
9744 if (insn->opc2 != 0xFF) {
9745 if (insn->opc3 != 0xFF) {
9746 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9747 insn->opc3, &insn->handler) < 0)
9748 return -1;
9749 } else {
9750 if (register_ind_insn(ppc_opcodes, insn->opc1,
9751 insn->opc2, &insn->handler) < 0)
9752 return -1;
9753 }
9754 } else {
9755 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9756 return -1;
9757 }
9758
9759 return 0;
9760}
9761
c227f099 9762static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 9763{
9764 int i, count, tmp;
9765
9766 for (i = 0, count = 0; i < len; i++) {
9767 /* Consistency fixup */
9768 if (table[i] == NULL)
9769 table[i] = &invalid_handler;
9770 if (table[i] != &invalid_handler) {
9771 if (is_indirect_opcode(table[i])) {
c227f099 9772 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 9773 if (tmp == 0) {
9774 free(table[i]);
9775 table[i] = &invalid_handler;
9776 } else {
9777 count++;
9778 }
9779 } else {
9780 count++;
9781 }
9782 }
9783 }
9784
9785 return count;
9786}
9787
c227f099 9788static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 9789{
c227f099 9790 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 9791 printf("*** WARNING: no opcode defined !\n");
9792}
9793
9794/*****************************************************************************/
2985b86b 9795static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
a750fc0b 9796{
2985b86b
AF		 9797 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9798 CPUPPCState *env = &cpu->env;
9799 const ppc_def_t *def = pcc->info;
c227f099 9800 opcode_t *opc;
a750fc0b
JM		 9801
9802 fill_new_table(env->opcodes, 0x40);
5c55ff99 9803 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
a5858d7a
AG		 9804 if (((opc->handler.type & def->insns_flags) != 0) ||
9805 ((opc->handler.type2 & def->insns_flags2) != 0)) {
a750fc0b 9806 if (register_insn(env->opcodes, opc) < 0) {
2985b86b
AF		 9807 error_setg(errp, "ERROR initializing PowerPC instruction "
9808 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9809 opc->opc3);
9810 return;
a750fc0b
JM		 9811 }
9812 }
9813 }
c227f099 9814 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 9815 fflush(stdout);
9816 fflush(stderr);
a750fc0b
JM		 9817}
9818
9819#if defined(PPC_DUMP_CPU)
25ba3a68 9820static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 9821{
c227f099 9822 opc_handler_t **table, *handler;
b55266b5 9823 const char *p, *q;
a750fc0b
JM		 9824 uint8_t opc1, opc2, opc3;
9825
9826 printf("Instructions set:\n");
9827 /* opc1 is 6 bits long */
9828 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9829 table = env->opcodes;
9830 handler = table[opc1];
9831 if (is_indirect_opcode(handler)) {
9832 /* opc2 is 5 bits long */
9833 for (opc2 = 0; opc2 < 0x20; opc2++) {
9834 table = env->opcodes;
9835 handler = env->opcodes[opc1];
9836 table = ind_table(handler);
9837 handler = table[opc2];
9838 if (is_indirect_opcode(handler)) {
9839 table = ind_table(handler);
9840 /* opc3 is 5 bits long */
9841 for (opc3 = 0; opc3 < 0x20; opc3++) {
9842 handler = table[opc3];
9843 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9844 /* Special hack to properly dump SPE insns */
9845 p = strchr(handler->oname, '_');
9846 if (p == NULL) {
9847 printf("INSN: %02x %02x %02x (%02d %04d) : "
9848 "%s\n",
9849 opc1, opc2, opc3, opc1,
9850 (opc3 << 5) | opc2,
9851 handler->oname);
9852 } else {
9853 q = "speundef";
9854 if ((p - handler->oname) != strlen(q) ||
9855 memcmp(handler->oname, q, strlen(q)) != 0) {
9856 /* First instruction */
9857 printf("INSN: %02x %02x %02x (%02d %04d) : "
9858 "%.*s\n",
9859 opc1, opc2 << 1, opc3, opc1,
9860 (opc3 << 6) | (opc2 << 1),
9861 (int)(p - handler->oname),
9862 handler->oname);
9863 }
9864 if (strcmp(p + 1, q) != 0) {
9865 /* Second instruction */
9866 printf("INSN: %02x %02x %02x (%02d %04d) : "
9867 "%s\n",
9868 opc1, (opc2 << 1) | 1, opc3, opc1,
9869 (opc3 << 6) | (opc2 << 1) | 1,
9870 p + 1);
9871 }
9872 }
a750fc0b
JM		 9873 }
9874 }
9875 } else {
9876 if (handler->handler != &gen_invalid) {
9877 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9878 opc1, opc2, opc1, opc2, handler->oname);
9879 }
9880 }
9881 }
9882 } else {
9883 if (handler->handler != &gen_invalid) {
9884 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9885 opc1, opc1, handler->oname);
9886 }
9887 }
9888 }
9889}
3a607854 9890#endif
a750fc0b 9891
1328c2bf 9892static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 9893{
9894 if (n < 32) {
9895 stfq_p(mem_buf, env->fpr[n]);
9896 return 8;
9897 }
9898 if (n == 32) {
5a576fb3 9899 stl_p(mem_buf, env->fpscr);
24951522
AJ		 9900 return 4;
9901 }
9902 return 0;
9903}
9904
1328c2bf 9905static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 9906{
9907 if (n < 32) {
9908 env->fpr[n] = ldfq_p(mem_buf);
9909 return 8;
9910 }
9911 if (n == 32) {
9912 /* FPSCR not implemented */
9913 return 4;
9914 }
9915 return 0;
9916}
9917
1328c2bf 9918static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 9919{
9920 if (n < 32) {
e2542fe2 9921#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9922 stq_p(mem_buf, env->avr[n].u64[0]);
9923 stq_p(mem_buf+8, env->avr[n].u64[1]);
9924#else
9925 stq_p(mem_buf, env->avr[n].u64[1]);
9926 stq_p(mem_buf+8, env->avr[n].u64[0]);
9927#endif
9928 return 16;
9929 }
70976a79 9930 if (n == 32) {
b4f8d821
AJ		 9931 stl_p(mem_buf, env->vscr);
9932 return 4;
9933 }
70976a79 9934 if (n == 33) {
b4f8d821
AJ		 9935 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9936 return 4;
9937 }
9938 return 0;
9939}
9940
1328c2bf 9941static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 9942{
9943 if (n < 32) {
e2542fe2 9944#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9945 env->avr[n].u64[0] = ldq_p(mem_buf);
9946 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9947#else
9948 env->avr[n].u64[1] = ldq_p(mem_buf);
9949 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9950#endif
9951 return 16;
9952 }
70976a79 9953 if (n == 32) {
b4f8d821
AJ		 9954 env->vscr = ldl_p(mem_buf);
9955 return 4;
9956 }
70976a79 9957 if (n == 33) {
b4f8d821
AJ		 9958 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9959 return 4;
9960 }
9961 return 0;
9962}
9963
1328c2bf 9964static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 9965{
9966 if (n < 32) {
9967#if defined(TARGET_PPC64)
9968 stl_p(mem_buf, env->gpr[n] >> 32);
9969#else
9970 stl_p(mem_buf, env->gprh[n]);
9971#endif
9972 return 4;
9973 }
70976a79 9974 if (n == 32) {
688890f7
AJ		 9975 stq_p(mem_buf, env->spe_acc);
9976 return 8;
9977 }
70976a79 9978 if (n == 33) {
d34defbc 9979 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 9980 return 4;
9981 }
9982 return 0;
9983}
9984
1328c2bf 9985static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 9986{
9987 if (n < 32) {
9988#if defined(TARGET_PPC64)
9989 target_ulong lo = (uint32_t)env->gpr[n];
9990 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9991 env->gpr[n] = lo | hi;
9992#else
9993 env->gprh[n] = ldl_p(mem_buf);
9994#endif
9995 return 4;
9996 }
70976a79 9997 if (n == 32) {
688890f7
AJ		 9998 env->spe_acc = ldq_p(mem_buf);
9999 return 8;
10000 }
70976a79 10001 if (n == 33) {
d34defbc 10002 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 10003 return 4;
10004 }
10005 return 0;
10006}
10007
12b1143b
DG		 10008static int ppc_fixup_cpu(CPUPPCState *env)
10009{
10010 /* TCG doesn't (yet) emulate some groups of instructions that
10011 * are implemented on some otherwise supported CPUs (e.g. VSX
10012 * and decimal floating point instructions on POWER7). We
10013 * remove unsupported instruction groups from the cpu state's
10014 * instruction masks and hope the guest can cope. For at
10015 * least the pseries machine, the unavailability of these
10016 * instructions can be advertised to the guest via the device
10017 * tree. */
10018 if ((env->insns_flags & ~PPC_TCG_INSNS)
10019 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
10020 fprintf(stderr, "Warning: Disabling some instructions which are not "
10021 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
10022 env->insns_flags & ~PPC_TCG_INSNS,
10023 env->insns_flags2 & ~PPC_TCG_INSNS2);
10024 }
10025 env->insns_flags &= PPC_TCG_INSNS;
10026 env->insns_flags2 &= PPC_TCG_INSNS2;
10027 return 0;
10028}
10029
2985b86b 10030static void ppc_cpu_realize(Object *obj, Error **errp)
a750fc0b 10031{
2985b86b
AF		 10032 PowerPCCPU *cpu = POWERPC_CPU(obj);
10033 CPUPPCState *env = &cpu->env;
10034 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10035 ppc_def_t *def = pcc->info;
10036 Error *local_err = NULL;
4656e1f0 10037
12b1143b
DG		 10038 if (kvm_enabled()) {
10039 if (kvmppc_fixup_cpu(env) != 0) {
2985b86b
AF		 10040 error_setg(errp, "Unable to virtualize selected CPU with KVM");
10041 return;
12b1143b
DG		 10042 }
10043 } else {
10044 if (ppc_fixup_cpu(env) != 0) {
2985b86b
AF		 10045 error_setg(errp, "Unable to emulate selected CPU with TCG");
10046 return;
12b1143b
DG		 10047 }
10048 }
10049
2985b86b
AF		 10050 create_ppc_opcodes(cpu, &local_err);
10051 if (local_err != NULL) {
10052 error_propagate(errp, local_err);
10053 return;
10054 }
a750fc0b 10055 init_ppc_proc(env, def);
24951522
AJ		 10056
10057 if (def->insns_flags & PPC_FLOAT) {
10058 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
10059 33, "power-fpu.xml", 0);
10060 }
b4f8d821
AJ		 10061 if (def->insns_flags & PPC_ALTIVEC) {
10062 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
10063 34, "power-altivec.xml", 0);
10064 }
40569b7e 10065 if (def->insns_flags & PPC_SPE) {
688890f7
AJ		 10066 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
10067 34, "power-spe.xml", 0);
10068 }
10069
2985b86b
AF		 10070 qemu_init_vcpu(env);
10071
a750fc0b 10072#if defined(PPC_DUMP_CPU)
3a607854 10073 {
b55266b5 10074 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 10075 switch (env->mmu_model) {
10076 case POWERPC_MMU_32B:
10077 mmu_model = "PowerPC 32";
10078 break;
a750fc0b
JM		 10079 case POWERPC_MMU_SOFT_6xx:
10080 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
10081 break;
10082 case POWERPC_MMU_SOFT_74xx:
10083 mmu_model = "PowerPC 74xx with software driven TLBs";
10084 break;
10085 case POWERPC_MMU_SOFT_4xx:
10086 mmu_model = "PowerPC 4xx with software driven TLBs";
10087 break;
10088 case POWERPC_MMU_SOFT_4xx_Z:
10089 mmu_model = "PowerPC 4xx with software driven TLBs "
10090 "and zones protections";
10091 break;
b4095fed
JM		 10092 case POWERPC_MMU_REAL:
10093 mmu_model = "PowerPC real mode only";
10094 break;
10095 case POWERPC_MMU_MPC8xx:
10096 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 10097 break;
10098 case POWERPC_MMU_BOOKE:
10099 mmu_model = "PowerPC BookE";
10100 break;
01662f3e
AG		 10101 case POWERPC_MMU_BOOKE206:
10102 mmu_model = "PowerPC BookE 2.06";
a750fc0b 10103 break;
b4095fed
JM		 10104 case POWERPC_MMU_601:
10105 mmu_model = "PowerPC 601";
10106 break;
00af685f
JM		 10107#if defined (TARGET_PPC64)
10108 case POWERPC_MMU_64B:
10109 mmu_model = "PowerPC 64";
10110 break;
add78955
JM		 10111 case POWERPC_MMU_620:
10112 mmu_model = "PowerPC 620";
10113 break;
00af685f 10114#endif
a750fc0b
JM		 10115 default:
10116 mmu_model = "Unknown or invalid";
10117 break;
10118 }
10119 switch (env->excp_model) {
10120 case POWERPC_EXCP_STD:
10121 excp_model = "PowerPC";
10122 break;
10123 case POWERPC_EXCP_40x:
10124 excp_model = "PowerPC 40x";
10125 break;
10126 case POWERPC_EXCP_601:
10127 excp_model = "PowerPC 601";
10128 break;
10129 case POWERPC_EXCP_602:
10130 excp_model = "PowerPC 602";
10131 break;
10132 case POWERPC_EXCP_603:
10133 excp_model = "PowerPC 603";
10134 break;
10135 case POWERPC_EXCP_603E:
10136 excp_model = "PowerPC 603e";
10137 break;
10138 case POWERPC_EXCP_604:
10139 excp_model = "PowerPC 604";
10140 break;
10141 case POWERPC_EXCP_7x0:
10142 excp_model = "PowerPC 740/750";
10143 break;
10144 case POWERPC_EXCP_7x5:
10145 excp_model = "PowerPC 745/755";
10146 break;
10147 case POWERPC_EXCP_74xx:
10148 excp_model = "PowerPC 74xx";
10149 break;
a750fc0b
JM		 10150 case POWERPC_EXCP_BOOKE:
10151 excp_model = "PowerPC BookE";
10152 break;
00af685f
JM		 10153#if defined (TARGET_PPC64)
10154 case POWERPC_EXCP_970:
10155 excp_model = "PowerPC 970";
10156 break;
10157#endif
a750fc0b
JM		 10158 default:
10159 excp_model = "Unknown or invalid";
10160 break;
10161 }
10162 switch (env->bus_model) {
10163 case PPC_FLAGS_INPUT_6xx:
10164 bus_model = "PowerPC 6xx";
10165 break;
10166 case PPC_FLAGS_INPUT_BookE:
10167 bus_model = "PowerPC BookE";
10168 break;
10169 case PPC_FLAGS_INPUT_405:
10170 bus_model = "PowerPC 405";
10171 break;
a750fc0b
JM		 10172 case PPC_FLAGS_INPUT_401:
10173 bus_model = "PowerPC 401/403";
10174 break;
b4095fed
JM		 10175 case PPC_FLAGS_INPUT_RCPU:
10176 bus_model = "RCPU / MPC8xx";
10177 break;
00af685f
JM		 10178#if defined (TARGET_PPC64)
10179 case PPC_FLAGS_INPUT_970:
10180 bus_model = "PowerPC 970";
10181 break;
10182#endif
a750fc0b
JM		 10183 default:
10184 bus_model = "Unknown or invalid";
10185 break;
10186 }
10187 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10188 " MMU model : %s\n",
10189 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 10190#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 10191 if (env->tlb != NULL) {
10192 printf(" %d %s TLB in %d ways\n",
10193 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10194 env->nb_ways);
10195 }
f2e63a42 10196#endif
a750fc0b
JM		 10197 printf(" Exceptions model : %s\n"
10198 " Bus model : %s\n",
10199 excp_model, bus_model);
25ba3a68
JM		 10200 printf(" MSR features :\n");
10201 if (env->flags & POWERPC_FLAG_SPE)
10202 printf(" signal processing engine enable"
10203 "\n");
10204 else if (env->flags & POWERPC_FLAG_VRE)
10205 printf(" vector processor enable\n");
10206 if (env->flags & POWERPC_FLAG_TGPR)
10207 printf(" temporary GPRs\n");
10208 else if (env->flags & POWERPC_FLAG_CE)
10209 printf(" critical input enable\n");
10210 if (env->flags & POWERPC_FLAG_SE)
10211 printf(" single-step trace mode\n");
10212 else if (env->flags & POWERPC_FLAG_DWE)
10213 printf(" debug wait enable\n");
10214 else if (env->flags & POWERPC_FLAG_UBLE)
10215 printf(" user BTB lock enable\n");
10216 if (env->flags & POWERPC_FLAG_BE)
10217 printf(" branch-step trace mode\n");
10218 else if (env->flags & POWERPC_FLAG_DE)
10219 printf(" debug interrupt enable\n");
10220 if (env->flags & POWERPC_FLAG_PX)
10221 printf(" inclusive protection\n");
10222 else if (env->flags & POWERPC_FLAG_PMM)
10223 printf(" performance monitor mark\n");
10224 if (env->flags == POWERPC_FLAG_NONE)
10225 printf(" none\n");
4018bae9
JM		 10226 printf(" Time-base/decrementer clock source: %s\n",
10227 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 10228 }
10229 dump_ppc_insns(env);
10230 dump_ppc_sprs(env);
10231 fflush(stdout);
3a607854 10232#endif
a750fc0b 10233}
3fc6c082 10234
2985b86b 10235static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
f0ad8c34 10236{
2985b86b
AF		 10237 ObjectClass *oc = (ObjectClass *)a;
10238 uint32_t pvr = *(uint32_t *)b;
10239 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10240
10241 /* -cpu host does a PVR lookup during construction */
10242 if (unlikely(strcmp(object_class_get_name(oc),
10243 TYPE_HOST_POWERPC_CPU) == 0)) {
10244 return -1;
f0ad8c34 10245 }
f0ad8c34 10246
2985b86b 10247 return pcc->info->pvr == pvr ? 0 : -1;
f0ad8c34
AG		 10248}
10249
2985b86b 10250PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
3fc6c082 10251{
2985b86b
AF		 10252 GSList *list, *item;
10253 PowerPCCPUClass *pcc = NULL;
be40edcd 10254
2985b86b
AF		 10255 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10256 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10257 if (item != NULL) {
10258 pcc = POWERPC_CPU_CLASS(item->data);
3fc6c082 10259 }
2985b86b
AF		 10260 g_slist_free(list);
10261
10262 return pcc;
10263}
10264
10265static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
10266{
10267 ObjectClass *oc = (ObjectClass *)a;
10268 const char *name = b;
ee4e83ed 10269
2985b86b
AF		 10270 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
10271 strcmp(object_class_get_name(oc) + strlen(name),
10272 "-" TYPE_POWERPC_CPU) == 0) {
10273 return 0;
10274 }
10275 return -1;
3fc6c082
FB		 10276}
10277
ee4e83ed 10278#include <ctype.h>
3fc6c082 10279
2985b86b 10280static ObjectClass *ppc_cpu_class_by_name(const char *name)
ee4e83ed 10281{
2985b86b
AF		 10282 GSList *list, *item;
10283 ObjectClass *ret = NULL;
b55266b5 10284 const char *p;
2985b86b 10285 int i, len;
ee4e83ed 10286
2985b86b
AF		 10287 if (strcasecmp(name, "host") == 0) {
10288 if (kvm_enabled()) {
10289 ret = object_class_by_name(TYPE_HOST_POWERPC_CPU);
10290 }
10291 return ret;
a1e98583
DG		 10292 }
10293
ee4e83ed
JM		 10294 /* Check if the given name is a PVR */
10295 len = strlen(name);
10296 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10297 p = name + 2;
10298 goto check_pvr;
10299 } else if (len == 8) {
10300 p = name;
10301 check_pvr:
10302 for (i = 0; i < 8; i++) {
cd390083 10303 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 10304 break;
10305 }
2985b86b
AF		 10306 if (i == 8) {
10307 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
10308 return ret;
f0ad8c34 10309 }
2985b86b 10310 }
f0ad8c34 10311
2985b86b
AF		 10312 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10313 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
10314 if (item != NULL) {
10315 ret = OBJECT_CLASS(item->data);
3fc6c082 10316 }
2985b86b 10317 g_slist_free(list);
ee4e83ed
JM		 10318
10319 return ret;
3fc6c082
FB		 10320}
10321
2985b86b 10322PowerPCCPU *cpu_ppc_init(const char *cpu_model)
3fc6c082 10323{
2985b86b
AF		 10324 PowerPCCPU *cpu;
10325 CPUPPCState *env;
10326 ObjectClass *oc;
10327 Error *err = NULL;
3fc6c082 10328
2985b86b
AF		 10329 oc = ppc_cpu_class_by_name(cpu_model);
10330 if (oc == NULL) {
10331 return NULL;
10332 }
f0ad8c34 10333
2985b86b
AF		 10334 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
10335 env = &cpu->env;
10336
10337 if (tcg_enabled()) {
10338 ppc_translate_init();
3fc6c082 10339 }
2985b86b
AF		 10340
10341 env->cpu_model_str = cpu_model;
10342
10343 ppc_cpu_realize(OBJECT(cpu), &err);
10344 if (err != NULL) {
10345 fprintf(stderr, "%s\n", error_get_pretty(err));
10346 error_free(err);
10347 object_delete(OBJECT(cpu));
10348 return NULL;
10349 }
10350
10351 return cpu;
10352}
10353
10354/* Sort by PVR, ordering special case "host" last. */
10355static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10356{
10357 ObjectClass *oc_a = (ObjectClass *)a;
10358 ObjectClass *oc_b = (ObjectClass *)b;
10359 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10360 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10361 const char *name_a = object_class_get_name(oc_a);
10362 const char *name_b = object_class_get_name(oc_b);
10363
10364 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10365 return 1;
10366 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10367 return -1;
10368 } else {
10369 /* Avoid an integer overflow during subtraction */
10370 if (pcc_a->info->pvr < pcc_b->info->pvr) {
10371 return -1;
10372 } else if (pcc_a->info->pvr > pcc_b->info->pvr) {
10373 return 1;
10374 } else {
10375 return 0;
10376 }
10377 }
10378}
10379
10380static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10381{
10382 ObjectClass *oc = data;
10383 CPUListState *s = user_data;
10384 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10385
10386 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
10387 pcc->info->name, pcc->info->pvr);
10388}
10389
10390void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10391{
10392 CPUListState s = {
10393 .file = f,
10394 .cpu_fprintf = cpu_fprintf,
10395 };
10396 GSList *list;
10397
10398 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10399 list = g_slist_sort(list, ppc_cpu_list_compare);
10400 g_slist_foreach(list, ppc_cpu_list_entry, &s);
10401 g_slist_free(list);
10402}
10403
10404static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10405{
10406 ObjectClass *oc = data;
10407 CpuDefinitionInfoList **first = user_data;
10408 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10409 CpuDefinitionInfoList *entry;
10410 CpuDefinitionInfo *info;
10411
10412 info = g_malloc0(sizeof(*info));
10413 info->name = g_strdup(pcc->info->name);
10414
10415 entry = g_malloc0(sizeof(*entry));
10416 entry->value = info;
10417 entry->next = *first;
10418 *first = entry;
3fc6c082 10419}
1d0cb67d 10420
76b64a7a 10421CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
70b7660a
AL		 10422{
10423 CpuDefinitionInfoList *cpu_list = NULL;
2985b86b 10424 GSList *list;
70b7660a 10425
2985b86b
AF		 10426 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10427 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10428 g_slist_free(list);
70b7660a 10429
2985b86b
AF		 10430 return cpu_list;
10431}
70b7660a 10432
2985b86b
AF		 10433static void ppc_cpu_def_class_init(ObjectClass *oc, void *data)
10434{
10435 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10436 ppc_def_t *info = data;
70b7660a 10437
2985b86b
AF		 10438 pcc->info = info;
10439}
70b7660a 10440
2985b86b
AF		 10441static void ppc_cpu_register_model(const ppc_def_t *def)
10442{
10443 TypeInfo type_info = {
10444 .parent = TYPE_POWERPC_CPU,
10445 .class_init = ppc_cpu_def_class_init,
10446 .class_data = (void *)def,
10447 };
10448
10449 type_info.name = g_strdup_printf("%s-" TYPE_POWERPC_CPU, def->name),
10450 type_register(&type_info);
10451 g_free((gpointer)type_info.name);
70b7660a
AL		 10452}
10453
1d0cb67d
AF		 10454/* CPUClass::reset() */
10455static void ppc_cpu_reset(CPUState *s)
10456{
10457 PowerPCCPU *cpu = POWERPC_CPU(s);
10458 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10459 CPUPPCState *env = &cpu->env;
a1389542
AF		 10460 target_ulong msr;
10461
10462 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
10463 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
10464 log_cpu_state(env, 0);
10465 }
1d0cb67d
AF		 10466
10467 pcc->parent_reset(s);
10468
a1389542
AF		 10469 msr = (target_ulong)0;
10470 if (0) {
10471 /* XXX: find a suitable condition to enable the hypervisor mode */
10472 msr |= (target_ulong)MSR_HVB;
10473 }
10474 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10475 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10476 msr |= (target_ulong)1 << MSR_EP;
10477#if defined(DO_SINGLE_STEP) && 0
10478 /* Single step trace mode */
10479 msr |= (target_ulong)1 << MSR_SE;
10480 msr |= (target_ulong)1 << MSR_BE;
10481#endif
10482#if defined(CONFIG_USER_ONLY)
10483 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10484 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10485 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10486 msr |= (target_ulong)1 << MSR_PR;
10487#else
10488 env->excp_prefix = env->hreset_excp_prefix;
10489 env->nip = env->hreset_vector | env->excp_prefix;
10490 if (env->mmu_model != POWERPC_MMU_REAL) {
10491 ppc_tlb_invalidate_all(env);
10492 }
10493#endif
10494 env->msr = msr & env->msr_mask;
10495#if defined(TARGET_PPC64)
10496 if (env->mmu_model & POWERPC_MMU_64) {
10497 env->msr |= (1ULL << MSR_SF);
10498 }
10499#endif
10500 hreg_compute_hflags(env);
10501 env->reserve_addr = (target_ulong)-1ULL;
10502 /* Be sure no exception or interrupt is pending */
10503 env->pending_interrupts = 0;
10504 env->exception_index = POWERPC_EXCP_NONE;
10505 env->error_code = 0;
2b15811c
DG		 10506
10507#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1bfb37d1
DG		 10508 env->vpa_addr = 0;
10509 env->slb_shadow_addr = 0;
10510 env->slb_shadow_size = 0;
10511 env->dtl_addr = 0;
2b15811c
DG		 10512 env->dtl_size = 0;
10513#endif /* TARGET_PPC64 */
10514
a1389542
AF		 10515 /* Flush all TLBs */
10516 tlb_flush(env, 1);
1d0cb67d
AF		 10517}
10518
6cca7ad6
AF		 10519static void ppc_cpu_initfn(Object *obj)
10520{
10521 PowerPCCPU *cpu = POWERPC_CPU(obj);
2985b86b 10522 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6cca7ad6 10523 CPUPPCState *env = &cpu->env;
2985b86b 10524 ppc_def_t *def = pcc->info;
6cca7ad6
AF		 10525
10526 cpu_exec_init(env);
2985b86b
AF		 10527
10528 env->msr_mask = def->msr_mask;
10529 env->mmu_model = def->mmu_model;
10530 env->excp_model = def->excp_model;
10531 env->bus_model = def->bus_model;
10532 env->insns_flags = def->insns_flags;
10533 env->insns_flags2 = def->insns_flags2;
10534 env->flags = def->flags;
10535 env->bfd_mach = def->bfd_mach;
10536 env->check_pow = def->check_pow;
10537
10538#if defined(TARGET_PPC64)
10539 if (def->sps) {
10540 env->sps = *def->sps;
10541 } else if (env->mmu_model & POWERPC_MMU_64) {
10542 /* Use default sets of page sizes */
10543 static const struct ppc_segment_page_sizes defsps = {
10544 .sps = {
10545 { .page_shift = 12, /* 4K */
10546 .slb_enc = 0,
10547 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10548 },
10549 { .page_shift = 24, /* 16M */
10550 .slb_enc = 0x100,
10551 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10552 },
10553 },
10554 };
10555 env->sps = defsps;
10556 }
10557#endif /* defined(TARGET_PPC64) */
6cca7ad6
AF		 10558}
10559
1d0cb67d
AF		 10560static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10561{
10562 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10563 CPUClass *cc = CPU_CLASS(oc);
10564
10565 pcc->parent_reset = cc->reset;
10566 cc->reset = ppc_cpu_reset;
10567}
10568
10569static const TypeInfo ppc_cpu_type_info = {
10570 .name = TYPE_POWERPC_CPU,
10571 .parent = TYPE_CPU,
10572 .instance_size = sizeof(PowerPCCPU),
6cca7ad6 10573 .instance_init = ppc_cpu_initfn,
2985b86b 10574 .abstract = true,
1d0cb67d
AF		 10575 .class_size = sizeof(PowerPCCPUClass),
10576 .class_init = ppc_cpu_class_init,
10577};
10578
10579static void ppc_cpu_register_types(void)
10580{
2985b86b
AF		 10581 int i;
10582
1d0cb67d 10583 type_register_static(&ppc_cpu_type_info);
2985b86b
AF		 10584
10585 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10586 const ppc_def_t *def = &ppc_defs[i];
10587#if defined(TARGET_PPCEMB)
10588 /* When using the ppcemb target, we only support 440 style cores */
10589 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10590 continue;
10591 }
10592#endif
10593 ppc_cpu_register_model(def);
10594 }
1d0cb67d
AF		 10595}
10596
10597type_init(ppc_cpu_register_types)
Empty description
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