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target-ppc: Register all types for TARGET_PPCEMB
[qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
f7aa5583 5 * Copyright 2011 Freescale Semiconductor, Inc.
3fc6c082
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
76cad711 26#include "disas/bfd.h"
022c62cb 27#include "exec/gdbstub.h"
9c17d615 28#include <sysemu/kvm.h>
a1e98583 29#include "kvm_ppc.h"
9c17d615 30#include "sysemu/arch_init.h"
fe828a4d 31#include "sysemu/cpus.h"
237c0af0 32
3fc6c082
FB		 33//#define PPC_DUMP_CPU
34//#define PPC_DEBUG_SPR
80d11f44
JM		 35//#define PPC_DUMP_SPR_ACCESSES
36#if defined(CONFIG_USER_ONLY)
37#define TODO_USER_ONLY 1
38#endif
3fc6c082 39
e9df014c
JM		 40/* For user-mode emulation, we don't emulate any IRQ controller */
41#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 42#define PPC_IRQ_INIT_FN(name) \
43static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
44{ \
e9df014c
JM		 45}
46#else
a750fc0b 47#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 48void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
49#endif
a750fc0b 50
4e290a0b 51PPC_IRQ_INIT_FN(40x);
e9df014c 52PPC_IRQ_INIT_FN(6xx);
d0dfae6e 53PPC_IRQ_INIT_FN(970);
9d52e907 54PPC_IRQ_INIT_FN(POWER7);
9fdc60bf 55PPC_IRQ_INIT_FN(e500);
e9df014c 56
3fc6c082
FB		 57/* Generic callbacks:
58 * do nothing but store/retrieve spr value
59 */
91f477fd
AG		 60static void spr_load_dump_spr(int sprn)
61{
62#ifdef PPC_DUMP_SPR_ACCESSES
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66#endif
67}
68
45d827d2 69static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 70{
45d827d2 71 gen_load_spr(cpu_gpr[gprn], sprn);
91f477fd
AG		 72 spr_load_dump_spr(sprn);
73}
74
75static void spr_store_dump_spr(int sprn)
76{
45d827d2 77#ifdef PPC_DUMP_SPR_ACCESSES
91f477fd
AG		 78 TCGv_i32 t0 = tcg_const_i32(sprn);
79 gen_helper_store_dump_spr(t0);
80 tcg_temp_free_i32(t0);
45d827d2 81#endif
a496775f
JM		 82}
83
45d827d2 84static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 85{
45d827d2 86 gen_store_spr(sprn, cpu_gpr[gprn]);
91f477fd 87 spr_store_dump_spr(sprn);
45d827d2 88}
a496775f
JM		 89
90#if !defined(CONFIG_USER_ONLY)
ba38ab8d
AG		 91static void spr_write_generic32(void *opaque, int sprn, int gprn)
92{
93#ifdef TARGET_PPC64
94 TCGv t0 = tcg_temp_new();
95 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
96 gen_store_spr(sprn, t0);
97 tcg_temp_free(t0);
98 spr_store_dump_spr(sprn);
99#else
100 spr_write_generic(opaque, sprn, gprn);
101#endif
102}
103
45d827d2 104static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 105{
45d827d2
AJ		 106 TCGv t0 = tcg_temp_new();
107 TCGv t1 = tcg_temp_new();
108 gen_load_spr(t0, sprn);
109 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
110 tcg_gen_and_tl(t0, t0, t1);
111 gen_store_spr(sprn, t0);
112 tcg_temp_free(t0);
113 tcg_temp_free(t1);
a496775f
JM		 114}
115#endif
116
76a66253 117/* SPR common to all PowerPC */
3fc6c082 118/* XER */
45d827d2 119static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 120{
da91a00f 121 gen_read_xer(cpu_gpr[gprn]);
3fc6c082
FB		 122}
123
45d827d2 124static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 125{
da91a00f 126 gen_write_xer(cpu_gpr[gprn]);
3fc6c082
FB		 127}
128
129/* LR */
45d827d2 130static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 131{
45d827d2 132 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 133}
134
45d827d2 135static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 136{
45d827d2 137 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 138}
139
697ab892
DG		 140/* CFAR */
141#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
142static void spr_read_cfar (void *opaque, int gprn, int sprn)
143{
144 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
145}
146
147static void spr_write_cfar (void *opaque, int sprn, int gprn)
148{
149 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
150}
151#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
152
3fc6c082 153/* CTR */
45d827d2 154static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 155{
45d827d2 156 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 157}
158
45d827d2 159static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 160{
45d827d2 161 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 162}
163
164/* User read access to SPR */
165/* USPRx */
166/* UMMCRx */
167/* UPMCx */
168/* USIA */
169/* UDECR */
45d827d2 170static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 171{
45d827d2 172 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 173}
174
76a66253 175/* SPR common to all non-embedded PowerPC */
3fc6c082 176/* DECR */
76a66253 177#if !defined(CONFIG_USER_ONLY)
45d827d2 178static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 179{
630ecca0
TG		 180 if (use_icount) {
181 gen_io_start();
182 }
d0f1562d 183 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 184 if (use_icount) {
185 gen_io_end();
186 gen_stop_exception(opaque);
187 }
3fc6c082
FB		 188}
189
45d827d2 190static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 191{
630ecca0
TG		 192 if (use_icount) {
193 gen_io_start();
194 }
d0f1562d 195 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 196 if (use_icount) {
197 gen_io_end();
198 gen_stop_exception(opaque);
199 }
3fc6c082 200}
76a66253 201#endif
3fc6c082 202
76a66253 203/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 204/* Time base */
45d827d2 205static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 206{
630ecca0
TG		 207 if (use_icount) {
208 gen_io_start();
209 }
d0f1562d 210 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 211 if (use_icount) {
212 gen_io_end();
213 gen_stop_exception(opaque);
214 }
3fc6c082
FB		 215}
216
45d827d2 217static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 218{
630ecca0
TG		 219 if (use_icount) {
220 gen_io_start();
221 }
d0f1562d 222 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
630ecca0
TG		 223 if (use_icount) {
224 gen_io_end();
225 gen_stop_exception(opaque);
226 }
3fc6c082
FB		 227}
228
a062e36c 229__attribute__ (( unused ))
45d827d2 230static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 231{
d0f1562d 232 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 233}
234
235__attribute__ (( unused ))
45d827d2 236static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 237{
d0f1562d 238 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
a062e36c
JM		 239}
240
76a66253 241#if !defined(CONFIG_USER_ONLY)
45d827d2 242static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 243{
630ecca0
TG		 244 if (use_icount) {
245 gen_io_start();
246 }
d0f1562d 247 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 248 if (use_icount) {
249 gen_io_end();
250 gen_stop_exception(opaque);
251 }
3fc6c082
FB		 252}
253
45d827d2 254static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 255{
630ecca0
TG		 256 if (use_icount) {
257 gen_io_start();
258 }
d0f1562d 259 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
630ecca0
TG		 260 if (use_icount) {
261 gen_io_end();
262 gen_stop_exception(opaque);
263 }
3fc6c082 264}
a062e36c
JM		 265
266__attribute__ (( unused ))
45d827d2 267static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 268{
d0f1562d 269 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
a062e36c
JM		 270}
271
272__attribute__ (( unused ))
45d827d2 273static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 274{
d0f1562d 275 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
a062e36c 276}
3a7f009a
DG		 277
278#if defined(TARGET_PPC64)
279__attribute__ (( unused ))
280static void spr_read_purr (void *opaque, int gprn, int sprn)
281{
d0f1562d 282 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
3a7f009a
DG		 283}
284#endif
76a66253 285#endif
3fc6c082 286
76a66253 287#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 288/* IBAT0U...IBAT0U */
289/* IBAT0L...IBAT7L */
45d827d2 290static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 291{
1328c2bf 292 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 293}
294
45d827d2 295static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 296{
1328c2bf 297 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 298}
299
45d827d2 300static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 301{
45d827d2 302 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 303 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 304 tcg_temp_free_i32(t0);
3fc6c082
FB		 305}
306
45d827d2 307static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 308{
8daf1781 309 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
c6c7cf05 310 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 311 tcg_temp_free_i32(t0);
3fc6c082
FB		 312}
313
45d827d2 314static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 315{
45d827d2 316 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
c6c7cf05 317 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 318 tcg_temp_free_i32(t0);
3fc6c082
FB		 319}
320
45d827d2 321static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 322{
8daf1781 323 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
c6c7cf05 324 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 325 tcg_temp_free_i32(t0);
3fc6c082
FB		 326}
327
328/* DBAT0U...DBAT7U */
329/* DBAT0L...DBAT7L */
45d827d2 330static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 331{
1328c2bf 332 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 333}
334
45d827d2 335static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 336{
1328c2bf 337 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 338}
339
45d827d2 340static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 341{
45d827d2 342 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
c6c7cf05 343 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 344 tcg_temp_free_i32(t0);
3fc6c082
FB		 345}
346
45d827d2 347static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 348{
45d827d2 349 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
c6c7cf05 350 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 351 tcg_temp_free_i32(t0);
3fc6c082
FB		 352}
353
45d827d2 354static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 355{
45d827d2 356 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
c6c7cf05 357 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 358 tcg_temp_free_i32(t0);
3fc6c082
FB		 359}
360
45d827d2 361static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 362{
45d827d2 363 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
c6c7cf05 364 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 365 tcg_temp_free_i32(t0);
3fc6c082
FB		 366}
367
368/* SDR1 */
45d827d2 369static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 370{
d523dd00 371 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
3fc6c082
FB		 372}
373
76a66253
JM		 374/* 64 bits PowerPC specific SPRs */
375/* ASR */
578bb252 376#if defined(TARGET_PPC64)
2adab7d6
BS		 377static void spr_read_hior (void *opaque, int gprn, int sprn)
378{
1328c2bf 379 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 380}
381
382static void spr_write_hior (void *opaque, int sprn, int gprn)
383{
384 TCGv t0 = tcg_temp_new();
385 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
1328c2bf 386 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
2adab7d6
BS		 387 tcg_temp_free(t0);
388}
389
45d827d2 390static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 391{
1328c2bf 392 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
76a66253
JM		 393}
394
45d827d2 395static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 396{
d523dd00 397 gen_helper_store_asr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 398}
399#endif
a750fc0b 400#endif
76a66253
JM		 401
402/* PowerPC 601 specific registers */
403/* RTC */
45d827d2 404static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 405{
d0f1562d 406 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
76a66253
JM		 407}
408
45d827d2 409static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 410{
d0f1562d 411 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
76a66253
JM		 412}
413
414#if !defined(CONFIG_USER_ONLY)
45d827d2 415static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 416{
d0f1562d 417 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 418}
419
45d827d2 420static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 421{
d0f1562d 422 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
76a66253 423}
056401ea 424
45d827d2 425static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 426{
427 DisasContext *ctx = opaque;
428
d523dd00 429 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
056401ea 430 /* Must stop the translation as endianness may have changed */
e06fcd75 431 gen_stop_exception(ctx);
056401ea 432}
76a66253
JM		 433#endif
434
435/* Unified bats */
436#if !defined(CONFIG_USER_ONLY)
45d827d2 437static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 438{
1328c2bf 439 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 440}
441
45d827d2 442static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 443{
45d827d2 444 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 445 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 446 tcg_temp_free_i32(t0);
76a66253
JM		 447}
448
45d827d2 449static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 450{
45d827d2 451 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
c6c7cf05 452 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 453 tcg_temp_free_i32(t0);
76a66253
JM		 454}
455#endif
456
457/* PowerPC 40x specific registers */
458#if !defined(CONFIG_USER_ONLY)
45d827d2 459static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 460{
d0f1562d 461 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
76a66253
JM		 462}
463
45d827d2 464static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 465{
d0f1562d 466 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 467}
468
45d827d2 469static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 470{
471 DisasContext *ctx = opaque;
472
d523dd00 473 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
8ecc7913 474 /* We must stop translation as we may have rebooted */
e06fcd75 475 gen_stop_exception(ctx);
8ecc7913
JM		 476}
477
45d827d2 478static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 479{
d523dd00 480 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
c294fc58
JM		 481}
482
45d827d2 483static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 484{
d0f1562d 485 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 486}
487
45d827d2 488static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 489{
d0f1562d 490 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
76a66253
JM		 491}
492#endif
493
494/* PowerPC 403 specific registers */
495/* PBL1 / PBU1 / PBL2 / PBU2 */
496#if !defined(CONFIG_USER_ONLY)
45d827d2 497static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 498{
1328c2bf 499 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 500}
501
45d827d2 502static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 503{
45d827d2 504 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
d523dd00 505 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
45d827d2 506 tcg_temp_free_i32(t0);
76a66253
JM		 507}
508
45d827d2 509static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 510{
45d827d2
AJ		 511 TCGv t0 = tcg_temp_new();
512 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
513 gen_store_spr(SPR_PIR, t0);
514 tcg_temp_free(t0);
3fc6c082 515}
76a66253 516#endif
3fc6c082 517
d34defbc
AJ		 518/* SPE specific registers */
519static void spr_read_spefscr (void *opaque, int gprn, int sprn)
520{
521 TCGv_i32 t0 = tcg_temp_new_i32();
1328c2bf 522 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 523 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
524 tcg_temp_free_i32(t0);
525}
526
527static void spr_write_spefscr (void *opaque, int sprn, int gprn)
528{
529 TCGv_i32 t0 = tcg_temp_new_i32();
530 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
1328c2bf 531 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
d34defbc
AJ		 532 tcg_temp_free_i32(t0);
533}
534
6f5d427d
JM		 535#if !defined(CONFIG_USER_ONLY)
536/* Callback used to write the exception vector base */
45d827d2 537static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 538{
45d827d2 539 TCGv t0 = tcg_temp_new();
1328c2bf 540 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
45d827d2 541 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 542 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
45d827d2 543 gen_store_spr(sprn, t0);
69bd5820 544 tcg_temp_free(t0);
6f5d427d
JM		 545}
546
45d827d2 547static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 548{
549 DisasContext *ctx = opaque;
e9205258 550 int sprn_offs;
6f5d427d
JM		 551
552 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
e9205258 553 sprn_offs = sprn - SPR_BOOKE_IVOR0;
6f5d427d 554 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
e9205258
AG		 555 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
556 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
557 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
6f5d427d
JM		 558 } else {
559 printf("Trying to write an unknown exception vector %d %03x\n",
560 sprn, sprn);
e06fcd75 561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
e9205258 562 return;
6f5d427d 563 }
e9205258
AG		 564
565 TCGv t0 = tcg_temp_new();
1328c2bf 566 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
e9205258 567 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1328c2bf 568 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
e9205258
AG		 569 gen_store_spr(sprn, t0);
570 tcg_temp_free(t0);
6f5d427d
JM		 571}
572#endif
573
cf8358c8
AJ		 574static inline void vscr_init (CPUPPCState *env, uint32_t val)
575{
576 env->vscr = val;
577 /* Altivec always uses round-to-nearest */
578 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
579 set_flush_to_zero(vscr_nj, &env->vec_status);
580}
581
76a66253
JM		 582#if defined(CONFIG_USER_ONLY)
583#define spr_register(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, initial_value) \
585do { \
586 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
587} while (0)
588static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 589 const char *name,
45d827d2
AJ		 590 void (*uea_read)(void *opaque, int gprn, int sprn),
591 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 592 target_ulong initial_value)
593#else
3fc6c082 594static inline void spr_register (CPUPPCState *env, int num,
b55266b5 595 const char *name,
45d827d2
AJ		 596 void (*uea_read)(void *opaque, int gprn, int sprn),
597 void (*uea_write)(void *opaque, int sprn, int gprn),
598 void (*oea_read)(void *opaque, int gprn, int sprn),
599 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 600 target_ulong initial_value)
76a66253 601#endif
3fc6c082 602{
c227f099 603 ppc_spr_t *spr;
3fc6c082
FB		 604
605 spr = &env->spr_cb[num];
606 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 607#if !defined(CONFIG_USER_ONLY)
608 spr->oea_read != NULL || spr->oea_write != NULL ||
609#endif
610 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 611 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
612 exit(1);
613 }
614#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 615 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
616 name, initial_value);
3fc6c082
FB		 617#endif
618 spr->name = name;
619 spr->uea_read = uea_read;
620 spr->uea_write = uea_write;
76a66253 621#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 622 spr->oea_read = oea_read;
623 spr->oea_write = oea_write;
76a66253 624#endif
3fc6c082
FB		 625 env->spr[num] = initial_value;
626}
627
628/* Generic PowerPC SPRs */
629static void gen_spr_generic (CPUPPCState *env)
630{
631 /* Integer processing */
632 spr_register(env, SPR_XER, "XER",
633 &spr_read_xer, &spr_write_xer,
634 &spr_read_xer, &spr_write_xer,
635 0x00000000);
636 /* Branch contol */
637 spr_register(env, SPR_LR, "LR",
638 &spr_read_lr, &spr_write_lr,
639 &spr_read_lr, &spr_write_lr,
640 0x00000000);
641 spr_register(env, SPR_CTR, "CTR",
642 &spr_read_ctr, &spr_write_ctr,
643 &spr_read_ctr, &spr_write_ctr,
644 0x00000000);
645 /* Interrupt processing */
646 spr_register(env, SPR_SRR0, "SRR0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 spr_register(env, SPR_SRR1, "SRR1",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_generic, &spr_write_generic,
653 0x00000000);
654 /* Processor control */
655 spr_register(env, SPR_SPRG0, "SPRG0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SPRG1, "SPRG1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 spr_register(env, SPR_SPRG2, "SPRG2",
664 SPR_NOACCESS, SPR_NOACCESS,
665 &spr_read_generic, &spr_write_generic,
666 0x00000000);
667 spr_register(env, SPR_SPRG3, "SPRG3",
668 SPR_NOACCESS, SPR_NOACCESS,
669 &spr_read_generic, &spr_write_generic,
670 0x00000000);
671}
672
673/* SPR common to all non-embedded PowerPC, including 601 */
674static void gen_spr_ne_601 (CPUPPCState *env)
675{
676 /* Exception processing */
677 spr_register(env, SPR_DSISR, "DSISR",
678 SPR_NOACCESS, SPR_NOACCESS,
679 &spr_read_generic, &spr_write_generic,
680 0x00000000);
681 spr_register(env, SPR_DAR, "DAR",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 0x00000000);
685 /* Timer */
686 spr_register(env, SPR_DECR, "DECR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_decr, &spr_write_decr,
689 0x00000000);
690 /* Memory management */
691 spr_register(env, SPR_SDR1, "SDR1",
692 SPR_NOACCESS, SPR_NOACCESS,
bb593904 693 &spr_read_generic, &spr_write_sdr1,
3fc6c082
FB		 694 0x00000000);
695}
696
697/* BATs 0-3 */
698static void gen_low_BATs (CPUPPCState *env)
699{
f2e63a42 700#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 701 spr_register(env, SPR_IBAT0U, "IBAT0U",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_ibat, &spr_write_ibatu,
704 0x00000000);
705 spr_register(env, SPR_IBAT0L, "IBAT0L",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_ibat, &spr_write_ibatl,
708 0x00000000);
709 spr_register(env, SPR_IBAT1U, "IBAT1U",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_ibat, &spr_write_ibatu,
712 0x00000000);
713 spr_register(env, SPR_IBAT1L, "IBAT1L",
714 SPR_NOACCESS, SPR_NOACCESS,
715 &spr_read_ibat, &spr_write_ibatl,
716 0x00000000);
717 spr_register(env, SPR_IBAT2U, "IBAT2U",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_ibat, &spr_write_ibatu,
720 0x00000000);
721 spr_register(env, SPR_IBAT2L, "IBAT2L",
722 SPR_NOACCESS, SPR_NOACCESS,
723 &spr_read_ibat, &spr_write_ibatl,
724 0x00000000);
725 spr_register(env, SPR_IBAT3U, "IBAT3U",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_ibat, &spr_write_ibatu,
728 0x00000000);
729 spr_register(env, SPR_IBAT3L, "IBAT3L",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_ibat, &spr_write_ibatl,
732 0x00000000);
733 spr_register(env, SPR_DBAT0U, "DBAT0U",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_dbat, &spr_write_dbatu,
736 0x00000000);
737 spr_register(env, SPR_DBAT0L, "DBAT0L",
738 SPR_NOACCESS, SPR_NOACCESS,
739 &spr_read_dbat, &spr_write_dbatl,
740 0x00000000);
741 spr_register(env, SPR_DBAT1U, "DBAT1U",
742 SPR_NOACCESS, SPR_NOACCESS,
743 &spr_read_dbat, &spr_write_dbatu,
744 0x00000000);
745 spr_register(env, SPR_DBAT1L, "DBAT1L",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_dbat, &spr_write_dbatl,
748 0x00000000);
749 spr_register(env, SPR_DBAT2U, "DBAT2U",
750 SPR_NOACCESS, SPR_NOACCESS,
751 &spr_read_dbat, &spr_write_dbatu,
752 0x00000000);
753 spr_register(env, SPR_DBAT2L, "DBAT2L",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_dbat, &spr_write_dbatl,
756 0x00000000);
757 spr_register(env, SPR_DBAT3U, "DBAT3U",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_dbat, &spr_write_dbatu,
760 0x00000000);
761 spr_register(env, SPR_DBAT3L, "DBAT3L",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_dbat, &spr_write_dbatl,
764 0x00000000);
a750fc0b 765 env->nb_BATs += 4;
f2e63a42 766#endif
3fc6c082
FB		 767}
768
769/* BATs 4-7 */
770static void gen_high_BATs (CPUPPCState *env)
771{
f2e63a42 772#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 773 spr_register(env, SPR_IBAT4U, "IBAT4U",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_ibat_h, &spr_write_ibatu_h,
776 0x00000000);
777 spr_register(env, SPR_IBAT4L, "IBAT4L",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_ibat_h, &spr_write_ibatl_h,
780 0x00000000);
781 spr_register(env, SPR_IBAT5U, "IBAT5U",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_ibat_h, &spr_write_ibatu_h,
784 0x00000000);
785 spr_register(env, SPR_IBAT5L, "IBAT5L",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_ibat_h, &spr_write_ibatl_h,
788 0x00000000);
789 spr_register(env, SPR_IBAT6U, "IBAT6U",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_ibat_h, &spr_write_ibatu_h,
792 0x00000000);
793 spr_register(env, SPR_IBAT6L, "IBAT6L",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_ibat_h, &spr_write_ibatl_h,
796 0x00000000);
797 spr_register(env, SPR_IBAT7U, "IBAT7U",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_ibat_h, &spr_write_ibatu_h,
800 0x00000000);
801 spr_register(env, SPR_IBAT7L, "IBAT7L",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_ibat_h, &spr_write_ibatl_h,
804 0x00000000);
805 spr_register(env, SPR_DBAT4U, "DBAT4U",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_dbat_h, &spr_write_dbatu_h,
808 0x00000000);
809 spr_register(env, SPR_DBAT4L, "DBAT4L",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_dbat_h, &spr_write_dbatl_h,
812 0x00000000);
813 spr_register(env, SPR_DBAT5U, "DBAT5U",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_dbat_h, &spr_write_dbatu_h,
816 0x00000000);
817 spr_register(env, SPR_DBAT5L, "DBAT5L",
818 SPR_NOACCESS, SPR_NOACCESS,
819 &spr_read_dbat_h, &spr_write_dbatl_h,
820 0x00000000);
821 spr_register(env, SPR_DBAT6U, "DBAT6U",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_dbat_h, &spr_write_dbatu_h,
824 0x00000000);
825 spr_register(env, SPR_DBAT6L, "DBAT6L",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_dbat_h, &spr_write_dbatl_h,
828 0x00000000);
829 spr_register(env, SPR_DBAT7U, "DBAT7U",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_dbat_h, &spr_write_dbatu_h,
832 0x00000000);
833 spr_register(env, SPR_DBAT7L, "DBAT7L",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_dbat_h, &spr_write_dbatl_h,
836 0x00000000);
a750fc0b 837 env->nb_BATs += 4;
f2e63a42 838#endif
3fc6c082
FB		 839}
840
841/* Generic PowerPC time base */
842static void gen_tbl (CPUPPCState *env)
843{
844 spr_register(env, SPR_VTBL, "TBL",
845 &spr_read_tbl, SPR_NOACCESS,
846 &spr_read_tbl, SPR_NOACCESS,
847 0x00000000);
848 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 849 &spr_read_tbl, SPR_NOACCESS,
850 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 851 0x00000000);
852 spr_register(env, SPR_VTBU, "TBU",
853 &spr_read_tbu, SPR_NOACCESS,
854 &spr_read_tbu, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 857 &spr_read_tbu, SPR_NOACCESS,
858 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 859 0x00000000);
860}
861
76a66253
JM		 862/* Softare table search registers */
863static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
864{
f2e63a42 865#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 866 env->nb_tlb = nb_tlbs;
867 env->nb_ways = nb_ways;
868 env->id_tlbs = 1;
1c53accc 869 env->tlb_type = TLB_6XX;
76a66253
JM		 870 spr_register(env, SPR_DMISS, "DMISS",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_DCMP, "DCMP",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_generic, SPR_NOACCESS,
877 0x00000000);
878 spr_register(env, SPR_HASH1, "HASH1",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_HASH2, "HASH2",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, SPR_NOACCESS,
885 0x00000000);
886 spr_register(env, SPR_IMISS, "IMISS",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, SPR_NOACCESS,
889 0x00000000);
890 spr_register(env, SPR_ICMP, "ICMP",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, SPR_NOACCESS,
893 0x00000000);
894 spr_register(env, SPR_RPA, "RPA",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
f2e63a42 898#endif
76a66253
JM		 899}
900
901/* SPR common to MPC755 and G2 */
902static void gen_spr_G2_755 (CPUPPCState *env)
903{
904 /* SGPRs */
905 spr_register(env, SPR_SPRG4, "SPRG4",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 spr_register(env, SPR_SPRG5, "SPRG5",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 spr_register(env, SPR_SPRG6, "SPRG6",
914 SPR_NOACCESS, SPR_NOACCESS,
915 &spr_read_generic, &spr_write_generic,
916 0x00000000);
917 spr_register(env, SPR_SPRG7, "SPRG7",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
76a66253
JM		 921}
922
3fc6c082
FB		 923/* SPR common to all 7xx PowerPC implementations */
924static void gen_spr_7xx (CPUPPCState *env)
925{
926 /* Breakpoints */
927 /* XXX : not implemented */
928 spr_register(env, SPR_DABR, "DABR",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_IABR, "IABR",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* Cache management */
938 /* XXX : not implemented */
939 spr_register(env, SPR_ICTC, "ICTC",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* Performance monitors */
944 /* XXX : not implemented */
945 spr_register(env, SPR_MMCR0, "MMCR0",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949 /* XXX : not implemented */
950 spr_register(env, SPR_MMCR1, "MMCR1",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* XXX : not implemented */
955 spr_register(env, SPR_PMC1, "PMC1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 /* XXX : not implemented */
960 spr_register(env, SPR_PMC2, "PMC2",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_PMC3, "PMC3",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_PMC4, "PMC4",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* XXX : not implemented */
a750fc0b 975 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, SPR_NOACCESS,
978 0x00000000);
578bb252 979 /* XXX : not implemented */
3fc6c082
FB		 980 spr_register(env, SPR_UMMCR0, "UMMCR0",
981 &spr_read_ureg, SPR_NOACCESS,
982 &spr_read_ureg, SPR_NOACCESS,
983 0x00000000);
578bb252 984 /* XXX : not implemented */
3fc6c082
FB		 985 spr_register(env, SPR_UMMCR1, "UMMCR1",
986 &spr_read_ureg, SPR_NOACCESS,
987 &spr_read_ureg, SPR_NOACCESS,
988 0x00000000);
578bb252 989 /* XXX : not implemented */
3fc6c082
FB		 990 spr_register(env, SPR_UPMC1, "UPMC1",
991 &spr_read_ureg, SPR_NOACCESS,
992 &spr_read_ureg, SPR_NOACCESS,
993 0x00000000);
578bb252 994 /* XXX : not implemented */
3fc6c082
FB		 995 spr_register(env, SPR_UPMC2, "UPMC2",
996 &spr_read_ureg, SPR_NOACCESS,
997 &spr_read_ureg, SPR_NOACCESS,
998 0x00000000);
578bb252 999 /* XXX : not implemented */
3fc6c082
FB		 1000 spr_register(env, SPR_UPMC3, "UPMC3",
1001 &spr_read_ureg, SPR_NOACCESS,
1002 &spr_read_ureg, SPR_NOACCESS,
1003 0x00000000);
578bb252 1004 /* XXX : not implemented */
3fc6c082
FB		 1005 spr_register(env, SPR_UPMC4, "UPMC4",
1006 &spr_read_ureg, SPR_NOACCESS,
1007 &spr_read_ureg, SPR_NOACCESS,
1008 0x00000000);
578bb252 1009 /* XXX : not implemented */
a750fc0b 1010 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 1011 &spr_read_ureg, SPR_NOACCESS,
1012 &spr_read_ureg, SPR_NOACCESS,
1013 0x00000000);
a750fc0b 1014 /* External access control */
3fc6c082 1015 /* XXX : not implemented */
a750fc0b 1016 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 1017 SPR_NOACCESS, SPR_NOACCESS,
1018 &spr_read_generic, &spr_write_generic,
1019 0x00000000);
a750fc0b
JM		 1020}
1021
1022static void gen_spr_thrm (CPUPPCState *env)
1023{
1024 /* Thermal management */
3fc6c082 1025 /* XXX : not implemented */
a750fc0b 1026 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 1027 SPR_NOACCESS, SPR_NOACCESS,
1028 &spr_read_generic, &spr_write_generic,
1029 0x00000000);
1030 /* XXX : not implemented */
a750fc0b 1031 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
3fc6c082 1035 /* XXX : not implemented */
a750fc0b 1036 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040}
1041
1042/* SPR specific to PowerPC 604 implementation */
1043static void gen_spr_604 (CPUPPCState *env)
1044{
1045 /* Processor identification */
1046 spr_register(env, SPR_PIR, "PIR",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_pir,
1049 0x00000000);
1050 /* Breakpoints */
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_IABR, "IABR",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_DABR, "DABR",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, &spr_write_generic,
1060 0x00000000);
1061 /* Performance counters */
1062 /* XXX : not implemented */
1063 spr_register(env, SPR_MMCR0, "MMCR0",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
1067 /* XXX : not implemented */
3fc6c082
FB		 1068 spr_register(env, SPR_PMC1, "PMC1",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 /* XXX : not implemented */
1073 spr_register(env, SPR_PMC2, "PMC2",
1074 SPR_NOACCESS, SPR_NOACCESS,
1075 &spr_read_generic, &spr_write_generic,
1076 0x00000000);
1077 /* XXX : not implemented */
a750fc0b 1078 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_generic, SPR_NOACCESS,
1081 0x00000000);
1082 /* XXX : not implemented */
1083 spr_register(env, SPR_SDA, "SDA",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_generic, SPR_NOACCESS,
1086 0x00000000);
1087 /* External access control */
1088 /* XXX : not implemented */
1089 spr_register(env, SPR_EAR, "EAR",
1090 SPR_NOACCESS, SPR_NOACCESS,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
1093}
1094
76a66253
JM		 1095/* SPR specific to PowerPC 603 implementation */
1096static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1097{
76a66253
JM		 1098 /* External access control */
1099 /* XXX : not implemented */
1100 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1101 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
3fc6c082
FB		 1104}
1105
76a66253
JM		 1106/* SPR specific to PowerPC G2 implementation */
1107static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1108{
76a66253
JM		 1109 /* Memory base address */
1110 /* MBAR */
578bb252 1111 /* XXX : not implemented */
76a66253
JM		 1112 spr_register(env, SPR_MBAR, "MBAR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
76a66253 1116 /* Exception processing */
363be49c 1117 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
363be49c 1121 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* Breakpoints */
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_DABR, "DABR",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_DABR2, "DABR2",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_IABR, "IABR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_IABR2, "IABR2",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_IBCR, "IBCR",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_DBCR, "DBCR",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156}
1157
1158/* SPR specific to PowerPC 602 implementation */
1159static void gen_spr_602 (CPUPPCState *env)
1160{
1161 /* ESA registers */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_SER, "SER",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_SEBR, "SEBR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* XXX : not implemented */
a750fc0b 1173 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* Floating point status */
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_SP, "SP",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 /* XXX : not implemented */
1184 spr_register(env, SPR_LT, "LT",
1185 SPR_NOACCESS, SPR_NOACCESS,
1186 &spr_read_generic, &spr_write_generic,
1187 0x00000000);
1188 /* Watchdog timer */
1189 /* XXX : not implemented */
1190 spr_register(env, SPR_TCR, "TCR",
1191 SPR_NOACCESS, SPR_NOACCESS,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* Interrupt base */
1195 spr_register(env, SPR_IBR, "IBR",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
a750fc0b
JM		 1199 /* XXX : not implemented */
1200 spr_register(env, SPR_IABR, "IABR",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
76a66253
JM		 1204}
1205
1206/* SPR specific to PowerPC 601 implementation */
1207static void gen_spr_601 (CPUPPCState *env)
1208{
1209 /* Multiplication/division register */
1210 /* MQ */
1211 spr_register(env, SPR_MQ, "MQ",
1212 &spr_read_generic, &spr_write_generic,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* RTC registers */
1216 spr_register(env, SPR_601_RTCU, "RTCU",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 SPR_NOACCESS, &spr_write_601_rtcu,
1219 0x00000000);
1220 spr_register(env, SPR_601_VRTCU, "RTCU",
1221 &spr_read_601_rtcu, SPR_NOACCESS,
1222 &spr_read_601_rtcu, SPR_NOACCESS,
1223 0x00000000);
1224 spr_register(env, SPR_601_RTCL, "RTCL",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 SPR_NOACCESS, &spr_write_601_rtcl,
1227 0x00000000);
1228 spr_register(env, SPR_601_VRTCL, "RTCL",
1229 &spr_read_601_rtcl, SPR_NOACCESS,
1230 &spr_read_601_rtcl, SPR_NOACCESS,
1231 0x00000000);
1232 /* Timer */
1233#if 0 /* ? */
1234 spr_register(env, SPR_601_UDECR, "UDECR",
1235 &spr_read_decr, SPR_NOACCESS,
1236 &spr_read_decr, SPR_NOACCESS,
1237 0x00000000);
1238#endif
1239 /* External access control */
1240 /* XXX : not implemented */
1241 spr_register(env, SPR_EAR, "EAR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 /* Memory management */
f2e63a42 1246#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1247 spr_register(env, SPR_IBAT0U, "IBAT0U",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_601_ubat, &spr_write_601_ubatu,
1250 0x00000000);
1251 spr_register(env, SPR_IBAT0L, "IBAT0L",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_601_ubat, &spr_write_601_ubatl,
1254 0x00000000);
1255 spr_register(env, SPR_IBAT1U, "IBAT1U",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_601_ubat, &spr_write_601_ubatu,
1258 0x00000000);
1259 spr_register(env, SPR_IBAT1L, "IBAT1L",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_601_ubat, &spr_write_601_ubatl,
1262 0x00000000);
1263 spr_register(env, SPR_IBAT2U, "IBAT2U",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_601_ubat, &spr_write_601_ubatu,
1266 0x00000000);
1267 spr_register(env, SPR_IBAT2L, "IBAT2L",
1268 SPR_NOACCESS, SPR_NOACCESS,
1269 &spr_read_601_ubat, &spr_write_601_ubatl,
1270 0x00000000);
1271 spr_register(env, SPR_IBAT3U, "IBAT3U",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_601_ubat, &spr_write_601_ubatu,
1274 0x00000000);
1275 spr_register(env, SPR_IBAT3L, "IBAT3L",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_601_ubat, &spr_write_601_ubatl,
1278 0x00000000);
a750fc0b 1279 env->nb_BATs = 4;
f2e63a42 1280#endif
a750fc0b
JM		 1281}
1282
1283static void gen_spr_74xx (CPUPPCState *env)
1284{
1285 /* Processor identification */
1286 spr_register(env, SPR_PIR, "PIR",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_pir,
1289 0x00000000);
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_MMCR2, "MMCR2",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
578bb252 1295 /* XXX : not implemented */
a750fc0b
JM		 1296 spr_register(env, SPR_UMMCR2, "UMMCR2",
1297 &spr_read_ureg, SPR_NOACCESS,
1298 &spr_read_ureg, SPR_NOACCESS,
1299 0x00000000);
1300 /* XXX: not implemented */
1301 spr_register(env, SPR_BAMR, "BAMR",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
578bb252 1305 /* XXX : not implemented */
a750fc0b
JM		 1306 spr_register(env, SPR_MSSCR0, "MSSCR0",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* Hardware implementation registers */
1311 /* XXX : not implemented */
1312 spr_register(env, SPR_HID0, "HID0",
1313 SPR_NOACCESS, SPR_NOACCESS,
1314 &spr_read_generic, &spr_write_generic,
1315 0x00000000);
1316 /* XXX : not implemented */
1317 spr_register(env, SPR_HID1, "HID1",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321 /* Altivec */
1322 spr_register(env, SPR_VRSAVE, "VRSAVE",
1323 &spr_read_generic, &spr_write_generic,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
bd928eba
JM		 1326 /* XXX : not implemented */
1327 spr_register(env, SPR_L2CR, "L2CR",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_generic, &spr_write_generic,
1330 0x00000000);
cf8358c8
AJ		 1331 /* Not strictly an SPR */
1332 vscr_init(env, 0x00010000);
a750fc0b
JM		 1333}
1334
a750fc0b
JM		 1335static void gen_l3_ctrl (CPUPPCState *env)
1336{
1337 /* L3CR */
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_L3CR, "L3CR",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* L3ITCR0 */
578bb252 1344 /* XXX : not implemented */
a750fc0b
JM		 1345 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
a750fc0b 1349 /* L3PM */
578bb252 1350 /* XXX : not implemented */
a750fc0b
JM		 1351 spr_register(env, SPR_L3PM, "L3PM",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355}
a750fc0b 1356
578bb252 1357static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1358{
f2e63a42 1359#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1360 env->nb_tlb = nb_tlbs;
1361 env->nb_ways = nb_ways;
1362 env->id_tlbs = 1;
1c53accc 1363 env->tlb_type = TLB_6XX;
578bb252 1364 /* XXX : not implemented */
a750fc0b
JM		 1365 spr_register(env, SPR_PTEHI, "PTEHI",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
578bb252 1369 /* XXX : not implemented */
a750fc0b
JM		 1370 spr_register(env, SPR_PTELO, "PTELO",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
578bb252 1374 /* XXX : not implemented */
a750fc0b
JM		 1375 spr_register(env, SPR_TLBMISS, "TLBMISS",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
f2e63a42 1379#endif
76a66253
JM		 1380}
1381
01662f3e
AG		 1382#if !defined(CONFIG_USER_ONLY)
1383static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1384{
1385 TCGv t0 = tcg_temp_new();
1386
1387 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1388 gen_store_spr(sprn, t0);
1389 tcg_temp_free(t0);
1390}
1391
1392static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1393{
1ff7854e 1394 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1395 gen_helper_booke206_tlbflush(cpu_env, t0);
1ff7854e 1396 tcg_temp_free_i32(t0);
01662f3e
AG		 1397}
1398
1399static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1400{
1ff7854e 1401 TCGv_i32 t0 = tcg_const_i32(sprn);
c6c7cf05 1402 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1ff7854e 1403 tcg_temp_free_i32(t0);
01662f3e
AG		 1404}
1405#endif
1406
80d11f44 1407static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1408{
80d11f44
JM		 1409 spr_register(env, SPR_USPRG4, "USPRG4",
1410 &spr_read_ureg, SPR_NOACCESS,
1411 &spr_read_ureg, SPR_NOACCESS,
1412 0x00000000);
1413 spr_register(env, SPR_USPRG5, "USPRG5",
1414 &spr_read_ureg, SPR_NOACCESS,
1415 &spr_read_ureg, SPR_NOACCESS,
1416 0x00000000);
1417 spr_register(env, SPR_USPRG6, "USPRG6",
1418 &spr_read_ureg, SPR_NOACCESS,
1419 &spr_read_ureg, SPR_NOACCESS,
1420 0x00000000);
1421 spr_register(env, SPR_USPRG7, "USPRG7",
1422 &spr_read_ureg, SPR_NOACCESS,
1423 &spr_read_ureg, SPR_NOACCESS,
76a66253 1424 0x00000000);
80d11f44
JM		 1425}
1426
1427/* PowerPC BookE SPR */
1428static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1429{
b55266b5 1430 const char *ivor_names[64] = {
80d11f44
JM		 1431 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1432 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1433 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1434 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1435 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1436 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1437 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1438 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1439 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1440 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1441 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1442 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1443 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1444 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1445 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1446 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1447 };
1448#define SPR_BOOKE_IVORxx (-1)
1449 int ivor_sprn[64] = {
1450 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1451 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1452 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1453 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1454 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1455 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1456 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1457 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1458 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
e9205258
AG		 1459 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1460 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
80d11f44
JM		 1461 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1462 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1463 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1464 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1465 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1466 };
1467 int i;
1468
76a66253 1469 /* Interrupt processing */
363be49c 1470 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
363be49c
JM		 1474 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
76a66253
JM		 1478 /* Debug */
1479 /* XXX : not implemented */
1480 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00000000);
1484 /* XXX : not implemented */
1485 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489 /* XXX : not implemented */
76a66253
JM		 1490 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_generic, &spr_write_generic,
1493 0x00000000);
1494 /* XXX : not implemented */
1495 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 /* XXX : not implemented */
76a66253
JM		 1500 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1501 SPR_NOACCESS, SPR_NOACCESS,
e598a9c5 1502 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1503 0x00000000);
1504 /* XXX : not implemented */
1505 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1506 SPR_NOACCESS, SPR_NOACCESS,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 /* XXX : not implemented */
1510 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, &spr_write_generic,
1513 0x00000000);
1514 /* XXX : not implemented */
1515 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1516 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1517 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1518 0x00000000);
1519 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523 spr_register(env, SPR_BOOKE_ESR, "ESR",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
363be49c
JM		 1527 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1528 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1529 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1530 0x00000000);
1531 /* Exception vectors */
80d11f44
JM		 1532 for (i = 0; i < 64; i++) {
1533 if (ivor_mask & (1ULL << i)) {
1534 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1535 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1536 exit(1);
1537 }
1538 spr_register(env, ivor_sprn[i], ivor_names[i],
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_excp_vector,
1541 0x00000000);
1542 }
1543 }
76a66253
JM		 1544 spr_register(env, SPR_BOOKE_PID, "PID",
1545 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1546 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 1547 0x00000000);
1548 spr_register(env, SPR_BOOKE_TCR, "TCR",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_booke_tcr,
1551 0x00000000);
1552 spr_register(env, SPR_BOOKE_TSR, "TSR",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_booke_tsr,
1555 0x00000000);
1556 /* Timer */
1557 spr_register(env, SPR_DECR, "DECR",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_decr, &spr_write_decr,
1560 0x00000000);
1561 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 SPR_NOACCESS, &spr_write_generic,
1564 0x00000000);
1565 /* SPRGs */
1566 spr_register(env, SPR_USPRG0, "USPRG0",
1567 &spr_read_generic, &spr_write_generic,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570 spr_register(env, SPR_SPRG4, "SPRG4",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, &spr_write_generic,
1573 0x00000000);
76a66253
JM		 1574 spr_register(env, SPR_SPRG5, "SPRG5",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
76a66253
JM		 1578 spr_register(env, SPR_SPRG6, "SPRG6",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
76a66253
JM		 1582 spr_register(env, SPR_SPRG7, "SPRG7",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
76a66253
JM		 1586}
1587
01662f3e
AG		 1588static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1589 uint32_t maxsize, uint32_t flags,
1590 uint32_t nentries)
1591{
1592 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1593 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1594 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1595 flags | nentries;
1596}
1597
1598/* BookE 2.06 storage control registers */
1599static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1600 uint32_t *tlbncfg)
363be49c 1601{
f2e63a42 1602#if !defined(CONFIG_USER_ONLY)
b55266b5 1603 const char *mas_names[8] = {
80d11f44
JM		 1604 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1605 };
1606 int mas_sprn[8] = {
1607 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1608 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1609 };
1610 int i;
1611
363be49c 1612 /* TLB assist registers */
578bb252 1613 /* XXX : not implemented */
80d11f44 1614 for (i = 0; i < 8; i++) {
ba38ab8d
AG		 1615 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1616 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1617 uea_write = &spr_write_generic;
1618 }
80d11f44
JM		 1619 if (mas_mask & (1 << i)) {
1620 spr_register(env, mas_sprn[i], mas_names[i],
1621 SPR_NOACCESS, SPR_NOACCESS,
ba38ab8d 1622 &spr_read_generic, uea_write,
80d11f44
JM		 1623 0x00000000);
1624 }
1625 }
363be49c 1626 if (env->nb_pids > 1) {
578bb252 1627 /* XXX : not implemented */
363be49c
JM		 1628 spr_register(env, SPR_BOOKE_PID1, "PID1",
1629 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1630 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1631 0x00000000);
1632 }
1633 if (env->nb_pids > 2) {
578bb252 1634 /* XXX : not implemented */
363be49c
JM		 1635 spr_register(env, SPR_BOOKE_PID2, "PID2",
1636 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1637 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1638 0x00000000);
1639 }
578bb252 1640 /* XXX : not implemented */
65f9ee8d 1641 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1642 SPR_NOACCESS, SPR_NOACCESS,
1643 &spr_read_generic, SPR_NOACCESS,
1644 0x00000000); /* TOFIX */
363be49c
JM		 1645 switch (env->nb_ways) {
1646 case 4:
1647 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, SPR_NOACCESS,
01662f3e 1650 tlbncfg[3]);
363be49c
JM		 1651 /* Fallthru */
1652 case 3:
1653 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1654 SPR_NOACCESS, SPR_NOACCESS,
1655 &spr_read_generic, SPR_NOACCESS,
01662f3e 1656 tlbncfg[2]);
363be49c
JM		 1657 /* Fallthru */
1658 case 2:
1659 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, SPR_NOACCESS,
01662f3e 1662 tlbncfg[1]);
363be49c
JM		 1663 /* Fallthru */
1664 case 1:
1665 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, SPR_NOACCESS,
01662f3e 1668 tlbncfg[0]);
363be49c
JM		 1669 /* Fallthru */
1670 case 0:
1671 default:
1672 break;
1673 }
f2e63a42 1674#endif
01662f3e
AG		 1675
1676 gen_spr_usprgh(env);
363be49c
JM		 1677}
1678
76a66253
JM		 1679/* SPR specific to PowerPC 440 implementation */
1680static void gen_spr_440 (CPUPPCState *env)
1681{
1682 /* Cache control */
1683 /* XXX : not implemented */
1684 spr_register(env, SPR_440_DNV0, "DNV0",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_440_DNV1, "DNV1",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
1694 spr_register(env, SPR_440_DNV2, "DNV2",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_440_DNV3, "DNV3",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* XXX : not implemented */
2662a059 1704 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 /* XXX : not implemented */
2662a059 1709 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
1713 /* XXX : not implemented */
2662a059 1714 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 /* XXX : not implemented */
2662a059 1719 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, &spr_write_generic,
1722 0x00000000);
1723 /* XXX : not implemented */
1724 spr_register(env, SPR_440_DVLIM, "DVLIM",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
1728 /* XXX : not implemented */
1729 spr_register(env, SPR_440_INV0, "INV0",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* XXX : not implemented */
1734 spr_register(env, SPR_440_INV1, "INV1",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_440_INV2, "INV2",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_INV3, "INV3",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* XXX : not implemented */
2662a059 1749 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
1752 0x00000000);
1753 /* XXX : not implemented */
2662a059 1754 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, &spr_write_generic,
1757 0x00000000);
1758 /* XXX : not implemented */
2662a059 1759 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_generic,
1762 0x00000000);
1763 /* XXX : not implemented */
2662a059 1764 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, &spr_write_generic,
1767 0x00000000);
1768 /* XXX : not implemented */
1769 spr_register(env, SPR_440_IVLIM, "IVLIM",
1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, &spr_write_generic,
1772 0x00000000);
1773 /* Cache debug */
1774 /* XXX : not implemented */
2662a059 1775 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, SPR_NOACCESS,
1778 0x00000000);
1779 /* XXX : not implemented */
2662a059 1780 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, SPR_NOACCESS,
1783 0x00000000);
1784 /* XXX : not implemented */
2662a059 1785 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, SPR_NOACCESS,
1788 0x00000000);
1789 /* XXX : not implemented */
2662a059 1790 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, SPR_NOACCESS,
1793 0x00000000);
1794 /* XXX : not implemented */
2662a059 1795 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, SPR_NOACCESS,
1798 0x00000000);
1799 /* XXX : not implemented */
1800 spr_register(env, SPR_440_DBDR, "DBDR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* Processor control */
1805 spr_register(env, SPR_4xx_CCR0, "CCR0",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, SPR_NOACCESS,
1812 0x00000000);
1813 /* Storage control */
1814 spr_register(env, SPR_440_MMUCR, "MMUCR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818}
1819
1820/* SPR shared between PowerPC 40x implementations */
1821static void gen_spr_40x (CPUPPCState *env)
1822{
1823 /* Cache */
5cbdb3a3 1824 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1825 spr_register(env, SPR_40x_DCCR, "DCCR",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_generic,
1828 0x00000000);
5cbdb3a3 1829 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1830 spr_register(env, SPR_40x_ICCR, "ICCR",
1831 SPR_NOACCESS, SPR_NOACCESS,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
5cbdb3a3 1834 /* not emulated, as QEMU do not emulate caches */
2662a059 1835 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_generic, SPR_NOACCESS,
1838 0x00000000);
76a66253
JM		 1839 /* Exception */
1840 spr_register(env, SPR_40x_DEAR, "DEAR",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_generic,
1843 0x00000000);
1844 spr_register(env, SPR_40x_ESR, "ESR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_generic,
1847 0x00000000);
1848 spr_register(env, SPR_40x_EVPR, "EVPR",
1849 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1850 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1851 0x00000000);
1852 spr_register(env, SPR_40x_SRR2, "SRR2",
1853 &spr_read_generic, &spr_write_generic,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
1856 spr_register(env, SPR_40x_SRR3, "SRR3",
1857 &spr_read_generic, &spr_write_generic,
1858 &spr_read_generic, &spr_write_generic,
1859 0x00000000);
1860 /* Timers */
1861 spr_register(env, SPR_40x_PIT, "PIT",
1862 SPR_NOACCESS, SPR_NOACCESS,
1863 &spr_read_40x_pit, &spr_write_40x_pit,
1864 0x00000000);
1865 spr_register(env, SPR_40x_TCR, "TCR",
1866 SPR_NOACCESS, SPR_NOACCESS,
1867 &spr_read_generic, &spr_write_booke_tcr,
1868 0x00000000);
1869 spr_register(env, SPR_40x_TSR, "TSR",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_booke_tsr,
1872 0x00000000);
2662a059
JM		 1873}
1874
1875/* SPR specific to PowerPC 405 implementation */
1876static void gen_spr_405 (CPUPPCState *env)
1877{
1878 /* MMU */
1879 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
2662a059 1883 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1886 0x00700000);
1887 /* Debug interface */
76a66253
JM		 1888 /* XXX : not implemented */
1889 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1890 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1891 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1892 0x00000000);
1893 /* XXX : not implemented */
2662a059
JM		 1894 spr_register(env, SPR_405_DBCR1, "DBCR1",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* XXX : not implemented */
76a66253
JM		 1899 spr_register(env, SPR_40x_DBSR, "DBSR",
1900 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1901 &spr_read_generic, &spr_write_clear,
1902 /* Last reset was system reset */
76a66253
JM		 1903 0x00000300);
1904 /* XXX : not implemented */
2662a059 1905 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
2662a059 1909 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_generic,
1912 0x00000000);
2662a059
JM		 1913 /* XXX : not implemented */
1914 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_generic,
2662a059 1917 0x00000000);
76a66253 1918 /* XXX : not implemented */
2662a059 1919 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1920 SPR_NOACCESS, SPR_NOACCESS,
1921 &spr_read_generic, &spr_write_generic,
1922 0x00000000);
1923 /* XXX : not implemented */
2662a059 1924 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1925 SPR_NOACCESS, SPR_NOACCESS,
1926 &spr_read_generic, &spr_write_generic,
1927 0x00000000);
2662a059 1928 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_405_IAC3, "IAC3",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* XXX : not implemented */
1938 spr_register(env, SPR_405_IAC4, "IAC4",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 /* Storage control */
035feb88 1943 /* XXX: TODO: not implemented */
76a66253
JM		 1944 spr_register(env, SPR_405_SLER, "SLER",
1945 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1946 &spr_read_generic, &spr_write_40x_sler,
76a66253 1947 0x00000000);
2662a059
JM		 1948 spr_register(env, SPR_40x_ZPR, "ZPR",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
76a66253
JM		 1952 /* XXX : not implemented */
1953 spr_register(env, SPR_405_SU0R, "SU0R",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 /* SPRG */
1958 spr_register(env, SPR_USPRG0, "USPRG0",
1959 &spr_read_ureg, SPR_NOACCESS,
1960 &spr_read_ureg, SPR_NOACCESS,
1961 0x00000000);
1962 spr_register(env, SPR_SPRG4, "SPRG4",
1963 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1964 &spr_read_generic, &spr_write_generic,
76a66253 1965 0x00000000);
76a66253
JM		 1966 spr_register(env, SPR_SPRG5, "SPRG5",
1967 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1968 spr_read_generic, &spr_write_generic,
76a66253 1969 0x00000000);
76a66253
JM		 1970 spr_register(env, SPR_SPRG6, "SPRG6",
1971 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1972 spr_read_generic, &spr_write_generic,
76a66253 1973 0x00000000);
76a66253
JM		 1974 spr_register(env, SPR_SPRG7, "SPRG7",
1975 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1976 spr_read_generic, &spr_write_generic,
76a66253 1977 0x00000000);
80d11f44 1978 gen_spr_usprgh(env);
76a66253
JM		 1979}
1980
1981/* SPR shared between PowerPC 401 & 403 implementations */
1982static void gen_spr_401_403 (CPUPPCState *env)
1983{
1984 /* Time base */
1985 spr_register(env, SPR_403_VTBL, "TBL",
1986 &spr_read_tbl, SPR_NOACCESS,
1987 &spr_read_tbl, SPR_NOACCESS,
1988 0x00000000);
1989 spr_register(env, SPR_403_TBL, "TBL",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 SPR_NOACCESS, &spr_write_tbl,
1992 0x00000000);
1993 spr_register(env, SPR_403_VTBU, "TBU",
1994 &spr_read_tbu, SPR_NOACCESS,
1995 &spr_read_tbu, SPR_NOACCESS,
1996 0x00000000);
1997 spr_register(env, SPR_403_TBU, "TBU",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 SPR_NOACCESS, &spr_write_tbu,
2000 0x00000000);
2001 /* Debug */
5cbdb3a3 2002 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 2003 spr_register(env, SPR_403_CDBCR, "CDBCR",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_generic, &spr_write_generic,
2006 0x00000000);
2007}
2008
2662a059
JM		 2009/* SPR specific to PowerPC 401 implementation */
2010static void gen_spr_401 (CPUPPCState *env)
2011{
2012 /* Debug interface */
2013 /* XXX : not implemented */
2014 spr_register(env, SPR_40x_DBCR0, "DBCR",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_40x_dbcr0,
2017 0x00000000);
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_40x_DBSR, "DBSR",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, &spr_write_clear,
2022 /* Last reset was system reset */
2023 0x00000300);
2024 /* XXX : not implemented */
2025 spr_register(env, SPR_40x_DAC1, "DAC",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, &spr_write_generic,
2028 0x00000000);
2029 /* XXX : not implemented */
2030 spr_register(env, SPR_40x_IAC1, "IAC",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 /* Storage control */
035feb88 2035 /* XXX: TODO: not implemented */
2662a059
JM		 2036 spr_register(env, SPR_405_SLER, "SLER",
2037 SPR_NOACCESS, SPR_NOACCESS,
2038 &spr_read_generic, &spr_write_40x_sler,
2039 0x00000000);
5cbdb3a3 2040 /* not emulated, as QEMU never does speculative access */
035feb88
JM		 2041 spr_register(env, SPR_40x_SGR, "SGR",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 &spr_read_generic, &spr_write_generic,
2044 0xFFFFFFFF);
5cbdb3a3 2045 /* not emulated, as QEMU do not emulate caches */
035feb88
JM		 2046 spr_register(env, SPR_40x_DCWR, "DCWR",
2047 SPR_NOACCESS, SPR_NOACCESS,
2048 &spr_read_generic, &spr_write_generic,
2049 0x00000000);
2662a059
JM		 2050}
2051
a750fc0b
JM		 2052static void gen_spr_401x2 (CPUPPCState *env)
2053{
2054 gen_spr_401(env);
2055 spr_register(env, SPR_40x_PID, "PID",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
2059 spr_register(env, SPR_40x_ZPR, "ZPR",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_generic,
2062 0x00000000);
2063}
2064
76a66253
JM		 2065/* SPR specific to PowerPC 403 implementation */
2066static void gen_spr_403 (CPUPPCState *env)
2067{
2662a059
JM		 2068 /* Debug interface */
2069 /* XXX : not implemented */
2070 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_40x_dbcr0,
2073 0x00000000);
2074 /* XXX : not implemented */
2075 spr_register(env, SPR_40x_DBSR, "DBSR",
2076 SPR_NOACCESS, SPR_NOACCESS,
2077 &spr_read_generic, &spr_write_clear,
2078 /* Last reset was system reset */
2079 0x00000300);
2080 /* XXX : not implemented */
2081 spr_register(env, SPR_40x_DAC1, "DAC1",
2082 SPR_NOACCESS, SPR_NOACCESS,
2083 &spr_read_generic, &spr_write_generic,
2084 0x00000000);
578bb252 2085 /* XXX : not implemented */
2662a059
JM		 2086 spr_register(env, SPR_40x_DAC2, "DAC2",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_generic, &spr_write_generic,
2089 0x00000000);
2090 /* XXX : not implemented */
2091 spr_register(env, SPR_40x_IAC1, "IAC1",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_generic, &spr_write_generic,
2094 0x00000000);
578bb252 2095 /* XXX : not implemented */
2662a059
JM		 2096 spr_register(env, SPR_40x_IAC2, "IAC2",
2097 SPR_NOACCESS, SPR_NOACCESS,
2098 &spr_read_generic, &spr_write_generic,
2099 0x00000000);
a750fc0b
JM		 2100}
2101
2102static void gen_spr_403_real (CPUPPCState *env)
2103{
76a66253
JM		 2104 spr_register(env, SPR_403_PBL1, "PBL1",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_403_pbr, &spr_write_403_pbr,
2107 0x00000000);
2108 spr_register(env, SPR_403_PBU1, "PBU1",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_403_pbr, &spr_write_403_pbr,
2111 0x00000000);
2112 spr_register(env, SPR_403_PBL2, "PBL2",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_403_pbr, &spr_write_403_pbr,
2115 0x00000000);
2116 spr_register(env, SPR_403_PBU2, "PBU2",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_403_pbr, &spr_write_403_pbr,
2119 0x00000000);
a750fc0b
JM		 2120}
2121
2122static void gen_spr_403_mmu (CPUPPCState *env)
2123{
2124 /* MMU */
2125 spr_register(env, SPR_40x_PID, "PID",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_generic,
2128 0x00000000);
2662a059 2129 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_generic, &spr_write_generic,
2132 0x00000000);
2133}
2134
2135/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2136static void gen_spr_compress (CPUPPCState *env)
2137{
578bb252 2138 /* XXX : not implemented */
76a66253
JM		 2139 spr_register(env, SPR_401_SKR, "SKR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143}
a750fc0b
JM		 2144
2145#if defined (TARGET_PPC64)
a750fc0b
JM		 2146/* SPR specific to PowerPC 620 */
2147static void gen_spr_620 (CPUPPCState *env)
2148{
082c6681
JM		 2149 /* Processor identification */
2150 spr_register(env, SPR_PIR, "PIR",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_pir,
2153 0x00000000);
2154 spr_register(env, SPR_ASR, "ASR",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_asr, &spr_write_asr,
2157 0x00000000);
2158 /* Breakpoints */
2159 /* XXX : not implemented */
2160 spr_register(env, SPR_IABR, "IABR",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 /* XXX : not implemented */
2165 spr_register(env, SPR_DABR, "DABR",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_SIAR, "SIAR",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, SPR_NOACCESS,
2173 0x00000000);
2174 /* XXX : not implemented */
2175 spr_register(env, SPR_SDA, "SDA",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, SPR_NOACCESS,
2178 0x00000000);
2179 /* XXX : not implemented */
2180 spr_register(env, SPR_620_PMC1R, "PMC1",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, SPR_NOACCESS,
2183 0x00000000);
2184 spr_register(env, SPR_620_PMC1W, "PMC1",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 SPR_NOACCESS, &spr_write_generic,
2187 0x00000000);
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_620_PMC2R, "PMC2",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, SPR_NOACCESS,
2192 0x00000000);
2193 spr_register(env, SPR_620_PMC2W, "PMC2",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 SPR_NOACCESS, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, SPR_NOACCESS,
2201 0x00000000);
2202 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 SPR_NOACCESS, &spr_write_generic,
2205 0x00000000);
2206 /* External access control */
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_EAR, "EAR",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212#if 0 // XXX: check this
578bb252 2213 /* XXX : not implemented */
a750fc0b
JM		 2214 spr_register(env, SPR_620_PMR0, "PMR0",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
578bb252 2218 /* XXX : not implemented */
a750fc0b
JM		 2219 spr_register(env, SPR_620_PMR1, "PMR1",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
578bb252 2223 /* XXX : not implemented */
a750fc0b
JM		 2224 spr_register(env, SPR_620_PMR2, "PMR2",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
578bb252 2228 /* XXX : not implemented */
a750fc0b
JM		 2229 spr_register(env, SPR_620_PMR3, "PMR3",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
578bb252 2233 /* XXX : not implemented */
a750fc0b
JM		 2234 spr_register(env, SPR_620_PMR4, "PMR4",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
578bb252 2238 /* XXX : not implemented */
a750fc0b
JM		 2239 spr_register(env, SPR_620_PMR5, "PMR5",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
578bb252 2243 /* XXX : not implemented */
a750fc0b
JM		 2244 spr_register(env, SPR_620_PMR6, "PMR6",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
578bb252 2248 /* XXX : not implemented */
a750fc0b
JM		 2249 spr_register(env, SPR_620_PMR7, "PMR7",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
578bb252 2253 /* XXX : not implemented */
a750fc0b
JM		 2254 spr_register(env, SPR_620_PMR8, "PMR8",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
578bb252 2258 /* XXX : not implemented */
a750fc0b
JM		 2259 spr_register(env, SPR_620_PMR9, "PMR9",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
578bb252 2263 /* XXX : not implemented */
a750fc0b
JM		 2264 spr_register(env, SPR_620_PMRA, "PMR10",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
578bb252 2268 /* XXX : not implemented */
a750fc0b
JM		 2269 spr_register(env, SPR_620_PMRB, "PMR11",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
578bb252 2273 /* XXX : not implemented */
a750fc0b
JM		 2274 spr_register(env, SPR_620_PMRC, "PMR12",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
578bb252 2278 /* XXX : not implemented */
a750fc0b
JM		 2279 spr_register(env, SPR_620_PMRD, "PMR13",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
578bb252 2283 /* XXX : not implemented */
a750fc0b
JM		 2284 spr_register(env, SPR_620_PMRE, "PMR14",
2285 SPR_NOACCESS, SPR_NOACCESS,
2286 &spr_read_generic, &spr_write_generic,
2287 0x00000000);
578bb252 2288 /* XXX : not implemented */
a750fc0b
JM		 2289 spr_register(env, SPR_620_PMRF, "PMR15",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
082c6681 2293#endif
578bb252 2294 /* XXX : not implemented */
082c6681 2295 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
578bb252 2299 /* XXX : not implemented */
082c6681
JM		 2300 spr_register(env, SPR_620_L2CR, "L2CR",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309}
a750fc0b 2310#endif /* defined (TARGET_PPC64) */
76a66253 2311
80d11f44 2312static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2313{
80d11f44
JM		 2314 /* Exception processing */
2315 spr_register(env, SPR_DSISR, "DSISR",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 spr_register(env, SPR_DAR, "DAR",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* Timer */
2324 spr_register(env, SPR_DECR, "DECR",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_decr, &spr_write_decr,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_MPC_EIE, "EIE",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_EID, "EID",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_MPC_NRI, "NRI",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_MPC_CMPA, "CMPA",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_MPC_CMPB, "CMPB",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_MPC_CMPC, "CMPC",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_MPC_CMPD, "CMPD",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_MPC_ECR, "ECR",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_MPC_DER, "DER",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_MPC_CMPE, "CMPE",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_MPC_CMPF, "CMPF",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_MPC_CMPG, "CMPG",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_MPC_CMPH, "CMPH",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_MPC_BAR, "BAR",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_MPC_DPDR, "DPDR",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_MPC_IMMR, "IMMR",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428}
2429
2430static void gen_spr_5xx (CPUPPCState *env)
2431{
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537}
2538
2539static void gen_spr_8xx (CPUPPCState *env)
2540{
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 /* XXX : not implemented */
2577 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2578 SPR_NOACCESS, SPR_NOACCESS,
2579 &spr_read_generic, &spr_write_generic,
2580 0x00000000);
2581 /* XXX : not implemented */
2582 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2583 SPR_NOACCESS, SPR_NOACCESS,
2584 &spr_read_generic, &spr_write_generic,
2585 0x00000000);
2586 /* XXX : not implemented */
2587 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2588 SPR_NOACCESS, SPR_NOACCESS,
2589 &spr_read_generic, &spr_write_generic,
2590 0x00000000);
2591 /* XXX : not implemented */
2592 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2593 SPR_NOACCESS, SPR_NOACCESS,
2594 &spr_read_generic, &spr_write_generic,
2595 0x00000000);
2596 /* XXX : not implemented */
2597 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2598 SPR_NOACCESS, SPR_NOACCESS,
2599 &spr_read_generic, &spr_write_generic,
2600 0x00000000);
2601 /* XXX : not implemented */
2602 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2603 SPR_NOACCESS, SPR_NOACCESS,
2604 &spr_read_generic, &spr_write_generic,
2605 0x00000000);
2606 /* XXX : not implemented */
2607 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2608 SPR_NOACCESS, SPR_NOACCESS,
2609 &spr_read_generic, &spr_write_generic,
2610 0x00000000);
2611 /* XXX : not implemented */
2612 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2613 SPR_NOACCESS, SPR_NOACCESS,
2614 &spr_read_generic, &spr_write_generic,
2615 0x00000000);
2616 /* XXX : not implemented */
2617 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2618 SPR_NOACCESS, SPR_NOACCESS,
2619 &spr_read_generic, &spr_write_generic,
2620 0x00000000);
2621 /* XXX : not implemented */
2622 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2623 SPR_NOACCESS, SPR_NOACCESS,
2624 &spr_read_generic, &spr_write_generic,
2625 0x00000000);
2626 /* XXX : not implemented */
2627 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2628 SPR_NOACCESS, SPR_NOACCESS,
2629 &spr_read_generic, &spr_write_generic,
2630 0x00000000);
2631 /* XXX : not implemented */
2632 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2633 SPR_NOACCESS, SPR_NOACCESS,
2634 &spr_read_generic, &spr_write_generic,
2635 0x00000000);
2636 /* XXX : not implemented */
2637 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641 /* XXX : not implemented */
2642 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2643 SPR_NOACCESS, SPR_NOACCESS,
2644 &spr_read_generic, &spr_write_generic,
2645 0x00000000);
2646 /* XXX : not implemented */
2647 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2648 SPR_NOACCESS, SPR_NOACCESS,
2649 &spr_read_generic, &spr_write_generic,
2650 0x00000000);
2651 /* XXX : not implemented */
2652 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2653 SPR_NOACCESS, SPR_NOACCESS,
2654 &spr_read_generic, &spr_write_generic,
2655 0x00000000);
2656 /* XXX : not implemented */
2657 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2658 SPR_NOACCESS, SPR_NOACCESS,
2659 &spr_read_generic, &spr_write_generic,
2660 0x00000000);
2661 /* XXX : not implemented */
2662 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2663 SPR_NOACCESS, SPR_NOACCESS,
2664 &spr_read_generic, &spr_write_generic,
2665 0x00000000);
2666}
2667
2668// XXX: TODO
2669/*
2670 * AMR => SPR 29 (Power 2.04)
2671 * CTRL => SPR 136 (Power 2.04)
2672 * CTRL => SPR 152 (Power 2.04)
2673 * SCOMC => SPR 276 (64 bits ?)
2674 * SCOMD => SPR 277 (64 bits ?)
2675 * TBU40 => SPR 286 (Power 2.04 hypv)
2676 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2677 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2678 * HDSISR => SPR 306 (Power 2.04 hypv)
2679 * HDAR => SPR 307 (Power 2.04 hypv)
2680 * PURR => SPR 309 (Power 2.04 hypv)
2681 * HDEC => SPR 310 (Power 2.04 hypv)
2682 * HIOR => SPR 311 (hypv)
2683 * RMOR => SPR 312 (970)
2684 * HRMOR => SPR 313 (Power 2.04 hypv)
2685 * HSRR0 => SPR 314 (Power 2.04 hypv)
2686 * HSRR1 => SPR 315 (Power 2.04 hypv)
2687 * LPCR => SPR 316 (970)
2688 * LPIDR => SPR 317 (970)
80d11f44
JM		 2689 * EPR => SPR 702 (Power 2.04 emb)
2690 * perf => 768-783 (Power 2.04)
2691 * perf => 784-799 (Power 2.04)
2692 * PPR => SPR 896 (Power 2.04)
2693 * EPLC => SPR 947 (Power 2.04 emb)
2694 * EPSC => SPR 948 (Power 2.04 emb)
2695 * DABRX => 1015 (Power 2.04 hypv)
2696 * FPECR => SPR 1022 (?)
2697 * ... and more (thermal management, performance counters, ...)
2698 */
2699
2700/*****************************************************************************/
2701/* Exception vectors models */
2702static void init_excp_4xx_real (CPUPPCState *env)
2703{
2704#if !defined(CONFIG_USER_ONLY)
2705 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2706 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2707 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2708 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2709 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2710 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2711 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2712 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2713 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2714 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2715 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2716 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2717 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2718 /* Hardware reset vector */
2719 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2720#endif
2721}
2722
80d11f44
JM		 2723static void init_excp_4xx_softmmu (CPUPPCState *env)
2724{
2725#if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2727 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2728 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2729 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2730 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2731 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2732 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2734 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2735 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2736 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2737 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2738 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2739 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2740 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2741 env->ivor_mask = 0x0000FFF0UL;
2742 env->ivpr_mask = 0xFFFF0000UL;
2743 /* Hardware reset vector */
2744 env->hreset_vector = 0xFFFFFFFCUL;
2745#endif
2746}
2747
2748static void init_excp_MPC5xx (CPUPPCState *env)
2749{
2750#if !defined(CONFIG_USER_ONLY)
2751 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2752 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2753 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2754 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2755 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2756 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2757 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2758 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2759 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2760 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2761 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2762 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2763 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2764 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2765 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2766 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2767 env->ivor_mask = 0x0000FFF0UL;
2768 env->ivpr_mask = 0xFFFF0000UL;
2769 /* Hardware reset vector */
2770 env->hreset_vector = 0xFFFFFFFCUL;
2771#endif
2772}
2773
2774static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2775{
2776#if !defined(CONFIG_USER_ONLY)
2777 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2778 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2779 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2780 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2781 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2782 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2783 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2784 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2785 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2786 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2787 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2788 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2789 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2790 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2791 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2792 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2793 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2794 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2795 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2796 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2797 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2798 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2799 env->ivor_mask = 0x0000FFF0UL;
2800 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2801 /* Hardware reset vector */
80d11f44 2802 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2803#endif
2804}
2805
80d11f44 2806static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2807{
2808#if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2810 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2811 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2812 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2813 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2814 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2815 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2816 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2817 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2818 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2820 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2821 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2822 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2823 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2824 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2825 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2826 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2827 /* Hardware reset vector */
2828 env->hreset_vector = 0xFFFFFFFCUL;
2829#endif
2830}
2831
e9cd84b9 2832static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
80d11f44
JM		 2833{
2834#if !defined(CONFIG_USER_ONLY)
2835 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2836 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2837 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2838 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
fc1c67bc 2855 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2856 env->ivor_mask = 0x0000FFF7UL;
e9cd84b9 2857 env->ivpr_mask = ivpr_mask;
80d11f44
JM		 2858 /* Hardware reset vector */
2859 env->hreset_vector = 0xFFFFFFFCUL;
2860#endif
2861}
2862
2863static void init_excp_BookE (CPUPPCState *env)
2864{
2865#if !defined(CONFIG_USER_ONLY)
2866 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2872 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2875 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
fc1c67bc 2882 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2883 env->ivor_mask = 0x0000FFE0UL;
2884 env->ivpr_mask = 0xFFFF0000UL;
2885 /* Hardware reset vector */
2886 env->hreset_vector = 0xFFFFFFFCUL;
2887#endif
2888}
2889
2890static void init_excp_601 (CPUPPCState *env)
2891{
2892#if !defined(CONFIG_USER_ONLY)
2893 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2894 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2895 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2896 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2897 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2898 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2899 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2900 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2901 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2902 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2903 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2904 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
fc1c67bc 2905 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2906 /* Hardware reset vector */
80d11f44 2907 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2908#endif
2909}
2910
80d11f44 2911static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2912{
2913#if !defined(CONFIG_USER_ONLY)
082c6681 2914 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2915 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2916 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2917 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2918 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2919 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2920 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2921 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2922 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2923 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2924 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2925 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2926 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2927 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2928 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2929 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2930 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2931 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2932 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
fc1c67bc 2933 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2934 /* Hardware reset vector */
2935 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2936#endif
2937}
2938
80d11f44 2939static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2940{
2941#if !defined(CONFIG_USER_ONLY)
2942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2953 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2954 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2955 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2956 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2957 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2958 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2959 /* Hardware reset vector */
2960 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2961#endif
2962}
2963
2964static void init_excp_604 (CPUPPCState *env)
2965{
2966#if !defined(CONFIG_USER_ONLY)
2967 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2968 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2969 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2970 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2971 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2972 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2973 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2974 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2975 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2976 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2977 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2978 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2979 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2980 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2d3eb7bf 2981 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2982 /* Hardware reset vector */
2d3eb7bf 2983 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2984#endif
2985}
2986
578bb252 2987#if defined(TARGET_PPC64)
e1833e1f
JM		 2988static void init_excp_620 (CPUPPCState *env)
2989{
2990#if !defined(CONFIG_USER_ONLY)
2991 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2992 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2993 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2994 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2995 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2996 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2997 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2998 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2999 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3000 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3001 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 3002 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3003 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3004 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3005 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 3006 /* Hardware reset vector */
faadf50e 3007 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3008#endif
3009}
578bb252 3010#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 3011
3012static void init_excp_7x0 (CPUPPCState *env)
3013{
3014#if !defined(CONFIG_USER_ONLY)
3015 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3016 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3017 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3018 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3019 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3020 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3021 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3022 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3023 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3024 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3025 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3026 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3027 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 3028 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 3029 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3030 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3031 /* Hardware reset vector */
3032 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3033#endif
3034}
3035
bd928eba 3036static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 3037{
3038#if !defined(CONFIG_USER_ONLY)
3039 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3040 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3041 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3042 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3043 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3044 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3045 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3046 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3047 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3048 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3049 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3050 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3051 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3052 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3053 env->hreset_excp_prefix = 0x00000000UL;
bd928eba
JM		 3054 /* Hardware reset vector */
3055 env->hreset_vector = 0xFFFFFFFCUL;
3056#endif
3057}
3058
3059static void init_excp_750cx (CPUPPCState *env)
3060{
3061#if !defined(CONFIG_USER_ONLY)
3062 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3063 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3064 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3065 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3066 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3067 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3068 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3069 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3070 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3071 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3072 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3073 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3074 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 3075 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3076 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3077 /* Hardware reset vector */
3078 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3079#endif
3080}
3081
7a3a6927
JM		 3082/* XXX: Check if this is correct */
3083static void init_excp_7x5 (CPUPPCState *env)
3084{
3085#if !defined(CONFIG_USER_ONLY)
3086 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3087 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3088 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3089 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3090 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3091 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3092 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3093 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3094 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3095 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3096 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 3097 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 3098 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3099 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3100 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3103 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3104 env->hreset_excp_prefix = 0x00000000UL;
7a3a6927
JM		 3105 /* Hardware reset vector */
3106 env->hreset_vector = 0xFFFFFFFCUL;
3107#endif
3108}
3109
e1833e1f
JM		 3110static void init_excp_7400 (CPUPPCState *env)
3111{
3112#if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3115 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3116 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3117 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3119 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3120 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3121 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3122 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3123 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3124 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3125 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3126 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3127 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3128 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3129 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3130 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3131 /* Hardware reset vector */
3132 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3133#endif
3134}
3135
e1833e1f
JM		 3136static void init_excp_7450 (CPUPPCState *env)
3137{
3138#if !defined(CONFIG_USER_ONLY)
3139 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3140 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3141 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3142 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3143 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3144 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3145 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3146 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3147 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3148 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3149 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3150 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3151 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3152 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3153 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3154 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3155 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3156 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3157 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
fc1c67bc 3158 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3159 /* Hardware reset vector */
3160 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3161#endif
3162}
e1833e1f
JM		 3163
3164#if defined (TARGET_PPC64)
3165static void init_excp_970 (CPUPPCState *env)
3166{
3167#if !defined(CONFIG_USER_ONLY)
3168 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3169 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3170 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3171 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3172 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3173 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3174 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3175 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3176 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3177 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3178 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3179 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3180 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3181 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3182 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3183 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3184 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3185 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3186 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3187 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
fc1c67bc 3188 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3189 /* Hardware reset vector */
3190 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3191#endif
3192}
9d52e907
DG		 3193
3194static void init_excp_POWER7 (CPUPPCState *env)
3195{
3196#if !defined(CONFIG_USER_ONLY)
3197 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3198 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3199 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3200 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3201 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3202 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3203 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3204 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3205 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3206 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3207 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3208 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3209 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3210 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3211 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3212 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3213 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3214 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3215 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3216 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3217 env->hreset_excp_prefix = 0;
3218 /* Hardware reset vector */
3219 env->hreset_vector = 0x0000000000000100ULL;
3220#endif
3221}
e1833e1f
JM		 3222#endif
3223
2f462816
JM		 3224/*****************************************************************************/
3225/* Power management enable checks */
3226static int check_pow_none (CPUPPCState *env)
3227{
3228 return 0;
3229}
3230
3231static int check_pow_nocheck (CPUPPCState *env)
3232{
3233 return 1;
3234}
3235
3236static int check_pow_hid0 (CPUPPCState *env)
3237{
3238 if (env->spr[SPR_HID0] & 0x00E00000)
3239 return 1;
3240
3241 return 0;
3242}
3243
4e777442
JM		 3244static int check_pow_hid0_74xx (CPUPPCState *env)
3245{
3246 if (env->spr[SPR_HID0] & 0x00600000)
3247 return 1;
3248
3249 return 0;
3250}
3251
a750fc0b
JM		 3252/*****************************************************************************/
3253/* PowerPC implementations definitions */
76a66253 3254
7856e3a4
AF		 3255#define POWERPC_FAMILY(_name) \
3256 static void \
3257 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3258 \
3259 static const TypeInfo \
3260 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3261 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3262 .parent = TYPE_POWERPC_CPU, \
3263 .abstract = true, \
3264 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3265 }; \
3266 \
3267 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3268 { \
3269 type_register_static( \
3270 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3271 } \
3272 \
3273 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3274 \
3275 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3276
a750fc0b 3277/* PowerPC 401 */
a750fc0b 3278#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3279#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3280#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3281#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3282#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3283#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3284 POWERPC_FLAG_BUS_CLK)
76a66253 3285
a750fc0b
JM		 3286static void init_proc_401 (CPUPPCState *env)
3287{
3288 gen_spr_40x(env);
3289 gen_spr_401_403(env);
3290 gen_spr_401(env);
e1833e1f 3291 init_excp_4xx_real(env);
d63001d1
JM		 3292 env->dcache_line_size = 32;
3293 env->icache_line_size = 32;
4e290a0b
JM		 3294 /* Allocate hardware IRQ controller */
3295 ppc40x_irq_init(env);
ddd1055b
FC		 3296
3297 SET_FIT_PERIOD(12, 16, 20, 24);
3298 SET_WDT_PERIOD(16, 20, 24, 28);
a750fc0b 3299}
76a66253 3300
7856e3a4
AF		 3301POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3302{
3303 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3304
3305 pcc->init_proc = init_proc_401;
3306 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3307 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3308 PPC_WRTEE | PPC_DCR |
3309 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3310 PPC_CACHE_DCBZ |
3311 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3312 PPC_4xx_COMMON | PPC_40x_EXCP;
3313 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3314}
3315
a750fc0b 3316/* PowerPC 401x2 */
a750fc0b
JM		 3317#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3318#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3319#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3320#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3321#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3322#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3323 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 3324
3325static void init_proc_401x2 (CPUPPCState *env)
3326{
3327 gen_spr_40x(env);
3328 gen_spr_401_403(env);
3329 gen_spr_401x2(env);
3330 gen_spr_compress(env);
a750fc0b 3331 /* Memory management */
f2e63a42 3332#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3333 env->nb_tlb = 64;
3334 env->nb_ways = 1;
3335 env->id_tlbs = 0;
1c53accc 3336 env->tlb_type = TLB_EMB;
f2e63a42 3337#endif
e1833e1f 3338 init_excp_4xx_softmmu(env);
d63001d1
JM		 3339 env->dcache_line_size = 32;
3340 env->icache_line_size = 32;
4e290a0b
JM		 3341 /* Allocate hardware IRQ controller */
3342 ppc40x_irq_init(env);
ddd1055b
FC		 3343
3344 SET_FIT_PERIOD(12, 16, 20, 24);
3345 SET_WDT_PERIOD(16, 20, 24, 28);
76a66253
JM		 3346}
3347
7856e3a4
AF		 3348POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3349{
3350 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3351
3352 pcc->init_proc = init_proc_401x2;
3353 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3354 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3355 PPC_DCR | PPC_WRTEE |
3356 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3357 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3358 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3359 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3360 PPC_4xx_COMMON | PPC_40x_EXCP;
3361 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3362}
3363
a750fc0b 3364/* PowerPC 401x3 */
a750fc0b
JM		 3365#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3366#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3367#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3368#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3369#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3370#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3371 POWERPC_FLAG_BUS_CLK)
a750fc0b 3372
e1833e1f 3373static void init_proc_401x3 (CPUPPCState *env)
76a66253 3374{
4e290a0b
JM		 3375 gen_spr_40x(env);
3376 gen_spr_401_403(env);
3377 gen_spr_401(env);
3378 gen_spr_401x2(env);
3379 gen_spr_compress(env);
e1833e1f 3380 init_excp_4xx_softmmu(env);
d63001d1
JM		 3381 env->dcache_line_size = 32;
3382 env->icache_line_size = 32;
4e290a0b
JM		 3383 /* Allocate hardware IRQ controller */
3384 ppc40x_irq_init(env);
ddd1055b
FC		 3385
3386 SET_FIT_PERIOD(12, 16, 20, 24);
3387 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082 3388}
a750fc0b 3389
7856e3a4
AF		 3390POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3391{
3392 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3393
3394 pcc->init_proc = init_proc_401x3;
3395 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3396 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3397 PPC_DCR | PPC_WRTEE |
3398 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3399 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3400 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3401 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3402 PPC_4xx_COMMON | PPC_40x_EXCP;
3403 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3404}
3405
a750fc0b 3406/* IOP480 */
a750fc0b
JM		 3407#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3408#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3409#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3410#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3411#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3412#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3413 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 3414
3415static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3416{
a750fc0b
JM		 3417 gen_spr_40x(env);
3418 gen_spr_401_403(env);
3419 gen_spr_401x2(env);
3420 gen_spr_compress(env);
a750fc0b 3421 /* Memory management */
f2e63a42 3422#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3423 env->nb_tlb = 64;
3424 env->nb_ways = 1;
3425 env->id_tlbs = 0;
1c53accc 3426 env->tlb_type = TLB_EMB;
f2e63a42 3427#endif
e1833e1f 3428 init_excp_4xx_softmmu(env);
d63001d1
JM		 3429 env->dcache_line_size = 32;
3430 env->icache_line_size = 32;
4e290a0b
JM		 3431 /* Allocate hardware IRQ controller */
3432 ppc40x_irq_init(env);
ddd1055b
FC		 3433
3434 SET_FIT_PERIOD(8, 12, 16, 20);
3435 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3436}
3437
7856e3a4
AF		 3438POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3439{
3440 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3441
3442 pcc->init_proc = init_proc_IOP480;
3443 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3444 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3445 PPC_DCR | PPC_WRTEE |
3446 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3447 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3448 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3449 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3450 PPC_4xx_COMMON | PPC_40x_EXCP;
3451 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3452}
3453
a750fc0b 3454/* PowerPC 403 */
a750fc0b 3455#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3456#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3457#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3458#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3459#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3460#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3461 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 3462
3463static void init_proc_403 (CPUPPCState *env)
3fc6c082 3464{
a750fc0b
JM		 3465 gen_spr_40x(env);
3466 gen_spr_401_403(env);
3467 gen_spr_403(env);
3468 gen_spr_403_real(env);
e1833e1f 3469 init_excp_4xx_real(env);
d63001d1
JM		 3470 env->dcache_line_size = 32;
3471 env->icache_line_size = 32;
4e290a0b
JM		 3472 /* Allocate hardware IRQ controller */
3473 ppc40x_irq_init(env);
ddd1055b
FC		 3474
3475 SET_FIT_PERIOD(8, 12, 16, 20);
3476 SET_WDT_PERIOD(16, 20, 24, 28);
3fc6c082
FB		 3477}
3478
7856e3a4
AF		 3479POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3480{
3481 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3482
3483 pcc->init_proc = init_proc_403;
3484 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3485 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3486 PPC_DCR | PPC_WRTEE |
3487 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3488 PPC_CACHE_DCBZ |
3489 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3490 PPC_4xx_COMMON | PPC_40x_EXCP;
3491 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3492}
3493
a750fc0b 3494/* PowerPC 403 GCX */
a750fc0b
JM		 3495#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3496#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3497#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3498#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3499#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3500#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3501 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 3502
3503static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3504{
a750fc0b
JM		 3505 gen_spr_40x(env);
3506 gen_spr_401_403(env);
3507 gen_spr_403(env);
3508 gen_spr_403_real(env);
3509 gen_spr_403_mmu(env);
3510 /* Bus access control */
5cbdb3a3 3511 /* not emulated, as QEMU never does speculative access */
a750fc0b
JM		 3512 spr_register(env, SPR_40x_SGR, "SGR",
3513 SPR_NOACCESS, SPR_NOACCESS,
3514 &spr_read_generic, &spr_write_generic,
3515 0xFFFFFFFF);
5cbdb3a3 3516 /* not emulated, as QEMU do not emulate caches */
a750fc0b
JM		 3517 spr_register(env, SPR_40x_DCWR, "DCWR",
3518 SPR_NOACCESS, SPR_NOACCESS,
3519 &spr_read_generic, &spr_write_generic,
3520 0x00000000);
3521 /* Memory management */
f2e63a42 3522#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3523 env->nb_tlb = 64;
3524 env->nb_ways = 1;
3525 env->id_tlbs = 0;
1c53accc 3526 env->tlb_type = TLB_EMB;
f2e63a42 3527#endif
80d11f44
JM		 3528 init_excp_4xx_softmmu(env);
3529 env->dcache_line_size = 32;
3530 env->icache_line_size = 32;
3531 /* Allocate hardware IRQ controller */
3532 ppc40x_irq_init(env);
ddd1055b
FC		 3533
3534 SET_FIT_PERIOD(8, 12, 16, 20);
3535 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3536}
3537
7856e3a4
AF		 3538POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3539{
3540 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3541
3542 pcc->init_proc = init_proc_403GCX;
3543 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3544 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3545 PPC_DCR | PPC_WRTEE |
3546 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3547 PPC_CACHE_DCBZ |
3548 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3549 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3550 PPC_4xx_COMMON | PPC_40x_EXCP;
3551 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3552}
3553
80d11f44 3554/* PowerPC 405 */
80d11f44
JM		 3555#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3556#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3557#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3558#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3559#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3560#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3561 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3562
3563static void init_proc_405 (CPUPPCState *env)
3564{
3565 /* Time base */
3566 gen_tbl(env);
3567 gen_spr_40x(env);
3568 gen_spr_405(env);
3569 /* Bus access control */
5cbdb3a3 3570 /* not emulated, as QEMU never does speculative access */
80d11f44
JM		 3571 spr_register(env, SPR_40x_SGR, "SGR",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_generic,
3574 0xFFFFFFFF);
5cbdb3a3 3575 /* not emulated, as QEMU do not emulate caches */
80d11f44
JM		 3576 spr_register(env, SPR_40x_DCWR, "DCWR",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 /* Memory management */
3581#if !defined(CONFIG_USER_ONLY)
3582 env->nb_tlb = 64;
3583 env->nb_ways = 1;
3584 env->id_tlbs = 0;
1c53accc 3585 env->tlb_type = TLB_EMB;
80d11f44
JM		 3586#endif
3587 init_excp_4xx_softmmu(env);
3588 env->dcache_line_size = 32;
3589 env->icache_line_size = 32;
3590 /* Allocate hardware IRQ controller */
3591 ppc40x_irq_init(env);
ddd1055b
FC		 3592
3593 SET_FIT_PERIOD(8, 12, 16, 20);
3594 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 3595}
3596
7856e3a4
AF		 3597POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3598{
3599 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3600
3601 pcc->init_proc = init_proc_405;
3602 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3603 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3604 PPC_DCR | PPC_WRTEE |
3605 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3606 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3607 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3608 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3609 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3610 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3611}
3612
80d11f44 3613/* PowerPC 440 EP */
c0a7e81a 3614#define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
80d11f44
JM		 3615#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3616#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3617#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3618#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3619#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3620 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3621
80d11f44
JM		 3622static void init_proc_440EP (CPUPPCState *env)
3623{
3624 /* Time base */
3625 gen_tbl(env);
3626 gen_spr_BookE(env, 0x000000000000FFFFULL);
3627 gen_spr_440(env);
3628 gen_spr_usprgh(env);
3629 /* Processor identification */
3630 spr_register(env, SPR_BOOKE_PIR, "PIR",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_pir,
3633 0x00000000);
3634 /* XXX : not implemented */
3635 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, &spr_write_generic,
3638 0x00000000);
3639 /* XXX : not implemented */
3640 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 /* XXX : not implemented */
3645 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3646 SPR_NOACCESS, SPR_NOACCESS,
3647 &spr_read_generic, &spr_write_generic,
3648 0x00000000);
3649 /* XXX : not implemented */
3650 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 /* XXX : not implemented */
3655 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3656 SPR_NOACCESS, SPR_NOACCESS,
3657 &spr_read_generic, &spr_write_generic,
3658 0x00000000);
3659 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_generic,
3662 0x00000000);
3663 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3664 SPR_NOACCESS, SPR_NOACCESS,
3665 &spr_read_generic, &spr_write_generic,
3666 0x00000000);
3667 /* XXX : not implemented */
3668 spr_register(env, SPR_440_CCR1, "CCR1",
3669 SPR_NOACCESS, SPR_NOACCESS,
3670 &spr_read_generic, &spr_write_generic,
3671 0x00000000);
3672 /* Memory management */
3673#if !defined(CONFIG_USER_ONLY)
3674 env->nb_tlb = 64;
3675 env->nb_ways = 1;
3676 env->id_tlbs = 0;
1c53accc 3677 env->tlb_type = TLB_EMB;
80d11f44
JM		 3678#endif
3679 init_excp_BookE(env);
3680 env->dcache_line_size = 32;
3681 env->icache_line_size = 32;
c0a7e81a 3682 ppc40x_irq_init(env);
ddd1055b
FC		 3683
3684 SET_FIT_PERIOD(12, 16, 20, 24);
3685 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3686}
3687
7856e3a4
AF		 3688POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3689{
3690 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3691
3692 pcc->init_proc = init_proc_440EP;
3693 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3694 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3695 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3696 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3697 PPC_FLOAT_STFIWX |
3698 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3699 PPC_CACHE | PPC_CACHE_ICBI |
3700 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3701 PPC_MEM_TLBSYNC | PPC_MFTB |
3702 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3703 PPC_440_SPEC;
3704 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3705}
3706
80d11f44 3707/* PowerPC 440 GP */
80d11f44
JM		 3708#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3709#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3710#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3711#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3712#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3713#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3714 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3715
80d11f44
JM		 3716static void init_proc_440GP (CPUPPCState *env)
3717{
3718 /* Time base */
3719 gen_tbl(env);
3720 gen_spr_BookE(env, 0x000000000000FFFFULL);
3721 gen_spr_440(env);
3722 gen_spr_usprgh(env);
3723 /* Processor identification */
3724 spr_register(env, SPR_BOOKE_PIR, "PIR",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_pir,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* XXX : not implemented */
3734 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3735 SPR_NOACCESS, SPR_NOACCESS,
3736 &spr_read_generic, &spr_write_generic,
3737 0x00000000);
3738 /* XXX : not implemented */
3739 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3740 SPR_NOACCESS, SPR_NOACCESS,
3741 &spr_read_generic, &spr_write_generic,
3742 0x00000000);
3743 /* XXX : not implemented */
3744 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3745 SPR_NOACCESS, SPR_NOACCESS,
3746 &spr_read_generic, &spr_write_generic,
3747 0x00000000);
3748 /* Memory management */
3749#if !defined(CONFIG_USER_ONLY)
3750 env->nb_tlb = 64;
3751 env->nb_ways = 1;
3752 env->id_tlbs = 0;
1c53accc 3753 env->tlb_type = TLB_EMB;
80d11f44
JM		 3754#endif
3755 init_excp_BookE(env);
3756 env->dcache_line_size = 32;
3757 env->icache_line_size = 32;
3758 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3759
3760 SET_FIT_PERIOD(12, 16, 20, 24);
3761 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 3762}
3763
7856e3a4
AF		 3764POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3765{
3766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3767
3768 pcc->init_proc = init_proc_440GP;
3769 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3770 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3771 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3772 PPC_CACHE | PPC_CACHE_ICBI |
3773 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3774 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3775 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3776 PPC_440_SPEC;
3777 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3778}
3779
80d11f44 3780/* PowerPC 440x4 */
80d11f44
JM		 3781#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3782#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3783#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3784#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3785#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3786#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3787 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3788
80d11f44
JM		 3789static void init_proc_440x4 (CPUPPCState *env)
3790{
3791 /* Time base */
3792 gen_tbl(env);
3793 gen_spr_BookE(env, 0x000000000000FFFFULL);
3794 gen_spr_440(env);
3795 gen_spr_usprgh(env);
3796 /* Processor identification */
3797 spr_register(env, SPR_BOOKE_PIR, "PIR",
3798 SPR_NOACCESS, SPR_NOACCESS,
3799 &spr_read_generic, &spr_write_pir,
3800 0x00000000);
3801 /* XXX : not implemented */
3802 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3803 SPR_NOACCESS, SPR_NOACCESS,
3804 &spr_read_generic, &spr_write_generic,
3805 0x00000000);
3806 /* XXX : not implemented */
3807 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3808 SPR_NOACCESS, SPR_NOACCESS,
3809 &spr_read_generic, &spr_write_generic,
3810 0x00000000);
3811 /* XXX : not implemented */
3812 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3813 SPR_NOACCESS, SPR_NOACCESS,
3814 &spr_read_generic, &spr_write_generic,
3815 0x00000000);
3816 /* XXX : not implemented */
3817 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3818 SPR_NOACCESS, SPR_NOACCESS,
3819 &spr_read_generic, &spr_write_generic,
3820 0x00000000);
3821 /* Memory management */
3822#if !defined(CONFIG_USER_ONLY)
3823 env->nb_tlb = 64;
3824 env->nb_ways = 1;
3825 env->id_tlbs = 0;
1c53accc 3826 env->tlb_type = TLB_EMB;
80d11f44
JM		 3827#endif
3828 init_excp_BookE(env);
d63001d1
JM		 3829 env->dcache_line_size = 32;
3830 env->icache_line_size = 32;
80d11f44 3831 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 3832
3833 SET_FIT_PERIOD(12, 16, 20, 24);
3834 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3835}
3836
7856e3a4
AF		 3837POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3838{
3839 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3840
3841 pcc->init_proc = init_proc_440x4;
3842 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3843 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3844 PPC_DCR | PPC_WRTEE |
3845 PPC_CACHE | PPC_CACHE_ICBI |
3846 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3847 PPC_MEM_TLBSYNC | PPC_MFTB |
3848 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3849 PPC_440_SPEC;
3850 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3851}
3852
80d11f44 3853/* PowerPC 440x5 */
80d11f44
JM		 3854#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3855#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3856#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3857#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3858#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3859#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3860 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
a750fc0b 3861
80d11f44 3862static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3863{
a750fc0b
JM		 3864 /* Time base */
3865 gen_tbl(env);
80d11f44
JM		 3866 gen_spr_BookE(env, 0x000000000000FFFFULL);
3867 gen_spr_440(env);
3868 gen_spr_usprgh(env);
3869 /* Processor identification */
3870 spr_register(env, SPR_BOOKE_PIR, "PIR",
3871 SPR_NOACCESS, SPR_NOACCESS,
3872 &spr_read_generic, &spr_write_pir,
3873 0x00000000);
3874 /* XXX : not implemented */
3875 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3878 0x00000000);
3879 /* XXX : not implemented */
3880 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 /* XXX : not implemented */
3885 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3886 SPR_NOACCESS, SPR_NOACCESS,
3887 &spr_read_generic, &spr_write_generic,
3888 0x00000000);
3889 /* XXX : not implemented */
3890 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_generic,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3904 SPR_NOACCESS, SPR_NOACCESS,
3905 &spr_read_generic, &spr_write_generic,
3906 0x00000000);
3907 /* XXX : not implemented */
3908 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3909 SPR_NOACCESS, SPR_NOACCESS,
3910 &spr_read_generic, &spr_write_generic,
3911 0x00000000);
3912 /* Memory management */
f2e63a42 3913#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3914 env->nb_tlb = 64;
3915 env->nb_ways = 1;
3916 env->id_tlbs = 0;
1c53accc 3917 env->tlb_type = TLB_EMB;
f2e63a42 3918#endif
80d11f44 3919 init_excp_BookE(env);
d63001d1
JM		 3920 env->dcache_line_size = 32;
3921 env->icache_line_size = 32;
95070372 3922 ppc40x_irq_init(env);
ddd1055b
FC		 3923
3924 SET_FIT_PERIOD(12, 16, 20, 24);
3925 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 3926}
3927
7856e3a4
AF		 3928POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3929{
3930 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3931
3932 pcc->init_proc = init_proc_440x5;
3933 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3934 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3935 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3936 PPC_CACHE | PPC_CACHE_ICBI |
3937 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3938 PPC_MEM_TLBSYNC | PPC_MFTB |
3939 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3940 PPC_440_SPEC;
3941 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 3942}
3943
80d11f44 3944/* PowerPC 460 (guessed) */
80d11f44
JM		 3945#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3946#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3947#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3948#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3949#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3950#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3951 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
a750fc0b 3952
80d11f44 3953static void init_proc_460 (CPUPPCState *env)
3fc6c082 3954{
a750fc0b
JM		 3955 /* Time base */
3956 gen_tbl(env);
80d11f44 3957 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3958 gen_spr_440(env);
80d11f44
JM		 3959 gen_spr_usprgh(env);
3960 /* Processor identification */
3961 spr_register(env, SPR_BOOKE_PIR, "PIR",
3962 SPR_NOACCESS, SPR_NOACCESS,
3963 &spr_read_generic, &spr_write_pir,
3964 0x00000000);
3965 /* XXX : not implemented */
3966 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3967 SPR_NOACCESS, SPR_NOACCESS,
3968 &spr_read_generic, &spr_write_generic,
3969 0x00000000);
3970 /* XXX : not implemented */
3971 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_generic,
3974 0x00000000);
3975 /* XXX : not implemented */
3976 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3977 SPR_NOACCESS, SPR_NOACCESS,
3978 &spr_read_generic, &spr_write_generic,
3979 0x00000000);
3980 /* XXX : not implemented */
3981 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3982 SPR_NOACCESS, SPR_NOACCESS,
3983 &spr_read_generic, &spr_write_generic,
3984 0x00000000);
578bb252 3985 /* XXX : not implemented */
a750fc0b
JM		 3986 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3987 SPR_NOACCESS, SPR_NOACCESS,
3988 &spr_read_generic, &spr_write_generic,
3989 0x00000000);
3990 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3991 SPR_NOACCESS, SPR_NOACCESS,
3992 &spr_read_generic, &spr_write_generic,
3993 0x00000000);
3994 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3995 SPR_NOACCESS, SPR_NOACCESS,
3996 &spr_read_generic, &spr_write_generic,
3997 0x00000000);
578bb252 3998 /* XXX : not implemented */
a750fc0b
JM		 3999 spr_register(env, SPR_440_CCR1, "CCR1",
4000 SPR_NOACCESS, SPR_NOACCESS,
4001 &spr_read_generic, &spr_write_generic,
4002 0x00000000);
80d11f44
JM		 4003 /* XXX : not implemented */
4004 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4005 &spr_read_generic, &spr_write_generic,
4006 &spr_read_generic, &spr_write_generic,
4007 0x00000000);
a750fc0b 4008 /* Memory management */
f2e63a42 4009#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4010 env->nb_tlb = 64;
4011 env->nb_ways = 1;
4012 env->id_tlbs = 0;
1c53accc 4013 env->tlb_type = TLB_EMB;
f2e63a42 4014#endif
e1833e1f 4015 init_excp_BookE(env);
d63001d1
JM		 4016 env->dcache_line_size = 32;
4017 env->icache_line_size = 32;
a750fc0b 4018 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 4019
4020 SET_FIT_PERIOD(12, 16, 20, 24);
4021 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4022}
4023
7856e3a4
AF		 4024POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4025{
4026 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4027
4028 pcc->init_proc = init_proc_460;
4029 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 4030 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4031 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4032 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4033 PPC_CACHE | PPC_CACHE_ICBI |
4034 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4035 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4036 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4037 PPC_440_SPEC;
4038 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4039}
4040
80d11f44 4041/* PowerPC 460F (guessed) */
80d11f44
JM		 4042#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
4043#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
4044#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
4045#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
4046#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
4047#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 4048 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
a750fc0b 4049
80d11f44 4050static void init_proc_460F (CPUPPCState *env)
3fc6c082 4051{
a750fc0b
JM		 4052 /* Time base */
4053 gen_tbl(env);
80d11f44 4054 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 4055 gen_spr_440(env);
80d11f44
JM		 4056 gen_spr_usprgh(env);
4057 /* Processor identification */
4058 spr_register(env, SPR_BOOKE_PIR, "PIR",
4059 SPR_NOACCESS, SPR_NOACCESS,
4060 &spr_read_generic, &spr_write_pir,
4061 0x00000000);
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 /* XXX : not implemented */
4078 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4079 SPR_NOACCESS, SPR_NOACCESS,
4080 &spr_read_generic, &spr_write_generic,
4081 0x00000000);
4082 /* XXX : not implemented */
4083 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4084 SPR_NOACCESS, SPR_NOACCESS,
4085 &spr_read_generic, &spr_write_generic,
4086 0x00000000);
4087 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4088 SPR_NOACCESS, SPR_NOACCESS,
4089 &spr_read_generic, &spr_write_generic,
4090 0x00000000);
4091 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 /* XXX : not implemented */
4096 spr_register(env, SPR_440_CCR1, "CCR1",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 /* XXX : not implemented */
4101 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4102 &spr_read_generic, &spr_write_generic,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
a750fc0b 4105 /* Memory management */
f2e63a42 4106#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 4107 env->nb_tlb = 64;
4108 env->nb_ways = 1;
4109 env->id_tlbs = 0;
1c53accc 4110 env->tlb_type = TLB_EMB;
f2e63a42 4111#endif
e1833e1f 4112 init_excp_BookE(env);
d63001d1
JM		 4113 env->dcache_line_size = 32;
4114 env->icache_line_size = 32;
a750fc0b 4115 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 4116
4117 SET_FIT_PERIOD(12, 16, 20, 24);
4118 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 4119}
4120
7856e3a4
AF		 4121POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4122{
4123 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4124
4125 pcc->init_proc = init_proc_460F;
4126 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 4127 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4128 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4129 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4130 PPC_FLOAT_STFIWX | PPC_MFTB |
4131 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4132 PPC_WRTEE | PPC_MFAPIDI |
4133 PPC_CACHE | PPC_CACHE_ICBI |
4134 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4135 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4136 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4137 PPC_440_SPEC;
4138 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4139}
4140
80d11f44 4141/* Freescale 5xx cores (aka RCPU) */
80d11f44
JM		 4142#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4143#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4144#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4145#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4146#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 4147#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4148 POWERPC_FLAG_BUS_CLK)
80d11f44 4149
80d11f44
JM		 4150static void init_proc_MPC5xx (CPUPPCState *env)
4151{
4152 /* Time base */
4153 gen_tbl(env);
4154 gen_spr_5xx_8xx(env);
4155 gen_spr_5xx(env);
4156 init_excp_MPC5xx(env);
4157 env->dcache_line_size = 32;
4158 env->icache_line_size = 32;
4159 /* XXX: TODO: allocate internal IRQ controller */
4160}
4161
7856e3a4
AF		 4162POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4163{
4164 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4165
4166 pcc->init_proc = init_proc_MPC5xx;
4167 pcc->check_pow = check_pow_none;
53116ebf
AF		 4168 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4169 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4170 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4171 PPC_MFTB;
4172 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4173}
4174
80d11f44 4175/* Freescale 8xx cores (aka PowerQUICC) */
80d11f44
JM		 4176#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4177#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4178#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4179#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4180#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 4181#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4182 POWERPC_FLAG_BUS_CLK)
80d11f44 4183
80d11f44
JM		 4184static void init_proc_MPC8xx (CPUPPCState *env)
4185{
4186 /* Time base */
4187 gen_tbl(env);
4188 gen_spr_5xx_8xx(env);
4189 gen_spr_8xx(env);
4190 init_excp_MPC8xx(env);
4191 env->dcache_line_size = 32;
4192 env->icache_line_size = 32;
4193 /* XXX: TODO: allocate internal IRQ controller */
4194}
4195
7856e3a4
AF		 4196POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4197{
4198 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4199
4200 pcc->init_proc = init_proc_MPC8xx;
4201 pcc->check_pow = check_pow_none;
53116ebf
AF		 4202 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4203 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4204 PPC_CACHE_ICBI | PPC_MFTB;
4205 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4206}
4207
80d11f44
JM		 4208/* Freescale 82xx cores (aka PowerQUICC-II) */
4209/* PowerPC G2 */
80d11f44
JM		 4210#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4211#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4212//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4213#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4214#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4215#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4216 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
a750fc0b 4217
80d11f44 4218static void init_proc_G2 (CPUPPCState *env)
3fc6c082 4219{
80d11f44
JM		 4220 gen_spr_ne_601(env);
4221 gen_spr_G2_755(env);
4222 gen_spr_G2(env);
a750fc0b
JM		 4223 /* Time base */
4224 gen_tbl(env);
bd928eba
JM		 4225 /* External access control */
4226 /* XXX : not implemented */
4227 spr_register(env, SPR_EAR, "EAR",
4228 SPR_NOACCESS, SPR_NOACCESS,
4229 &spr_read_generic, &spr_write_generic,
4230 0x00000000);
80d11f44
JM		 4231 /* Hardware implementation register */
4232 /* XXX : not implemented */
4233 spr_register(env, SPR_HID0, "HID0",
4234 SPR_NOACCESS, SPR_NOACCESS,
4235 &spr_read_generic, &spr_write_generic,
4236 0x00000000);
4237 /* XXX : not implemented */
4238 spr_register(env, SPR_HID1, "HID1",
4239 SPR_NOACCESS, SPR_NOACCESS,
4240 &spr_read_generic, &spr_write_generic,
4241 0x00000000);
4242 /* XXX : not implemented */
4243 spr_register(env, SPR_HID2, "HID2",
4244 SPR_NOACCESS, SPR_NOACCESS,
4245 &spr_read_generic, &spr_write_generic,
4246 0x00000000);
a750fc0b 4247 /* Memory management */
80d11f44
JM		 4248 gen_low_BATs(env);
4249 gen_high_BATs(env);
4250 gen_6xx_7xx_soft_tlb(env, 64, 2);
4251 init_excp_G2(env);
d63001d1
JM		 4252 env->dcache_line_size = 32;
4253 env->icache_line_size = 32;
80d11f44
JM		 4254 /* Allocate hardware IRQ controller */
4255 ppc6xx_irq_init(env);
3fc6c082 4256}
a750fc0b 4257
7856e3a4
AF		 4258POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4259{
4260 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4261
4262 pcc->init_proc = init_proc_G2;
4263 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4264 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4265 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4266 PPC_FLOAT_STFIWX |
4267 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4268 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4269 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4270 PPC_SEGMENT | PPC_EXTERN;
4271 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4272}
4273
80d11f44 4274/* PowerPC G2LE */
80d11f44
JM		 4275#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4276#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4277#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4278#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4279#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4280#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4281 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
a750fc0b 4282
80d11f44 4283static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4284{
80d11f44
JM		 4285 gen_spr_ne_601(env);
4286 gen_spr_G2_755(env);
4287 gen_spr_G2(env);
a750fc0b
JM		 4288 /* Time base */
4289 gen_tbl(env);
bd928eba
JM		 4290 /* External access control */
4291 /* XXX : not implemented */
4292 spr_register(env, SPR_EAR, "EAR",
4293 SPR_NOACCESS, SPR_NOACCESS,
4294 &spr_read_generic, &spr_write_generic,
4295 0x00000000);
80d11f44 4296 /* Hardware implementation register */
578bb252 4297 /* XXX : not implemented */
80d11f44 4298 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
80d11f44
JM		 4302 /* XXX : not implemented */
4303 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4304 SPR_NOACCESS, SPR_NOACCESS,
4305 &spr_read_generic, &spr_write_generic,
4306 0x00000000);
578bb252 4307 /* XXX : not implemented */
80d11f44 4308 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4309 SPR_NOACCESS, SPR_NOACCESS,
4310 &spr_read_generic, &spr_write_generic,
4311 0x00000000);
4312 /* Memory management */
80d11f44
JM		 4313 gen_low_BATs(env);
4314 gen_high_BATs(env);
4315 gen_6xx_7xx_soft_tlb(env, 64, 2);
4316 init_excp_G2(env);
d63001d1
JM		 4317 env->dcache_line_size = 32;
4318 env->icache_line_size = 32;
80d11f44
JM		 4319 /* Allocate hardware IRQ controller */
4320 ppc6xx_irq_init(env);
3fc6c082
FB		 4321}
4322
7856e3a4
AF		 4323POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4324{
4325 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4326
4327 pcc->init_proc = init_proc_G2LE;
4328 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4329 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4330 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4331 PPC_FLOAT_STFIWX |
4332 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4333 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4334 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4335 PPC_SEGMENT | PPC_EXTERN;
4336 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4337}
4338
80d11f44 4339/* e200 core */
80d11f44 4340#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
01662f3e 4341#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
80d11f44
JM		 4342#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4343#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4344#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4345#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4346 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4347 POWERPC_FLAG_BUS_CLK)
80d11f44 4348
80d11f44 4349static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4350{
e1833e1f
JM		 4351 /* Time base */
4352 gen_tbl(env);
80d11f44 4353 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4354 /* XXX : not implemented */
80d11f44 4355 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4356 &spr_read_spefscr, &spr_write_spefscr,
4357 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4358 0x00000000);
80d11f44 4359 /* Memory management */
01662f3e 4360 gen_spr_BookE206(env, 0x0000005D, NULL);
80d11f44
JM		 4361 /* XXX : not implemented */
4362 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4363 SPR_NOACCESS, SPR_NOACCESS,
4364 &spr_read_generic, &spr_write_generic,
4365 0x00000000);
80d11f44
JM		 4366 /* XXX : not implemented */
4367 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4368 SPR_NOACCESS, SPR_NOACCESS,
4369 &spr_read_generic, &spr_write_generic,
4370 0x00000000);
578bb252 4371 /* XXX : not implemented */
80d11f44 4372 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
578bb252 4376 /* XXX : not implemented */
80d11f44
JM		 4377 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4378 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4379 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4380 0x00000000);
4381 /* XXX : not implemented */
4382 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4383 SPR_NOACCESS, SPR_NOACCESS,
4384 &spr_read_generic, &spr_write_generic,
4385 0x00000000);
4386 /* XXX : not implemented */
4387 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4388 SPR_NOACCESS, SPR_NOACCESS,
4389 &spr_read_generic, &spr_write_generic,
4390 0x00000000);
4391 /* XXX : not implemented */
4392 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4393 SPR_NOACCESS, SPR_NOACCESS,
4394 &spr_read_generic, &spr_write_generic,
4395 0x00000000);
4396 /* XXX : not implemented */
4397 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4398 SPR_NOACCESS, SPR_NOACCESS,
4399 &spr_read_generic, &spr_write_generic,
4400 0x00000000);
4401 /* XXX : not implemented */
4402 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4403 SPR_NOACCESS, SPR_NOACCESS,
4404 &spr_read_generic, &spr_write_generic,
4405 0x00000000);
4406 /* XXX : not implemented */
4407 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4408 SPR_NOACCESS, SPR_NOACCESS,
4409 &spr_read_generic, &spr_write_generic,
4410 0x00000000);
4411 /* XXX : not implemented */
4412 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4413 SPR_NOACCESS, SPR_NOACCESS,
4414 &spr_read_generic, &spr_write_generic,
4415 0x00000000);
4416 /* XXX : not implemented */
4417 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4418 SPR_NOACCESS, SPR_NOACCESS,
4419 &spr_read_generic, &spr_write_generic,
4420 0x00000000);
4421 /* XXX : not implemented */
4422 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4423 SPR_NOACCESS, SPR_NOACCESS,
4424 &spr_read_generic, &spr_write_generic,
4425 0x00000000);
4426 /* XXX : not implemented */
4427 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4428 SPR_NOACCESS, SPR_NOACCESS,
4429 &spr_read_generic, &spr_write_generic,
4430 0x00000000);
01662f3e
AG		 4431 /* XXX : not implemented */
4432 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4433 SPR_NOACCESS, SPR_NOACCESS,
4434 &spr_read_generic, &spr_write_generic,
4435 0x00000000); /* TOFIX */
80d11f44
JM		 4436 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4437 SPR_NOACCESS, SPR_NOACCESS,
4438 &spr_read_generic, &spr_write_generic,
4439 0x00000000);
4440 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4441 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4442 &spr_read_generic, &spr_write_generic,
4443 0x00000000);
f2e63a42 4444#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4445 env->nb_tlb = 64;
4446 env->nb_ways = 1;
4447 env->id_tlbs = 0;
1c53accc 4448 env->tlb_type = TLB_EMB;
f2e63a42 4449#endif
e9cd84b9 4450 init_excp_e200(env, 0xFFFF0000UL);
d63001d1
JM		 4451 env->dcache_line_size = 32;
4452 env->icache_line_size = 32;
e1833e1f 4453 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4454}
a750fc0b 4455
7856e3a4
AF		 4456POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4457{
4458 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4459
4460 pcc->init_proc = init_proc_e200;
4461 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4462 /* XXX: unimplemented instructions:
4463 * dcblc
4464 * dcbtlst
4465 * dcbtstls
4466 * icblc
4467 * icbtls
4468 * tlbivax
4469 * all SPE multiply-accumulate instructions
4470 */
4471 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4472 PPC_SPE | PPC_SPE_SINGLE |
4473 PPC_WRTEE | PPC_RFDI |
4474 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4475 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4476 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4477 PPC_BOOKE;
4478 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4479}
4480
80d11f44 4481/* e300 core */
80d11f44
JM		 4482#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4483#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4484#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4485#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4486#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4487#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4488 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
a750fc0b 4489
80d11f44 4490static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4491{
80d11f44
JM		 4492 gen_spr_ne_601(env);
4493 gen_spr_603(env);
a750fc0b
JM		 4494 /* Time base */
4495 gen_tbl(env);
80d11f44
JM		 4496 /* hardware implementation registers */
4497 /* XXX : not implemented */
4498 spr_register(env, SPR_HID0, "HID0",
4499 SPR_NOACCESS, SPR_NOACCESS,
4500 &spr_read_generic, &spr_write_generic,
4501 0x00000000);
4502 /* XXX : not implemented */
4503 spr_register(env, SPR_HID1, "HID1",
4504 SPR_NOACCESS, SPR_NOACCESS,
4505 &spr_read_generic, &spr_write_generic,
4506 0x00000000);
8daf1781
TM		 4507 /* XXX : not implemented */
4508 spr_register(env, SPR_HID2, "HID2",
4509 SPR_NOACCESS, SPR_NOACCESS,
4510 &spr_read_generic, &spr_write_generic,
4511 0x00000000);
80d11f44
JM		 4512 /* Memory management */
4513 gen_low_BATs(env);
8daf1781 4514 gen_high_BATs(env);
80d11f44
JM		 4515 gen_6xx_7xx_soft_tlb(env, 64, 2);
4516 init_excp_603(env);
4517 env->dcache_line_size = 32;
4518 env->icache_line_size = 32;
4519 /* Allocate hardware IRQ controller */
4520 ppc6xx_irq_init(env);
4521}
4522
7856e3a4
AF		 4523POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4524{
4525 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4526
4527 pcc->init_proc = init_proc_e300;
4528 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4529 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4530 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4531 PPC_FLOAT_STFIWX |
4532 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4533 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4534 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4535 PPC_SEGMENT | PPC_EXTERN;
4536 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4537}
4538
bd5ea513 4539/* e500v1 core */
bd5ea513 4540#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
01662f3e 4541#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4542#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4543#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4544#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4545#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4546 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4547 POWERPC_FLAG_BUS_CLK)
bd5ea513
AJ		 4548
4549/* e500v2 core */
bd5ea513 4550#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
01662f3e 4551#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4552#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4553#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4554#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4555#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4556 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4557 POWERPC_FLAG_BUS_CLK)
80d11f44 4558
f7aa5583 4559/* e500mc core */
f7aa5583
VS		 4560#define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4561#define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4562#define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4563#define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4564/* Fixme: figure out the correct flag for e500mc */
4565#define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4566#define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4567 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
f7aa5583 4568
b81ccf8a 4569/* e5500 core */
b81ccf8a
AG		 4570#define POWERPC_MSRM_e5500 (0x000000009402FB36ULL)
4571#define POWERPC_MMU_e5500 (POWERPC_MMU_BOOKE206)
4572#define POWERPC_EXCP_e5500 (POWERPC_EXCP_BOOKE)
4573#define POWERPC_INPUT_e5500 (PPC_FLAGS_INPUT_BookE)
4574/* Fixme: figure out the correct flag for e5500 */
4575#define POWERPC_BFDM_e5500 (bfd_mach_ppc_e500)
4576#define POWERPC_FLAG_e5500 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4577 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
b81ccf8a
AG		 4578
4579#if !defined(CONFIG_USER_ONLY)
4580static void spr_write_mas73(void *opaque, int sprn, int gprn)
4581{
4582 TCGv val = tcg_temp_new();
4583 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4584 gen_store_spr(SPR_BOOKE_MAS3, val);
cfee0218 4585 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
b81ccf8a
AG		 4586 gen_store_spr(SPR_BOOKE_MAS7, val);
4587 tcg_temp_free(val);
4588}
4589
4590static void spr_read_mas73(void *opaque, int gprn, int sprn)
4591{
4592 TCGv mas7 = tcg_temp_new();
4593 TCGv mas3 = tcg_temp_new();
4594 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4595 tcg_gen_shli_tl(mas7, mas7, 32);
4596 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4597 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4598 tcg_temp_free(mas3);
4599 tcg_temp_free(mas7);
4600}
4601
b81ccf8a
AG		 4602#endif
4603
f7aa5583
VS		 4604enum fsl_e500_version {
4605 fsl_e500v1,
4606 fsl_e500v2,
4607 fsl_e500mc,
b81ccf8a 4608 fsl_e5500,
f7aa5583
VS		 4609};
4610
01662f3e 4611static void init_proc_e500 (CPUPPCState *env, int version)
80d11f44 4612{
01662f3e 4613 uint32_t tlbncfg[2];
b81ccf8a 4614 uint64_t ivor_mask;
e9cd84b9 4615 uint64_t ivpr_mask = 0xFFFF0000ULL;
a496e8ee
AG		 4616 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4617 | 0x0020; /* 32 kb */
01662f3e
AG		 4618#if !defined(CONFIG_USER_ONLY)
4619 int i;
4620#endif
4621
80d11f44
JM		 4622 /* Time base */
4623 gen_tbl(env);
01662f3e
AG		 4624 /*
4625 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4626 * complain when accessing them.
4627 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4628 */
b81ccf8a
AG		 4629 switch (version) {
4630 case fsl_e500v1:
4631 case fsl_e500v2:
4632 default:
4633 ivor_mask = 0x0000000F0000FFFFULL;
4634 break;
4635 case fsl_e500mc:
4636 case fsl_e5500:
4637 ivor_mask = 0x000003FE0000FFFFULL;
4638 break;
2c9732db
AG		 4639 }
4640 gen_spr_BookE(env, ivor_mask);
80d11f44
JM		 4641 /* Processor identification */
4642 spr_register(env, SPR_BOOKE_PIR, "PIR",
4643 SPR_NOACCESS, SPR_NOACCESS,
4644 &spr_read_generic, &spr_write_pir,
4645 0x00000000);
4646 /* XXX : not implemented */
4647 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4648 &spr_read_spefscr, &spr_write_spefscr,
4649 &spr_read_spefscr, &spr_write_spefscr,
80d11f44 4650 0x00000000);
892c587f 4651#if !defined(CONFIG_USER_ONLY)
80d11f44 4652 /* Memory management */
80d11f44 4653 env->nb_pids = 3;
01662f3e
AG		 4654 env->nb_ways = 2;
4655 env->id_tlbs = 0;
4656 switch (version) {
f7aa5583 4657 case fsl_e500v1:
01662f3e
AG		 4658 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4659 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4660 break;
f7aa5583 4661 case fsl_e500v2:
01662f3e
AG		 4662 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4663 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
f7aa5583
VS		 4664 break;
4665 case fsl_e500mc:
b81ccf8a 4666 case fsl_e5500:
f7aa5583
VS		 4667 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4668 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
892c587f
AG		 4669 break;
4670 default:
4671 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4672 }
4673#endif
4674 /* Cache sizes */
4675 switch (version) {
4676 case fsl_e500v1:
4677 case fsl_e500v2:
4678 env->dcache_line_size = 32;
4679 env->icache_line_size = 32;
4680 break;
4681 case fsl_e500mc:
b81ccf8a 4682 case fsl_e5500:
f7aa5583
VS		 4683 env->dcache_line_size = 64;
4684 env->icache_line_size = 64;
a496e8ee 4685 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
01662f3e
AG		 4686 break;
4687 default:
4688 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4689 }
01662f3e 4690 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
80d11f44
JM		 4691 /* XXX : not implemented */
4692 spr_register(env, SPR_HID0, "HID0",
4693 SPR_NOACCESS, SPR_NOACCESS,
4694 &spr_read_generic, &spr_write_generic,
4695 0x00000000);
4696 /* XXX : not implemented */
4697 spr_register(env, SPR_HID1, "HID1",
4698 SPR_NOACCESS, SPR_NOACCESS,
4699 &spr_read_generic, &spr_write_generic,
4700 0x00000000);
4701 /* XXX : not implemented */
4702 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4703 SPR_NOACCESS, SPR_NOACCESS,
4704 &spr_read_generic, &spr_write_generic,
4705 0x00000000);
4706 /* XXX : not implemented */
4707 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4708 SPR_NOACCESS, SPR_NOACCESS,
4709 &spr_read_generic, &spr_write_generic,
4710 0x00000000);
4711 /* XXX : not implemented */
4712 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4713 SPR_NOACCESS, SPR_NOACCESS,
4714 &spr_read_generic, &spr_write_generic,
4715 0x00000000);
578bb252 4716 /* XXX : not implemented */
a750fc0b
JM		 4717 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4718 SPR_NOACCESS, SPR_NOACCESS,
4719 &spr_read_generic, &spr_write_generic,
4720 0x00000000);
80d11f44
JM		 4721 /* XXX : not implemented */
4722 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4723 SPR_NOACCESS, SPR_NOACCESS,
4724 &spr_read_generic, &spr_write_generic,
4725 0x00000000);
80d11f44
JM		 4726 /* XXX : not implemented */
4727 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4728 SPR_NOACCESS, SPR_NOACCESS,
4729 &spr_read_generic, &spr_write_generic,
4730 0x00000000);
578bb252 4731 /* XXX : not implemented */
80d11f44 4732 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4733 SPR_NOACCESS, SPR_NOACCESS,
4734 &spr_read_generic, &spr_write_generic,
a496e8ee 4735 l1cfg0);
578bb252 4736 /* XXX : not implemented */
80d11f44
JM		 4737 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4738 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 4739 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44
JM		 4740 0x00000000);
4741 /* XXX : not implemented */
4742 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4743 SPR_NOACCESS, SPR_NOACCESS,
4744 &spr_read_generic, &spr_write_generic,
4745 0x00000000);
80d11f44
JM		 4746 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4747 SPR_NOACCESS, SPR_NOACCESS,
4748 &spr_read_generic, &spr_write_generic,
4749 0x00000000);
4750 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4751 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4752 &spr_read_generic, &spr_write_generic,
4753 0x00000000);
01662f3e
AG		 4754 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4755 SPR_NOACCESS, SPR_NOACCESS,
4756 &spr_read_generic, &spr_write_booke206_mmucsr0,
4757 0x00000000);
b81ccf8a
AG		 4758 spr_register(env, SPR_BOOKE_EPR, "EPR",
4759 SPR_NOACCESS, SPR_NOACCESS,
68c2dd70 4760 &spr_read_generic, SPR_NOACCESS,
b81ccf8a
AG		 4761 0x00000000);
4762 /* XXX better abstract into Emb.xxx features */
4763 if (version == fsl_e5500) {
4764 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4765 SPR_NOACCESS, SPR_NOACCESS,
4766 &spr_read_generic, &spr_write_generic,
4767 0x00000000);
4768 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4769 SPR_NOACCESS, SPR_NOACCESS,
4770 &spr_read_mas73, &spr_write_mas73,
4771 0x00000000);
4772 ivpr_mask = (target_ulong)~0xFFFFULL;
4773 }
01662f3e 4774
f2e63a42 4775#if !defined(CONFIG_USER_ONLY)
01662f3e 4776 env->nb_tlb = 0;
1c53accc 4777 env->tlb_type = TLB_MAS;
01662f3e
AG		 4778 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4779 env->nb_tlb += booke206_tlb_size(env, i);
4780 }
f2e63a42 4781#endif
01662f3e 4782
e9cd84b9 4783 init_excp_e200(env, ivpr_mask);
9fdc60bf
AJ		 4784 /* Allocate hardware IRQ controller */
4785 ppce500_irq_init(env);
3fc6c082 4786}
a750fc0b 4787
01662f3e
AG		 4788static void init_proc_e500v1(CPUPPCState *env)
4789{
f7aa5583 4790 init_proc_e500(env, fsl_e500v1);
01662f3e
AG		 4791}
4792
7856e3a4
AF		 4793POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4794{
4795 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4796
4797 pcc->init_proc = init_proc_e500v1;
4798 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4799 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4800 PPC_SPE | PPC_SPE_SINGLE |
4801 PPC_WRTEE | PPC_RFDI |
4802 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4803 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4804 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4805 pcc->insns_flags2 = PPC2_BOOKE206;
7856e3a4
AF		 4806}
4807
01662f3e
AG		 4808static void init_proc_e500v2(CPUPPCState *env)
4809{
f7aa5583
VS		 4810 init_proc_e500(env, fsl_e500v2);
4811}
4812
7856e3a4
AF		 4813POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4814{
4815 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4816
4817 pcc->init_proc = init_proc_e500v2;
4818 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4819 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4820 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4821 PPC_WRTEE | PPC_RFDI |
4822 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4823 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4824 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4825 pcc->insns_flags2 = PPC2_BOOKE206;
7856e3a4
AF		 4826}
4827
f7aa5583
VS		 4828static void init_proc_e500mc(CPUPPCState *env)
4829{
4830 init_proc_e500(env, fsl_e500mc);
01662f3e
AG		 4831}
4832
7856e3a4
AF		 4833POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4834{
4835 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4836
4837 pcc->init_proc = init_proc_e500mc;
4838 pcc->check_pow = check_pow_none;
53116ebf
AF		 4839 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4840 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4841 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4842 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4843 PPC_FLOAT | PPC_FLOAT_FRES |
4844 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4845 PPC_FLOAT_STFIWX | PPC_WAIT |
4846 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4847 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
7856e3a4
AF		 4848}
4849
b81ccf8a
AG		 4850#ifdef TARGET_PPC64
4851static void init_proc_e5500(CPUPPCState *env)
4852{
4853 init_proc_e500(env, fsl_e5500);
4854}
7856e3a4
AF		 4855
4856POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4857{
4858 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4859
4860 pcc->init_proc = init_proc_e5500;
4861 pcc->check_pow = check_pow_none;
53116ebf
AF		 4862 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4863 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4864 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4865 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4866 PPC_FLOAT | PPC_FLOAT_FRES |
4867 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4868 PPC_FLOAT_STFIWX | PPC_WAIT |
4869 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4870 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4871 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
7856e3a4 4872}
b81ccf8a
AG		 4873#endif
4874
a750fc0b 4875/* Non-embedded PowerPC */
a750fc0b
JM		 4876
4877/* POWER : same as 601, without mfmsr, mfsr */
4878#if defined(TODO)
a750fc0b
JM		 4879/* POWER RSC (from RAD6000) */
4880#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
53116ebf
AF		 4881
4882POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4883{
4884 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4885
4886 pcc->insns_flags = XXX_TODO;
4887}
a750fc0b
JM		 4888#endif /* TODO */
4889
4890/* PowerPC 601 */
25ba3a68 4891#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4892#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4893//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4894//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4895#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4896#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4897#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
a750fc0b
JM		 4898
4899static void init_proc_601 (CPUPPCState *env)
3fc6c082 4900{
a750fc0b
JM		 4901 gen_spr_ne_601(env);
4902 gen_spr_601(env);
4903 /* Hardware implementation registers */
4904 /* XXX : not implemented */
4905 spr_register(env, SPR_HID0, "HID0",
4906 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4907 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4908 0x80010080);
a750fc0b
JM		 4909 /* XXX : not implemented */
4910 spr_register(env, SPR_HID1, "HID1",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* XXX : not implemented */
4915 spr_register(env, SPR_601_HID2, "HID2",
4916 SPR_NOACCESS, SPR_NOACCESS,
4917 &spr_read_generic, &spr_write_generic,
4918 0x00000000);
4919 /* XXX : not implemented */
4920 spr_register(env, SPR_601_HID5, "HID5",
4921 SPR_NOACCESS, SPR_NOACCESS,
4922 &spr_read_generic, &spr_write_generic,
4923 0x00000000);
a750fc0b 4924 /* Memory management */
e1833e1f 4925 init_excp_601(env);
082c6681
JM		 4926 /* XXX: beware that dcache line size is 64
4927 * but dcbz uses 32 bytes "sectors"
4928 * XXX: this breaks clcs instruction !
4929 */
4930 env->dcache_line_size = 32;
d63001d1 4931 env->icache_line_size = 64;
faadf50e
JM		 4932 /* Allocate hardware IRQ controller */
4933 ppc6xx_irq_init(env);
3fc6c082
FB		 4934}
4935
7856e3a4
AF		 4936POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4937{
4938 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4939
4940 pcc->init_proc = init_proc_601;
4941 pcc->check_pow = check_pow_none;
53116ebf
AF		 4942 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4943 PPC_FLOAT |
4944 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4945 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4946 PPC_SEGMENT | PPC_EXTERN;
4947 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4948}
4949
082c6681 4950/* PowerPC 601v */
082c6681
JM		 4951#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4952#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4953#define POWERPC_MMU_601v (POWERPC_MMU_601)
4954#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4955#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4956#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4957#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
082c6681
JM		 4958
4959static void init_proc_601v (CPUPPCState *env)
4960{
4961 init_proc_601(env);
4962 /* XXX : not implemented */
4963 spr_register(env, SPR_601_HID15, "HID15",
4964 SPR_NOACCESS, SPR_NOACCESS,
4965 &spr_read_generic, &spr_write_generic,
4966 0x00000000);
4967}
4968
7856e3a4
AF		 4969POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4970{
4971 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4972
4973 pcc->init_proc = init_proc_601v;
4974 pcc->check_pow = check_pow_none;
53116ebf
AF		 4975 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4976 PPC_FLOAT |
4977 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4978 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4979 PPC_SEGMENT | PPC_EXTERN;
4980 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 4981}
4982
a750fc0b 4983/* PowerPC 602 */
082c6681
JM		 4984#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4985/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4986#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4987//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4988#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4989#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4990#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4991 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 4992
4993static void init_proc_602 (CPUPPCState *env)
3fc6c082 4994{
a750fc0b
JM		 4995 gen_spr_ne_601(env);
4996 gen_spr_602(env);
4997 /* Time base */
4998 gen_tbl(env);
4999 /* hardware implementation registers */
5000 /* XXX : not implemented */
5001 spr_register(env, SPR_HID0, "HID0",
5002 SPR_NOACCESS, SPR_NOACCESS,
5003 &spr_read_generic, &spr_write_generic,
5004 0x00000000);
5005 /* XXX : not implemented */
5006 spr_register(env, SPR_HID1, "HID1",
5007 SPR_NOACCESS, SPR_NOACCESS,
5008 &spr_read_generic, &spr_write_generic,
5009 0x00000000);
5010 /* Memory management */
5011 gen_low_BATs(env);
5012 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5013 init_excp_602(env);
d63001d1
JM		 5014 env->dcache_line_size = 32;
5015 env->icache_line_size = 32;
a750fc0b
JM		 5016 /* Allocate hardware IRQ controller */
5017 ppc6xx_irq_init(env);
5018}
3fc6c082 5019
7856e3a4
AF		 5020POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5021{
5022 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5023
5024 pcc->init_proc = init_proc_602;
5025 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5026 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5027 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5028 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5029 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5030 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5031 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5032 PPC_SEGMENT | PPC_602_SPEC;
5033 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5034}
5035
a750fc0b 5036/* PowerPC 603 */
25ba3a68 5037#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 5038#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
5039//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
5040#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 5041#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 5042#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 5043 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 5044
5045static void init_proc_603 (CPUPPCState *env)
5046{
5047 gen_spr_ne_601(env);
5048 gen_spr_603(env);
5049 /* Time base */
5050 gen_tbl(env);
5051 /* hardware implementation registers */
5052 /* XXX : not implemented */
5053 spr_register(env, SPR_HID0, "HID0",
5054 SPR_NOACCESS, SPR_NOACCESS,
5055 &spr_read_generic, &spr_write_generic,
5056 0x00000000);
5057 /* XXX : not implemented */
5058 spr_register(env, SPR_HID1, "HID1",
5059 SPR_NOACCESS, SPR_NOACCESS,
5060 &spr_read_generic, &spr_write_generic,
5061 0x00000000);
5062 /* Memory management */
5063 gen_low_BATs(env);
5064 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5065 init_excp_603(env);
d63001d1
JM		 5066 env->dcache_line_size = 32;
5067 env->icache_line_size = 32;
a750fc0b
JM		 5068 /* Allocate hardware IRQ controller */
5069 ppc6xx_irq_init(env);
3fc6c082
FB		 5070}
5071
7856e3a4
AF		 5072POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5073{
5074 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5075
5076 pcc->init_proc = init_proc_603;
5077 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5078 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5079 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5080 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5081 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5082 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5083 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5084 PPC_SEGMENT | PPC_EXTERN;
5085 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5086}
5087
a750fc0b 5088/* PowerPC 603e */
a750fc0b
JM		 5089#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
5090#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
5091//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
5092#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 5093#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 5094#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 5095 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 5096
5097static void init_proc_603E (CPUPPCState *env)
5098{
5099 gen_spr_ne_601(env);
5100 gen_spr_603(env);
5101 /* Time base */
5102 gen_tbl(env);
5103 /* hardware implementation registers */
5104 /* XXX : not implemented */
5105 spr_register(env, SPR_HID0, "HID0",
5106 SPR_NOACCESS, SPR_NOACCESS,
5107 &spr_read_generic, &spr_write_generic,
5108 0x00000000);
5109 /* XXX : not implemented */
5110 spr_register(env, SPR_HID1, "HID1",
5111 SPR_NOACCESS, SPR_NOACCESS,
5112 &spr_read_generic, &spr_write_generic,
5113 0x00000000);
5114 /* XXX : not implemented */
5115 spr_register(env, SPR_IABR, "IABR",
5116 SPR_NOACCESS, SPR_NOACCESS,
5117 &spr_read_generic, &spr_write_generic,
5118 0x00000000);
5119 /* Memory management */
5120 gen_low_BATs(env);
5121 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 5122 init_excp_603(env);
d63001d1
JM		 5123 env->dcache_line_size = 32;
5124 env->icache_line_size = 32;
a750fc0b
JM		 5125 /* Allocate hardware IRQ controller */
5126 ppc6xx_irq_init(env);
5127}
5128
7856e3a4
AF		 5129POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5130{
5131 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5132
5133 pcc->init_proc = init_proc_603E;
5134 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5135 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5136 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5137 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5138 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5139 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5140 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5141 PPC_SEGMENT | PPC_EXTERN;
5142 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5143}
5144
a750fc0b 5145/* PowerPC 604 */
a750fc0b
JM		 5146#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
5147#define POWERPC_MMU_604 (POWERPC_MMU_32B)
5148//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
5149#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 5150#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 5151#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5152 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 5153
5154static void init_proc_604 (CPUPPCState *env)
5155{
5156 gen_spr_ne_601(env);
5157 gen_spr_604(env);
5158 /* Time base */
5159 gen_tbl(env);
5160 /* Hardware implementation registers */
5161 /* XXX : not implemented */
082c6681
JM		 5162 spr_register(env, SPR_HID0, "HID0",
5163 SPR_NOACCESS, SPR_NOACCESS,
5164 &spr_read_generic, &spr_write_generic,
5165 0x00000000);
5166 /* Memory management */
5167 gen_low_BATs(env);
5168 init_excp_604(env);
5169 env->dcache_line_size = 32;
5170 env->icache_line_size = 32;
5171 /* Allocate hardware IRQ controller */
5172 ppc6xx_irq_init(env);
5173}
5174
7856e3a4
AF		 5175POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5176{
5177 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5178
5179 pcc->init_proc = init_proc_604;
5180 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 5181 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5182 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5183 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5184 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5185 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5186 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5187 PPC_SEGMENT | PPC_EXTERN;
5188 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5189}
5190
082c6681 5191/* PowerPC 604E */
082c6681
JM		 5192#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
5193#define POWERPC_MMU_604E (POWERPC_MMU_32B)
5194#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
5195#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
5196#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
5197#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5198 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
082c6681
JM		 5199
5200static void init_proc_604E (CPUPPCState *env)
5201{
5202 gen_spr_ne_601(env);
5203 gen_spr_604(env);
5204 /* XXX : not implemented */
5205 spr_register(env, SPR_MMCR1, "MMCR1",
5206 SPR_NOACCESS, SPR_NOACCESS,
5207 &spr_read_generic, &spr_write_generic,
5208 0x00000000);
5209 /* XXX : not implemented */
5210 spr_register(env, SPR_PMC3, "PMC3",
5211 SPR_NOACCESS, SPR_NOACCESS,
5212 &spr_read_generic, &spr_write_generic,
5213 0x00000000);
5214 /* XXX : not implemented */
5215 spr_register(env, SPR_PMC4, "PMC4",
5216 SPR_NOACCESS, SPR_NOACCESS,
5217 &spr_read_generic, &spr_write_generic,
5218 0x00000000);
5219 /* Time base */
5220 gen_tbl(env);
5221 /* Hardware implementation registers */
5222 /* XXX : not implemented */
a750fc0b
JM		 5223 spr_register(env, SPR_HID0, "HID0",
5224 SPR_NOACCESS, SPR_NOACCESS,
5225 &spr_read_generic, &spr_write_generic,
5226 0x00000000);
5227 /* XXX : not implemented */
5228 spr_register(env, SPR_HID1, "HID1",
5229 SPR_NOACCESS, SPR_NOACCESS,
5230 &spr_read_generic, &spr_write_generic,
5231 0x00000000);
5232 /* Memory management */
5233 gen_low_BATs(env);
e1833e1f 5234 init_excp_604(env);
d63001d1
JM		 5235 env->dcache_line_size = 32;
5236 env->icache_line_size = 32;
a750fc0b
JM		 5237 /* Allocate hardware IRQ controller */
5238 ppc6xx_irq_init(env);
5239}
5240
7856e3a4
AF		 5241POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5242{
5243 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5244
5245 pcc->init_proc = init_proc_604E;
5246 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 5247 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5248 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5249 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5250 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5251 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5252 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5253 PPC_SEGMENT | PPC_EXTERN;
5254 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5255}
5256
bd928eba 5257/* PowerPC 740 */
bd928eba
JM		 5258#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
5259#define POWERPC_MMU_740 (POWERPC_MMU_32B)
5260#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
5261#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
5262#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
5263#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5264 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
a750fc0b 5265
bd928eba 5266static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 5267{
5268 gen_spr_ne_601(env);
5269 gen_spr_7xx(env);
5270 /* Time base */
5271 gen_tbl(env);
5272 /* Thermal management */
5273 gen_spr_thrm(env);
5274 /* Hardware implementation registers */
5275 /* XXX : not implemented */
5276 spr_register(env, SPR_HID0, "HID0",
5277 SPR_NOACCESS, SPR_NOACCESS,
5278 &spr_read_generic, &spr_write_generic,
5279 0x00000000);
5280 /* XXX : not implemented */
5281 spr_register(env, SPR_HID1, "HID1",
5282 SPR_NOACCESS, SPR_NOACCESS,
5283 &spr_read_generic, &spr_write_generic,
5284 0x00000000);
5285 /* Memory management */
5286 gen_low_BATs(env);
e1833e1f 5287 init_excp_7x0(env);
d63001d1
JM		 5288 env->dcache_line_size = 32;
5289 env->icache_line_size = 32;
a750fc0b
JM		 5290 /* Allocate hardware IRQ controller */
5291 ppc6xx_irq_init(env);
5292}
5293
7856e3a4
AF		 5294POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5295{
5296 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5297
5298 pcc->init_proc = init_proc_740;
5299 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5300 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5301 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5302 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5303 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5304 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5305 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5306 PPC_SEGMENT | PPC_EXTERN;
5307 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5308}
5309
bd928eba 5310/* PowerPC 750 */
bd928eba
JM		 5311#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
5312#define POWERPC_MMU_750 (POWERPC_MMU_32B)
5313#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
5314#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
5315#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
5316#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5317 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba
JM		 5318
5319static void init_proc_750 (CPUPPCState *env)
5320{
5321 gen_spr_ne_601(env);
5322 gen_spr_7xx(env);
5323 /* XXX : not implemented */
5324 spr_register(env, SPR_L2CR, "L2CR",
5325 SPR_NOACCESS, SPR_NOACCESS,
5326 &spr_read_generic, &spr_write_generic,
5327 0x00000000);
5328 /* Time base */
5329 gen_tbl(env);
5330 /* Thermal management */
5331 gen_spr_thrm(env);
5332 /* Hardware implementation registers */
5333 /* XXX : not implemented */
5334 spr_register(env, SPR_HID0, "HID0",
5335 SPR_NOACCESS, SPR_NOACCESS,
5336 &spr_read_generic, &spr_write_generic,
5337 0x00000000);
5338 /* XXX : not implemented */
5339 spr_register(env, SPR_HID1, "HID1",
5340 SPR_NOACCESS, SPR_NOACCESS,
5341 &spr_read_generic, &spr_write_generic,
5342 0x00000000);
5343 /* Memory management */
5344 gen_low_BATs(env);
5345 /* XXX: high BATs are also present but are known to be bugged on
5346 * die version 1.x
5347 */
5348 init_excp_7x0(env);
5349 env->dcache_line_size = 32;
5350 env->icache_line_size = 32;
5351 /* Allocate hardware IRQ controller */
5352 ppc6xx_irq_init(env);
5353}
5354
7856e3a4
AF		 5355POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5356{
5357 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5358
5359 pcc->init_proc = init_proc_750;
5360 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5361 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5362 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5363 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5364 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5365 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5366 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5367 PPC_SEGMENT | PPC_EXTERN;
5368 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5369}
5370
bd928eba 5371/* PowerPC 750 CL */
bd928eba
JM		 5372#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5373#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5374#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5375#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5376#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5377#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5378 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba
JM		 5379
5380static void init_proc_750cl (CPUPPCState *env)
5381{
5382 gen_spr_ne_601(env);
5383 gen_spr_7xx(env);
5384 /* XXX : not implemented */
5385 spr_register(env, SPR_L2CR, "L2CR",
5386 SPR_NOACCESS, SPR_NOACCESS,
5387 &spr_read_generic, &spr_write_generic,
5388 0x00000000);
5389 /* Time base */
5390 gen_tbl(env);
5391 /* Thermal management */
5392 /* Those registers are fake on 750CL */
5393 spr_register(env, SPR_THRM1, "THRM1",
5394 SPR_NOACCESS, SPR_NOACCESS,
5395 &spr_read_generic, &spr_write_generic,
5396 0x00000000);
5397 spr_register(env, SPR_THRM2, "THRM2",
5398 SPR_NOACCESS, SPR_NOACCESS,
5399 &spr_read_generic, &spr_write_generic,
5400 0x00000000);
5401 spr_register(env, SPR_THRM3, "THRM3",
5402 SPR_NOACCESS, SPR_NOACCESS,
5403 &spr_read_generic, &spr_write_generic,
5404 0x00000000);
5405 /* XXX: not implemented */
5406 spr_register(env, SPR_750_TDCL, "TDCL",
5407 SPR_NOACCESS, SPR_NOACCESS,
5408 &spr_read_generic, &spr_write_generic,
5409 0x00000000);
5410 spr_register(env, SPR_750_TDCH, "TDCH",
5411 SPR_NOACCESS, SPR_NOACCESS,
5412 &spr_read_generic, &spr_write_generic,
5413 0x00000000);
5414 /* DMA */
5415 /* XXX : not implemented */
5416 spr_register(env, SPR_750_WPAR, "WPAR",
5417 SPR_NOACCESS, SPR_NOACCESS,
5418 &spr_read_generic, &spr_write_generic,
5419 0x00000000);
5420 spr_register(env, SPR_750_DMAL, "DMAL",
5421 SPR_NOACCESS, SPR_NOACCESS,
5422 &spr_read_generic, &spr_write_generic,
5423 0x00000000);
5424 spr_register(env, SPR_750_DMAU, "DMAU",
5425 SPR_NOACCESS, SPR_NOACCESS,
5426 &spr_read_generic, &spr_write_generic,
5427 0x00000000);
5428 /* Hardware implementation registers */
5429 /* XXX : not implemented */
5430 spr_register(env, SPR_HID0, "HID0",
5431 SPR_NOACCESS, SPR_NOACCESS,
5432 &spr_read_generic, &spr_write_generic,
5433 0x00000000);
5434 /* XXX : not implemented */
5435 spr_register(env, SPR_HID1, "HID1",
5436 SPR_NOACCESS, SPR_NOACCESS,
5437 &spr_read_generic, &spr_write_generic,
5438 0x00000000);
5439 /* XXX : not implemented */
5440 spr_register(env, SPR_750CL_HID2, "HID2",
5441 SPR_NOACCESS, SPR_NOACCESS,
5442 &spr_read_generic, &spr_write_generic,
5443 0x00000000);
5444 /* XXX : not implemented */
5445 spr_register(env, SPR_750CL_HID4, "HID4",
5446 SPR_NOACCESS, SPR_NOACCESS,
5447 &spr_read_generic, &spr_write_generic,
5448 0x00000000);
5449 /* Quantization registers */
5450 /* XXX : not implemented */
5451 spr_register(env, SPR_750_GQR0, "GQR0",
5452 SPR_NOACCESS, SPR_NOACCESS,
5453 &spr_read_generic, &spr_write_generic,
5454 0x00000000);
5455 /* XXX : not implemented */
5456 spr_register(env, SPR_750_GQR1, "GQR1",
5457 SPR_NOACCESS, SPR_NOACCESS,
5458 &spr_read_generic, &spr_write_generic,
5459 0x00000000);
5460 /* XXX : not implemented */
5461 spr_register(env, SPR_750_GQR2, "GQR2",
5462 SPR_NOACCESS, SPR_NOACCESS,
5463 &spr_read_generic, &spr_write_generic,
5464 0x00000000);
5465 /* XXX : not implemented */
5466 spr_register(env, SPR_750_GQR3, "GQR3",
5467 SPR_NOACCESS, SPR_NOACCESS,
5468 &spr_read_generic, &spr_write_generic,
5469 0x00000000);
5470 /* XXX : not implemented */
5471 spr_register(env, SPR_750_GQR4, "GQR4",
5472 SPR_NOACCESS, SPR_NOACCESS,
5473 &spr_read_generic, &spr_write_generic,
5474 0x00000000);
5475 /* XXX : not implemented */
5476 spr_register(env, SPR_750_GQR5, "GQR5",
5477 SPR_NOACCESS, SPR_NOACCESS,
5478 &spr_read_generic, &spr_write_generic,
5479 0x00000000);
5480 /* XXX : not implemented */
5481 spr_register(env, SPR_750_GQR6, "GQR6",
5482 SPR_NOACCESS, SPR_NOACCESS,
5483 &spr_read_generic, &spr_write_generic,
5484 0x00000000);
5485 /* XXX : not implemented */
5486 spr_register(env, SPR_750_GQR7, "GQR7",
5487 SPR_NOACCESS, SPR_NOACCESS,
5488 &spr_read_generic, &spr_write_generic,
5489 0x00000000);
5490 /* Memory management */
5491 gen_low_BATs(env);
5492 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5493 gen_high_BATs(env);
5494 init_excp_750cl(env);
5495 env->dcache_line_size = 32;
5496 env->icache_line_size = 32;
5497 /* Allocate hardware IRQ controller */
5498 ppc6xx_irq_init(env);
5499}
5500
7856e3a4
AF		 5501POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5502{
5503 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5504
5505 pcc->init_proc = init_proc_750cl;
5506 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5507 /* XXX: not implemented:
5508 * cache lock instructions:
5509 * dcbz_l
5510 * floating point paired instructions
5511 * psq_lux
5512 * psq_lx
5513 * psq_stux
5514 * psq_stx
5515 * ps_abs
5516 * ps_add
5517 * ps_cmpo0
5518 * ps_cmpo1
5519 * ps_cmpu0
5520 * ps_cmpu1
5521 * ps_div
5522 * ps_madd
5523 * ps_madds0
5524 * ps_madds1
5525 * ps_merge00
5526 * ps_merge01
5527 * ps_merge10
5528 * ps_merge11
5529 * ps_mr
5530 * ps_msub
5531 * ps_mul
5532 * ps_muls0
5533 * ps_muls1
5534 * ps_nabs
5535 * ps_neg
5536 * ps_nmadd
5537 * ps_nmsub
5538 * ps_res
5539 * ps_rsqrte
5540 * ps_sel
5541 * ps_sub
5542 * ps_sum0
5543 * ps_sum1
5544 */
5545 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5546 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5547 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5548 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5549 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5550 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5551 PPC_SEGMENT | PPC_EXTERN;
5552 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5553}
5554
4e777442 5555/* PowerPC 750CX */
bd928eba
JM		 5556#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5557#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5558#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5559#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5560#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5561#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5562 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba
JM		 5563
5564static void init_proc_750cx (CPUPPCState *env)
5565{
5566 gen_spr_ne_601(env);
5567 gen_spr_7xx(env);
5568 /* XXX : not implemented */
5569 spr_register(env, SPR_L2CR, "L2CR",
5570 SPR_NOACCESS, SPR_NOACCESS,
5571 &spr_read_generic, &spr_write_generic,
5572 0x00000000);
5573 /* Time base */
5574 gen_tbl(env);
5575 /* Thermal management */
5576 gen_spr_thrm(env);
5577 /* This register is not implemented but is present for compatibility */
5578 spr_register(env, SPR_SDA, "SDA",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic,
5581 0x00000000);
5582 /* Hardware implementation registers */
5583 /* XXX : not implemented */
5584 spr_register(env, SPR_HID0, "HID0",
5585 SPR_NOACCESS, SPR_NOACCESS,
5586 &spr_read_generic, &spr_write_generic,
5587 0x00000000);
5588 /* XXX : not implemented */
5589 spr_register(env, SPR_HID1, "HID1",
5590 SPR_NOACCESS, SPR_NOACCESS,
5591 &spr_read_generic, &spr_write_generic,
5592 0x00000000);
5593 /* Memory management */
5594 gen_low_BATs(env);
4e777442
JM		 5595 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5596 gen_high_BATs(env);
bd928eba
JM		 5597 init_excp_750cx(env);
5598 env->dcache_line_size = 32;
5599 env->icache_line_size = 32;
5600 /* Allocate hardware IRQ controller */
5601 ppc6xx_irq_init(env);
5602}
5603
7856e3a4
AF		 5604POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5605{
5606 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5607
5608 pcc->init_proc = init_proc_750cx;
5609 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5610 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5611 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5612 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5613 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5614 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5615 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5616 PPC_SEGMENT | PPC_EXTERN;
5617 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5618}
5619
bd928eba 5620/* PowerPC 750FX */
25ba3a68 5621#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 5622#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5623#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5624#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 5625#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 5626#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5627 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 5628
5629static void init_proc_750fx (CPUPPCState *env)
5630{
5631 gen_spr_ne_601(env);
5632 gen_spr_7xx(env);
bd928eba
JM		 5633 /* XXX : not implemented */
5634 spr_register(env, SPR_L2CR, "L2CR",
5635 SPR_NOACCESS, SPR_NOACCESS,
5636 &spr_read_generic, &spr_write_generic,
5637 0x00000000);
a750fc0b
JM		 5638 /* Time base */
5639 gen_tbl(env);
5640 /* Thermal management */
5641 gen_spr_thrm(env);
bd928eba
JM		 5642 /* XXX : not implemented */
5643 spr_register(env, SPR_750_THRM4, "THRM4",
5644 SPR_NOACCESS, SPR_NOACCESS,
5645 &spr_read_generic, &spr_write_generic,
5646 0x00000000);
a750fc0b
JM		 5647 /* Hardware implementation registers */
5648 /* XXX : not implemented */
5649 spr_register(env, SPR_HID0, "HID0",
5650 SPR_NOACCESS, SPR_NOACCESS,
5651 &spr_read_generic, &spr_write_generic,
5652 0x00000000);
5653 /* XXX : not implemented */
5654 spr_register(env, SPR_HID1, "HID1",
5655 SPR_NOACCESS, SPR_NOACCESS,
5656 &spr_read_generic, &spr_write_generic,
5657 0x00000000);
5658 /* XXX : not implemented */
bd928eba 5659 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5660 SPR_NOACCESS, SPR_NOACCESS,
5661 &spr_read_generic, &spr_write_generic,
5662 0x00000000);
5663 /* Memory management */
5664 gen_low_BATs(env);
5665 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5666 gen_high_BATs(env);
bd928eba 5667 init_excp_7x0(env);
d63001d1
JM		 5668 env->dcache_line_size = 32;
5669 env->icache_line_size = 32;
a750fc0b
JM		 5670 /* Allocate hardware IRQ controller */
5671 ppc6xx_irq_init(env);
5672}
5673
7856e3a4
AF		 5674POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5675{
5676 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5677
5678 pcc->init_proc = init_proc_750fx;
5679 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5680 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5681 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5682 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5683 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5684 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5685 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5686 PPC_SEGMENT | PPC_EXTERN;
5687 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5688}
5689
bd928eba 5690/* PowerPC 750GX */
bd928eba
JM		 5691#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5692#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5693#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5694#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5695#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5696#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5697 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba
JM		 5698
5699static void init_proc_750gx (CPUPPCState *env)
5700{
5701 gen_spr_ne_601(env);
5702 gen_spr_7xx(env);
5703 /* XXX : not implemented (XXX: different from 750fx) */
5704 spr_register(env, SPR_L2CR, "L2CR",
5705 SPR_NOACCESS, SPR_NOACCESS,
5706 &spr_read_generic, &spr_write_generic,
5707 0x00000000);
5708 /* Time base */
5709 gen_tbl(env);
5710 /* Thermal management */
5711 gen_spr_thrm(env);
5712 /* XXX : not implemented */
5713 spr_register(env, SPR_750_THRM4, "THRM4",
5714 SPR_NOACCESS, SPR_NOACCESS,
5715 &spr_read_generic, &spr_write_generic,
5716 0x00000000);
5717 /* Hardware implementation registers */
5718 /* XXX : not implemented (XXX: different from 750fx) */
5719 spr_register(env, SPR_HID0, "HID0",
5720 SPR_NOACCESS, SPR_NOACCESS,
5721 &spr_read_generic, &spr_write_generic,
5722 0x00000000);
5723 /* XXX : not implemented */
5724 spr_register(env, SPR_HID1, "HID1",
5725 SPR_NOACCESS, SPR_NOACCESS,
5726 &spr_read_generic, &spr_write_generic,
5727 0x00000000);
5728 /* XXX : not implemented (XXX: different from 750fx) */
5729 spr_register(env, SPR_750FX_HID2, "HID2",
5730 SPR_NOACCESS, SPR_NOACCESS,
5731 &spr_read_generic, &spr_write_generic,
5732 0x00000000);
5733 /* Memory management */
5734 gen_low_BATs(env);
5735 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5736 gen_high_BATs(env);
5737 init_excp_7x0(env);
5738 env->dcache_line_size = 32;
5739 env->icache_line_size = 32;
5740 /* Allocate hardware IRQ controller */
5741 ppc6xx_irq_init(env);
5742}
5743
7856e3a4
AF		 5744POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5745{
5746 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5747
5748 pcc->init_proc = init_proc_750gx;
5749 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5750 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5751 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5752 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5753 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5754 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5755 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5756 PPC_SEGMENT | PPC_EXTERN;
5757 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5758}
5759
bd928eba 5760/* PowerPC 745 */
bd928eba
JM		 5761#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5762#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5763#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5764#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5765#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5766#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5767 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba
JM		 5768
5769static void init_proc_745 (CPUPPCState *env)
5770{
5771 gen_spr_ne_601(env);
5772 gen_spr_7xx(env);
5773 gen_spr_G2_755(env);
5774 /* Time base */
5775 gen_tbl(env);
5776 /* Thermal management */
5777 gen_spr_thrm(env);
5778 /* Hardware implementation registers */
5779 /* XXX : not implemented */
5780 spr_register(env, SPR_HID0, "HID0",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x00000000);
5784 /* XXX : not implemented */
5785 spr_register(env, SPR_HID1, "HID1",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 0x00000000);
5789 /* XXX : not implemented */
5790 spr_register(env, SPR_HID2, "HID2",
5791 SPR_NOACCESS, SPR_NOACCESS,
5792 &spr_read_generic, &spr_write_generic,
5793 0x00000000);
5794 /* Memory management */
5795 gen_low_BATs(env);
5796 gen_high_BATs(env);
5797 gen_6xx_7xx_soft_tlb(env, 64, 2);
5798 init_excp_7x5(env);
5799 env->dcache_line_size = 32;
5800 env->icache_line_size = 32;
5801 /* Allocate hardware IRQ controller */
5802 ppc6xx_irq_init(env);
5803}
5804
7856e3a4
AF		 5805POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5806{
5807 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5808
5809 pcc->init_proc = init_proc_745;
5810 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5811 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5812 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5813 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5814 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5815 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5816 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5817 PPC_SEGMENT | PPC_EXTERN;
5818 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5819}
5820
bd928eba 5821/* PowerPC 755 */
bd928eba
JM		 5822#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5823#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5824#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5825#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5826#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5827#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5828 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
a750fc0b 5829
bd928eba 5830static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5831{
5832 gen_spr_ne_601(env);
bd928eba 5833 gen_spr_7xx(env);
a750fc0b
JM		 5834 gen_spr_G2_755(env);
5835 /* Time base */
5836 gen_tbl(env);
5837 /* L2 cache control */
5838 /* XXX : not implemented */
bd928eba 5839 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5840 SPR_NOACCESS, SPR_NOACCESS,
5841 &spr_read_generic, &spr_write_generic,
5842 0x00000000);
5843 /* XXX : not implemented */
5844 spr_register(env, SPR_L2PMCR, "L2PMCR",
5845 SPR_NOACCESS, SPR_NOACCESS,
5846 &spr_read_generic, &spr_write_generic,
5847 0x00000000);
bd928eba
JM		 5848 /* Thermal management */
5849 gen_spr_thrm(env);
a750fc0b
JM		 5850 /* Hardware implementation registers */
5851 /* XXX : not implemented */
5852 spr_register(env, SPR_HID0, "HID0",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 /* XXX : not implemented */
5857 spr_register(env, SPR_HID1, "HID1",
5858 SPR_NOACCESS, SPR_NOACCESS,
5859 &spr_read_generic, &spr_write_generic,
5860 0x00000000);
5861 /* XXX : not implemented */
5862 spr_register(env, SPR_HID2, "HID2",
5863 SPR_NOACCESS, SPR_NOACCESS,
5864 &spr_read_generic, &spr_write_generic,
5865 0x00000000);
5866 /* Memory management */
5867 gen_low_BATs(env);
5868 gen_high_BATs(env);
5869 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5870 init_excp_7x5(env);
d63001d1
JM		 5871 env->dcache_line_size = 32;
5872 env->icache_line_size = 32;
a750fc0b
JM		 5873 /* Allocate hardware IRQ controller */
5874 ppc6xx_irq_init(env);
5875}
5876
7856e3a4
AF		 5877POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5878{
5879 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5880
5881 pcc->init_proc = init_proc_755;
5882 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5883 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5884 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5885 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5886 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5887 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5888 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5889 PPC_SEGMENT | PPC_EXTERN;
5890 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5891}
5892
a750fc0b 5893/* PowerPC 7400 (aka G4) */
a750fc0b
JM		 5894#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5895#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5896#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5897#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5898#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5899#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5900 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5901 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 5902
5903static void init_proc_7400 (CPUPPCState *env)
5904{
5905 gen_spr_ne_601(env);
5906 gen_spr_7xx(env);
5907 /* Time base */
5908 gen_tbl(env);
5909 /* 74xx specific SPR */
5910 gen_spr_74xx(env);
4e777442
JM		 5911 /* XXX : not implemented */
5912 spr_register(env, SPR_UBAMR, "UBAMR",
5913 &spr_read_ureg, SPR_NOACCESS,
5914 &spr_read_ureg, SPR_NOACCESS,
5915 0x00000000);
5916 /* XXX: this seems not implemented on all revisions. */
5917 /* XXX : not implemented */
5918 spr_register(env, SPR_MSSCR1, "MSSCR1",
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 &spr_read_generic, &spr_write_generic,
5921 0x00000000);
a750fc0b
JM		 5922 /* Thermal management */
5923 gen_spr_thrm(env);
5924 /* Memory management */
5925 gen_low_BATs(env);
e1833e1f 5926 init_excp_7400(env);
d63001d1
JM		 5927 env->dcache_line_size = 32;
5928 env->icache_line_size = 32;
a750fc0b
JM		 5929 /* Allocate hardware IRQ controller */
5930 ppc6xx_irq_init(env);
5931}
5932
7856e3a4
AF		 5933POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5934{
5935 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5936
5937 pcc->init_proc = init_proc_7400;
5938 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 5939 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5940 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5941 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5942 PPC_FLOAT_STFIWX |
5943 PPC_CACHE | PPC_CACHE_ICBI |
5944 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5945 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5946 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5947 PPC_MEM_TLBIA |
5948 PPC_SEGMENT | PPC_EXTERN |
5949 PPC_ALTIVEC;
5950 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 5951}
5952
a750fc0b 5953/* PowerPC 7410 (aka G4) */
a750fc0b
JM		 5954#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5955#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5956#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5957#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5958#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5959#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5960 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5961 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 5962
5963static void init_proc_7410 (CPUPPCState *env)
5964{
5965 gen_spr_ne_601(env);
5966 gen_spr_7xx(env);
5967 /* Time base */
5968 gen_tbl(env);
5969 /* 74xx specific SPR */
5970 gen_spr_74xx(env);
4e777442
JM		 5971 /* XXX : not implemented */
5972 spr_register(env, SPR_UBAMR, "UBAMR",
5973 &spr_read_ureg, SPR_NOACCESS,
5974 &spr_read_ureg, SPR_NOACCESS,
5975 0x00000000);
a750fc0b
JM		 5976 /* Thermal management */
5977 gen_spr_thrm(env);
5978 /* L2PMCR */
5979 /* XXX : not implemented */
5980 spr_register(env, SPR_L2PMCR, "L2PMCR",
5981 SPR_NOACCESS, SPR_NOACCESS,
5982 &spr_read_generic, &spr_write_generic,
5983 0x00000000);
5984 /* LDSTDB */
5985 /* XXX : not implemented */
5986 spr_register(env, SPR_LDSTDB, "LDSTDB",
5987 SPR_NOACCESS, SPR_NOACCESS,
5988 &spr_read_generic, &spr_write_generic,
5989 0x00000000);
5990 /* Memory management */
5991 gen_low_BATs(env);
e1833e1f 5992 init_excp_7400(env);
d63001d1
JM		 5993 env->dcache_line_size = 32;
5994 env->icache_line_size = 32;
a750fc0b
JM		 5995 /* Allocate hardware IRQ controller */
5996 ppc6xx_irq_init(env);
5997}
5998
7856e3a4
AF		 5999POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6000{
6001 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6002
6003 pcc->init_proc = init_proc_7410;
6004 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 6005 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6006 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6007 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6008 PPC_FLOAT_STFIWX |
6009 PPC_CACHE | PPC_CACHE_ICBI |
6010 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6011 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6013 PPC_MEM_TLBIA |
6014 PPC_SEGMENT | PPC_EXTERN |
6015 PPC_ALTIVEC;
6016 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6017}
6018
a750fc0b 6019/* PowerPC 7440 (aka G4) */
a750fc0b
JM		 6020#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
6021#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
6022#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
6023#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 6024#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 6025#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6026 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6027 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 6028
6029static void init_proc_7440 (CPUPPCState *env)
6030{
6031 gen_spr_ne_601(env);
6032 gen_spr_7xx(env);
6033 /* Time base */
6034 gen_tbl(env);
6035 /* 74xx specific SPR */
6036 gen_spr_74xx(env);
4e777442
JM		 6037 /* XXX : not implemented */
6038 spr_register(env, SPR_UBAMR, "UBAMR",
6039 &spr_read_ureg, SPR_NOACCESS,
6040 &spr_read_ureg, SPR_NOACCESS,
6041 0x00000000);
a750fc0b
JM		 6042 /* LDSTCR */
6043 /* XXX : not implemented */
6044 spr_register(env, SPR_LDSTCR, "LDSTCR",
6045 SPR_NOACCESS, SPR_NOACCESS,
6046 &spr_read_generic, &spr_write_generic,
6047 0x00000000);
6048 /* ICTRL */
6049 /* XXX : not implemented */
6050 spr_register(env, SPR_ICTRL, "ICTRL",
6051 SPR_NOACCESS, SPR_NOACCESS,
6052 &spr_read_generic, &spr_write_generic,
6053 0x00000000);
6054 /* MSSSR0 */
578bb252 6055 /* XXX : not implemented */
a750fc0b
JM		 6056 spr_register(env, SPR_MSSSR0, "MSSSR0",
6057 SPR_NOACCESS, SPR_NOACCESS,
6058 &spr_read_generic, &spr_write_generic,
6059 0x00000000);
6060 /* PMC */
6061 /* XXX : not implemented */
6062 spr_register(env, SPR_PMC5, "PMC5",
6063 SPR_NOACCESS, SPR_NOACCESS,
6064 &spr_read_generic, &spr_write_generic,
6065 0x00000000);
578bb252 6066 /* XXX : not implemented */
a750fc0b
JM		 6067 spr_register(env, SPR_UPMC5, "UPMC5",
6068 &spr_read_ureg, SPR_NOACCESS,
6069 &spr_read_ureg, SPR_NOACCESS,
6070 0x00000000);
578bb252 6071 /* XXX : not implemented */
a750fc0b
JM		 6072 spr_register(env, SPR_PMC6, "PMC6",
6073 SPR_NOACCESS, SPR_NOACCESS,
6074 &spr_read_generic, &spr_write_generic,
6075 0x00000000);
578bb252 6076 /* XXX : not implemented */
a750fc0b
JM		 6077 spr_register(env, SPR_UPMC6, "UPMC6",
6078 &spr_read_ureg, SPR_NOACCESS,
6079 &spr_read_ureg, SPR_NOACCESS,
6080 0x00000000);
6081 /* Memory management */
6082 gen_low_BATs(env);
578bb252 6083 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 6084 init_excp_7450(env);
d63001d1
JM		 6085 env->dcache_line_size = 32;
6086 env->icache_line_size = 32;
a750fc0b
JM		 6087 /* Allocate hardware IRQ controller */
6088 ppc6xx_irq_init(env);
6089}
a750fc0b 6090
7856e3a4
AF		 6091POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6092{
6093 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6094
6095 pcc->init_proc = init_proc_7440;
6096 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6097 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6098 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6099 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6100 PPC_FLOAT_STFIWX |
6101 PPC_CACHE | PPC_CACHE_ICBI |
6102 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6103 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6104 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6105 PPC_MEM_TLBIA | PPC_74xx_TLB |
6106 PPC_SEGMENT | PPC_EXTERN |
6107 PPC_ALTIVEC;
6108 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6109}
6110
a750fc0b 6111/* PowerPC 7450 (aka G4) */
a750fc0b
JM		 6112#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
6113#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
6114#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
6115#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 6116#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 6117#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6118 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6119 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 6120
6121static void init_proc_7450 (CPUPPCState *env)
6122{
6123 gen_spr_ne_601(env);
6124 gen_spr_7xx(env);
6125 /* Time base */
6126 gen_tbl(env);
6127 /* 74xx specific SPR */
6128 gen_spr_74xx(env);
6129 /* Level 3 cache control */
6130 gen_l3_ctrl(env);
4e777442
JM		 6131 /* L3ITCR1 */
6132 /* XXX : not implemented */
6133 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6134 SPR_NOACCESS, SPR_NOACCESS,
6135 &spr_read_generic, &spr_write_generic,
6136 0x00000000);
6137 /* L3ITCR2 */
6138 /* XXX : not implemented */
6139 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6140 SPR_NOACCESS, SPR_NOACCESS,
6141 &spr_read_generic, &spr_write_generic,
6142 0x00000000);
6143 /* L3ITCR3 */
6144 /* XXX : not implemented */
6145 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6146 SPR_NOACCESS, SPR_NOACCESS,
6147 &spr_read_generic, &spr_write_generic,
6148 0x00000000);
6149 /* L3OHCR */
6150 /* XXX : not implemented */
6151 spr_register(env, SPR_L3OHCR, "L3OHCR",
6152 SPR_NOACCESS, SPR_NOACCESS,
6153 &spr_read_generic, &spr_write_generic,
6154 0x00000000);
6155 /* XXX : not implemented */
6156 spr_register(env, SPR_UBAMR, "UBAMR",
6157 &spr_read_ureg, SPR_NOACCESS,
6158 &spr_read_ureg, SPR_NOACCESS,
6159 0x00000000);
a750fc0b
JM		 6160 /* LDSTCR */
6161 /* XXX : not implemented */
6162 spr_register(env, SPR_LDSTCR, "LDSTCR",
6163 SPR_NOACCESS, SPR_NOACCESS,
6164 &spr_read_generic, &spr_write_generic,
6165 0x00000000);
6166 /* ICTRL */
6167 /* XXX : not implemented */
6168 spr_register(env, SPR_ICTRL, "ICTRL",
6169 SPR_NOACCESS, SPR_NOACCESS,
6170 &spr_read_generic, &spr_write_generic,
6171 0x00000000);
6172 /* MSSSR0 */
578bb252 6173 /* XXX : not implemented */
a750fc0b
JM		 6174 spr_register(env, SPR_MSSSR0, "MSSSR0",
6175 SPR_NOACCESS, SPR_NOACCESS,
6176 &spr_read_generic, &spr_write_generic,
6177 0x00000000);
6178 /* PMC */
6179 /* XXX : not implemented */
6180 spr_register(env, SPR_PMC5, "PMC5",
6181 SPR_NOACCESS, SPR_NOACCESS,
6182 &spr_read_generic, &spr_write_generic,
6183 0x00000000);
578bb252 6184 /* XXX : not implemented */
a750fc0b
JM		 6185 spr_register(env, SPR_UPMC5, "UPMC5",
6186 &spr_read_ureg, SPR_NOACCESS,
6187 &spr_read_ureg, SPR_NOACCESS,
6188 0x00000000);
578bb252 6189 /* XXX : not implemented */
a750fc0b
JM		 6190 spr_register(env, SPR_PMC6, "PMC6",
6191 SPR_NOACCESS, SPR_NOACCESS,
6192 &spr_read_generic, &spr_write_generic,
6193 0x00000000);
578bb252 6194 /* XXX : not implemented */
a750fc0b
JM		 6195 spr_register(env, SPR_UPMC6, "UPMC6",
6196 &spr_read_ureg, SPR_NOACCESS,
6197 &spr_read_ureg, SPR_NOACCESS,
6198 0x00000000);
6199 /* Memory management */
6200 gen_low_BATs(env);
578bb252 6201 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6202 init_excp_7450(env);
d63001d1
JM		 6203 env->dcache_line_size = 32;
6204 env->icache_line_size = 32;
a750fc0b
JM		 6205 /* Allocate hardware IRQ controller */
6206 ppc6xx_irq_init(env);
6207}
a750fc0b 6208
7856e3a4
AF		 6209POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6210{
6211 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6212
6213 pcc->init_proc = init_proc_7450;
6214 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6215 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6216 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6217 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6218 PPC_FLOAT_STFIWX |
6219 PPC_CACHE | PPC_CACHE_ICBI |
6220 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6221 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6222 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6223 PPC_MEM_TLBIA | PPC_74xx_TLB |
6224 PPC_SEGMENT | PPC_EXTERN |
6225 PPC_ALTIVEC;
6226 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6227}
6228
a750fc0b 6229/* PowerPC 7445 (aka G4) */
a750fc0b
JM		 6230#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
6231#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
6232#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
6233#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 6234#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 6235#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6236 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6237 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 6238
6239static void init_proc_7445 (CPUPPCState *env)
6240{
6241 gen_spr_ne_601(env);
6242 gen_spr_7xx(env);
6243 /* Time base */
6244 gen_tbl(env);
6245 /* 74xx specific SPR */
6246 gen_spr_74xx(env);
6247 /* LDSTCR */
6248 /* XXX : not implemented */
6249 spr_register(env, SPR_LDSTCR, "LDSTCR",
6250 SPR_NOACCESS, SPR_NOACCESS,
6251 &spr_read_generic, &spr_write_generic,
6252 0x00000000);
6253 /* ICTRL */
6254 /* XXX : not implemented */
6255 spr_register(env, SPR_ICTRL, "ICTRL",
6256 SPR_NOACCESS, SPR_NOACCESS,
6257 &spr_read_generic, &spr_write_generic,
6258 0x00000000);
6259 /* MSSSR0 */
578bb252 6260 /* XXX : not implemented */
a750fc0b
JM		 6261 spr_register(env, SPR_MSSSR0, "MSSSR0",
6262 SPR_NOACCESS, SPR_NOACCESS,
6263 &spr_read_generic, &spr_write_generic,
6264 0x00000000);
6265 /* PMC */
6266 /* XXX : not implemented */
6267 spr_register(env, SPR_PMC5, "PMC5",
6268 SPR_NOACCESS, SPR_NOACCESS,
6269 &spr_read_generic, &spr_write_generic,
6270 0x00000000);
578bb252 6271 /* XXX : not implemented */
a750fc0b
JM		 6272 spr_register(env, SPR_UPMC5, "UPMC5",
6273 &spr_read_ureg, SPR_NOACCESS,
6274 &spr_read_ureg, SPR_NOACCESS,
6275 0x00000000);
578bb252 6276 /* XXX : not implemented */
a750fc0b
JM		 6277 spr_register(env, SPR_PMC6, "PMC6",
6278 SPR_NOACCESS, SPR_NOACCESS,
6279 &spr_read_generic, &spr_write_generic,
6280 0x00000000);
578bb252 6281 /* XXX : not implemented */
a750fc0b
JM		 6282 spr_register(env, SPR_UPMC6, "UPMC6",
6283 &spr_read_ureg, SPR_NOACCESS,
6284 &spr_read_ureg, SPR_NOACCESS,
6285 0x00000000);
6286 /* SPRGs */
6287 spr_register(env, SPR_SPRG4, "SPRG4",
6288 SPR_NOACCESS, SPR_NOACCESS,
6289 &spr_read_generic, &spr_write_generic,
6290 0x00000000);
6291 spr_register(env, SPR_USPRG4, "USPRG4",
6292 &spr_read_ureg, SPR_NOACCESS,
6293 &spr_read_ureg, SPR_NOACCESS,
6294 0x00000000);
6295 spr_register(env, SPR_SPRG5, "SPRG5",
6296 SPR_NOACCESS, SPR_NOACCESS,
6297 &spr_read_generic, &spr_write_generic,
6298 0x00000000);
6299 spr_register(env, SPR_USPRG5, "USPRG5",
6300 &spr_read_ureg, SPR_NOACCESS,
6301 &spr_read_ureg, SPR_NOACCESS,
6302 0x00000000);
6303 spr_register(env, SPR_SPRG6, "SPRG6",
6304 SPR_NOACCESS, SPR_NOACCESS,
6305 &spr_read_generic, &spr_write_generic,
6306 0x00000000);
6307 spr_register(env, SPR_USPRG6, "USPRG6",
6308 &spr_read_ureg, SPR_NOACCESS,
6309 &spr_read_ureg, SPR_NOACCESS,
6310 0x00000000);
6311 spr_register(env, SPR_SPRG7, "SPRG7",
6312 SPR_NOACCESS, SPR_NOACCESS,
6313 &spr_read_generic, &spr_write_generic,
6314 0x00000000);
6315 spr_register(env, SPR_USPRG7, "USPRG7",
6316 &spr_read_ureg, SPR_NOACCESS,
6317 &spr_read_ureg, SPR_NOACCESS,
6318 0x00000000);
6319 /* Memory management */
6320 gen_low_BATs(env);
6321 gen_high_BATs(env);
578bb252 6322 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6323 init_excp_7450(env);
d63001d1
JM		 6324 env->dcache_line_size = 32;
6325 env->icache_line_size = 32;
a750fc0b
JM		 6326 /* Allocate hardware IRQ controller */
6327 ppc6xx_irq_init(env);
6328}
a750fc0b 6329
7856e3a4
AF		 6330POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6331{
6332 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6333
6334 pcc->init_proc = init_proc_7445;
6335 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6336 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6337 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6338 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6339 PPC_FLOAT_STFIWX |
6340 PPC_CACHE | PPC_CACHE_ICBI |
6341 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6342 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6343 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6344 PPC_MEM_TLBIA | PPC_74xx_TLB |
6345 PPC_SEGMENT | PPC_EXTERN |
6346 PPC_ALTIVEC;
6347 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6348}
6349
a750fc0b 6350/* PowerPC 7455 (aka G4) */
a750fc0b
JM		 6351#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
6352#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
6353#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
6354#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 6355#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 6356#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6357 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6358 POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 6359
6360static void init_proc_7455 (CPUPPCState *env)
6361{
6362 gen_spr_ne_601(env);
6363 gen_spr_7xx(env);
6364 /* Time base */
6365 gen_tbl(env);
6366 /* 74xx specific SPR */
6367 gen_spr_74xx(env);
6368 /* Level 3 cache control */
6369 gen_l3_ctrl(env);
6370 /* LDSTCR */
6371 /* XXX : not implemented */
6372 spr_register(env, SPR_LDSTCR, "LDSTCR",
6373 SPR_NOACCESS, SPR_NOACCESS,
6374 &spr_read_generic, &spr_write_generic,
6375 0x00000000);
6376 /* ICTRL */
6377 /* XXX : not implemented */
6378 spr_register(env, SPR_ICTRL, "ICTRL",
6379 SPR_NOACCESS, SPR_NOACCESS,
6380 &spr_read_generic, &spr_write_generic,
6381 0x00000000);
6382 /* MSSSR0 */
578bb252 6383 /* XXX : not implemented */
a750fc0b
JM		 6384 spr_register(env, SPR_MSSSR0, "MSSSR0",
6385 SPR_NOACCESS, SPR_NOACCESS,
6386 &spr_read_generic, &spr_write_generic,
6387 0x00000000);
6388 /* PMC */
6389 /* XXX : not implemented */
6390 spr_register(env, SPR_PMC5, "PMC5",
6391 SPR_NOACCESS, SPR_NOACCESS,
6392 &spr_read_generic, &spr_write_generic,
6393 0x00000000);
578bb252 6394 /* XXX : not implemented */
a750fc0b
JM		 6395 spr_register(env, SPR_UPMC5, "UPMC5",
6396 &spr_read_ureg, SPR_NOACCESS,
6397 &spr_read_ureg, SPR_NOACCESS,
6398 0x00000000);
578bb252 6399 /* XXX : not implemented */
a750fc0b
JM		 6400 spr_register(env, SPR_PMC6, "PMC6",
6401 SPR_NOACCESS, SPR_NOACCESS,
6402 &spr_read_generic, &spr_write_generic,
6403 0x00000000);
578bb252 6404 /* XXX : not implemented */
a750fc0b
JM		 6405 spr_register(env, SPR_UPMC6, "UPMC6",
6406 &spr_read_ureg, SPR_NOACCESS,
6407 &spr_read_ureg, SPR_NOACCESS,
6408 0x00000000);
6409 /* SPRGs */
6410 spr_register(env, SPR_SPRG4, "SPRG4",
6411 SPR_NOACCESS, SPR_NOACCESS,
6412 &spr_read_generic, &spr_write_generic,
6413 0x00000000);
6414 spr_register(env, SPR_USPRG4, "USPRG4",
6415 &spr_read_ureg, SPR_NOACCESS,
6416 &spr_read_ureg, SPR_NOACCESS,
6417 0x00000000);
6418 spr_register(env, SPR_SPRG5, "SPRG5",
6419 SPR_NOACCESS, SPR_NOACCESS,
6420 &spr_read_generic, &spr_write_generic,
6421 0x00000000);
6422 spr_register(env, SPR_USPRG5, "USPRG5",
6423 &spr_read_ureg, SPR_NOACCESS,
6424 &spr_read_ureg, SPR_NOACCESS,
6425 0x00000000);
6426 spr_register(env, SPR_SPRG6, "SPRG6",
6427 SPR_NOACCESS, SPR_NOACCESS,
6428 &spr_read_generic, &spr_write_generic,
6429 0x00000000);
6430 spr_register(env, SPR_USPRG6, "USPRG6",
6431 &spr_read_ureg, SPR_NOACCESS,
6432 &spr_read_ureg, SPR_NOACCESS,
6433 0x00000000);
6434 spr_register(env, SPR_SPRG7, "SPRG7",
6435 SPR_NOACCESS, SPR_NOACCESS,
6436 &spr_read_generic, &spr_write_generic,
6437 0x00000000);
6438 spr_register(env, SPR_USPRG7, "USPRG7",
6439 &spr_read_ureg, SPR_NOACCESS,
6440 &spr_read_ureg, SPR_NOACCESS,
6441 0x00000000);
6442 /* Memory management */
6443 gen_low_BATs(env);
6444 gen_high_BATs(env);
578bb252 6445 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 6446 init_excp_7450(env);
d63001d1
JM		 6447 env->dcache_line_size = 32;
6448 env->icache_line_size = 32;
a750fc0b
JM		 6449 /* Allocate hardware IRQ controller */
6450 ppc6xx_irq_init(env);
6451}
a750fc0b 6452
7856e3a4
AF		 6453POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6454{
6455 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6456
6457 pcc->init_proc = init_proc_7455;
6458 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6459 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6460 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6461 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6462 PPC_FLOAT_STFIWX |
6463 PPC_CACHE | PPC_CACHE_ICBI |
6464 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6465 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6466 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6467 PPC_MEM_TLBIA | PPC_74xx_TLB |
6468 PPC_SEGMENT | PPC_EXTERN |
6469 PPC_ALTIVEC;
6470 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6471}
6472
4e777442 6473/* PowerPC 7457 (aka G4) */
4e777442
JM		 6474#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6475#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6476#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6477#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6478#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6479#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6480 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6481 POWERPC_FLAG_BUS_CLK)
4e777442 6482
4e777442
JM		 6483static void init_proc_7457 (CPUPPCState *env)
6484{
6485 gen_spr_ne_601(env);
6486 gen_spr_7xx(env);
6487 /* Time base */
6488 gen_tbl(env);
6489 /* 74xx specific SPR */
6490 gen_spr_74xx(env);
6491 /* Level 3 cache control */
6492 gen_l3_ctrl(env);
6493 /* L3ITCR1 */
6494 /* XXX : not implemented */
6495 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6496 SPR_NOACCESS, SPR_NOACCESS,
6497 &spr_read_generic, &spr_write_generic,
6498 0x00000000);
6499 /* L3ITCR2 */
6500 /* XXX : not implemented */
6501 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6502 SPR_NOACCESS, SPR_NOACCESS,
6503 &spr_read_generic, &spr_write_generic,
6504 0x00000000);
6505 /* L3ITCR3 */
6506 /* XXX : not implemented */
6507 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6508 SPR_NOACCESS, SPR_NOACCESS,
6509 &spr_read_generic, &spr_write_generic,
6510 0x00000000);
6511 /* L3OHCR */
6512 /* XXX : not implemented */
6513 spr_register(env, SPR_L3OHCR, "L3OHCR",
6514 SPR_NOACCESS, SPR_NOACCESS,
6515 &spr_read_generic, &spr_write_generic,
6516 0x00000000);
6517 /* LDSTCR */
6518 /* XXX : not implemented */
6519 spr_register(env, SPR_LDSTCR, "LDSTCR",
6520 SPR_NOACCESS, SPR_NOACCESS,
6521 &spr_read_generic, &spr_write_generic,
6522 0x00000000);
6523 /* ICTRL */
6524 /* XXX : not implemented */
6525 spr_register(env, SPR_ICTRL, "ICTRL",
6526 SPR_NOACCESS, SPR_NOACCESS,
6527 &spr_read_generic, &spr_write_generic,
6528 0x00000000);
6529 /* MSSSR0 */
6530 /* XXX : not implemented */
6531 spr_register(env, SPR_MSSSR0, "MSSSR0",
6532 SPR_NOACCESS, SPR_NOACCESS,
6533 &spr_read_generic, &spr_write_generic,
6534 0x00000000);
6535 /* PMC */
6536 /* XXX : not implemented */
6537 spr_register(env, SPR_PMC5, "PMC5",
6538 SPR_NOACCESS, SPR_NOACCESS,
6539 &spr_read_generic, &spr_write_generic,
6540 0x00000000);
6541 /* XXX : not implemented */
6542 spr_register(env, SPR_UPMC5, "UPMC5",
6543 &spr_read_ureg, SPR_NOACCESS,
6544 &spr_read_ureg, SPR_NOACCESS,
6545 0x00000000);
6546 /* XXX : not implemented */
6547 spr_register(env, SPR_PMC6, "PMC6",
6548 SPR_NOACCESS, SPR_NOACCESS,
6549 &spr_read_generic, &spr_write_generic,
6550 0x00000000);
6551 /* XXX : not implemented */
6552 spr_register(env, SPR_UPMC6, "UPMC6",
6553 &spr_read_ureg, SPR_NOACCESS,
6554 &spr_read_ureg, SPR_NOACCESS,
6555 0x00000000);
6556 /* SPRGs */
6557 spr_register(env, SPR_SPRG4, "SPRG4",
6558 SPR_NOACCESS, SPR_NOACCESS,
6559 &spr_read_generic, &spr_write_generic,
6560 0x00000000);
6561 spr_register(env, SPR_USPRG4, "USPRG4",
6562 &spr_read_ureg, SPR_NOACCESS,
6563 &spr_read_ureg, SPR_NOACCESS,
6564 0x00000000);
6565 spr_register(env, SPR_SPRG5, "SPRG5",
6566 SPR_NOACCESS, SPR_NOACCESS,
6567 &spr_read_generic, &spr_write_generic,
6568 0x00000000);
6569 spr_register(env, SPR_USPRG5, "USPRG5",
6570 &spr_read_ureg, SPR_NOACCESS,
6571 &spr_read_ureg, SPR_NOACCESS,
6572 0x00000000);
6573 spr_register(env, SPR_SPRG6, "SPRG6",
6574 SPR_NOACCESS, SPR_NOACCESS,
6575 &spr_read_generic, &spr_write_generic,
6576 0x00000000);
6577 spr_register(env, SPR_USPRG6, "USPRG6",
6578 &spr_read_ureg, SPR_NOACCESS,
6579 &spr_read_ureg, SPR_NOACCESS,
6580 0x00000000);
6581 spr_register(env, SPR_SPRG7, "SPRG7",
6582 SPR_NOACCESS, SPR_NOACCESS,
6583 &spr_read_generic, &spr_write_generic,
6584 0x00000000);
6585 spr_register(env, SPR_USPRG7, "USPRG7",
6586 &spr_read_ureg, SPR_NOACCESS,
6587 &spr_read_ureg, SPR_NOACCESS,
6588 0x00000000);
6589 /* Memory management */
6590 gen_low_BATs(env);
6591 gen_high_BATs(env);
6592 gen_74xx_soft_tlb(env, 128, 2);
6593 init_excp_7450(env);
6594 env->dcache_line_size = 32;
6595 env->icache_line_size = 32;
6596 /* Allocate hardware IRQ controller */
6597 ppc6xx_irq_init(env);
6598}
6599
7856e3a4
AF		 6600POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6601{
6602 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6603
6604 pcc->init_proc = init_proc_7457;
6605 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 6606 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6607 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6608 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6609 PPC_FLOAT_STFIWX |
6610 PPC_CACHE | PPC_CACHE_ICBI |
6611 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6612 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6613 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6614 PPC_MEM_TLBIA | PPC_74xx_TLB |
6615 PPC_SEGMENT | PPC_EXTERN |
6616 PPC_ALTIVEC;
6617 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6618}
6619
a750fc0b
JM		 6620#if defined (TARGET_PPC64)
6621/* PowerPC 970 */
a750fc0b 6622#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 6623#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 6624//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6625#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 6626#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 6627#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6628 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6629 POWERPC_FLAG_BUS_CLK)
a750fc0b 6630
417bf010
JM		 6631#if defined(CONFIG_USER_ONLY)
6632#define POWERPC970_HID5_INIT 0x00000080
6633#else
6634#define POWERPC970_HID5_INIT 0x00000000
6635#endif
6636
2f462816
JM		 6637static int check_pow_970 (CPUPPCState *env)
6638{
6639 if (env->spr[SPR_HID0] & 0x00600000)
6640 return 1;
6641
6642 return 0;
6643}
6644
a750fc0b
JM		 6645static void init_proc_970 (CPUPPCState *env)
6646{
6647 gen_spr_ne_601(env);
6648 gen_spr_7xx(env);
6649 /* Time base */
6650 gen_tbl(env);
6651 /* Hardware implementation registers */
6652 /* XXX : not implemented */
6653 spr_register(env, SPR_HID0, "HID0",
6654 SPR_NOACCESS, SPR_NOACCESS,
06403421 6655 &spr_read_generic, &spr_write_clear,
d63001d1 6656 0x60000000);
a750fc0b
JM		 6657 /* XXX : not implemented */
6658 spr_register(env, SPR_HID1, "HID1",
6659 SPR_NOACCESS, SPR_NOACCESS,
6660 &spr_read_generic, &spr_write_generic,
6661 0x00000000);
6662 /* XXX : not implemented */
bd928eba 6663 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6664 SPR_NOACCESS, SPR_NOACCESS,
6665 &spr_read_generic, &spr_write_generic,
6666 0x00000000);
e57448f1
JM		 6667 /* XXX : not implemented */
6668 spr_register(env, SPR_970_HID5, "HID5",
6669 SPR_NOACCESS, SPR_NOACCESS,
6670 &spr_read_generic, &spr_write_generic,
417bf010 6671 POWERPC970_HID5_INIT);
bd928eba
JM		 6672 /* XXX : not implemented */
6673 spr_register(env, SPR_L2CR, "L2CR",
6674 SPR_NOACCESS, SPR_NOACCESS,
6675 &spr_read_generic, &spr_write_generic,
6676 0x00000000);
a750fc0b
JM		 6677 /* Memory management */
6678 /* XXX: not correct */
6679 gen_low_BATs(env);
12de9a39
JM		 6680 /* XXX : not implemented */
6681 spr_register(env, SPR_MMUCFG, "MMUCFG",
6682 SPR_NOACCESS, SPR_NOACCESS,
6683 &spr_read_generic, SPR_NOACCESS,
6684 0x00000000); /* TOFIX */
6685 /* XXX : not implemented */
6686 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6687 SPR_NOACCESS, SPR_NOACCESS,
6688 &spr_read_generic, &spr_write_generic,
6689 0x00000000); /* TOFIX */
6690 spr_register(env, SPR_HIOR, "SPR_HIOR",
6691 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6692 &spr_read_hior, &spr_write_hior,
6693 0x00000000);
f2e63a42 6694#if !defined(CONFIG_USER_ONLY)
12de9a39 6695 env->slb_nr = 32;
f2e63a42 6696#endif
e1833e1f 6697 init_excp_970(env);
d63001d1
JM		 6698 env->dcache_line_size = 128;
6699 env->icache_line_size = 128;
a750fc0b
JM		 6700 /* Allocate hardware IRQ controller */
6701 ppc970_irq_init(env);
cf8358c8
AJ		 6702 /* Can't find information on what this should be on reset. This
6703 * value is the one used by 74xx processors. */
6704 vscr_init(env, 0x00010000);
a750fc0b 6705}
a750fc0b 6706
7856e3a4
AF		 6707POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6708{
6709 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6710
6711 pcc->init_proc = init_proc_970;
6712 pcc->check_pow = check_pow_970;
53116ebf
AF		 6713 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6714 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6715 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6716 PPC_FLOAT_STFIWX |
6717 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6718 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6719 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6720 PPC_64B | PPC_ALTIVEC |
6721 PPC_SEGMENT_64B | PPC_SLBI;
6722 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6723}
6724
a750fc0b 6725/* PowerPC 970FX (aka G5) */
a750fc0b 6726#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 6727#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 6728#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6729#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 6730#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 6731#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6732 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6733 POWERPC_FLAG_BUS_CLK)
a750fc0b 6734
2f462816
JM		 6735static int check_pow_970FX (CPUPPCState *env)
6736{
6737 if (env->spr[SPR_HID0] & 0x00600000)
6738 return 1;
6739
6740 return 0;
6741}
6742
a750fc0b
JM		 6743static void init_proc_970FX (CPUPPCState *env)
6744{
6745 gen_spr_ne_601(env);
6746 gen_spr_7xx(env);
6747 /* Time base */
6748 gen_tbl(env);
6749 /* Hardware implementation registers */
6750 /* XXX : not implemented */
6751 spr_register(env, SPR_HID0, "HID0",
6752 SPR_NOACCESS, SPR_NOACCESS,
06403421 6753 &spr_read_generic, &spr_write_clear,
d63001d1 6754 0x60000000);
a750fc0b
JM		 6755 /* XXX : not implemented */
6756 spr_register(env, SPR_HID1, "HID1",
6757 SPR_NOACCESS, SPR_NOACCESS,
6758 &spr_read_generic, &spr_write_generic,
6759 0x00000000);
6760 /* XXX : not implemented */
bd928eba 6761 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6762 SPR_NOACCESS, SPR_NOACCESS,
6763 &spr_read_generic, &spr_write_generic,
6764 0x00000000);
d63001d1
JM		 6765 /* XXX : not implemented */
6766 spr_register(env, SPR_970_HID5, "HID5",
6767 SPR_NOACCESS, SPR_NOACCESS,
6768 &spr_read_generic, &spr_write_generic,
417bf010 6769 POWERPC970_HID5_INIT);
bd928eba
JM		 6770 /* XXX : not implemented */
6771 spr_register(env, SPR_L2CR, "L2CR",
6772 SPR_NOACCESS, SPR_NOACCESS,
6773 &spr_read_generic, &spr_write_generic,
6774 0x00000000);
a750fc0b
JM		 6775 /* Memory management */
6776 /* XXX: not correct */
6777 gen_low_BATs(env);
12de9a39
JM		 6778 /* XXX : not implemented */
6779 spr_register(env, SPR_MMUCFG, "MMUCFG",
6780 SPR_NOACCESS, SPR_NOACCESS,
6781 &spr_read_generic, SPR_NOACCESS,
6782 0x00000000); /* TOFIX */
6783 /* XXX : not implemented */
6784 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6785 SPR_NOACCESS, SPR_NOACCESS,
6786 &spr_read_generic, &spr_write_generic,
6787 0x00000000); /* TOFIX */
6788 spr_register(env, SPR_HIOR, "SPR_HIOR",
6789 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6790 &spr_read_hior, &spr_write_hior,
6791 0x00000000);
4e98d8cf
BS		 6792 spr_register(env, SPR_CTRL, "SPR_CTRL",
6793 SPR_NOACCESS, SPR_NOACCESS,
6794 &spr_read_generic, &spr_write_generic,
6795 0x00000000);
6796 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6797 SPR_NOACCESS, SPR_NOACCESS,
6798 &spr_read_generic, &spr_write_generic,
6799 0x00000000);
6800 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6801 &spr_read_generic, &spr_write_generic,
6802 &spr_read_generic, &spr_write_generic,
6803 0x00000000);
f2e63a42 6804#if !defined(CONFIG_USER_ONLY)
8eee0af9 6805 env->slb_nr = 64;
f2e63a42 6806#endif
e1833e1f 6807 init_excp_970(env);
d63001d1
JM		 6808 env->dcache_line_size = 128;
6809 env->icache_line_size = 128;
a750fc0b
JM		 6810 /* Allocate hardware IRQ controller */
6811 ppc970_irq_init(env);
cf8358c8
AJ		 6812 /* Can't find information on what this should be on reset. This
6813 * value is the one used by 74xx processors. */
6814 vscr_init(env, 0x00010000);
a750fc0b 6815}
a750fc0b 6816
7856e3a4
AF		 6817POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6818{
6819 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6820
6821 pcc->init_proc = init_proc_970FX;
6822 pcc->check_pow = check_pow_970FX;
53116ebf
AF		 6823 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6824 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6825 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6826 PPC_FLOAT_STFIWX |
6827 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6828 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6829 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6830 PPC_64B | PPC_ALTIVEC |
6831 PPC_SEGMENT_64B | PPC_SLBI;
6832 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6833}
6834
a750fc0b 6835/* PowerPC 970 GX */
a750fc0b 6836#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6837#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6838#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6839#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6840#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6841#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6842 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6843 POWERPC_FLAG_BUS_CLK)
a750fc0b 6844
2f462816
JM		 6845static int check_pow_970GX (CPUPPCState *env)
6846{
6847 if (env->spr[SPR_HID0] & 0x00600000)
6848 return 1;
6849
6850 return 0;
6851}
6852
a750fc0b
JM		 6853static void init_proc_970GX (CPUPPCState *env)
6854{
6855 gen_spr_ne_601(env);
6856 gen_spr_7xx(env);
6857 /* Time base */
6858 gen_tbl(env);
6859 /* Hardware implementation registers */
6860 /* XXX : not implemented */
6861 spr_register(env, SPR_HID0, "HID0",
6862 SPR_NOACCESS, SPR_NOACCESS,
06403421 6863 &spr_read_generic, &spr_write_clear,
d63001d1 6864 0x60000000);
a750fc0b
JM		 6865 /* XXX : not implemented */
6866 spr_register(env, SPR_HID1, "HID1",
6867 SPR_NOACCESS, SPR_NOACCESS,
6868 &spr_read_generic, &spr_write_generic,
6869 0x00000000);
6870 /* XXX : not implemented */
bd928eba 6871 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6872 SPR_NOACCESS, SPR_NOACCESS,
6873 &spr_read_generic, &spr_write_generic,
6874 0x00000000);
d63001d1
JM		 6875 /* XXX : not implemented */
6876 spr_register(env, SPR_970_HID5, "HID5",
6877 SPR_NOACCESS, SPR_NOACCESS,
6878 &spr_read_generic, &spr_write_generic,
417bf010 6879 POWERPC970_HID5_INIT);
bd928eba
JM		 6880 /* XXX : not implemented */
6881 spr_register(env, SPR_L2CR, "L2CR",
6882 SPR_NOACCESS, SPR_NOACCESS,
6883 &spr_read_generic, &spr_write_generic,
6884 0x00000000);
a750fc0b
JM		 6885 /* Memory management */
6886 /* XXX: not correct */
6887 gen_low_BATs(env);
12de9a39
JM		 6888 /* XXX : not implemented */
6889 spr_register(env, SPR_MMUCFG, "MMUCFG",
6890 SPR_NOACCESS, SPR_NOACCESS,
6891 &spr_read_generic, SPR_NOACCESS,
6892 0x00000000); /* TOFIX */
6893 /* XXX : not implemented */
6894 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6895 SPR_NOACCESS, SPR_NOACCESS,
6896 &spr_read_generic, &spr_write_generic,
6897 0x00000000); /* TOFIX */
6898 spr_register(env, SPR_HIOR, "SPR_HIOR",
6899 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6900 &spr_read_hior, &spr_write_hior,
6901 0x00000000);
f2e63a42 6902#if !defined(CONFIG_USER_ONLY)
12de9a39 6903 env->slb_nr = 32;
f2e63a42 6904#endif
e1833e1f 6905 init_excp_970(env);
d63001d1
JM		 6906 env->dcache_line_size = 128;
6907 env->icache_line_size = 128;
a750fc0b
JM		 6908 /* Allocate hardware IRQ controller */
6909 ppc970_irq_init(env);
cf8358c8
AJ		 6910 /* Can't find information on what this should be on reset. This
6911 * value is the one used by 74xx processors. */
6912 vscr_init(env, 0x00010000);
a750fc0b 6913}
a750fc0b 6914
7856e3a4
AF		 6915POWERPC_FAMILY(970GX)(ObjectClass *oc, void *data)
6916{
6917 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6918
6919 pcc->init_proc = init_proc_970GX;
6920 pcc->check_pow = check_pow_970GX;
53116ebf
AF		 6921 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6922 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6923 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6924 PPC_FLOAT_STFIWX |
6925 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6926 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6927 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6928 PPC_64B | PPC_ALTIVEC |
6929 PPC_SEGMENT_64B | PPC_SLBI;
6930 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 6931}
6932
2f462816 6933/* PowerPC 970 MP */
2f462816
JM		 6934#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6935#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6936#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6937#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6938#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6939#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6940 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6941 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6942
6943static int check_pow_970MP (CPUPPCState *env)
6944{
6945 if (env->spr[SPR_HID0] & 0x01C00000)
6946 return 1;
6947
6948 return 0;
6949}
6950
6951static void init_proc_970MP (CPUPPCState *env)
6952{
6953 gen_spr_ne_601(env);
6954 gen_spr_7xx(env);
6955 /* Time base */
6956 gen_tbl(env);
6957 /* Hardware implementation registers */
6958 /* XXX : not implemented */
6959 spr_register(env, SPR_HID0, "HID0",
6960 SPR_NOACCESS, SPR_NOACCESS,
6961 &spr_read_generic, &spr_write_clear,
6962 0x60000000);
6963 /* XXX : not implemented */
6964 spr_register(env, SPR_HID1, "HID1",
6965 SPR_NOACCESS, SPR_NOACCESS,
6966 &spr_read_generic, &spr_write_generic,
6967 0x00000000);
6968 /* XXX : not implemented */
bd928eba 6969 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6970 SPR_NOACCESS, SPR_NOACCESS,
6971 &spr_read_generic, &spr_write_generic,
6972 0x00000000);
6973 /* XXX : not implemented */
6974 spr_register(env, SPR_970_HID5, "HID5",
6975 SPR_NOACCESS, SPR_NOACCESS,
6976 &spr_read_generic, &spr_write_generic,
6977 POWERPC970_HID5_INIT);
bd928eba
JM		 6978 /* XXX : not implemented */
6979 spr_register(env, SPR_L2CR, "L2CR",
6980 SPR_NOACCESS, SPR_NOACCESS,
6981 &spr_read_generic, &spr_write_generic,
6982 0x00000000);
2f462816
JM		 6983 /* Memory management */
6984 /* XXX: not correct */
6985 gen_low_BATs(env);
6986 /* XXX : not implemented */
6987 spr_register(env, SPR_MMUCFG, "MMUCFG",
6988 SPR_NOACCESS, SPR_NOACCESS,
6989 &spr_read_generic, SPR_NOACCESS,
6990 0x00000000); /* TOFIX */
6991 /* XXX : not implemented */
6992 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6993 SPR_NOACCESS, SPR_NOACCESS,
6994 &spr_read_generic, &spr_write_generic,
6995 0x00000000); /* TOFIX */
6996 spr_register(env, SPR_HIOR, "SPR_HIOR",
6997 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6998 &spr_read_hior, &spr_write_hior,
6999 0x00000000);
2f462816
JM		 7000#if !defined(CONFIG_USER_ONLY)
7001 env->slb_nr = 32;
7002#endif
7003 init_excp_970(env);
7004 env->dcache_line_size = 128;
7005 env->icache_line_size = 128;
7006 /* Allocate hardware IRQ controller */
7007 ppc970_irq_init(env);
cf8358c8
AJ		 7008 /* Can't find information on what this should be on reset. This
7009 * value is the one used by 74xx processors. */
7010 vscr_init(env, 0x00010000);
2f462816
JM		 7011}
7012
7856e3a4
AF		 7013POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
7014{
7015 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7016
7017 pcc->init_proc = init_proc_970MP;
7018 pcc->check_pow = check_pow_970MP;
53116ebf
AF		 7019 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7020 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7021 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7022 PPC_FLOAT_STFIWX |
7023 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7024 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7025 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7026 PPC_64B | PPC_ALTIVEC |
7027 PPC_SEGMENT_64B | PPC_SLBI;
7028 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 7029}
7030
9d52e907 7031/* POWER7 */
9d52e907
DG		 7032#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
7033#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
7034#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
7035#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
7036#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
7037#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
7038 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
697ab892 7039 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
9d52e907
DG		 7040
7041static void init_proc_POWER7 (CPUPPCState *env)
7042{
7043 gen_spr_ne_601(env);
7044 gen_spr_7xx(env);
7045 /* Time base */
7046 gen_tbl(env);
2e06214f
NW		 7047 /* Processor identification */
7048 spr_register(env, SPR_PIR, "PIR",
7049 SPR_NOACCESS, SPR_NOACCESS,
7050 &spr_read_generic, &spr_write_pir,
7051 0x00000000);
9d52e907
DG		 7052#if !defined(CONFIG_USER_ONLY)
7053 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7054 spr_register(env, SPR_PURR, "PURR",
7055 &spr_read_purr, SPR_NOACCESS,
7056 &spr_read_purr, SPR_NOACCESS,
7057 0x00000000);
7058 spr_register(env, SPR_SPURR, "SPURR",
7059 &spr_read_purr, SPR_NOACCESS,
7060 &spr_read_purr, SPR_NOACCESS,
7061 0x00000000);
697ab892
DG		 7062 spr_register(env, SPR_CFAR, "SPR_CFAR",
7063 SPR_NOACCESS, SPR_NOACCESS,
7064 &spr_read_cfar, &spr_write_cfar,
7065 0x00000000);
7066 spr_register(env, SPR_DSCR, "SPR_DSCR",
7067 SPR_NOACCESS, SPR_NOACCESS,
7068 &spr_read_generic, &spr_write_generic,
7069 0x00000000);
9d52e907
DG		 7070#endif /* !CONFIG_USER_ONLY */
7071 /* Memory management */
7072 /* XXX : not implemented */
7073 spr_register(env, SPR_MMUCFG, "MMUCFG",
7074 SPR_NOACCESS, SPR_NOACCESS,
7075 &spr_read_generic, SPR_NOACCESS,
7076 0x00000000); /* TOFIX */
7077 /* XXX : not implemented */
7078 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7079 SPR_NOACCESS, SPR_NOACCESS,
7080 &spr_read_generic, &spr_write_generic,
7081 0x80800000);
7082 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7083 SPR_NOACCESS, SPR_NOACCESS,
7084 &spr_read_generic, &spr_write_generic,
7085 0x80800000);
7086 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7087 &spr_read_generic, &spr_write_generic,
7088 &spr_read_generic, &spr_write_generic,
7089 0x00000000);
7090#if !defined(CONFIG_USER_ONLY)
7091 env->slb_nr = 32;
7092#endif
7093 init_excp_POWER7(env);
7094 env->dcache_line_size = 128;
7095 env->icache_line_size = 128;
7096 /* Allocate hardware IRQ controller */
7097 ppcPOWER7_irq_init(env);
7098 /* Can't find information on what this should be on reset. This
7099 * value is the one used by 74xx processors. */
7100 vscr_init(env, 0x00010000);
7101}
9d52e907 7102
7856e3a4
AF		 7103POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7104{
7105 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7106
7107 pcc->init_proc = init_proc_POWER7;
7108 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 7109 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7110 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7111 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7112 PPC_FLOAT_STFIWX |
7113 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7114 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7115 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7116 PPC_64B | PPC_ALTIVEC |
7117 PPC_SEGMENT_64B | PPC_SLBI |
7118 PPC_POPCNTB | PPC_POPCNTWD;
7119 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
7856e3a4
AF		 7120}
7121
a750fc0b 7122/* PowerPC 620 */
add78955
JM		 7123#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
7124//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 7125#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 7126#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 7127#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 7128#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 7129 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
a750fc0b
JM		 7130
7131static void init_proc_620 (CPUPPCState *env)
7132{
7133 gen_spr_ne_601(env);
7134 gen_spr_620(env);
7135 /* Time base */
7136 gen_tbl(env);
7137 /* Hardware implementation registers */
7138 /* XXX : not implemented */
7139 spr_register(env, SPR_HID0, "HID0",
7140 SPR_NOACCESS, SPR_NOACCESS,
7141 &spr_read_generic, &spr_write_generic,
7142 0x00000000);
7143 /* Memory management */
7144 gen_low_BATs(env);
e1833e1f 7145 init_excp_620(env);
d63001d1
JM		 7146 env->dcache_line_size = 64;
7147 env->icache_line_size = 64;
faadf50e
JM		 7148 /* Allocate hardware IRQ controller */
7149 ppc6xx_irq_init(env);
a750fc0b 7150}
7856e3a4
AF		 7151
7152POWERPC_FAMILY(620)(ObjectClass *oc, void *data)
7153{
7154 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7155
7156 pcc->init_proc = init_proc_620;
7157 pcc->check_pow = check_pow_nocheck; /* Check this */
53116ebf
AF		 7158 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7159 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7160 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7161 PPC_FLOAT_STFIWX |
7162 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7163 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7164 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7165 PPC_SEGMENT | PPC_EXTERN |
7166 PPC_64B | PPC_SLBI;
7167 pcc->insns_flags2 = PPC_NONE;
7856e3a4
AF		 7168}
7169
a750fc0b
JM		 7170#endif /* defined (TARGET_PPC64) */
7171
a750fc0b
JM		 7172/*****************************************************************************/
7173/* PVR definitions for most known PowerPC */
7174enum {
7175 /* PowerPC 401 family */
7176 /* Generic PowerPC 401 */
80d11f44 7177#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 7178 /* PowerPC 401 cores */
80d11f44
JM		 7179 CPU_POWERPC_401A1 = 0x00210000,
7180 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 7181#if 0
80d11f44 7182 CPU_POWERPC_401B3 = xxx,
a750fc0b 7183#endif
80d11f44
JM		 7184 CPU_POWERPC_401C2 = 0x00230000,
7185 CPU_POWERPC_401D2 = 0x00240000,
7186 CPU_POWERPC_401E2 = 0x00250000,
7187 CPU_POWERPC_401F2 = 0x00260000,
7188 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 7189 /* PowerPC 401 microcontrolers */
7190#if 0
80d11f44 7191 CPU_POWERPC_401GF = xxx,
a750fc0b 7192#endif
80d11f44 7193#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 7194 /* IBM Processor for Network Resources */
80d11f44 7195 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 7196#if 0
80d11f44 7197 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 7198#endif
7199 /* PowerPC 403 family */
a750fc0b 7200 /* PowerPC 403 microcontrollers */
80d11f44
JM		 7201 CPU_POWERPC_403GA = 0x00200011,
7202 CPU_POWERPC_403GB = 0x00200100,
7203 CPU_POWERPC_403GC = 0x00200200,
7204 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 7205#if 0
80d11f44 7206 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 7207#endif
7208 /* PowerPC 405 family */
a750fc0b
JM		 7209 /* PowerPC 405 cores */
7210#if 0
80d11f44 7211 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 7212#endif
7213#if 0
80d11f44 7214 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 7215#endif
7216#if 0
80d11f44 7217 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 7218#endif
7219#if 0
80d11f44 7220 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 7221#endif
7222#if 0
80d11f44 7223 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 7224#endif
7225#if 0
80d11f44 7226 CPU_POWERPC_405C4 = xxx,
a750fc0b 7227#endif
80d11f44 7228 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 7229#if 0
80d11f44 7230 CPU_POWERPC_405D3 = xxx,
a750fc0b 7231#endif
80d11f44 7232 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 7233#if 0
80d11f44 7234 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 7235#endif
7236#if 0
80d11f44 7237 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 7238#endif
7239#if 0
80d11f44 7240 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 7241#endif
7242#if 0
80d11f44 7243 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 7244#endif
7245#if 0
80d11f44 7246 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 7247#endif
7248 /* PowerPC 405 microcontrolers */
7249 /* XXX: missing 0x200108a0 */
80d11f44
JM		 7250 CPU_POWERPC_405CRa = 0x40110041,
7251 CPU_POWERPC_405CRb = 0x401100C5,
7252 CPU_POWERPC_405CRc = 0x40110145,
7253 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 7254#if 0
80d11f44 7255 CPU_POWERPC_405EXr = xxx,
a750fc0b 7256#endif
80d11f44 7257 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 7258#if 0
80d11f44
JM		 7259 CPU_POWERPC_405FX = xxx,
7260#endif
80d11f44
JM		 7261 CPU_POWERPC_405GPa = 0x40110000,
7262 CPU_POWERPC_405GPb = 0x40110040,
7263 CPU_POWERPC_405GPc = 0x40110082,
7264 CPU_POWERPC_405GPd = 0x401100C4,
80d11f44 7265 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 7266#if 0
80d11f44 7267 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 7268#endif
7269#if 0
80d11f44 7270 CPU_POWERPC_405L = xxx,
a750fc0b 7271#endif
80d11f44 7272 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 7273#if 0
80d11f44 7274 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 7275#endif
7276#if 0
80d11f44 7277 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 7278#endif
7279#if 0
80d11f44 7280 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 7281#endif
7282 /* IBM network processors */
80d11f44
JM		 7283 CPU_POWERPC_NPE405H = 0x414100C0,
7284 CPU_POWERPC_NPE405H2 = 0x41410140,
7285 CPU_POWERPC_NPE405L = 0x416100C0,
7286 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 7287#if 0
80d11f44 7288 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 7289#endif
7290#if 0
80d11f44 7291 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 7292#endif
7293#if 0
80d11f44 7294 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 7295#endif
7296 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
7297#if 0
80d11f44 7298 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 7299#endif
7300#if 0
80d11f44 7301 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 7302#endif
7303#if 0
80d11f44 7304 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 7305#endif
80d11f44 7306 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 7307#if 0
80d11f44 7308 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 7309#endif
7310#if 0
80d11f44 7311 CPU_POWERPC_STB045 = xxx,
a750fc0b 7312#endif
80d11f44
JM		 7313 CPU_POWERPC_STB04 = 0x41810000,
7314 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 7315#if 0
80d11f44 7316 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 7317#endif
7318 /* Xilinx cores */
80d11f44 7319 CPU_POWERPC_X2VP4 = 0x20010820,
80d11f44 7320 CPU_POWERPC_X2VP20 = 0x20010860,
a750fc0b 7321#if 0
80d11f44 7322 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 7323#endif
7324#if 0
80d11f44 7325 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 7326#endif
7327#if 0
80d11f44 7328 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 7329#endif
7330#if 0
80d11f44 7331 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 7332#endif
7333 /* PowerPC 440 family */
7334 /* Generic PowerPC 440 */
80d11f44 7335#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 7336 /* PowerPC 440 cores */
7337#if 0
80d11f44 7338 CPU_POWERPC_440A4 = xxx,
a750fc0b 7339#endif
95070372 7340 CPU_POWERPC_440_XILINX = 0x7ff21910,
a750fc0b 7341#if 0
80d11f44 7342 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 7343#endif
7344#if 0
80d11f44 7345 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 7346#endif
7347#if 0
80d11f44 7348 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 7349#endif
7350#if 0
80d11f44 7351 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 7352#endif
7353#if 0
80d11f44 7354 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 7355#endif
7356#if 0
80d11f44 7357 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 7358#endif
7359 /* PowerPC 440 microcontrolers */
80d11f44
JM		 7360 CPU_POWERPC_440EPa = 0x42221850,
7361 CPU_POWERPC_440EPb = 0x422218D3,
80d11f44
JM		 7362 CPU_POWERPC_440GPb = 0x40120440,
7363 CPU_POWERPC_440GPc = 0x40120481,
80d11f44
JM		 7364#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
7365 CPU_POWERPC_440GRX = 0x200008D0,
7366#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
80d11f44
JM		 7367 CPU_POWERPC_440GXa = 0x51B21850,
7368 CPU_POWERPC_440GXb = 0x51B21851,
7369 CPU_POWERPC_440GXc = 0x51B21892,
7370 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 7371#if 0
80d11f44 7372 CPU_POWERPC_440S = xxx,
a750fc0b 7373#endif
80d11f44
JM		 7374 CPU_POWERPC_440SP = 0x53221850,
7375 CPU_POWERPC_440SP2 = 0x53221891,
7376 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 7377 /* PowerPC 460 family */
7378#if 0
7379 /* Generic PowerPC 464 */
80d11f44 7380#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 7381#endif
7382 /* PowerPC 464 microcontrolers */
7383#if 0
80d11f44 7384 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 7385#endif
7386#if 0
80d11f44 7387 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 7388#endif
7389 /* Freescale embedded PowerPC cores */
c3e36823 7390 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44 7391 CPU_POWERPC_MPC5xx = 0x00020020,
c3e36823 7392 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44 7393 CPU_POWERPC_MPC8xx = 0x00500000,
c3e36823 7394 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 7395 CPU_POWERPC_G2 = 0x00810011,
7396 CPU_POWERPC_G2H4 = 0x80811010,
7397 CPU_POWERPC_G2gp = 0x80821010,
7398 CPU_POWERPC_G2ls = 0x90810010,
7399 CPU_POWERPC_MPC603 = 0x00810100,
7400 CPU_POWERPC_G2_HIP3 = 0x00810101,
7401 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 7402 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 7403 CPU_POWERPC_G2LE = 0x80820010,
7404 CPU_POWERPC_G2LEgp = 0x80822010,
7405 CPU_POWERPC_G2LEls = 0xA0822010,
7406 CPU_POWERPC_G2LEgp1 = 0x80822011,
7407 CPU_POWERPC_G2LEgp3 = 0x80822013,
7408 /* MPC52xx microcontrollers */
c3e36823 7409 /* XXX: MPC 5121 ? */
80d11f44
JM		 7410#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7411#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7412#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
80d11f44
JM		 7413#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7414#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
a750fc0b 7415 /* e200 family */
80d11f44 7416 /* e200 cores */
a750fc0b 7417#if 0
80d11f44 7418 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 7419#endif
7420#if 0
80d11f44 7421 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 7422#endif
7423#if 0 /* ? */
80d11f44
JM		 7424 CPU_POWERPC_e200z3 = 0x81120000,
7425#endif
7426 CPU_POWERPC_e200z5 = 0x81000000,
7427 CPU_POWERPC_e200z6 = 0x81120000,
7428 /* MPC55xx microcontrollers */
7429#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7430#if 0
7431#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7432#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7433#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7434#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7435#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7436#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7437#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7438#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7439#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7440#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7441#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7442#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7443#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7444#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7445#endif
7446#if 0
7447#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7448#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7449#endif
7450#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7451#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7452#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7453#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7454#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7455#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 7456 /* e300 family */
80d11f44 7457 /* e300 cores */
80d11f44
JM		 7458 CPU_POWERPC_e300c1 = 0x00830010,
7459 CPU_POWERPC_e300c2 = 0x00840010,
7460 CPU_POWERPC_e300c3 = 0x00850010,
7461 CPU_POWERPC_e300c4 = 0x00860010,
7462 /* MPC83xx microcontrollers */
74d77cae
TM		 7463#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7464#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7465#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7466#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7467#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7468#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
a750fc0b 7469 /* e500 family */
80d11f44
JM		 7470 /* e500 cores */
7471#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 7472 CPU_POWERPC_e500v1_v10 = 0x80200010,
7473 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 7474 CPU_POWERPC_e500v2_v10 = 0x80210010,
7475 CPU_POWERPC_e500v2_v11 = 0x80210011,
7476 CPU_POWERPC_e500v2_v20 = 0x80210020,
7477 CPU_POWERPC_e500v2_v21 = 0x80210021,
7478 CPU_POWERPC_e500v2_v22 = 0x80210022,
7479 CPU_POWERPC_e500v2_v30 = 0x80210030,
f7aa5583 7480 CPU_POWERPC_e500mc = 0x80230020,
b81ccf8a 7481 CPU_POWERPC_e5500 = 0x80240020,
80d11f44 7482 /* MPC85xx microcontrollers */
80d11f44
JM		 7483#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7484#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
80d11f44
JM		 7485#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7486#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 7487#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7488#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7489#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
bd5ea513
AJ		 7490#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7491#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
bd5ea513
AJ		 7492#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7493#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 7494#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7495#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7496#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7497#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
80d11f44
JM		 7498#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7499#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7500#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7501#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
80d11f44
JM		 7502#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7503#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7504#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
80d11f44 7505#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
80d11f44
JM		 7506#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7507#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7508#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
80d11f44
JM		 7509#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7510#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7511#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
80d11f44
JM		 7512#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7513#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7514#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
80d11f44
JM		 7515#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7516#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7517#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7518#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
80d11f44
JM		 7519#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7520#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7521#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7522#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
80d11f44
JM		 7523#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7524#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
80d11f44
JM		 7525#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7526#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
80d11f44
JM		 7527#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7528#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7529#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7530#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7531#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7532#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7533#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7534#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7535#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 7536 /* e600 family */
80d11f44
JM		 7537 /* e600 cores */
7538 CPU_POWERPC_e600 = 0x80040010,
7539 /* MPC86xx microcontrollers */
7540#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7541#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7542#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 7543 /* PowerPC 6xx cores */
80d11f44
JM		 7544 CPU_POWERPC_601_v0 = 0x00010001,
7545 CPU_POWERPC_601_v1 = 0x00010001,
7546 CPU_POWERPC_601_v2 = 0x00010002,
7547 CPU_POWERPC_602 = 0x00050100,
7548 CPU_POWERPC_603 = 0x00030100,
80d11f44
JM		 7549 CPU_POWERPC_603E_v11 = 0x00060101,
7550 CPU_POWERPC_603E_v12 = 0x00060102,
7551 CPU_POWERPC_603E_v13 = 0x00060103,
7552 CPU_POWERPC_603E_v14 = 0x00060104,
7553 CPU_POWERPC_603E_v22 = 0x00060202,
7554 CPU_POWERPC_603E_v3 = 0x00060300,
7555 CPU_POWERPC_603E_v4 = 0x00060400,
7556 CPU_POWERPC_603E_v41 = 0x00060401,
7557 CPU_POWERPC_603E7t = 0x00071201,
7558 CPU_POWERPC_603E7v = 0x00070100,
7559 CPU_POWERPC_603E7v1 = 0x00070101,
7560 CPU_POWERPC_603E7v2 = 0x00070201,
7561 CPU_POWERPC_603E7 = 0x00070200,
7562 CPU_POWERPC_603P = 0x00070000,
c3e36823 7563 /* XXX: missing 0x00040303 (604) */
80d11f44 7564 CPU_POWERPC_604 = 0x00040103,
c3e36823
JM		 7565 /* XXX: missing 0x00091203 */
7566 /* XXX: missing 0x00092110 */
7567 /* XXX: missing 0x00092120 */
80d11f44
JM		 7568 CPU_POWERPC_604E_v10 = 0x00090100,
7569 CPU_POWERPC_604E_v22 = 0x00090202,
7570 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 7571 /* XXX: missing 0x000a0100 */
7572 /* XXX: missing 0x00093102 */
80d11f44 7573 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 7574#if 0
80d11f44 7575 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 7576#endif
7577 /* PowerPC 740/750 cores (aka G3) */
7578 /* XXX: missing 0x00084202 */
bd928eba 7579 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 7580 CPU_POWERPC_7x0_v20 = 0x00080200,
7581 CPU_POWERPC_7x0_v21 = 0x00080201,
7582 CPU_POWERPC_7x0_v22 = 0x00080202,
7583 CPU_POWERPC_7x0_v30 = 0x00080300,
7584 CPU_POWERPC_7x0_v31 = 0x00080301,
7585 CPU_POWERPC_740E = 0x00080100,
bd928eba 7586 CPU_POWERPC_750E = 0x00080200,
80d11f44 7587 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 7588 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 7589 CPU_POWERPC_750CL_v10 = 0x00087200,
7590 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
bd928eba
JM		 7591 CPU_POWERPC_750CX_v10 = 0x00082100,
7592 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 7593 CPU_POWERPC_750CX_v21 = 0x00082201,
7594 CPU_POWERPC_750CX_v22 = 0x00082202,
80d11f44
JM		 7595 CPU_POWERPC_750CXE_v21 = 0x00082211,
7596 CPU_POWERPC_750CXE_v22 = 0x00082212,
7597 CPU_POWERPC_750CXE_v23 = 0x00082213,
7598 CPU_POWERPC_750CXE_v24 = 0x00082214,
7599 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 7600 CPU_POWERPC_750CXE_v30 = 0x00082310,
7601 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 7602 CPU_POWERPC_750CXE_v31b = 0x00083311,
7603 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 7604 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 7605 CPU_POWERPC_750FX_v10 = 0x70000100,
7606 CPU_POWERPC_750FX_v20 = 0x70000200,
7607 CPU_POWERPC_750FX_v21 = 0x70000201,
7608 CPU_POWERPC_750FX_v22 = 0x70000202,
7609 CPU_POWERPC_750FX_v23 = 0x70000203,
7610 CPU_POWERPC_750GL = 0x70020102,
80d11f44
JM		 7611 CPU_POWERPC_750GX_v10 = 0x70020100,
7612 CPU_POWERPC_750GX_v11 = 0x70020101,
7613 CPU_POWERPC_750GX_v12 = 0x70020102,
bd928eba
JM		 7614 CPU_POWERPC_750L_v20 = 0x00088200,
7615 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 7616 CPU_POWERPC_750L_v22 = 0x00088202,
7617 CPU_POWERPC_750L_v30 = 0x00088300,
7618 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 7619 /* PowerPC 745/755 cores */
80d11f44
JM		 7620 CPU_POWERPC_7x5_v10 = 0x00083100,
7621 CPU_POWERPC_7x5_v11 = 0x00083101,
7622 CPU_POWERPC_7x5_v20 = 0x00083200,
7623 CPU_POWERPC_7x5_v21 = 0x00083201,
7624 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7625 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7626 CPU_POWERPC_7x5_v24 = 0x00083204,
7627 CPU_POWERPC_7x5_v25 = 0x00083205,
7628 CPU_POWERPC_7x5_v26 = 0x00083206,
7629 CPU_POWERPC_7x5_v27 = 0x00083207,
7630 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 7631#if 0
80d11f44 7632 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 7633#endif
7634 /* PowerPC 74xx cores (aka G4) */
7635 /* XXX: missing 0x000C1101 */
80d11f44
JM		 7636 CPU_POWERPC_7400_v10 = 0x000C0100,
7637 CPU_POWERPC_7400_v11 = 0x000C0101,
7638 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 7639 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 7640 CPU_POWERPC_7400_v22 = 0x000C0202,
7641 CPU_POWERPC_7400_v26 = 0x000C0206,
7642 CPU_POWERPC_7400_v27 = 0x000C0207,
7643 CPU_POWERPC_7400_v28 = 0x000C0208,
7644 CPU_POWERPC_7400_v29 = 0x000C0209,
80d11f44
JM		 7645 CPU_POWERPC_7410_v10 = 0x800C1100,
7646 CPU_POWERPC_7410_v11 = 0x800C1101,
7647 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7648 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7649 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
80d11f44
JM		 7650 CPU_POWERPC_7448_v10 = 0x80040100,
7651 CPU_POWERPC_7448_v11 = 0x80040101,
7652 CPU_POWERPC_7448_v20 = 0x80040200,
7653 CPU_POWERPC_7448_v21 = 0x80040201,
80d11f44
JM		 7654 CPU_POWERPC_7450_v10 = 0x80000100,
7655 CPU_POWERPC_7450_v11 = 0x80000101,
7656 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 7657 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 7658 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 7659 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7660 /* XXX: this entry might be a bug in some documentation */
7661 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44 7662 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 7663 /* XXX: missing 0x80010200 */
80d11f44
JM		 7664 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7665 CPU_POWERPC_74x5_v32 = 0x80010302,
7666 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7667 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
80d11f44 7668 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 7669 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 7670 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 7671 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7672 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7673 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 7674 /* 64 bits PowerPC */
00af685f 7675#if defined(TARGET_PPC64)
80d11f44
JM		 7676 CPU_POWERPC_620 = 0x00140000,
7677 CPU_POWERPC_630 = 0x00400000,
7678 CPU_POWERPC_631 = 0x00410104,
7679 CPU_POWERPC_POWER4 = 0x00350000,
7680 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 7681 /* XXX: missing 0x003A0201 */
80d11f44
JM		 7682 CPU_POWERPC_POWER5 = 0x003A0203,
7683#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7684 CPU_POWERPC_POWER5P = 0x003B0000,
7685#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7686 CPU_POWERPC_POWER6 = 0x003E0000,
7687 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7688 CPU_POWERPC_POWER6A = 0x0F000002,
9d52e907 7689 CPU_POWERPC_POWER7_v20 = 0x003F0200,
37e305ce
DG		 7690 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7691 CPU_POWERPC_POWER7_v23 = 0x003F0203,
80d11f44 7692 CPU_POWERPC_970 = 0x00390202,
80d11f44
JM		 7693 CPU_POWERPC_970FX_v10 = 0x00391100,
7694 CPU_POWERPC_970FX_v20 = 0x003C0200,
7695 CPU_POWERPC_970FX_v21 = 0x003C0201,
7696 CPU_POWERPC_970FX_v30 = 0x003C0300,
7697 CPU_POWERPC_970FX_v31 = 0x003C0301,
7698 CPU_POWERPC_970GX = 0x00450000,
80d11f44
JM		 7699 CPU_POWERPC_970MP_v10 = 0x00440100,
7700 CPU_POWERPC_970MP_v11 = 0x00440101,
7701#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7702 CPU_POWERPC_CELL_v10 = 0x00700100,
7703 CPU_POWERPC_CELL_v20 = 0x00700400,
7704 CPU_POWERPC_CELL_v30 = 0x00700500,
7705 CPU_POWERPC_CELL_v31 = 0x00700501,
7706#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7707 CPU_POWERPC_RS64 = 0x00330000,
7708 CPU_POWERPC_RS64II = 0x00340000,
7709 CPU_POWERPC_RS64III = 0x00360000,
7710 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 7711#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 7712 /* Original POWER */
7713 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7714 * POWER2 (RIOS2) & RSC2 (P2SC) here
7715 */
7716#if 0
80d11f44 7717 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 7718#endif
7719#if 0
80d11f44 7720 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7721#endif
7722 /* PA Semi core */
80d11f44 7723 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7724};
7725
7726/* System version register (used on MPC 8xxx) */
7727enum {
80d11f44 7728 POWERPC_SVR_NONE = 0x00000000,
80d11f44
JM		 7729 POWERPC_SVR_5200_v10 = 0x80110010,
7730 POWERPC_SVR_5200_v11 = 0x80110011,
7731 POWERPC_SVR_5200_v12 = 0x80110012,
80d11f44
JM		 7732 POWERPC_SVR_5200B_v20 = 0x80110020,
7733 POWERPC_SVR_5200B_v21 = 0x80110021,
7734#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7735#if 0
80d11f44 7736 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7737#endif
7738#if 0
80d11f44 7739 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7740#endif
7741#if 0
80d11f44 7742 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7743#endif
7744#if 0
80d11f44 7745 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7746#endif
7747#if 0
80d11f44 7748 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7749#endif
7750#if 0
80d11f44 7751 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7752#endif
7753#if 0
80d11f44 7754 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7755#endif
7756#if 0
80d11f44 7757 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7758#endif
7759#if 0
80d11f44 7760 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7761#endif
7762#if 0
80d11f44 7763 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7764#endif
7765#if 0
80d11f44 7766 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7767#endif
7768#if 0
80d11f44 7769 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7770#endif
7771#if 0
80d11f44 7772 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7773#endif
7774#if 0
80d11f44 7775 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7776#endif
7777#if 0
80d11f44 7778 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7779#endif
7780#if 0
80d11f44 7781 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7782#endif
7783#if 0
80d11f44 7784 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7785#endif
7786#if 0
80d11f44
JM		 7787 POWERPC_SVR_8323E = xxx,
7788#endif
492d7bf5 7789 POWERPC_SVR_8343 = 0x80570010,
80d11f44 7790 POWERPC_SVR_8343A = 0x80570030,
492d7bf5 7791 POWERPC_SVR_8343E = 0x80560010,
80d11f44 7792 POWERPC_SVR_8343EA = 0x80560030,
492d7bf5
TM		 7793 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7794 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
80d11f44
JM		 7795 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7796 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
492d7bf5
TM		 7797 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7798 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
80d11f44
JM		 7799 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7800 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7801 POWERPC_SVR_8349 = 0x80510010,
7802 POWERPC_SVR_8349A = 0x80510030,
7803 POWERPC_SVR_8349E = 0x80500010,
7804 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7805#if 0
80d11f44 7806 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7807#endif
7808#if 0
80d11f44
JM		 7809 POWERPC_SVR_8360E = xxx,
7810#endif
7811#define POWERPC_SVR_E500 0x40000000
7812 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7813 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7814 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7815 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7816 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7817 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
80d11f44
JM		 7818 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7819 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
80d11f44
JM		 7820 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7821 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
80d11f44
JM		 7822 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7823 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7824 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
80d11f44
JM		 7825 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7826 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
80d11f44
JM		 7827 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7828 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
80d11f44
JM		 7829 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7830 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7831 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7832 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
80d11f44
JM		 7833 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7834 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7835 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7836 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
80d11f44
JM		 7837 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7838 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
80d11f44
JM		 7839 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7840 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
80d11f44
JM		 7841 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7842 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
80d11f44
JM		 7843 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7844 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
80d11f44
JM		 7845 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7846 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
80d11f44
JM		 7847 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7848 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7849 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7850 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
80d11f44
JM		 7851 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7852 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7853 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7854 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
80d11f44
JM		 7855 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7856 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
80d11f44
JM		 7857 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7858 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
80d11f44
JM		 7859 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7860 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7861 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7862 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7863 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7864 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7865 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7866 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7867 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7868#if 0
80d11f44 7869 POWERPC_SVR_8610 = xxx,
c3e36823 7870#endif
80d11f44
JM		 7871 POWERPC_SVR_8641 = 0x80900021,
7872 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7873};
7874
3fc6c082 7875/*****************************************************************************/
a750fc0b 7876/* PowerPC CPU definitions */
cfe34f44
AF		 7877#define POWERPC_DEF_PREFIX(pvr, svr, type) \
7878 glue(glue(glue(glue(pvr, _), svr), _), type)
80d11f44 7879#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
cfe34f44
AF		 7880 static void \
7881 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init) \
7882 (ObjectClass *oc, void *data) \
7883 { \
7884 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); \
7885 \
7886 pcc->pvr = _pvr; \
7887 pcc->svr = _svr; \
cfe34f44
AF		 7888 pcc->msr_mask = glue(POWERPC_MSRM_, _type); \
7889 pcc->mmu_model = glue(POWERPC_MMU_, _type); \
7890 pcc->excp_model = glue(POWERPC_EXCP_, _type); \
7891 pcc->bus_model = glue(POWERPC_INPUT_, _type); \
7892 pcc->bfd_mach = glue(POWERPC_BFDM_, _type); \
7893 pcc->flags = glue(POWERPC_FLAG_, _type); \
cfe34f44
AF		 7894 } \
7895 \
7896 static const TypeInfo \
7897 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info) = { \
7898 .name = _name "-" TYPE_POWERPC_CPU, \
7856e3a4 7899 .parent = stringify(_type) "-family-" TYPE_POWERPC_CPU, \
cfe34f44
AF		 7900 .class_init = \
7901 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_class_init), \
7902 }; \
7903 \
7904 static void \
7905 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types)(void) \
7906 { \
cfe34f44
AF		 7907 type_register_static( \
7908 &glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_type_info)); \
7909 } \
7910 \
7911 type_init( \
7912 glue(POWERPC_DEF_PREFIX(_pvr, _svr, _type), _cpu_register_types))
7913
80d11f44
JM		 7914#define POWERPC_DEF(_name, _pvr, _type) \
7915POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7916
a750fc0b
JM		 7917 /* Embedded PowerPC */
7918 /* PowerPC 401 family */
2662a059 7919 /* Generic PowerPC 401 */
c4d0a36c 7920 POWERPC_DEF("401", CPU_POWERPC_401, 401)
a750fc0b 7921 /* PowerPC 401 cores */
2662a059 7922 /* PowerPC 401A1 */
c4d0a36c 7923 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401)
a750fc0b 7924 /* PowerPC 401B2 */
c4d0a36c 7925 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2)
2662a059 7926#if defined (TODO)
a750fc0b 7927 /* PowerPC 401B3 */
c4d0a36c 7928 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3)
a750fc0b
JM		 7929#endif
7930 /* PowerPC 401C2 */
c4d0a36c 7931 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2)
a750fc0b 7932 /* PowerPC 401D2 */
c4d0a36c 7933 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2)
a750fc0b 7934 /* PowerPC 401E2 */
c4d0a36c 7935 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2)
a750fc0b 7936 /* PowerPC 401F2 */
c4d0a36c 7937 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2)
a750fc0b
JM		 7938 /* PowerPC 401G2 */
7939 /* XXX: to be checked */
c4d0a36c 7940 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2)
a750fc0b 7941 /* PowerPC 401 microcontrolers */
2662a059 7942#if defined (TODO)
a750fc0b 7943 /* PowerPC 401GF */
c4d0a36c 7944 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401)
3fc6c082 7945#endif
a750fc0b 7946 /* IOP480 (401 microcontroler) */
c4d0a36c 7947 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480)
a750fc0b 7948 /* IBM Processor for Network Resources */
c4d0a36c 7949 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401)
3fc6c082 7950#if defined (TODO)
c4d0a36c 7951 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401)
3fc6c082 7952#endif
a750fc0b 7953 /* PowerPC 403 family */
a750fc0b
JM		 7954 /* PowerPC 403 microcontrolers */
7955 /* PowerPC 403 GA */
c4d0a36c 7956 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403)
a750fc0b 7957 /* PowerPC 403 GB */
c4d0a36c 7958 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403)
a750fc0b 7959 /* PowerPC 403 GC */
c4d0a36c 7960 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403)
a750fc0b 7961 /* PowerPC 403 GCX */
c4d0a36c 7962 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX)
3fc6c082 7963#if defined (TODO)
a750fc0b 7964 /* PowerPC 403 GP */
c4d0a36c 7965 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403)
3fc6c082 7966#endif
a750fc0b 7967 /* PowerPC 405 family */
a750fc0b 7968 /* PowerPC 405 cores */
2662a059 7969#if defined (TODO)
a750fc0b 7970 /* PowerPC 405 A3 */
c4d0a36c 7971 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405)
3a607854 7972#endif
3a607854 7973#if defined (TODO)
a750fc0b 7974 /* PowerPC 405 A4 */
c4d0a36c 7975 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405)
3a607854 7976#endif
3a607854 7977#if defined (TODO)
a750fc0b 7978 /* PowerPC 405 B3 */
c4d0a36c 7979 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405)
3fc6c082
FB		 7980#endif
7981#if defined (TODO)
a750fc0b 7982 /* PowerPC 405 B4 */
c4d0a36c 7983 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405)
a750fc0b
JM		 7984#endif
7985#if defined (TODO)
7986 /* PowerPC 405 C3 */
c4d0a36c 7987 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405)
a750fc0b
JM		 7988#endif
7989#if defined (TODO)
7990 /* PowerPC 405 C4 */
c4d0a36c 7991 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405)
a750fc0b
JM		 7992#endif
7993 /* PowerPC 405 D2 */
c4d0a36c 7994 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405)
a750fc0b
JM		 7995#if defined (TODO)
7996 /* PowerPC 405 D3 */
c4d0a36c 7997 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405)
a750fc0b
JM		 7998#endif
7999 /* PowerPC 405 D4 */
c4d0a36c 8000 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405)
a750fc0b
JM		 8001#if defined (TODO)
8002 /* PowerPC 405 D5 */
c4d0a36c 8003 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405)
a750fc0b
JM		 8004#endif
8005#if defined (TODO)
8006 /* PowerPC 405 E4 */
c4d0a36c 8007 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405)
a750fc0b
JM		 8008#endif
8009#if defined (TODO)
8010 /* PowerPC 405 F4 */
c4d0a36c 8011 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405)
a750fc0b
JM		 8012#endif
8013#if defined (TODO)
8014 /* PowerPC 405 F5 */
c4d0a36c 8015 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405)
a750fc0b
JM		 8016#endif
8017#if defined (TODO)
8018 /* PowerPC 405 F6 */
c4d0a36c 8019 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405)
a750fc0b
JM		 8020#endif
8021 /* PowerPC 405 microcontrolers */
a750fc0b 8022 /* PowerPC 405 CRa */
c4d0a36c 8023 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405)
a750fc0b 8024 /* PowerPC 405 CRb */
c4d0a36c 8025 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405)
a750fc0b 8026 /* PowerPC 405 CRc */
c4d0a36c 8027 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405)
a750fc0b 8028 /* PowerPC 405 EP */
c4d0a36c 8029 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405)
a750fc0b
JM		 8030#if defined(TODO)
8031 /* PowerPC 405 EXr */
c4d0a36c 8032 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405)
a750fc0b
JM		 8033#endif
8034 /* PowerPC 405 EZ */
c4d0a36c 8035 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405)
a750fc0b
JM		 8036#if defined(TODO)
8037 /* PowerPC 405 FX */
c4d0a36c 8038 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405)
a750fc0b 8039#endif
a750fc0b 8040 /* PowerPC 405 GPa */
c4d0a36c 8041 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405)
a750fc0b 8042 /* PowerPC 405 GPb */
c4d0a36c 8043 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405)
a750fc0b 8044 /* PowerPC 405 GPc */
c4d0a36c 8045 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405)
a750fc0b 8046 /* PowerPC 405 GPd */
c4d0a36c 8047 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405)
a750fc0b 8048 /* PowerPC 405 GPR */
c4d0a36c 8049 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405)
a750fc0b
JM		 8050#if defined(TODO)
8051 /* PowerPC 405 H */
c4d0a36c 8052 POWERPC_DEF("405H", CPU_POWERPC_405H, 405)
a750fc0b
JM		 8053#endif
8054#if defined(TODO)
8055 /* PowerPC 405 L */
c4d0a36c 8056 POWERPC_DEF("405L", CPU_POWERPC_405L, 405)
a750fc0b
JM		 8057#endif
8058 /* PowerPC 405 LP */
c4d0a36c 8059 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405)
a750fc0b
JM		 8060#if defined(TODO)
8061 /* PowerPC 405 PM */
c4d0a36c 8062 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405)
a750fc0b
JM		 8063#endif
8064#if defined(TODO)
8065 /* PowerPC 405 PS */
c4d0a36c 8066 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405)
a750fc0b
JM		 8067#endif
8068#if defined(TODO)
8069 /* PowerPC 405 S */
c4d0a36c 8070 POWERPC_DEF("405S", CPU_POWERPC_405S, 405)
a750fc0b
JM		 8071#endif
8072 /* Npe405 H */
c4d0a36c 8073 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405)
a750fc0b 8074 /* Npe405 H2 */
c4d0a36c 8075 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405)
a750fc0b 8076 /* Npe405 L */
c4d0a36c 8077 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405)
a750fc0b 8078 /* Npe4GS3 */
c4d0a36c 8079 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405)
a750fc0b 8080#if defined (TODO)
c4d0a36c 8081 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405)
a750fc0b
JM		 8082#endif
8083#if defined (TODO)
c4d0a36c 8084 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405)
a750fc0b
JM		 8085#endif
8086#if defined (TODO)
8087 /* PowerPC LC77700 (Sanyo) */
c4d0a36c 8088 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405)
a750fc0b
JM		 8089#endif
8090 /* PowerPC 401/403/405 based set-top-box microcontrolers */
8091#if defined (TODO)
8092 /* STB010000 */
c4d0a36c 8093 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2)
a750fc0b
JM		 8094#endif
8095#if defined (TODO)
8096 /* STB01010 */
c4d0a36c 8097 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2)
a750fc0b
JM		 8098#endif
8099#if defined (TODO)
8100 /* STB0210 */
c4d0a36c 8101 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3)
a750fc0b
JM		 8102#endif
8103 /* STB03xx */
c4d0a36c 8104 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405)
a750fc0b
JM		 8105#if defined (TODO)
8106 /* STB043x */
c4d0a36c 8107 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405)
a750fc0b
JM		 8108#endif
8109#if defined (TODO)
8110 /* STB045x */
c4d0a36c 8111 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405)
a750fc0b
JM		 8112#endif
8113 /* STB04xx */
c4d0a36c 8114 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405)
a750fc0b 8115 /* STB25xx */
c4d0a36c 8116 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405)
a750fc0b
JM		 8117#if defined (TODO)
8118 /* STB130 */
c4d0a36c 8119 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405)
a750fc0b
JM		 8120#endif
8121 /* Xilinx PowerPC 405 cores */
c4d0a36c 8122 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405)
c4d0a36c 8123 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405)
a750fc0b
JM		 8124#if defined (TODO)
8125 /* Zarlink ZL10310 */
c4d0a36c 8126 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405)
a750fc0b
JM		 8127#endif
8128#if defined (TODO)
8129 /* Zarlink ZL10311 */
c4d0a36c 8130 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405)
a750fc0b
JM		 8131#endif
8132#if defined (TODO)
8133 /* Zarlink ZL10320 */
c4d0a36c 8134 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405)
a750fc0b
JM		 8135#endif
8136#if defined (TODO)
8137 /* Zarlink ZL10321 */
c4d0a36c 8138 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405)
a750fc0b
JM		 8139#endif
8140 /* PowerPC 440 family */
80d11f44 8141#if defined(TODO_USER_ONLY)
a750fc0b 8142 /* Generic PowerPC 440 */
c4d0a36c 8143 POWERPC_DEF("440", CPU_POWERPC_440, 440GP)
80d11f44 8144#endif
a750fc0b
JM		 8145 /* PowerPC 440 cores */
8146#if defined (TODO)
8147 /* PowerPC 440 A4 */
c4d0a36c 8148 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4)
a750fc0b 8149#endif
95070372 8150 /* PowerPC 440 Xilinx 5 */
c4d0a36c 8151 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5)
a750fc0b
JM		 8152#if defined (TODO)
8153 /* PowerPC 440 A5 */
c4d0a36c 8154 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5)
a750fc0b
JM		 8155#endif
8156#if defined (TODO)
8157 /* PowerPC 440 B4 */
c4d0a36c 8158 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4)
a750fc0b
JM		 8159#endif
8160#if defined (TODO)
8161 /* PowerPC 440 G4 */
c4d0a36c 8162 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4)
a750fc0b
JM		 8163#endif
8164#if defined (TODO)
8165 /* PowerPC 440 F5 */
c4d0a36c 8166 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5)
a750fc0b
JM		 8167#endif
8168#if defined (TODO)
8169 /* PowerPC 440 G5 */
c4d0a36c 8170 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5)
a750fc0b
JM		 8171#endif
8172#if defined (TODO)
8173 /* PowerPC 440H4 */
c4d0a36c 8174 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4)
a750fc0b
JM		 8175#endif
8176#if defined (TODO)
8177 /* PowerPC 440H6 */
c4d0a36c 8178 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5)
a750fc0b
JM		 8179#endif
8180 /* PowerPC 440 microcontrolers */
a750fc0b 8181 /* PowerPC 440 EPa */
c4d0a36c 8182 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP)
a750fc0b 8183 /* PowerPC 440 EPb */
c4d0a36c 8184 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP)
a750fc0b 8185 /* PowerPC 440 EPX */
c4d0a36c 8186 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP)
80d11f44 8187#if defined(TODO_USER_ONLY)
a750fc0b 8188 /* PowerPC 440 GPb */
c4d0a36c 8189 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP)
80d11f44
JM		 8190#endif
8191#if defined(TODO_USER_ONLY)
a750fc0b 8192 /* PowerPC 440 GPc */
c4d0a36c 8193 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP)
80d11f44 8194#endif
80d11f44 8195#if defined(TODO_USER_ONLY)
a750fc0b 8196 /* PowerPC 440 GRa */
c4d0a36c 8197 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5)
80d11f44
JM		 8198#endif
8199#if defined(TODO_USER_ONLY)
a750fc0b 8200 /* PowerPC 440 GRX */
c4d0a36c 8201 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5)
80d11f44 8202#endif
80d11f44 8203#if defined(TODO_USER_ONLY)
a750fc0b 8204 /* PowerPC 440 GXa */
c4d0a36c 8205 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP)
80d11f44
JM		 8206#endif
8207#if defined(TODO_USER_ONLY)
a750fc0b 8208 /* PowerPC 440 GXb */
c4d0a36c 8209 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP)
80d11f44
JM		 8210#endif
8211#if defined(TODO_USER_ONLY)
a750fc0b 8212 /* PowerPC 440 GXc */
c4d0a36c 8213 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP)
80d11f44
JM		 8214#endif
8215#if defined(TODO_USER_ONLY)
a750fc0b 8216 /* PowerPC 440 GXf */
c4d0a36c 8217 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP)
80d11f44 8218#endif
a750fc0b
JM		 8219#if defined(TODO)
8220 /* PowerPC 440 S */
c4d0a36c 8221 POWERPC_DEF("440S", CPU_POWERPC_440S, 440)
a750fc0b 8222#endif
80d11f44 8223#if defined(TODO_USER_ONLY)
a750fc0b 8224 /* PowerPC 440 SP */
c4d0a36c 8225 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP)
80d11f44
JM		 8226#endif
8227#if defined(TODO_USER_ONLY)
a750fc0b 8228 /* PowerPC 440 SP2 */
c4d0a36c 8229 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP)
80d11f44
JM		 8230#endif
8231#if defined(TODO_USER_ONLY)
a750fc0b 8232 /* PowerPC 440 SPE */
c4d0a36c 8233 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP)
80d11f44 8234#endif
a750fc0b
JM		 8235 /* PowerPC 460 family */
8236#if defined (TODO)
8237 /* Generic PowerPC 464 */
c4d0a36c 8238 POWERPC_DEF("464", CPU_POWERPC_464, 460)
a750fc0b
JM		 8239#endif
8240 /* PowerPC 464 microcontrolers */
8241#if defined (TODO)
8242 /* PowerPC 464H90 */
c4d0a36c 8243 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460)
a750fc0b
JM		 8244#endif
8245#if defined (TODO)
8246 /* PowerPC 464H90F */
c4d0a36c 8247 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F)
a750fc0b
JM		 8248#endif
8249 /* Freescale embedded PowerPC cores */
80d11f44
JM		 8250 /* MPC5xx family (aka RCPU) */
8251#if defined(TODO_USER_ONLY)
8252 /* Generic MPC5xx core */
c4d0a36c 8253 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx)
80d11f44
JM		 8254#endif
8255 /* MPC8xx family (aka PowerQUICC) */
8256#if defined(TODO_USER_ONLY)
8257 /* Generic MPC8xx core */
c4d0a36c 8258 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx)
80d11f44
JM		 8259#endif
8260 /* MPC82xx family (aka PowerQUICC-II) */
80d11f44 8261 /* PowerPC G2 core */
c4d0a36c 8262 POWERPC_DEF("G2", CPU_POWERPC_G2, G2)
80d11f44 8263 /* PowerPC G2 H4 core */
c4d0a36c 8264 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2)
80d11f44 8265 /* PowerPC G2 GP core */
c4d0a36c 8266 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2)
80d11f44 8267 /* PowerPC G2 LS core */
c4d0a36c 8268 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2)
80d11f44 8269 /* PowerPC G2 HiP3 core */
c4d0a36c 8270 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2)
80d11f44 8271 /* PowerPC G2 HiP4 core */
c4d0a36c 8272 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2)
80d11f44 8273 /* PowerPC MPC603 core */
c4d0a36c 8274 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E)
80d11f44 8275 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
c4d0a36c 8276 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE)
80d11f44 8277 /* PowerPC G2LE GP core */
c4d0a36c 8278 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE)
80d11f44 8279 /* PowerPC G2LE LS core */
c4d0a36c 8280 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE)
80d11f44 8281 /* PowerPC G2LE GP1 core */
c4d0a36c 8282 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE)
80d11f44 8283 /* PowerPC G2LE GP3 core */
c4d0a36c 8284 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp3, G2LE)
80d11f44 8285 /* PowerPC G2 microcontrollers */
082c6681 8286#if defined(TODO)
80d11f44
JM		 8287 /* MPC5121 */
8288 POWERPC_DEF_SVR("MPC5121",
c4d0a36c 8289 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE)
80d11f44 8290#endif
80d11f44
JM		 8291 /* MPC5200 v1.0 */
8292 POWERPC_DEF_SVR("MPC5200_v10",
c4d0a36c 8293 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE)
80d11f44
JM		 8294 /* MPC5200 v1.1 */
8295 POWERPC_DEF_SVR("MPC5200_v11",
c4d0a36c 8296 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE)
80d11f44
JM		 8297 /* MPC5200 v1.2 */
8298 POWERPC_DEF_SVR("MPC5200_v12",
c4d0a36c 8299 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE)
80d11f44
JM		 8300 /* MPC5200B v2.0 */
8301 POWERPC_DEF_SVR("MPC5200B_v20",
c4d0a36c 8302 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE)
80d11f44
JM		 8303 /* MPC5200B v2.1 */
8304 POWERPC_DEF_SVR("MPC5200B_v21",
c4d0a36c 8305 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE)
a750fc0b 8306 /* e200 family */
80d11f44
JM		 8307 /* Generic MPC55xx core */
8308#if defined (TODO)
8309 POWERPC_DEF_SVR("MPC55xx",
c4d0a36c 8310 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200)
a750fc0b
JM		 8311#endif
8312#if defined (TODO)
80d11f44 8313 /* PowerPC e200z0 core */
c4d0a36c 8314 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200)
a750fc0b
JM		 8315#endif
8316#if defined (TODO)
80d11f44 8317 /* PowerPC e200z1 core */
c4d0a36c 8318 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200)
80d11f44
JM		 8319#endif
8320#if defined (TODO)
8321 /* PowerPC e200z3 core */
c4d0a36c 8322 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200)
80d11f44
JM		 8323#endif
8324 /* PowerPC e200z5 core */
c4d0a36c 8325 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200)
a750fc0b 8326 /* PowerPC e200z6 core */
c4d0a36c 8327 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200)
80d11f44
JM		 8328 /* PowerPC e200 microcontrollers */
8329#if defined (TODO)
8330 /* MPC5514E */
8331 POWERPC_DEF_SVR("MPC5514E",
c4d0a36c 8332 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200)
a750fc0b 8333#endif
a750fc0b 8334#if defined (TODO)
80d11f44
JM		 8335 /* MPC5514E v0 */
8336 POWERPC_DEF_SVR("MPC5514E_v0",
c4d0a36c 8337 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200)
a750fc0b
JM		 8338#endif
8339#if defined (TODO)
80d11f44
JM		 8340 /* MPC5514E v1 */
8341 POWERPC_DEF_SVR("MPC5514E_v1",
c4d0a36c 8342 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200)
a750fc0b
JM		 8343#endif
8344#if defined (TODO)
80d11f44
JM		 8345 /* MPC5514G */
8346 POWERPC_DEF_SVR("MPC5514G",
c4d0a36c 8347 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200)
a750fc0b
JM		 8348#endif
8349#if defined (TODO)
80d11f44
JM		 8350 /* MPC5514G v0 */
8351 POWERPC_DEF_SVR("MPC5514G_v0",
c4d0a36c 8352 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200)
a750fc0b 8353#endif
a750fc0b 8354#if defined (TODO)
80d11f44
JM		 8355 /* MPC5514G v1 */
8356 POWERPC_DEF_SVR("MPC5514G_v1",
c4d0a36c 8357 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200)
a750fc0b
JM		 8358#endif
8359#if defined (TODO)
80d11f44
JM		 8360 /* MPC5515S */
8361 POWERPC_DEF_SVR("MPC5515S",
c4d0a36c 8362 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200)
a750fc0b
JM		 8363#endif
8364#if defined (TODO)
80d11f44
JM		 8365 /* MPC5516E */
8366 POWERPC_DEF_SVR("MPC5516E",
c4d0a36c 8367 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200)
a750fc0b
JM		 8368#endif
8369#if defined (TODO)
80d11f44
JM		 8370 /* MPC5516E v0 */
8371 POWERPC_DEF_SVR("MPC5516E_v0",
c4d0a36c 8372 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200)
a750fc0b
JM		 8373#endif
8374#if defined (TODO)
80d11f44
JM		 8375 /* MPC5516E v1 */
8376 POWERPC_DEF_SVR("MPC5516E_v1",
c4d0a36c 8377 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200)
a750fc0b 8378#endif
a750fc0b 8379#if defined (TODO)
80d11f44
JM		 8380 /* MPC5516G */
8381 POWERPC_DEF_SVR("MPC5516G",
c4d0a36c 8382 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200)
a750fc0b 8383#endif
a750fc0b 8384#if defined (TODO)
80d11f44
JM		 8385 /* MPC5516G v0 */
8386 POWERPC_DEF_SVR("MPC5516G_v0",
c4d0a36c 8387 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200)
a750fc0b 8388#endif
a750fc0b 8389#if defined (TODO)
80d11f44
JM		 8390 /* MPC5516G v1 */
8391 POWERPC_DEF_SVR("MPC5516G_v1",
c4d0a36c 8392 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200)
a750fc0b 8393#endif
a750fc0b 8394#if defined (TODO)
80d11f44
JM		 8395 /* MPC5516S */
8396 POWERPC_DEF_SVR("MPC5516S",
c4d0a36c 8397 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200)
a750fc0b
JM		 8398#endif
8399#if defined (TODO)
80d11f44
JM		 8400 /* MPC5533 */
8401 POWERPC_DEF_SVR("MPC5533",
c4d0a36c 8402 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200)
a750fc0b
JM		 8403#endif
8404#if defined (TODO)
80d11f44
JM		 8405 /* MPC5534 */
8406 POWERPC_DEF_SVR("MPC5534",
c4d0a36c 8407 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200)
a750fc0b 8408#endif
80d11f44
JM		 8409#if defined (TODO)
8410 /* MPC5553 */
8411 POWERPC_DEF_SVR("MPC5553",
c4d0a36c 8412 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200)
80d11f44
JM		 8413#endif
8414#if defined (TODO)
8415 /* MPC5554 */
8416 POWERPC_DEF_SVR("MPC5554",
c4d0a36c 8417 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200)
80d11f44
JM		 8418#endif
8419#if defined (TODO)
8420 /* MPC5561 */
8421 POWERPC_DEF_SVR("MPC5561",
c4d0a36c 8422 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200)
80d11f44
JM		 8423#endif
8424#if defined (TODO)
8425 /* MPC5565 */
8426 POWERPC_DEF_SVR("MPC5565",
c4d0a36c 8427 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200)
80d11f44
JM		 8428#endif
8429#if defined (TODO)
8430 /* MPC5566 */
8431 POWERPC_DEF_SVR("MPC5566",
c4d0a36c 8432 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200)
80d11f44
JM		 8433#endif
8434#if defined (TODO)
8435 /* MPC5567 */
8436 POWERPC_DEF_SVR("MPC5567",
c4d0a36c 8437 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200)
80d11f44
JM		 8438#endif
8439 /* e300 family */
80d11f44 8440 /* PowerPC e300c1 core */
c4d0a36c 8441 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300)
80d11f44 8442 /* PowerPC e300c2 core */
c4d0a36c 8443 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300)
80d11f44 8444 /* PowerPC e300c3 core */
c4d0a36c 8445 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300)
80d11f44 8446 /* PowerPC e300c4 core */
c4d0a36c 8447 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300)
80d11f44
JM		 8448 /* PowerPC e300 microcontrollers */
8449#if defined (TODO)
8450 /* MPC8313 */
8451 POWERPC_DEF_SVR("MPC8313",
c4d0a36c 8452 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300)
80d11f44
JM		 8453#endif
8454#if defined (TODO)
8455 /* MPC8313E */
8456 POWERPC_DEF_SVR("MPC8313E",
c4d0a36c 8457 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300)
80d11f44
JM		 8458#endif
8459#if defined (TODO)
8460 /* MPC8314 */
8461 POWERPC_DEF_SVR("MPC8314",
c4d0a36c 8462 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300)
80d11f44
JM		 8463#endif
8464#if defined (TODO)
8465 /* MPC8314E */
8466 POWERPC_DEF_SVR("MPC8314E",
c4d0a36c 8467 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300)
80d11f44
JM		 8468#endif
8469#if defined (TODO)
8470 /* MPC8315 */
8471 POWERPC_DEF_SVR("MPC8315",
c4d0a36c 8472 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300)
80d11f44
JM		 8473#endif
8474#if defined (TODO)
8475 /* MPC8315E */
8476 POWERPC_DEF_SVR("MPC8315E",
c4d0a36c 8477 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300)
80d11f44
JM		 8478#endif
8479#if defined (TODO)
8480 /* MPC8321 */
8481 POWERPC_DEF_SVR("MPC8321",
c4d0a36c 8482 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300)
80d11f44
JM		 8483#endif
8484#if defined (TODO)
8485 /* MPC8321E */
8486 POWERPC_DEF_SVR("MPC8321E",
c4d0a36c 8487 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300)
80d11f44
JM		 8488#endif
8489#if defined (TODO)
8490 /* MPC8323 */
8491 POWERPC_DEF_SVR("MPC8323",
c4d0a36c 8492 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300)
80d11f44
JM		 8493#endif
8494#if defined (TODO)
8495 /* MPC8323E */
8496 POWERPC_DEF_SVR("MPC8323E",
c4d0a36c 8497 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300)
80d11f44 8498#endif
492d7bf5
TM		 8499 /* MPC8343 */
8500 POWERPC_DEF_SVR("MPC8343",
c4d0a36c 8501 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300)
80d11f44
JM		 8502 /* MPC8343A */
8503 POWERPC_DEF_SVR("MPC8343A",
c4d0a36c 8504 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300)
492d7bf5
TM		 8505 /* MPC8343E */
8506 POWERPC_DEF_SVR("MPC8343E",
c4d0a36c 8507 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300)
80d11f44
JM		 8508 /* MPC8343EA */
8509 POWERPC_DEF_SVR("MPC8343EA",
c4d0a36c 8510 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300)
492d7bf5
TM		 8511 /* MPC8347T */
8512 POWERPC_DEF_SVR("MPC8347T",
c4d0a36c 8513 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300)
492d7bf5
TM		 8514 /* MPC8347P */
8515 POWERPC_DEF_SVR("MPC8347P",
c4d0a36c 8516 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300)
80d11f44
JM		 8517 /* MPC8347AT */
8518 POWERPC_DEF_SVR("MPC8347AT",
c4d0a36c 8519 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300)
80d11f44
JM		 8520 /* MPC8347AP */
8521 POWERPC_DEF_SVR("MPC8347AP",
c4d0a36c 8522 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300)
492d7bf5
TM		 8523 /* MPC8347ET */
8524 POWERPC_DEF_SVR("MPC8347ET",
c4d0a36c 8525 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300)
492d7bf5
TM		 8526 /* MPC8343EP */
8527 POWERPC_DEF_SVR("MPC8347EP",
c4d0a36c 8528 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300)
80d11f44
JM		 8529 /* MPC8347EAT */
8530 POWERPC_DEF_SVR("MPC8347EAT",
c4d0a36c 8531 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300)
80d11f44
JM		 8532 /* MPC8343EAP */
8533 POWERPC_DEF_SVR("MPC8347EAP",
c4d0a36c 8534 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300)
80d11f44
JM		 8535 /* MPC8349 */
8536 POWERPC_DEF_SVR("MPC8349",
c4d0a36c 8537 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300)
80d11f44
JM		 8538 /* MPC8349A */
8539 POWERPC_DEF_SVR("MPC8349A",
c4d0a36c 8540 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300)
80d11f44
JM		 8541 /* MPC8349E */
8542 POWERPC_DEF_SVR("MPC8349E",
c4d0a36c 8543 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300)
80d11f44
JM		 8544 /* MPC8349EA */
8545 POWERPC_DEF_SVR("MPC8349EA",
c4d0a36c 8546 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300)
80d11f44
JM		 8547#if defined (TODO)
8548 /* MPC8358E */
8549 POWERPC_DEF_SVR("MPC8358E",
c4d0a36c 8550 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300)
80d11f44
JM		 8551#endif
8552#if defined (TODO)
8553 /* MPC8360E */
8554 POWERPC_DEF_SVR("MPC8360E",
c4d0a36c 8555 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300)
80d11f44
JM		 8556#endif
8557 /* MPC8377 */
8558 POWERPC_DEF_SVR("MPC8377",
c4d0a36c 8559 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300)
80d11f44
JM		 8560 /* MPC8377E */
8561 POWERPC_DEF_SVR("MPC8377E",
c4d0a36c 8562 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300)
80d11f44
JM		 8563 /* MPC8378 */
8564 POWERPC_DEF_SVR("MPC8378",
c4d0a36c 8565 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300)
80d11f44
JM		 8566 /* MPC8378E */
8567 POWERPC_DEF_SVR("MPC8378E",
c4d0a36c 8568 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300)
80d11f44
JM		 8569 /* MPC8379 */
8570 POWERPC_DEF_SVR("MPC8379",
c4d0a36c 8571 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300)
80d11f44
JM		 8572 /* MPC8379E */
8573 POWERPC_DEF_SVR("MPC8379E",
c4d0a36c 8574 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300)
80d11f44 8575 /* e500 family */
80d11f44 8576 /* PowerPC e500 v1.0 core */
c4d0a36c 8577 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1)
80d11f44 8578 /* PowerPC e500 v2.0 core */
c4d0a36c 8579 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1)
80d11f44 8580 /* PowerPC e500v2 v1.0 core */
c4d0a36c 8581 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2)
80d11f44 8582 /* PowerPC e500v2 v2.0 core */
c4d0a36c 8583 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2)
80d11f44 8584 /* PowerPC e500v2 v2.1 core */
c4d0a36c 8585 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2)
80d11f44 8586 /* PowerPC e500v2 v2.2 core */
c4d0a36c 8587 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2)
80d11f44 8588 /* PowerPC e500v2 v3.0 core */
c4d0a36c
AF		 8589 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2)
8590 POWERPC_DEF_SVR("e500mc", CPU_POWERPC_e500mc, POWERPC_SVR_E500, e500mc)
b81ccf8a 8591#ifdef TARGET_PPC64
c4d0a36c 8592 POWERPC_DEF_SVR("e5500", CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500)
b81ccf8a 8593#endif
80d11f44 8594 /* PowerPC e500 microcontrollers */
80d11f44
JM		 8595 /* MPC8533 v1.0 */
8596 POWERPC_DEF_SVR("MPC8533_v10",
c4d0a36c 8597 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2)
80d11f44
JM		 8598 /* MPC8533 v1.1 */
8599 POWERPC_DEF_SVR("MPC8533_v11",
c4d0a36c 8600 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2)
80d11f44
JM		 8601 /* MPC8533E v1.0 */
8602 POWERPC_DEF_SVR("MPC8533E_v10",
c4d0a36c 8603 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2)
80d11f44 8604 POWERPC_DEF_SVR("MPC8533E_v11",
c4d0a36c 8605 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2)
80d11f44
JM		 8606 /* MPC8540 v1.0 */
8607 POWERPC_DEF_SVR("MPC8540_v10",
c4d0a36c 8608 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1)
80d11f44
JM		 8609 /* MPC8540 v2.0 */
8610 POWERPC_DEF_SVR("MPC8540_v20",
c4d0a36c 8611 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1)
80d11f44
JM		 8612 /* MPC8540 v2.1 */
8613 POWERPC_DEF_SVR("MPC8540_v21",
c4d0a36c 8614 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1)
80d11f44
JM		 8615 /* MPC8541 v1.0 */
8616 POWERPC_DEF_SVR("MPC8541_v10",
c4d0a36c 8617 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1)
80d11f44
JM		 8618 /* MPC8541 v1.1 */
8619 POWERPC_DEF_SVR("MPC8541_v11",
c4d0a36c 8620 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1)
80d11f44
JM		 8621 /* MPC8541E v1.0 */
8622 POWERPC_DEF_SVR("MPC8541E_v10",
c4d0a36c 8623 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1)
80d11f44
JM		 8624 /* MPC8541E v1.1 */
8625 POWERPC_DEF_SVR("MPC8541E_v11",
c4d0a36c 8626 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1)
80d11f44
JM		 8627 /* MPC8543 v1.0 */
8628 POWERPC_DEF_SVR("MPC8543_v10",
c4d0a36c 8629 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2)
80d11f44
JM		 8630 /* MPC8543 v1.1 */
8631 POWERPC_DEF_SVR("MPC8543_v11",
c4d0a36c 8632 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2)
80d11f44
JM		 8633 /* MPC8543 v2.0 */
8634 POWERPC_DEF_SVR("MPC8543_v20",
c4d0a36c 8635 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2)
80d11f44
JM		 8636 /* MPC8543 v2.1 */
8637 POWERPC_DEF_SVR("MPC8543_v21",
c4d0a36c 8638 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2)
80d11f44
JM		 8639 /* MPC8543E v1.0 */
8640 POWERPC_DEF_SVR("MPC8543E_v10",
c4d0a36c 8641 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2)
80d11f44
JM		 8642 /* MPC8543E v1.1 */
8643 POWERPC_DEF_SVR("MPC8543E_v11",
c4d0a36c 8644 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2)
80d11f44
JM		 8645 /* MPC8543E v2.0 */
8646 POWERPC_DEF_SVR("MPC8543E_v20",
c4d0a36c 8647 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2)
80d11f44
JM		 8648 /* MPC8543E v2.1 */
8649 POWERPC_DEF_SVR("MPC8543E_v21",
c4d0a36c 8650 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2)
80d11f44
JM		 8651 /* MPC8544 v1.0 */
8652 POWERPC_DEF_SVR("MPC8544_v10",
c4d0a36c 8653 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2)
80d11f44
JM		 8654 /* MPC8544 v1.1 */
8655 POWERPC_DEF_SVR("MPC8544_v11",
c4d0a36c 8656 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2)
80d11f44
JM		 8657 /* MPC8544E v1.0 */
8658 POWERPC_DEF_SVR("MPC8544E_v10",
c4d0a36c 8659 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2)
80d11f44
JM		 8660 /* MPC8544E v1.1 */
8661 POWERPC_DEF_SVR("MPC8544E_v11",
c4d0a36c 8662 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2)
80d11f44
JM		 8663 /* MPC8545 v2.0 */
8664 POWERPC_DEF_SVR("MPC8545_v20",
c4d0a36c 8665 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2)
80d11f44
JM		 8666 /* MPC8545 v2.1 */
8667 POWERPC_DEF_SVR("MPC8545_v21",
c4d0a36c 8668 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2)
80d11f44
JM		 8669 /* MPC8545E v2.0 */
8670 POWERPC_DEF_SVR("MPC8545E_v20",
c4d0a36c 8671 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2)
80d11f44
JM		 8672 /* MPC8545E v2.1 */
8673 POWERPC_DEF_SVR("MPC8545E_v21",
c4d0a36c 8674 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2)
80d11f44
JM		 8675 /* MPC8547E v2.0 */
8676 POWERPC_DEF_SVR("MPC8547E_v20",
c4d0a36c 8677 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2)
80d11f44
JM		 8678 /* MPC8547E v2.1 */
8679 POWERPC_DEF_SVR("MPC8547E_v21",
c4d0a36c 8680 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2)
80d11f44
JM		 8681 /* MPC8548 v1.0 */
8682 POWERPC_DEF_SVR("MPC8548_v10",
c4d0a36c 8683 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2)
80d11f44
JM		 8684 /* MPC8548 v1.1 */
8685 POWERPC_DEF_SVR("MPC8548_v11",
c4d0a36c 8686 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2)
80d11f44
JM		 8687 /* MPC8548 v2.0 */
8688 POWERPC_DEF_SVR("MPC8548_v20",
c4d0a36c 8689 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2)
80d11f44
JM		 8690 /* MPC8548 v2.1 */
8691 POWERPC_DEF_SVR("MPC8548_v21",
c4d0a36c 8692 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2)
80d11f44
JM		 8693 /* MPC8548E v1.0 */
8694 POWERPC_DEF_SVR("MPC8548E_v10",
c4d0a36c 8695 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2)
80d11f44
JM		 8696 /* MPC8548E v1.1 */
8697 POWERPC_DEF_SVR("MPC8548E_v11",
c4d0a36c 8698 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2)
80d11f44
JM		 8699 /* MPC8548E v2.0 */
8700 POWERPC_DEF_SVR("MPC8548E_v20",
c4d0a36c 8701 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2)
80d11f44
JM		 8702 /* MPC8548E v2.1 */
8703 POWERPC_DEF_SVR("MPC8548E_v21",
c4d0a36c 8704 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2)
80d11f44
JM		 8705 /* MPC8555 v1.0 */
8706 POWERPC_DEF_SVR("MPC8555_v10",
c4d0a36c 8707 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2)
80d11f44
JM		 8708 /* MPC8555 v1.1 */
8709 POWERPC_DEF_SVR("MPC8555_v11",
c4d0a36c 8710 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2)
80d11f44
JM		 8711 /* MPC8555E v1.0 */
8712 POWERPC_DEF_SVR("MPC8555E_v10",
c4d0a36c 8713 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2)
80d11f44
JM		 8714 /* MPC8555E v1.1 */
8715 POWERPC_DEF_SVR("MPC8555E_v11",
c4d0a36c 8716 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2)
80d11f44
JM		 8717 /* MPC8560 v1.0 */
8718 POWERPC_DEF_SVR("MPC8560_v10",
c4d0a36c 8719 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2)
80d11f44
JM		 8720 /* MPC8560 v2.0 */
8721 POWERPC_DEF_SVR("MPC8560_v20",
c4d0a36c 8722 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2)
80d11f44
JM		 8723 /* MPC8560 v2.1 */
8724 POWERPC_DEF_SVR("MPC8560_v21",
c4d0a36c 8725 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2)
80d11f44
JM		 8726 /* MPC8567 */
8727 POWERPC_DEF_SVR("MPC8567",
c4d0a36c 8728 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2)
80d11f44
JM		 8729 /* MPC8567E */
8730 POWERPC_DEF_SVR("MPC8567E",
c4d0a36c 8731 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2)
80d11f44
JM		 8732 /* MPC8568 */
8733 POWERPC_DEF_SVR("MPC8568",
c4d0a36c 8734 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2)
80d11f44
JM		 8735 /* MPC8568E */
8736 POWERPC_DEF_SVR("MPC8568E",
c4d0a36c 8737 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2)
80d11f44
JM		 8738 /* MPC8572 */
8739 POWERPC_DEF_SVR("MPC8572",
c4d0a36c 8740 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2)
80d11f44
JM		 8741 /* MPC8572E */
8742 POWERPC_DEF_SVR("MPC8572E",
c4d0a36c 8743 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2)
80d11f44
JM		 8744 /* e600 family */
8745 /* PowerPC e600 core */
c4d0a36c 8746 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400)
80d11f44
JM		 8747 /* PowerPC e600 microcontrollers */
8748#if defined (TODO)
8749 /* MPC8610 */
8750 POWERPC_DEF_SVR("MPC8610",
c4d0a36c 8751 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400)
80d11f44
JM		 8752#endif
8753 /* MPC8641 */
8754 POWERPC_DEF_SVR("MPC8641",
c4d0a36c 8755 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400)
80d11f44
JM		 8756 /* MPC8641D */
8757 POWERPC_DEF_SVR("MPC8641D",
c4d0a36c 8758 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400)
a750fc0b
JM		 8759 /* 32 bits "classic" PowerPC */
8760 /* PowerPC 6xx family */
c3e36823 8761 /* PowerPC 601v0 */
c4d0a36c 8762 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601)
c3e36823 8763 /* PowerPC 601v1 */
c4d0a36c 8764 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601)
a750fc0b 8765 /* PowerPC 601v2 */
c4d0a36c 8766 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v)
a750fc0b 8767 /* PowerPC 602 */
c4d0a36c 8768 POWERPC_DEF("602", CPU_POWERPC_602, 602)
a750fc0b 8769 /* PowerPC 603 */
c4d0a36c 8770 POWERPC_DEF("603", CPU_POWERPC_603, 603)
a750fc0b 8771 /* PowerPC 603e v1.1 */
c4d0a36c 8772 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E)
a750fc0b 8773 /* PowerPC 603e v1.2 */
c4d0a36c 8774 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E)
a750fc0b 8775 /* PowerPC 603e v1.3 */
c4d0a36c 8776 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E)
a750fc0b 8777 /* PowerPC 603e v1.4 */
c4d0a36c 8778 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E)
a750fc0b 8779 /* PowerPC 603e v2.2 */
c4d0a36c 8780 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E)
a750fc0b 8781 /* PowerPC 603e v3 */
c4d0a36c 8782 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E)
a750fc0b 8783 /* PowerPC 603e v4 */
c4d0a36c 8784 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E)
a750fc0b 8785 /* PowerPC 603e v4.1 */
c4d0a36c 8786 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E)
082c6681 8787 /* PowerPC 603e (aka PID7) */
c4d0a36c 8788 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E)
a750fc0b 8789 /* PowerPC 603e7t */
c4d0a36c 8790 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E)
a750fc0b 8791 /* PowerPC 603e7v */
c4d0a36c 8792 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E)
a750fc0b 8793 /* PowerPC 603e7v1 */
c4d0a36c 8794 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E)
a750fc0b 8795 /* PowerPC 603e7v2 */
c4d0a36c 8796 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E)
082c6681 8797 /* PowerPC 603p (aka PID7v) */
c4d0a36c 8798 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E)
a750fc0b 8799 /* PowerPC 604 */
c4d0a36c 8800 POWERPC_DEF("604", CPU_POWERPC_604, 604)
a750fc0b 8801 /* PowerPC 604e v1.0 */
c4d0a36c 8802 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E)
a750fc0b 8803 /* PowerPC 604e v2.2 */
c4d0a36c 8804 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E)
a750fc0b 8805 /* PowerPC 604e v2.4 */
c4d0a36c 8806 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E)
082c6681 8807 /* PowerPC 604r (aka PIDA) */
c4d0a36c 8808 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E)
a750fc0b
JM		 8809#if defined(TODO)
8810 /* PowerPC 604ev */
c4d0a36c 8811 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E)
a750fc0b
JM		 8812#endif
8813 /* PowerPC 7xx family */
bd928eba 8814 /* PowerPC 740 v1.0 (G3) */
c4d0a36c 8815 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740)
bd928eba 8816 /* PowerPC 750 v1.0 (G3) */
c4d0a36c 8817 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750)
a750fc0b 8818 /* PowerPC 740 v2.0 (G3) */
c4d0a36c 8819 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740)
a750fc0b 8820 /* PowerPC 750 v2.0 (G3) */
c4d0a36c 8821 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750)
a750fc0b 8822 /* PowerPC 740 v2.1 (G3) */
c4d0a36c 8823 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740)
a750fc0b 8824 /* PowerPC 750 v2.1 (G3) */
c4d0a36c 8825 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750)
a750fc0b 8826 /* PowerPC 740 v2.2 (G3) */
c4d0a36c 8827 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740)
a750fc0b 8828 /* PowerPC 750 v2.2 (G3) */
c4d0a36c 8829 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750)
a750fc0b 8830 /* PowerPC 740 v3.0 (G3) */
c4d0a36c 8831 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740)
a750fc0b 8832 /* PowerPC 750 v3.0 (G3) */
c4d0a36c 8833 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750)
a750fc0b 8834 /* PowerPC 740 v3.1 (G3) */
c4d0a36c 8835 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740)
a750fc0b 8836 /* PowerPC 750 v3.1 (G3) */
c4d0a36c 8837 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750)
a750fc0b 8838 /* PowerPC 740E (G3) */
c4d0a36c 8839 POWERPC_DEF("740e", CPU_POWERPC_740E, 740)
bd928eba 8840 /* PowerPC 750E (G3) */
c4d0a36c 8841 POWERPC_DEF("750e", CPU_POWERPC_750E, 750)
a750fc0b 8842 /* PowerPC 740P (G3) */
c4d0a36c 8843 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740)
a750fc0b 8844 /* PowerPC 750P (G3) */
c4d0a36c 8845 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750)
bd928eba 8846 /* PowerPC 750CL v1.0 */
c4d0a36c 8847 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl)
bd928eba 8848 /* PowerPC 750CL v2.0 */
c4d0a36c 8849 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl)
bd928eba 8850 /* PowerPC 750CX v1.0 (G3 embedded) */
c4d0a36c 8851 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx)
bd928eba 8852 /* PowerPC 750CX v2.1 (G3 embedded) */
c4d0a36c 8853 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx)
a750fc0b 8854 /* PowerPC 750CX v2.1 (G3 embedded) */
c4d0a36c 8855 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx)
a750fc0b 8856 /* PowerPC 750CX v2.2 (G3 embedded) */
c4d0a36c 8857 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx)
a750fc0b 8858 /* PowerPC 750CXe v2.1 (G3 embedded) */
c4d0a36c 8859 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx)
a750fc0b 8860 /* PowerPC 750CXe v2.2 (G3 embedded) */
c4d0a36c 8861 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx)
a750fc0b 8862 /* PowerPC 750CXe v2.3 (G3 embedded) */
c4d0a36c 8863 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx)
a750fc0b 8864 /* PowerPC 750CXe v2.4 (G3 embedded) */
c4d0a36c 8865 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx)
a750fc0b 8866 /* PowerPC 750CXe v2.4b (G3 embedded) */
c4d0a36c 8867 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx)
bd928eba 8868 /* PowerPC 750CXe v3.0 (G3 embedded) */
c4d0a36c 8869 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx)
a750fc0b 8870 /* PowerPC 750CXe v3.1 (G3 embedded) */
c4d0a36c 8871 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx)
a750fc0b 8872 /* PowerPC 750CXe v3.1b (G3 embedded) */
c4d0a36c 8873 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx)
a750fc0b 8874 /* PowerPC 750CXr (G3 embedded) */
c4d0a36c 8875 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx)
a750fc0b 8876 /* PowerPC 750FL (G3 embedded) */
c4d0a36c 8877 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx)
a750fc0b 8878 /* PowerPC 750FX v1.0 (G3 embedded) */
c4d0a36c 8879 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx)
a750fc0b 8880 /* PowerPC 750FX v2.0 (G3 embedded) */
c4d0a36c 8881 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx)
a750fc0b 8882 /* PowerPC 750FX v2.1 (G3 embedded) */
c4d0a36c 8883 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx)
a750fc0b 8884 /* PowerPC 750FX v2.2 (G3 embedded) */
c4d0a36c 8885 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx)
a750fc0b 8886 /* PowerPC 750FX v2.3 (G3 embedded) */
c4d0a36c 8887 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx)
a750fc0b 8888 /* PowerPC 750GL (G3 embedded) */
c4d0a36c 8889 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx)
a750fc0b 8890 /* PowerPC 750GX v1.0 (G3 embedded) */
c4d0a36c 8891 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx)
a750fc0b 8892 /* PowerPC 750GX v1.1 (G3 embedded) */
c4d0a36c 8893 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx)
a750fc0b 8894 /* PowerPC 750GX v1.2 (G3 embedded) */
c4d0a36c 8895 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx)
bd928eba 8896 /* PowerPC 750L v2.0 (G3 embedded) */
c4d0a36c 8897 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750)
bd928eba 8898 /* PowerPC 750L v2.1 (G3 embedded) */
c4d0a36c 8899 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750)
a750fc0b 8900 /* PowerPC 750L v2.2 (G3 embedded) */
c4d0a36c 8901 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750)
a750fc0b 8902 /* PowerPC 750L v3.0 (G3 embedded) */
c4d0a36c 8903 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750)
a750fc0b 8904 /* PowerPC 750L v3.2 (G3 embedded) */
c4d0a36c 8905 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750)
a750fc0b 8906 /* PowerPC 745 v1.0 */
c4d0a36c 8907 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745)
a750fc0b 8908 /* PowerPC 755 v1.0 */
c4d0a36c 8909 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755)
a750fc0b 8910 /* PowerPC 745 v1.1 */
c4d0a36c 8911 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745)
a750fc0b 8912 /* PowerPC 755 v1.1 */
c4d0a36c 8913 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755)
a750fc0b 8914 /* PowerPC 745 v2.0 */
c4d0a36c 8915 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745)
a750fc0b 8916 /* PowerPC 755 v2.0 */
c4d0a36c 8917 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755)
a750fc0b 8918 /* PowerPC 745 v2.1 */
c4d0a36c 8919 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745)
a750fc0b 8920 /* PowerPC 755 v2.1 */
c4d0a36c 8921 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755)
a750fc0b 8922 /* PowerPC 745 v2.2 */
c4d0a36c 8923 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745)
a750fc0b 8924 /* PowerPC 755 v2.2 */
c4d0a36c 8925 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755)
a750fc0b 8926 /* PowerPC 745 v2.3 */
c4d0a36c 8927 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745)
a750fc0b 8928 /* PowerPC 755 v2.3 */
c4d0a36c 8929 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755)
a750fc0b 8930 /* PowerPC 745 v2.4 */
c4d0a36c 8931 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745)
a750fc0b 8932 /* PowerPC 755 v2.4 */
c4d0a36c 8933 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755)
a750fc0b 8934 /* PowerPC 745 v2.5 */
c4d0a36c 8935 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745)
a750fc0b 8936 /* PowerPC 755 v2.5 */
c4d0a36c 8937 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755)
a750fc0b 8938 /* PowerPC 745 v2.6 */
c4d0a36c 8939 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745)
a750fc0b 8940 /* PowerPC 755 v2.6 */
c4d0a36c 8941 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755)
a750fc0b 8942 /* PowerPC 745 v2.7 */
c4d0a36c 8943 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745)
a750fc0b 8944 /* PowerPC 755 v2.7 */
c4d0a36c 8945 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755)
a750fc0b 8946 /* PowerPC 745 v2.8 */
c4d0a36c 8947 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745)
a750fc0b 8948 /* PowerPC 755 v2.8 */
c4d0a36c 8949 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755)
a750fc0b
JM		 8950#if defined (TODO)
8951 /* PowerPC 745P (G3) */
c4d0a36c 8952 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745)
a750fc0b 8953 /* PowerPC 755P (G3) */
c4d0a36c 8954 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755)
a750fc0b
JM		 8955#endif
8956 /* PowerPC 74xx family */
a750fc0b 8957 /* PowerPC 7400 v1.0 (G4) */
c4d0a36c 8958 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400)
a750fc0b 8959 /* PowerPC 7400 v1.1 (G4) */
c4d0a36c 8960 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400)
a750fc0b 8961 /* PowerPC 7400 v2.0 (G4) */
c4d0a36c 8962 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400)
4e777442 8963 /* PowerPC 7400 v2.1 (G4) */
c4d0a36c 8964 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400)
a750fc0b 8965 /* PowerPC 7400 v2.2 (G4) */
c4d0a36c 8966 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400)
a750fc0b 8967 /* PowerPC 7400 v2.6 (G4) */
c4d0a36c 8968 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400)
a750fc0b 8969 /* PowerPC 7400 v2.7 (G4) */
c4d0a36c 8970 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400)
a750fc0b 8971 /* PowerPC 7400 v2.8 (G4) */
c4d0a36c 8972 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400)
a750fc0b 8973 /* PowerPC 7400 v2.9 (G4) */
c4d0a36c 8974 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400)
a750fc0b 8975 /* PowerPC 7410 v1.0 (G4) */
c4d0a36c 8976 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410)
a750fc0b 8977 /* PowerPC 7410 v1.1 (G4) */
c4d0a36c 8978 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410)
a750fc0b 8979 /* PowerPC 7410 v1.2 (G4) */
c4d0a36c 8980 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410)
a750fc0b 8981 /* PowerPC 7410 v1.3 (G4) */
c4d0a36c 8982 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410)
a750fc0b 8983 /* PowerPC 7410 v1.4 (G4) */
c4d0a36c 8984 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410)
a750fc0b 8985 /* PowerPC 7448 v1.0 (G4) */
c4d0a36c 8986 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400)
a750fc0b 8987 /* PowerPC 7448 v1.1 (G4) */
c4d0a36c 8988 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400)
a750fc0b 8989 /* PowerPC 7448 v2.0 (G4) */
c4d0a36c 8990 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400)
a750fc0b 8991 /* PowerPC 7448 v2.1 (G4) */
c4d0a36c 8992 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400)
a750fc0b 8993 /* PowerPC 7450 v1.0 (G4) */
c4d0a36c 8994 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450)
a750fc0b 8995 /* PowerPC 7450 v1.1 (G4) */
c4d0a36c 8996 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450)
a750fc0b 8997 /* PowerPC 7450 v1.2 (G4) */
c4d0a36c 8998 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450)
a750fc0b 8999 /* PowerPC 7450 v2.0 (G4) */
c4d0a36c 9000 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450)
a750fc0b 9001 /* PowerPC 7450 v2.1 (G4) */
c4d0a36c 9002 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450)
4e777442 9003 /* PowerPC 7441 v2.1 (G4) */
c4d0a36c 9004 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440)
4e777442 9005 /* PowerPC 7441 v2.3 (G4) */
c4d0a36c 9006 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440)
4e777442 9007 /* PowerPC 7451 v2.3 (G4) */
c4d0a36c 9008 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450)
4e777442 9009 /* PowerPC 7441 v2.10 (G4) */
c4d0a36c 9010 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440)
4e777442 9011 /* PowerPC 7451 v2.10 (G4) */
c4d0a36c 9012 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450)
a750fc0b 9013 /* PowerPC 7445 v1.0 (G4) */
c4d0a36c 9014 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445)
a750fc0b 9015 /* PowerPC 7455 v1.0 (G4) */
c4d0a36c 9016 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455)
a750fc0b 9017 /* PowerPC 7445 v2.1 (G4) */
c4d0a36c 9018 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445)
a750fc0b 9019 /* PowerPC 7455 v2.1 (G4) */
c4d0a36c 9020 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455)
a750fc0b 9021 /* PowerPC 7445 v3.2 (G4) */
c4d0a36c 9022 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445)
a750fc0b 9023 /* PowerPC 7455 v3.2 (G4) */
c4d0a36c 9024 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455)
a750fc0b 9025 /* PowerPC 7445 v3.3 (G4) */
c4d0a36c 9026 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445)
a750fc0b 9027 /* PowerPC 7455 v3.3 (G4) */
c4d0a36c 9028 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455)
a750fc0b 9029 /* PowerPC 7445 v3.4 (G4) */
c4d0a36c 9030 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445)
a750fc0b 9031 /* PowerPC 7455 v3.4 (G4) */
c4d0a36c 9032 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455)
a750fc0b 9033 /* PowerPC 7447 v1.0 (G4) */
c4d0a36c 9034 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445)
a750fc0b 9035 /* PowerPC 7457 v1.0 (G4) */
c4d0a36c 9036 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455)
a750fc0b 9037 /* PowerPC 7447 v1.1 (G4) */
c4d0a36c 9038 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445)
a750fc0b 9039 /* PowerPC 7457 v1.1 (G4) */
c4d0a36c 9040 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455)
a750fc0b 9041 /* PowerPC 7457 v1.2 (G4) */
c4d0a36c 9042 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455)
082c6681 9043 /* PowerPC 7447A v1.0 (G4) */
c4d0a36c 9044 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445)
082c6681 9045 /* PowerPC 7457A v1.0 (G4) */
c4d0a36c 9046 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455)
082c6681 9047 /* PowerPC 7447A v1.1 (G4) */
c4d0a36c 9048 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445)
082c6681 9049 /* PowerPC 7457A v1.1 (G4) */
c4d0a36c 9050 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455)
082c6681 9051 /* PowerPC 7447A v1.2 (G4) */
c4d0a36c 9052 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445)
082c6681 9053 /* PowerPC 7457A v1.2 (G4) */
c4d0a36c 9054 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455)
a750fc0b
JM		 9055 /* 64 bits PowerPC */
9056#if defined (TARGET_PPC64)
a750fc0b 9057 /* PowerPC 620 */
c4d0a36c 9058 POWERPC_DEF("620", CPU_POWERPC_620, 620)
3fc6c082 9059#if defined (TODO)
a750fc0b 9060 /* PowerPC 630 (POWER3) */
c4d0a36c 9061 POWERPC_DEF("630", CPU_POWERPC_630, 630)
a750fc0b 9062#endif
3a607854 9063#if defined (TODO)
a750fc0b 9064 /* PowerPC 631 (Power 3+) */
c4d0a36c 9065 POWERPC_DEF("631", CPU_POWERPC_631, 631)
3a607854
JM		 9066#endif
9067#if defined (TODO)
a750fc0b 9068 /* POWER4 */
c4d0a36c 9069 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4)
a750fc0b 9070#endif
3a607854 9071#if defined (TODO)
a750fc0b 9072 /* POWER4p */
c4d0a36c 9073 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P)
a750fc0b 9074#endif
2662a059 9075#if defined (TODO)
a750fc0b 9076 /* POWER5 */
c4d0a36c 9077 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5)
a750fc0b 9078 /* POWER5GR */
c4d0a36c 9079 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5)
2662a059 9080#endif
3a607854 9081#if defined (TODO)
a750fc0b 9082 /* POWER5+ */
c4d0a36c 9083 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P)
a750fc0b 9084 /* POWER5GS */
c4d0a36c 9085 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P)
a750fc0b 9086#endif
2662a059 9087#if defined (TODO)
a750fc0b 9088 /* POWER6 */
c4d0a36c 9089 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6)
a750fc0b 9090 /* POWER6 running in POWER5 mode */
c4d0a36c 9091 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5)
a750fc0b 9092 /* POWER6A */
c4d0a36c 9093 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6)
2662a059 9094#endif
9d52e907 9095 /* POWER7 */
c4d0a36c
AF		 9096 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7)
9097 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7)
9098 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7)
a750fc0b 9099 /* PowerPC 970 */
c4d0a36c 9100 POWERPC_DEF("970", CPU_POWERPC_970, 970)
a750fc0b 9101 /* PowerPC 970FX v1.0 (G5) */
c4d0a36c 9102 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX)
a750fc0b 9103 /* PowerPC 970FX v2.0 (G5) */
c4d0a36c 9104 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX)
a750fc0b 9105 /* PowerPC 970FX v2.1 (G5) */
c4d0a36c 9106 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX)
a750fc0b 9107 /* PowerPC 970FX v3.0 (G5) */
c4d0a36c 9108 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX)
a750fc0b 9109 /* PowerPC 970FX v3.1 (G5) */
c4d0a36c 9110 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX)
a750fc0b 9111 /* PowerPC 970GX (G5) */
c4d0a36c 9112 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX)
a750fc0b 9113 /* PowerPC 970MP v1.0 */
c4d0a36c 9114 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP)
a750fc0b 9115 /* PowerPC 970MP v1.1 */
c4d0a36c 9116 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP)
3a607854 9117#if defined (TODO)
a750fc0b 9118 /* PowerPC Cell */
c4d0a36c 9119 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970)
2662a059
JM		 9120#endif
9121#if defined (TODO)
a750fc0b 9122 /* PowerPC Cell v1.0 */
c4d0a36c 9123 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970)
2662a059
JM		 9124#endif
9125#if defined (TODO)
a750fc0b 9126 /* PowerPC Cell v2.0 */
c4d0a36c 9127 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970)
2662a059
JM		 9128#endif
9129#if defined (TODO)
a750fc0b 9130 /* PowerPC Cell v3.0 */
c4d0a36c 9131 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970)
3a607854 9132#endif
3a607854 9133#if defined (TODO)
a750fc0b 9134 /* PowerPC Cell v3.1 */
c4d0a36c 9135 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970)
2662a059
JM		 9136#endif
9137#if defined (TODO)
a750fc0b 9138 /* PowerPC Cell v3.2 */
c4d0a36c 9139 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970)
2662a059
JM		 9140#endif
9141#if defined (TODO)
a750fc0b
JM		 9142 /* RS64 (Apache/A35) */
9143 /* This one seems to support the whole POWER2 instruction set
9144 * and the PowerPC 64 one.
9145 */
9146 /* What about A10 & A30 ? */
c4d0a36c 9147 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64)
3a607854
JM		 9148#endif
9149#if defined (TODO)
a750fc0b 9150 /* RS64-II (NorthStar/A50) */
c4d0a36c 9151 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64)
3a607854
JM		 9152#endif
9153#if defined (TODO)
a750fc0b 9154 /* RS64-III (Pulsar) */
c4d0a36c 9155 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64)
2662a059
JM		 9156#endif
9157#if defined (TODO)
a750fc0b 9158 /* RS64-IV (IceStar/IStar/SStar) */
c4d0a36c 9159 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64)
3a607854 9160#endif
a750fc0b
JM		 9161#endif /* defined (TARGET_PPC64) */
9162 /* POWER */
3fc6c082 9163#if defined (TODO)
a750fc0b 9164 /* Original POWER */
c4d0a36c 9165 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER)
76a66253
JM		 9166#endif
9167#if defined (TODO)
a750fc0b 9168 /* POWER2 */
c4d0a36c 9169 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER)
a750fc0b
JM		 9170#endif
9171 /* PA semi cores */
9172#if defined (TODO)
9173 /* PA PA6T */
c4d0a36c 9174 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T)
a750fc0b 9175#endif
fd5ed418
AF		 9176
9177typedef struct PowerPCCPUAlias {
9178 const char *alias;
9179 const char *model;
9180} PowerPCCPUAlias;
9181
9182static const PowerPCCPUAlias ppc_cpu_aliases[] = {
8f43bc78
AF		 9183 { "403", "403GC" },
9184 { "405", "405D4" },
9185 { "405CR", "405CRc" },
9186 { "405GP", "405GPd" },
4bdba7fd 9187 { "405GPe", "405CRc" },
8f43bc78
AF		 9188 { "x2vp7", "x2vp4" },
9189 { "x2vp50", "x2vp20" },
9190
8c00a999
AF		 9191 { "440EP", "440EPb" },
9192 { "440GP", "440GPc" },
9193 { "440GR", "440GRa" },
9194 { "440GX", "440GXf" },
9195
fd5ed418 9196 { "RCPU", "MPC5xx" },
e0b9a74e
AF		 9197 /* MPC5xx microcontrollers */
9198 { "MGT560", "MPC5xx" },
9199 { "MPC509", "MPC5xx" },
9200 { "MPC533", "MPC5xx" },
9201 { "MPC534", "MPC5xx" },
9202 { "MPC555", "MPC5xx" },
9203 { "MPC556", "MPC5xx" },
9204 { "MPC560", "MPC5xx" },
9205 { "MPC561", "MPC5xx" },
9206 { "MPC562", "MPC5xx" },
9207 { "MPC563", "MPC5xx" },
9208 { "MPC564", "MPC5xx" },
9209 { "MPC565", "MPC5xx" },
9210 { "MPC566", "MPC5xx" },
9211
fd5ed418 9212 { "PowerQUICC", "MPC8xx" },
20267b6f
AF		 9213 /* MPC8xx microcontrollers */
9214 { "MGT823", "MPC8xx" },
9215 { "MPC821", "MPC8xx" },
9216 { "MPC823", "MPC8xx" },
9217 { "MPC850", "MPC8xx" },
9218 { "MPC852T", "MPC8xx" },
9219 { "MPC855T", "MPC8xx" },
9220 { "MPC857", "MPC8xx" },
9221 { "MPC859", "MPC8xx" },
9222 { "MPC860", "MPC8xx" },
9223 { "MPC862", "MPC8xx" },
9224 { "MPC866", "MPC8xx" },
9225 { "MPC870", "MPC8xx" },
9226 { "MPC875", "MPC8xx" },
9227 { "MPC880", "MPC8xx" },
9228 { "MPC885", "MPC8xx" },
9229
7b48a1ad
AF		 9230 /* PowerPC MPC603 microcontrollers */
9231 { "MPC8240", "603" },
9232
cf9314cd 9233 { "MPC52xx", "MPC5200" },
236824f2
AF		 9234 { "MPC5200", "MPC5200_v12" },
9235 { "MPC5200B", "MPC5200B_v21" },
cf9314cd 9236
63499f21 9237 { "MPC82xx", "MPC8280" },
fd5ed418 9238 { "PowerQUICC-II", "MPC82xx" },
d329ceb2
AF		 9239 { "MPC8241", "G2HiP4" },
9240 { "MPC8245", "G2HiP4" },
4d55320f
AF		 9241 { "MPC8247", "G2leGP3" },
9242 { "MPC8248", "G2leGP3" },
f172e4b9 9243 { "MPC8250", "MPC8250_HiP4" },
d329ceb2
AF		 9244 { "MPC8250_HiP3", "G2HiP3" },
9245 { "MPC8250_HiP4", "G2HiP4" },
f172e4b9 9246 { "MPC8255", "MPC8255_HiP4" },
d329ceb2
AF		 9247 { "MPC8255_HiP3", "G2HiP3" },
9248 { "MPC8255_HiP4", "G2HiP4" },
f172e4b9 9249 { "MPC8260", "MPC8260_HiP4" },
d329ceb2
AF		 9250 { "MPC8260_HiP3", "G2HiP3" },
9251 { "MPC8260_HiP4", "G2HiP4" },
f172e4b9 9252 { "MPC8264", "MPC8264_HiP4" },
d329ceb2
AF		 9253 { "MPC8264_HiP3", "G2HiP3" },
9254 { "MPC8264_HiP4", "G2HiP4" },
f172e4b9 9255 { "MPC8265", "MPC8265_HiP4" },
d329ceb2
AF		 9256 { "MPC8265_HiP3", "G2HiP3" },
9257 { "MPC8265_HiP4", "G2HiP4" },
f172e4b9 9258 { "MPC8266", "MPC8266_HiP4" },
d329ceb2
AF		 9259 { "MPC8266_HiP3", "G2HiP3" },
9260 { "MPC8266_HiP4", "G2HiP4" },
4d55320f
AF		 9261 { "MPC8270", "G2leGP3" },
9262 { "MPC8271", "G2leGP3" },
9263 { "MPC8272", "G2leGP3" },
9264 { "MPC8275", "G2leGP3" },
9265 { "MPC8280", "G2leGP3" },
4475e98f 9266 { "e200", "e200z6" },
0683641c 9267 { "e300", "e300c3" },
9538de4f
AF		 9268 { "MPC8347", "MPC8347T" },
9269 { "MPC8347A", "MPC8347AT" },
9270 { "MPC8347E", "MPC8347ET" },
9271 { "MPC8347EA", "MPC8347EAT" },
fd5ed418 9272 { "e500", "e500v2_v22" },
6d4decb4
AF		 9273 { "e500v1", "e500_v20" },
9274 { "e500v2", "e500v2_v22" },
52d80768
AF		 9275 { "MPC8533", "MPC8533_v11" },
9276 { "MPC8533E", "MPC8533E_v11" },
9277 { "MPC8540", "MPC8540_v21" },
9278 { "MPC8541", "MPC8541_v11" },
9279 { "MPC8541E", "MPC8541E_v11" },
9280 { "MPC8543", "MPC8543_v21" },
9281 { "MPC8543E", "MPC8543E_v21" },
9282 { "MPC8544", "MPC8544_v11" },
9283 { "MPC8544E", "MPC8544E_v11" },
9284 { "MPC8545", "MPC8545_v21" },
9285 { "MPC8545E", "MPC8545E_v21" },
9286 { "MPC8547E", "MPC8547E_v21" },
9287 { "MPC8548", "MPC8548_v21" },
9288 { "MPC8548E", "MPC8548E_v21" },
9289 { "MPC8555", "MPC8555_v11" },
9290 { "MPC8555E", "MPC8555E_v11" },
9291 { "MPC8560", "MPC8560_v21" },
336c8632
AF		 9292 { "601", "601_v2" },
9293 { "601v", "601_v2" },
fd5ed418 9294 { "Vanilla", "603" },
16a17733 9295 { "603e", "603e_v4.1" },
fd5ed418
AF		 9296 { "Stretch", "603e" },
9297 { "Vaillant", "603e7v" },
4ae0e9d8 9298 { "603r", "603e7t" },
fd5ed418 9299 { "Goldeneye", "603r" },
91b5d028 9300 { "604e", "604e_v2.4" },
fd5ed418
AF		 9301 { "Sirocco", "604e" },
9302 { "Mach5", "604r" },
0446aecd 9303 { "740", "740_v3.1" },
fd5ed418 9304 { "Arthur", "740" },
0446aecd 9305 { "750", "750_v3.1" },
fd5ed418
AF		 9306 { "Typhoon", "750" },
9307 { "G3", "750" },
9308 { "Conan/Doyle", "750p" },
8fc82f9e
AF		 9309 { "750cl", "750cl_v2.0" },
9310 { "750cx", "750cx_v2.2" },
9311 { "750cxe", "750cxe_v3.1b" },
9312 { "750fx", "750fx_v2.3" },
9313 { "750gx", "750gx_v1.2" },
9314 { "750l", "750l_v3.2" },
fd5ed418 9315 { "LoneStar", "750l" },
80c7abd3
AF		 9316 { "745", "745_v2.8" },
9317 { "755", "755_v2.8" },
fd5ed418 9318 { "Goldfinger", "755" },
06704e9c 9319 { "7400", "7400_v2.9" },
fd5ed418
AF		 9320 { "Max", "7400" },
9321 { "G4", "7400" },
08546b91 9322 { "7410", "7410_v1.4" },
fd5ed418 9323 { "Nitro", "7410" },
df502ce8 9324 { "7448", "7448_v2.1" },
e9a7cf3b 9325 { "7450", "7450_v2.1" },
fd5ed418 9326 { "Vger", "7450" },
078840e1
AF		 9327 { "7441", "7441_v2.3" },
9328 { "7451", "7451_v2.3" },
d96c8a23
AF		 9329 { "7445", "7445_v3.2" },
9330 { "7455", "7455_v3.2" },
fd5ed418 9331 { "Apollo6", "7455" },
4c739207
AF		 9332 { "7447", "7447_v1.2" },
9333 { "7457", "7457_v1.2" },
fd5ed418 9334 { "Apollo7", "7457" },
4c739207
AF		 9335 { "7447A", "7447A_v1.2" },
9336 { "7457A", "7457A_v1.2" },
fd5ed418
AF		 9337 { "Apollo7PM", "7457A_v1.0" },
9338#if defined(TARGET_PPC64)
9339 { "Trident", "620" },
9340 { "POWER3", "630" },
9341 { "Boxer", "POWER3" },
9342 { "Dino", "POWER3" },
9343 { "POWER3+", "631" },
f591784b 9344 { "POWER7", "POWER7_v2.0" },
df43f4b8
AF		 9345 { "970fx", "970fx_v3.1" },
9346 { "970mp", "970mp_v1.1" },
fd5ed418
AF		 9347 { "Apache", "RS64" },
9348 { "A35", "RS64" },
9349 { "NorthStar", "RS64-II" },
9350 { "A50", "RS64-II" },
9351 { "Pulsar", "RS64-III" },
9352 { "IceStar", "RS64-IV" },
9353 { "IStar", "RS64-IV" },
9354 { "SStar", "RS64-IV" },
9355#endif
9356 { "RIOS", "POWER" },
9357 { "RSC", "POWER" },
9358 { "RSC3308", "POWER" },
9359 { "RSC4608", "POWER" },
9360 { "RSC2", "POWER2" },
9361 { "P2SC", "POWER2" },
9362
a7de06e1
AF		 9363 /* Generic PowerPCs */
9364#if defined(TARGET_PPC64)
9365 { "ppc64", "970fx" },
9366#endif
9367 { "ppc32", "604" },
f7851859 9368 { "ppc", "ppc32" },
fd5ed418 9369 { "default", "ppc" },
a750fc0b
JM		 9370};
9371
9372/*****************************************************************************/
60b14d95 9373/* Generic CPU instantiation routine */
cfe34f44 9374static void init_ppc_proc(PowerPCCPU *cpu)
a750fc0b 9375{
cfe34f44
AF		 9376 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9377 CPUPPCState *env = &cpu->env;
a750fc0b 9378#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 9379 int i;
9380
a750fc0b 9381 env->irq_inputs = NULL;
e1833e1f
JM		 9382 /* Set all exception vectors to an invalid address */
9383 for (i = 0; i < POWERPC_EXCP_NB; i++)
9384 env->excp_vectors[i] = (target_ulong)(-1ULL);
fc1c67bc 9385 env->hreset_excp_prefix = 0x00000000;
e1833e1f
JM		 9386 env->ivor_mask = 0x00000000;
9387 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 9388 /* Default MMU definitions */
9389 env->nb_BATs = 0;
9390 env->nb_tlb = 0;
9391 env->nb_ways = 0;
1c53accc 9392 env->tlb_type = TLB_NONE;
f2e63a42 9393#endif
a750fc0b
JM		 9394 /* Register SPR common to all PowerPC implementations */
9395 gen_spr_generic(env);
9396 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 9397 /* Linux permits userspace to read PVR */
9398#if defined(CONFIG_LINUX_USER)
9399 &spr_read_generic,
9400#else
9401 SPR_NOACCESS,
9402#endif
9403 SPR_NOACCESS,
a750fc0b 9404 &spr_read_generic, SPR_NOACCESS,
cfe34f44 9405 pcc->pvr);
80d11f44 9406 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
cfe34f44
AF		 9407 if (pcc->svr != POWERPC_SVR_NONE) {
9408 if (pcc->svr & POWERPC_SVR_E500) {
80d11f44
JM		 9409 spr_register(env, SPR_E500_SVR, "SVR",
9410 SPR_NOACCESS, SPR_NOACCESS,
9411 &spr_read_generic, SPR_NOACCESS,
cfe34f44 9412 pcc->svr & ~POWERPC_SVR_E500);
80d11f44
JM		 9413 } else {
9414 spr_register(env, SPR_SVR, "SVR",
9415 SPR_NOACCESS, SPR_NOACCESS,
9416 &spr_read_generic, SPR_NOACCESS,
cfe34f44 9417 pcc->svr);
80d11f44
JM		 9418 }
9419 }
a750fc0b 9420 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
cfe34f44 9421 (*pcc->init_proc)(env);
fc1c67bc
BS		 9422#if !defined(CONFIG_USER_ONLY)
9423 env->excp_prefix = env->hreset_excp_prefix;
9424#endif
25ba3a68
JM		 9425 /* MSR bits & flags consistency checks */
9426 if (env->msr_mask & (1 << 25)) {
9427 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9428 case POWERPC_FLAG_SPE:
9429 case POWERPC_FLAG_VRE:
9430 break;
9431 default:
9432 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9433 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9434 exit(1);
9435 }
9436 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9437 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9438 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9439 exit(1);
9440 }
9441 if (env->msr_mask & (1 << 17)) {
9442 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9443 case POWERPC_FLAG_TGPR:
9444 case POWERPC_FLAG_CE:
9445 break;
9446 default:
9447 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9448 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9449 exit(1);
9450 }
9451 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9452 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9453 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9454 exit(1);
9455 }
9456 if (env->msr_mask & (1 << 10)) {
9457 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9458 POWERPC_FLAG_UBLE)) {
9459 case POWERPC_FLAG_SE:
9460 case POWERPC_FLAG_DWE:
9461 case POWERPC_FLAG_UBLE:
9462 break;
9463 default:
9464 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9465 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9466 "POWERPC_FLAG_UBLE\n");
9467 exit(1);
9468 }
9469 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9470 POWERPC_FLAG_UBLE)) {
9471 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9472 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9473 "POWERPC_FLAG_UBLE\n");
9474 exit(1);
9475 }
9476 if (env->msr_mask & (1 << 9)) {
9477 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9478 case POWERPC_FLAG_BE:
9479 case POWERPC_FLAG_DE:
9480 break;
9481 default:
9482 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9483 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9484 exit(1);
9485 }
9486 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9487 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9488 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9489 exit(1);
9490 }
9491 if (env->msr_mask & (1 << 2)) {
9492 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9493 case POWERPC_FLAG_PX:
9494 case POWERPC_FLAG_PMM:
9495 break;
9496 default:
9497 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9498 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9499 exit(1);
9500 }
9501 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9502 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9503 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9504 exit(1);
9505 }
4018bae9
JM		 9506 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9507 fprintf(stderr, "PowerPC flags inconsistency\n"
9508 "Should define the time-base and decrementer clock source\n");
9509 exit(1);
9510 }
a750fc0b 9511 /* Allocate TLBs buffer when needed */
f2e63a42 9512#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9513 if (env->nb_tlb != 0) {
9514 int nb_tlb = env->nb_tlb;
9515 if (env->id_tlbs != 0)
9516 nb_tlb *= 2;
1c53accc
AG		 9517 switch (env->tlb_type) {
9518 case TLB_6XX:
7267c094 9519 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
1c53accc
AG		 9520 break;
9521 case TLB_EMB:
7267c094 9522 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
1c53accc
AG		 9523 break;
9524 case TLB_MAS:
7267c094 9525 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
1c53accc
AG		 9526 break;
9527 }
a750fc0b
JM		 9528 /* Pre-compute some useful values */
9529 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9530 }
a750fc0b
JM		 9531 if (env->irq_inputs == NULL) {
9532 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5cbdb3a3 9533 " Attempt QEMU to crash very soon !\n");
a750fc0b
JM		 9534 }
9535#endif
2f462816
JM		 9536 if (env->check_pow == NULL) {
9537 fprintf(stderr, "WARNING: no power management check handler "
9538 "registered.\n"
5cbdb3a3 9539 " Attempt QEMU to crash very soon !\n");
2f462816 9540 }
a750fc0b
JM		 9541}
9542
9543#if defined(PPC_DUMP_CPU)
9544static void dump_ppc_sprs (CPUPPCState *env)
9545{
9546 ppc_spr_t *spr;
9547#if !defined(CONFIG_USER_ONLY)
9548 uint32_t sr, sw;
9549#endif
9550 uint32_t ur, uw;
9551 int i, j, n;
9552
9553 printf("Special purpose registers:\n");
9554 for (i = 0; i < 32; i++) {
9555 for (j = 0; j < 32; j++) {
9556 n = (i << 5) | j;
9557 spr = &env->spr_cb[n];
9558 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9559 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9560#if !defined(CONFIG_USER_ONLY)
9561 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9562 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9563 if (sw || sr || uw || ur) {
9564 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9565 (i << 5) | j, (i << 5) | j, spr->name,
9566 sw ? 'w' : '-', sr ? 'r' : '-',
9567 uw ? 'w' : '-', ur ? 'r' : '-');
9568 }
9569#else
9570 if (uw || ur) {
9571 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9572 (i << 5) | j, (i << 5) | j, spr->name,
9573 uw ? 'w' : '-', ur ? 'r' : '-');
9574 }
9575#endif
9576 }
9577 }
9578 fflush(stdout);
9579 fflush(stderr);
9580}
9581#endif
9582
9583/*****************************************************************************/
9584#include <stdlib.h>
9585#include <string.h>
9586
a750fc0b
JM		 9587/* Opcode types */
9588enum {
9589 PPC_DIRECT = 0, /* Opcode routine */
9590 PPC_INDIRECT = 1, /* Indirect opcode table */
9591};
9592
9593static inline int is_indirect_opcode (void *handler)
9594{
5724753e 9595 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
a750fc0b
JM		 9596}
9597
c227f099 9598static inline opc_handler_t **ind_table(void *handler)
a750fc0b 9599{
5724753e 9600 return (opc_handler_t **)((uintptr_t)handler & ~3);
a750fc0b
JM		 9601}
9602
9603/* Instruction table creation */
9604/* Opcodes tables creation */
c227f099 9605static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 9606{
9607 int i;
9608
9609 for (i = 0; i < len; i++)
9610 table[i] = &invalid_handler;
9611}
9612
c227f099 9613static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 9614{
c227f099 9615 opc_handler_t **tmp;
a750fc0b 9616
c227f099 9617 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 9618 fill_new_table(tmp, 0x20);
5724753e 9619 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
a750fc0b
JM		 9620
9621 return 0;
9622}
9623
c227f099
AL		 9624static int insert_in_table (opc_handler_t **table, unsigned char idx,
9625 opc_handler_t *handler)
a750fc0b
JM		 9626{
9627 if (table[idx] != &invalid_handler)
9628 return -1;
9629 table[idx] = handler;
9630
9631 return 0;
9632}
9633
c227f099
AL		 9634static int register_direct_insn (opc_handler_t **ppc_opcodes,
9635 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 9636{
9637 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9638 printf("*** ERROR: opcode %02x already assigned in main "
9639 "opcode table\n", idx);
4c1b1bfe
JM		 9640#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9641 printf(" Registered handler '%s' - new handler '%s'\n",
9642 ppc_opcodes[idx]->oname, handler->oname);
9643#endif
a750fc0b
JM		 9644 return -1;
9645 }
9646
9647 return 0;
9648}
9649
c227f099 9650static int register_ind_in_table (opc_handler_t **table,
a750fc0b 9651 unsigned char idx1, unsigned char idx2,
c227f099 9652 opc_handler_t *handler)
a750fc0b
JM		 9653{
9654 if (table[idx1] == &invalid_handler) {
9655 if (create_new_table(table, idx1) < 0) {
9656 printf("*** ERROR: unable to create indirect table "
9657 "idx=%02x\n", idx1);
9658 return -1;
9659 }
9660 } else {
9661 if (!is_indirect_opcode(table[idx1])) {
9662 printf("*** ERROR: idx %02x already assigned to a direct "
9663 "opcode\n", idx1);
4c1b1bfe
JM		 9664#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9665 printf(" Registered handler '%s' - new handler '%s'\n",
9666 ind_table(table[idx1])[idx2]->oname, handler->oname);
9667#endif
a750fc0b
JM		 9668 return -1;
9669 }
3a607854 9670 }
a750fc0b
JM		 9671 if (handler != NULL &&
9672 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9673 printf("*** ERROR: opcode %02x already assigned in "
9674 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9675#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9676 printf(" Registered handler '%s' - new handler '%s'\n",
9677 ind_table(table[idx1])[idx2]->oname, handler->oname);
9678#endif
a750fc0b 9679 return -1;
3a607854 9680 }
a750fc0b
JM		 9681
9682 return 0;
9683}
9684
c227f099 9685static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9686 unsigned char idx1, unsigned char idx2,
c227f099 9687 opc_handler_t *handler)
a750fc0b
JM		 9688{
9689 int ret;
9690
9691 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9692
9693 return ret;
9694}
9695
c227f099 9696static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9697 unsigned char idx1, unsigned char idx2,
c227f099 9698 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 9699{
9700 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9701 printf("*** ERROR: unable to join indirect table idx "
9702 "[%02x-%02x]\n", idx1, idx2);
9703 return -1;
9704 }
9705 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9706 handler) < 0) {
9707 printf("*** ERROR: unable to insert opcode "
9708 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9709 return -1;
9710 }
9711
9712 return 0;
9713}
9714
c227f099 9715static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 9716{
9717 if (insn->opc2 != 0xFF) {
9718 if (insn->opc3 != 0xFF) {
9719 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9720 insn->opc3, &insn->handler) < 0)
9721 return -1;
9722 } else {
9723 if (register_ind_insn(ppc_opcodes, insn->opc1,
9724 insn->opc2, &insn->handler) < 0)
9725 return -1;
9726 }
9727 } else {
9728 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9729 return -1;
9730 }
9731
9732 return 0;
9733}
9734
c227f099 9735static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 9736{
9737 int i, count, tmp;
9738
9739 for (i = 0, count = 0; i < len; i++) {
9740 /* Consistency fixup */
9741 if (table[i] == NULL)
9742 table[i] = &invalid_handler;
9743 if (table[i] != &invalid_handler) {
9744 if (is_indirect_opcode(table[i])) {
c227f099 9745 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 9746 if (tmp == 0) {
9747 free(table[i]);
9748 table[i] = &invalid_handler;
9749 } else {
9750 count++;
9751 }
9752 } else {
9753 count++;
9754 }
9755 }
9756 }
9757
9758 return count;
9759}
9760
c227f099 9761static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 9762{
c227f099 9763 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 9764 printf("*** WARNING: no opcode defined !\n");
9765}
9766
9767/*****************************************************************************/
2985b86b 9768static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
a750fc0b 9769{
2985b86b
AF		 9770 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9771 CPUPPCState *env = &cpu->env;
c227f099 9772 opcode_t *opc;
a750fc0b
JM		 9773
9774 fill_new_table(env->opcodes, 0x40);
5c55ff99 9775 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
cfe34f44
AF		 9776 if (((opc->handler.type & pcc->insns_flags) != 0) ||
9777 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
a750fc0b 9778 if (register_insn(env->opcodes, opc) < 0) {
2985b86b 9779 error_setg(errp, "ERROR initializing PowerPC instruction "
312fd5f2 9780 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
2985b86b
AF		 9781 opc->opc3);
9782 return;
a750fc0b
JM		 9783 }
9784 }
9785 }
c227f099 9786 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 9787 fflush(stdout);
9788 fflush(stderr);
a750fc0b
JM		 9789}
9790
9791#if defined(PPC_DUMP_CPU)
25ba3a68 9792static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 9793{
c227f099 9794 opc_handler_t **table, *handler;
b55266b5 9795 const char *p, *q;
a750fc0b
JM		 9796 uint8_t opc1, opc2, opc3;
9797
9798 printf("Instructions set:\n");
9799 /* opc1 is 6 bits long */
9800 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9801 table = env->opcodes;
9802 handler = table[opc1];
9803 if (is_indirect_opcode(handler)) {
9804 /* opc2 is 5 bits long */
9805 for (opc2 = 0; opc2 < 0x20; opc2++) {
9806 table = env->opcodes;
9807 handler = env->opcodes[opc1];
9808 table = ind_table(handler);
9809 handler = table[opc2];
9810 if (is_indirect_opcode(handler)) {
9811 table = ind_table(handler);
9812 /* opc3 is 5 bits long */
9813 for (opc3 = 0; opc3 < 0x20; opc3++) {
9814 handler = table[opc3];
9815 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9816 /* Special hack to properly dump SPE insns */
9817 p = strchr(handler->oname, '_');
9818 if (p == NULL) {
9819 printf("INSN: %02x %02x %02x (%02d %04d) : "
9820 "%s\n",
9821 opc1, opc2, opc3, opc1,
9822 (opc3 << 5) | opc2,
9823 handler->oname);
9824 } else {
9825 q = "speundef";
9826 if ((p - handler->oname) != strlen(q) ||
9827 memcmp(handler->oname, q, strlen(q)) != 0) {
9828 /* First instruction */
9829 printf("INSN: %02x %02x %02x (%02d %04d) : "
9830 "%.*s\n",
9831 opc1, opc2 << 1, opc3, opc1,
9832 (opc3 << 6) | (opc2 << 1),
9833 (int)(p - handler->oname),
9834 handler->oname);
9835 }
9836 if (strcmp(p + 1, q) != 0) {
9837 /* Second instruction */
9838 printf("INSN: %02x %02x %02x (%02d %04d) : "
9839 "%s\n",
9840 opc1, (opc2 << 1) | 1, opc3, opc1,
9841 (opc3 << 6) | (opc2 << 1) | 1,
9842 p + 1);
9843 }
9844 }
a750fc0b
JM		 9845 }
9846 }
9847 } else {
9848 if (handler->handler != &gen_invalid) {
9849 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9850 opc1, opc2, opc1, opc2, handler->oname);
9851 }
9852 }
9853 }
9854 } else {
9855 if (handler->handler != &gen_invalid) {
9856 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9857 opc1, opc1, handler->oname);
9858 }
9859 }
9860 }
9861}
3a607854 9862#endif
a750fc0b 9863
1328c2bf 9864static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 9865{
9866 if (n < 32) {
9867 stfq_p(mem_buf, env->fpr[n]);
9868 return 8;
9869 }
9870 if (n == 32) {
5a576fb3 9871 stl_p(mem_buf, env->fpscr);
24951522
AJ		 9872 return 4;
9873 }
9874 return 0;
9875}
9876
1328c2bf 9877static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
24951522
AJ		 9878{
9879 if (n < 32) {
9880 env->fpr[n] = ldfq_p(mem_buf);
9881 return 8;
9882 }
9883 if (n == 32) {
9884 /* FPSCR not implemented */
9885 return 4;
9886 }
9887 return 0;
9888}
9889
1328c2bf 9890static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 9891{
9892 if (n < 32) {
e2542fe2 9893#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9894 stq_p(mem_buf, env->avr[n].u64[0]);
9895 stq_p(mem_buf+8, env->avr[n].u64[1]);
9896#else
9897 stq_p(mem_buf, env->avr[n].u64[1]);
9898 stq_p(mem_buf+8, env->avr[n].u64[0]);
9899#endif
9900 return 16;
9901 }
70976a79 9902 if (n == 32) {
b4f8d821
AJ		 9903 stl_p(mem_buf, env->vscr);
9904 return 4;
9905 }
70976a79 9906 if (n == 33) {
b4f8d821
AJ		 9907 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9908 return 4;
9909 }
9910 return 0;
9911}
9912
1328c2bf 9913static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
b4f8d821
AJ		 9914{
9915 if (n < 32) {
e2542fe2 9916#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9917 env->avr[n].u64[0] = ldq_p(mem_buf);
9918 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9919#else
9920 env->avr[n].u64[1] = ldq_p(mem_buf);
9921 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9922#endif
9923 return 16;
9924 }
70976a79 9925 if (n == 32) {
b4f8d821
AJ		 9926 env->vscr = ldl_p(mem_buf);
9927 return 4;
9928 }
70976a79 9929 if (n == 33) {
b4f8d821
AJ		 9930 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9931 return 4;
9932 }
9933 return 0;
9934}
9935
1328c2bf 9936static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 9937{
9938 if (n < 32) {
9939#if defined(TARGET_PPC64)
9940 stl_p(mem_buf, env->gpr[n] >> 32);
9941#else
9942 stl_p(mem_buf, env->gprh[n]);
9943#endif
9944 return 4;
9945 }
70976a79 9946 if (n == 32) {
688890f7
AJ		 9947 stq_p(mem_buf, env->spe_acc);
9948 return 8;
9949 }
70976a79 9950 if (n == 33) {
d34defbc 9951 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 9952 return 4;
9953 }
9954 return 0;
9955}
9956
1328c2bf 9957static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
688890f7
AJ		 9958{
9959 if (n < 32) {
9960#if defined(TARGET_PPC64)
9961 target_ulong lo = (uint32_t)env->gpr[n];
9962 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9963 env->gpr[n] = lo | hi;
9964#else
9965 env->gprh[n] = ldl_p(mem_buf);
9966#endif
9967 return 4;
9968 }
70976a79 9969 if (n == 32) {
688890f7
AJ		 9970 env->spe_acc = ldq_p(mem_buf);
9971 return 8;
9972 }
70976a79 9973 if (n == 33) {
d34defbc 9974 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 9975 return 4;
9976 }
9977 return 0;
9978}
9979
55e5c285 9980static int ppc_fixup_cpu(PowerPCCPU *cpu)
12b1143b 9981{
55e5c285
AF		 9982 CPUPPCState *env = &cpu->env;
9983
12b1143b
DG		 9984 /* TCG doesn't (yet) emulate some groups of instructions that
9985 * are implemented on some otherwise supported CPUs (e.g. VSX
9986 * and decimal floating point instructions on POWER7). We
9987 * remove unsupported instruction groups from the cpu state's
9988 * instruction masks and hope the guest can cope. For at
9989 * least the pseries machine, the unavailability of these
9990 * instructions can be advertised to the guest via the device
9991 * tree. */
9992 if ((env->insns_flags & ~PPC_TCG_INSNS)
9993 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9994 fprintf(stderr, "Warning: Disabling some instructions which are not "
9995 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9996 env->insns_flags & ~PPC_TCG_INSNS,
9997 env->insns_flags2 & ~PPC_TCG_INSNS2);
9998 }
9999 env->insns_flags &= PPC_TCG_INSNS;
10000 env->insns_flags2 &= PPC_TCG_INSNS2;
10001 return 0;
10002}
10003
4776ce60 10004static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
a750fc0b 10005{
4776ce60 10006 PowerPCCPU *cpu = POWERPC_CPU(dev);
2985b86b
AF		 10007 CPUPPCState *env = &cpu->env;
10008 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2985b86b 10009 Error *local_err = NULL;
fe828a4d
MQ		 10010#if !defined(CONFIG_USER_ONLY)
10011 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
10012#endif
10013
10014#if !defined(CONFIG_USER_ONLY)
10015 if (smp_threads > max_smt) {
5e95acc8
AF		 10016 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
10017 max_smt, kvm_enabled() ? "KVM" : "TCG");
10018 return;
fe828a4d
MQ		 10019 }
10020#endif
4656e1f0 10021
12b1143b 10022 if (kvm_enabled()) {
55e5c285 10023 if (kvmppc_fixup_cpu(cpu) != 0) {
2985b86b
AF		 10024 error_setg(errp, "Unable to virtualize selected CPU with KVM");
10025 return;
12b1143b
DG		 10026 }
10027 } else {
55e5c285 10028 if (ppc_fixup_cpu(cpu) != 0) {
2985b86b
AF		 10029 error_setg(errp, "Unable to emulate selected CPU with TCG");
10030 return;
12b1143b
DG		 10031 }
10032 }
10033
4d7fb187
AF		 10034#if defined(TARGET_PPCEMB)
10035 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
10036 error_setg(errp, "CPU does not possess a BookE MMU. "
10037 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
10038 "or choose another CPU model.");
10039 return;
10040 }
10041#endif
10042
2985b86b
AF		 10043 create_ppc_opcodes(cpu, &local_err);
10044 if (local_err != NULL) {
10045 error_propagate(errp, local_err);
10046 return;
10047 }
cfe34f44 10048 init_ppc_proc(cpu);
24951522 10049
cfe34f44 10050 if (pcc->insns_flags & PPC_FLOAT) {
24951522
AJ		 10051 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
10052 33, "power-fpu.xml", 0);
10053 }
cfe34f44 10054 if (pcc->insns_flags & PPC_ALTIVEC) {
b4f8d821
AJ		 10055 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
10056 34, "power-altivec.xml", 0);
10057 }
cfe34f44 10058 if (pcc->insns_flags & PPC_SPE) {
688890f7
AJ		 10059 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
10060 34, "power-spe.xml", 0);
10061 }
10062
2985b86b
AF		 10063 qemu_init_vcpu(env);
10064
4776ce60
AF		 10065 pcc->parent_realize(dev, errp);
10066
a750fc0b 10067#if defined(PPC_DUMP_CPU)
3a607854 10068 {
b55266b5 10069 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 10070 switch (env->mmu_model) {
10071 case POWERPC_MMU_32B:
10072 mmu_model = "PowerPC 32";
10073 break;
a750fc0b
JM		 10074 case POWERPC_MMU_SOFT_6xx:
10075 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
10076 break;
10077 case POWERPC_MMU_SOFT_74xx:
10078 mmu_model = "PowerPC 74xx with software driven TLBs";
10079 break;
10080 case POWERPC_MMU_SOFT_4xx:
10081 mmu_model = "PowerPC 4xx with software driven TLBs";
10082 break;
10083 case POWERPC_MMU_SOFT_4xx_Z:
10084 mmu_model = "PowerPC 4xx with software driven TLBs "
10085 "and zones protections";
10086 break;
b4095fed
JM		 10087 case POWERPC_MMU_REAL:
10088 mmu_model = "PowerPC real mode only";
10089 break;
10090 case POWERPC_MMU_MPC8xx:
10091 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 10092 break;
10093 case POWERPC_MMU_BOOKE:
10094 mmu_model = "PowerPC BookE";
10095 break;
01662f3e
AG		 10096 case POWERPC_MMU_BOOKE206:
10097 mmu_model = "PowerPC BookE 2.06";
a750fc0b 10098 break;
b4095fed
JM		 10099 case POWERPC_MMU_601:
10100 mmu_model = "PowerPC 601";
10101 break;
00af685f
JM		 10102#if defined (TARGET_PPC64)
10103 case POWERPC_MMU_64B:
10104 mmu_model = "PowerPC 64";
10105 break;
add78955
JM		 10106 case POWERPC_MMU_620:
10107 mmu_model = "PowerPC 620";
10108 break;
00af685f 10109#endif
a750fc0b
JM		 10110 default:
10111 mmu_model = "Unknown or invalid";
10112 break;
10113 }
10114 switch (env->excp_model) {
10115 case POWERPC_EXCP_STD:
10116 excp_model = "PowerPC";
10117 break;
10118 case POWERPC_EXCP_40x:
10119 excp_model = "PowerPC 40x";
10120 break;
10121 case POWERPC_EXCP_601:
10122 excp_model = "PowerPC 601";
10123 break;
10124 case POWERPC_EXCP_602:
10125 excp_model = "PowerPC 602";
10126 break;
10127 case POWERPC_EXCP_603:
10128 excp_model = "PowerPC 603";
10129 break;
10130 case POWERPC_EXCP_603E:
10131 excp_model = "PowerPC 603e";
10132 break;
10133 case POWERPC_EXCP_604:
10134 excp_model = "PowerPC 604";
10135 break;
10136 case POWERPC_EXCP_7x0:
10137 excp_model = "PowerPC 740/750";
10138 break;
10139 case POWERPC_EXCP_7x5:
10140 excp_model = "PowerPC 745/755";
10141 break;
10142 case POWERPC_EXCP_74xx:
10143 excp_model = "PowerPC 74xx";
10144 break;
a750fc0b
JM		 10145 case POWERPC_EXCP_BOOKE:
10146 excp_model = "PowerPC BookE";
10147 break;
00af685f
JM		 10148#if defined (TARGET_PPC64)
10149 case POWERPC_EXCP_970:
10150 excp_model = "PowerPC 970";
10151 break;
10152#endif
a750fc0b
JM		 10153 default:
10154 excp_model = "Unknown or invalid";
10155 break;
10156 }
10157 switch (env->bus_model) {
10158 case PPC_FLAGS_INPUT_6xx:
10159 bus_model = "PowerPC 6xx";
10160 break;
10161 case PPC_FLAGS_INPUT_BookE:
10162 bus_model = "PowerPC BookE";
10163 break;
10164 case PPC_FLAGS_INPUT_405:
10165 bus_model = "PowerPC 405";
10166 break;
a750fc0b
JM		 10167 case PPC_FLAGS_INPUT_401:
10168 bus_model = "PowerPC 401/403";
10169 break;
b4095fed
JM		 10170 case PPC_FLAGS_INPUT_RCPU:
10171 bus_model = "RCPU / MPC8xx";
10172 break;
00af685f
JM		 10173#if defined (TARGET_PPC64)
10174 case PPC_FLAGS_INPUT_970:
10175 bus_model = "PowerPC 970";
10176 break;
10177#endif
a750fc0b
JM		 10178 default:
10179 bus_model = "Unknown or invalid";
10180 break;
10181 }
10182 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10183 " MMU model : %s\n",
cfe34f44 10184 pcc->name, pcc->pvr, pcc->msr_mask, mmu_model);
f2e63a42 10185#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 10186 if (env->tlb != NULL) {
10187 printf(" %d %s TLB in %d ways\n",
10188 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10189 env->nb_ways);
10190 }
f2e63a42 10191#endif
a750fc0b
JM		 10192 printf(" Exceptions model : %s\n"
10193 " Bus model : %s\n",
10194 excp_model, bus_model);
25ba3a68
JM		 10195 printf(" MSR features :\n");
10196 if (env->flags & POWERPC_FLAG_SPE)
10197 printf(" signal processing engine enable"
10198 "\n");
10199 else if (env->flags & POWERPC_FLAG_VRE)
10200 printf(" vector processor enable\n");
10201 if (env->flags & POWERPC_FLAG_TGPR)
10202 printf(" temporary GPRs\n");
10203 else if (env->flags & POWERPC_FLAG_CE)
10204 printf(" critical input enable\n");
10205 if (env->flags & POWERPC_FLAG_SE)
10206 printf(" single-step trace mode\n");
10207 else if (env->flags & POWERPC_FLAG_DWE)
10208 printf(" debug wait enable\n");
10209 else if (env->flags & POWERPC_FLAG_UBLE)
10210 printf(" user BTB lock enable\n");
10211 if (env->flags & POWERPC_FLAG_BE)
10212 printf(" branch-step trace mode\n");
10213 else if (env->flags & POWERPC_FLAG_DE)
10214 printf(" debug interrupt enable\n");
10215 if (env->flags & POWERPC_FLAG_PX)
10216 printf(" inclusive protection\n");
10217 else if (env->flags & POWERPC_FLAG_PMM)
10218 printf(" performance monitor mark\n");
10219 if (env->flags == POWERPC_FLAG_NONE)
10220 printf(" none\n");
4018bae9
JM		 10221 printf(" Time-base/decrementer clock source: %s\n",
10222 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 10223 }
10224 dump_ppc_insns(env);
10225 dump_ppc_sprs(env);
10226 fflush(stdout);
3a607854 10227#endif
a750fc0b 10228}
3fc6c082 10229
2985b86b 10230static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
f0ad8c34 10231{
2985b86b
AF		 10232 ObjectClass *oc = (ObjectClass *)a;
10233 uint32_t pvr = *(uint32_t *)b;
10234 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10235
10236 /* -cpu host does a PVR lookup during construction */
10237 if (unlikely(strcmp(object_class_get_name(oc),
10238 TYPE_HOST_POWERPC_CPU) == 0)) {
10239 return -1;
f0ad8c34 10240 }
f0ad8c34 10241
4d7fb187
AF		 10242#if defined(TARGET_PPCEMB)
10243 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
10244 return -1;
10245 }
10246#endif
10247
cfe34f44 10248 return pcc->pvr == pvr ? 0 : -1;
f0ad8c34
AG		 10249}
10250
2985b86b 10251PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
3fc6c082 10252{
2985b86b
AF		 10253 GSList *list, *item;
10254 PowerPCCPUClass *pcc = NULL;
be40edcd 10255
2985b86b
AF		 10256 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10257 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10258 if (item != NULL) {
10259 pcc = POWERPC_CPU_CLASS(item->data);
3fc6c082 10260 }
2985b86b
AF		 10261 g_slist_free(list);
10262
10263 return pcc;
10264}
10265
10266static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
10267{
10268 ObjectClass *oc = (ObjectClass *)a;
10269 const char *name = b;
4d7fb187
AF		 10270#if defined(TARGET_PPCEMB)
10271 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10272#endif
ee4e83ed 10273
2985b86b 10274 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
4d7fb187
AF		 10275#if defined(TARGET_PPCEMB)
10276 pcc->mmu_model == POWERPC_MMU_BOOKE &&
10277#endif
2985b86b
AF		 10278 strcmp(object_class_get_name(oc) + strlen(name),
10279 "-" TYPE_POWERPC_CPU) == 0) {
10280 return 0;
10281 }
10282 return -1;
3fc6c082
FB		 10283}
10284
ee4e83ed 10285#include <ctype.h>
3fc6c082 10286
2985b86b 10287static ObjectClass *ppc_cpu_class_by_name(const char *name)
ee4e83ed 10288{
2985b86b
AF		 10289 GSList *list, *item;
10290 ObjectClass *ret = NULL;
b55266b5 10291 const char *p;
2985b86b 10292 int i, len;
ee4e83ed 10293
2985b86b
AF		 10294 if (strcasecmp(name, "host") == 0) {
10295 if (kvm_enabled()) {
10296 ret = object_class_by_name(TYPE_HOST_POWERPC_CPU);
10297 }
10298 return ret;
a1e98583
DG		 10299 }
10300
ee4e83ed
JM		 10301 /* Check if the given name is a PVR */
10302 len = strlen(name);
10303 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10304 p = name + 2;
10305 goto check_pvr;
10306 } else if (len == 8) {
10307 p = name;
10308 check_pvr:
10309 for (i = 0; i < 8; i++) {
cd390083 10310 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 10311 break;
10312 }
2985b86b
AF		 10313 if (i == 8) {
10314 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
10315 return ret;
f0ad8c34 10316 }
2985b86b 10317 }
f0ad8c34 10318
fd5ed418
AF		 10319 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
10320 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
10321 return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
10322 }
10323 }
10324
2985b86b
AF		 10325 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10326 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
10327 if (item != NULL) {
10328 ret = OBJECT_CLASS(item->data);
3fc6c082 10329 }
2985b86b 10330 g_slist_free(list);
ee4e83ed
JM		 10331
10332 return ret;
3fc6c082
FB		 10333}
10334
2985b86b 10335PowerPCCPU *cpu_ppc_init(const char *cpu_model)
3fc6c082 10336{
2985b86b
AF		 10337 PowerPCCPU *cpu;
10338 CPUPPCState *env;
10339 ObjectClass *oc;
10340 Error *err = NULL;
3fc6c082 10341
2985b86b
AF		 10342 oc = ppc_cpu_class_by_name(cpu_model);
10343 if (oc == NULL) {
10344 return NULL;
10345 }
f0ad8c34 10346
2985b86b
AF		 10347 cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
10348 env = &cpu->env;
2985b86b
AF		 10349 env->cpu_model_str = cpu_model;
10350
4776ce60 10351 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
2985b86b
AF		 10352 if (err != NULL) {
10353 fprintf(stderr, "%s\n", error_get_pretty(err));
10354 error_free(err);
5c099537 10355 object_unref(OBJECT(cpu));
2985b86b
AF		 10356 return NULL;
10357 }
10358
10359 return cpu;
10360}
10361
10362/* Sort by PVR, ordering special case "host" last. */
10363static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10364{
10365 ObjectClass *oc_a = (ObjectClass *)a;
10366 ObjectClass *oc_b = (ObjectClass *)b;
10367 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10368 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10369 const char *name_a = object_class_get_name(oc_a);
10370 const char *name_b = object_class_get_name(oc_b);
10371
10372 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10373 return 1;
10374 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10375 return -1;
10376 } else {
10377 /* Avoid an integer overflow during subtraction */
cfe34f44 10378 if (pcc_a->pvr < pcc_b->pvr) {
2985b86b 10379 return -1;
cfe34f44 10380 } else if (pcc_a->pvr > pcc_b->pvr) {
2985b86b
AF		 10381 return 1;
10382 } else {
10383 return 0;
10384 }
10385 }
10386}
10387
10388static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10389{
10390 ObjectClass *oc = data;
10391 CPUListState *s = user_data;
10392 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
de400129
AF		 10393 const char *typename = object_class_get_name(oc);
10394 char *name;
2985b86b 10395
4d7fb187
AF		 10396#if defined(TARGET_PPCEMB)
10397 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
10398 return;
10399 }
10400#endif
10401
de400129
AF		 10402 name = g_strndup(typename,
10403 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
2985b86b 10404 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
cfe34f44 10405 name, pcc->pvr);
de400129 10406 g_free(name);
2985b86b
AF		 10407}
10408
10409void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10410{
10411 CPUListState s = {
10412 .file = f,
10413 .cpu_fprintf = cpu_fprintf,
10414 };
10415 GSList *list;
fd5ed418 10416 int i;
2985b86b
AF		 10417
10418 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10419 list = g_slist_sort(list, ppc_cpu_list_compare);
10420 g_slist_foreach(list, ppc_cpu_list_entry, &s);
10421 g_slist_free(list);
fd5ed418
AF		 10422
10423 cpu_fprintf(f, "\n");
10424 for (i = 0; i < ARRAY_SIZE(ppc_cpu_aliases); i++) {
10425 ObjectClass *oc = ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
10426 if (oc == NULL) {
10427 /* Hide aliases that point to a TODO or TODO_USER_ONLY model */
10428 continue;
10429 }
10430 cpu_fprintf(f, "PowerPC %-16s\n",
10431 ppc_cpu_aliases[i].alias);
10432 }
2985b86b
AF		 10433}
10434
10435static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10436{
10437 ObjectClass *oc = data;
10438 CpuDefinitionInfoList **first = user_data;
de400129 10439 const char *typename;
2985b86b
AF		 10440 CpuDefinitionInfoList *entry;
10441 CpuDefinitionInfo *info;
4d7fb187
AF		 10442#if defined(TARGET_PPCEMB)
10443 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10444
10445 if (pcc->mmu_model != POWERPC_MMU_BOOKE) {
10446 return;
10447 }
10448#endif
2985b86b 10449
de400129 10450 typename = object_class_get_name(oc);
2985b86b 10451 info = g_malloc0(sizeof(*info));
de400129
AF		 10452 info->name = g_strndup(typename,
10453 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
2985b86b
AF		 10454
10455 entry = g_malloc0(sizeof(*entry));
10456 entry->value = info;
10457 entry->next = *first;
10458 *first = entry;
3fc6c082 10459}
1d0cb67d 10460
76b64a7a 10461CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
70b7660a
AL		 10462{
10463 CpuDefinitionInfoList *cpu_list = NULL;
2985b86b 10464 GSList *list;
70b7660a 10465
2985b86b
AF		 10466 list = object_class_get_list(TYPE_POWERPC_CPU, false);
10467 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10468 g_slist_free(list);
70b7660a 10469
2985b86b
AF		 10470 return cpu_list;
10471}
70b7660a 10472
1d0cb67d
AF		 10473/* CPUClass::reset() */
10474static void ppc_cpu_reset(CPUState *s)
10475{
10476 PowerPCCPU *cpu = POWERPC_CPU(s);
10477 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10478 CPUPPCState *env = &cpu->env;
a1389542
AF		 10479 target_ulong msr;
10480
10481 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 10482 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
a1389542
AF		 10483 log_cpu_state(env, 0);
10484 }
1d0cb67d
AF		 10485
10486 pcc->parent_reset(s);
10487
a1389542
AF		 10488 msr = (target_ulong)0;
10489 if (0) {
10490 /* XXX: find a suitable condition to enable the hypervisor mode */
10491 msr |= (target_ulong)MSR_HVB;
10492 }
10493 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10494 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10495 msr |= (target_ulong)1 << MSR_EP;
10496#if defined(DO_SINGLE_STEP) && 0
10497 /* Single step trace mode */
10498 msr |= (target_ulong)1 << MSR_SE;
10499 msr |= (target_ulong)1 << MSR_BE;
10500#endif
10501#if defined(CONFIG_USER_ONLY)
10502 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10503 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10504 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10505 msr |= (target_ulong)1 << MSR_PR;
10506#else
10507 env->excp_prefix = env->hreset_excp_prefix;
10508 env->nip = env->hreset_vector | env->excp_prefix;
10509 if (env->mmu_model != POWERPC_MMU_REAL) {
10510 ppc_tlb_invalidate_all(env);
10511 }
10512#endif
10513 env->msr = msr & env->msr_mask;
10514#if defined(TARGET_PPC64)
10515 if (env->mmu_model & POWERPC_MMU_64) {
10516 env->msr |= (1ULL << MSR_SF);
10517 }
10518#endif
10519 hreg_compute_hflags(env);
10520 env->reserve_addr = (target_ulong)-1ULL;
10521 /* Be sure no exception or interrupt is pending */
10522 env->pending_interrupts = 0;
10523 env->exception_index = POWERPC_EXCP_NONE;
10524 env->error_code = 0;
2b15811c
DG		 10525
10526#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1bfb37d1
DG		 10527 env->vpa_addr = 0;
10528 env->slb_shadow_addr = 0;
10529 env->slb_shadow_size = 0;
10530 env->dtl_addr = 0;
2b15811c
DG		 10531 env->dtl_size = 0;
10532#endif /* TARGET_PPC64 */
10533
a1389542
AF		 10534 /* Flush all TLBs */
10535 tlb_flush(env, 1);
1d0cb67d
AF		 10536}
10537
6cca7ad6
AF		 10538static void ppc_cpu_initfn(Object *obj)
10539{
c05efcb1 10540 CPUState *cs = CPU(obj);
6cca7ad6 10541 PowerPCCPU *cpu = POWERPC_CPU(obj);
2985b86b 10542 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6cca7ad6
AF		 10543 CPUPPCState *env = &cpu->env;
10544
c05efcb1 10545 cs->env_ptr = env;
6cca7ad6 10546 cpu_exec_init(env);
2985b86b 10547
cfe34f44
AF		 10548 env->msr_mask = pcc->msr_mask;
10549 env->mmu_model = pcc->mmu_model;
10550 env->excp_model = pcc->excp_model;
10551 env->bus_model = pcc->bus_model;
10552 env->insns_flags = pcc->insns_flags;
10553 env->insns_flags2 = pcc->insns_flags2;
10554 env->flags = pcc->flags;
10555 env->bfd_mach = pcc->bfd_mach;
10556 env->check_pow = pcc->check_pow;
2985b86b
AF		 10557
10558#if defined(TARGET_PPC64)
cfe34f44
AF		 10559 if (pcc->sps) {
10560 env->sps = *pcc->sps;
2985b86b
AF		 10561 } else if (env->mmu_model & POWERPC_MMU_64) {
10562 /* Use default sets of page sizes */
10563 static const struct ppc_segment_page_sizes defsps = {
10564 .sps = {
10565 { .page_shift = 12, /* 4K */
10566 .slb_enc = 0,
10567 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10568 },
10569 { .page_shift = 24, /* 16M */
10570 .slb_enc = 0x100,
10571 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10572 },
10573 },
10574 };
10575 env->sps = defsps;
10576 }
10577#endif /* defined(TARGET_PPC64) */
60925d26
AF		 10578
10579 if (tcg_enabled()) {
10580 ppc_translate_init();
10581 }
6cca7ad6
AF		 10582}
10583
1d0cb67d
AF		 10584static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10585{
10586 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10587 CPUClass *cc = CPU_CLASS(oc);
4776ce60
AF		 10588 DeviceClass *dc = DEVICE_CLASS(oc);
10589
10590 pcc->parent_realize = dc->realize;
10591 dc->realize = ppc_cpu_realizefn;
1d0cb67d
AF		 10592
10593 pcc->parent_reset = cc->reset;
10594 cc->reset = ppc_cpu_reset;
2b8c2754
AF		 10595
10596 cc->class_by_name = ppc_cpu_class_by_name;
1d0cb67d
AF		 10597}
10598
10599static const TypeInfo ppc_cpu_type_info = {
10600 .name = TYPE_POWERPC_CPU,
10601 .parent = TYPE_CPU,
10602 .instance_size = sizeof(PowerPCCPU),
6cca7ad6 10603 .instance_init = ppc_cpu_initfn,
2985b86b 10604 .abstract = true,
1d0cb67d
AF		 10605 .class_size = sizeof(PowerPCCPUClass),
10606 .class_init = ppc_cpu_class_init,
10607};
10608
10609static void ppc_cpu_register_types(void)
10610{
10611 type_register_static(&ppc_cpu_type_info);
10612}
10613
10614type_init(ppc_cpu_register_types)
Empty description
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