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CommitLineData
6cbf4c8c
CM
1/*
2 * Inter-VM Shared Memory PCI device.
3 *
4 * Author:
5 * Cam Macdonell <[email protected]>
6 *
7 * Based On: cirrus_vga.c
8 * Copyright (c) 2004 Fabrice Bellard
9 * Copyright (c) 2004 Makoto Suzuki (suzu)
10 *
11 * and rtl8139.c
12 * Copyright (c) 2006 Igor Kovalenko
13 *
14 * This code is licensed under the GNU GPL v2.
6b620ca3
PB
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
6cbf4c8c 18 */
0d1c9782 19#include "qemu/osdep.h"
da34e65c 20#include "qapi/error.h"
f348b6d1 21#include "qemu/cutils.h"
83c9f4ca 22#include "hw/hw.h"
0d09e41a 23#include "hw/i386/pc.h"
83c9f4ca 24#include "hw/pci/pci.h"
660c97ee 25#include "hw/pci/msi.h"
83c9f4ca 26#include "hw/pci/msix.h"
9c17d615 27#include "sysemu/kvm.h"
795c40b8 28#include "migration/blocker.h"
d49b6836 29#include "qemu/error-report.h"
1de7afc9 30#include "qemu/event_notifier.h"
5503e285 31#include "qom/object_interfaces.h"
4d43a603 32#include "chardev/char-fe.h"
d9453c93 33#include "sysemu/hostmem.h"
5400c02b 34#include "sysemu/qtest.h"
d9453c93 35#include "qapi/visitor.h"
6cbf4c8c 36
5105b1d8
DM
37#include "hw/misc/ivshmem.h"
38
b8ef62a9
PB
39#define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET
40#define PCI_DEVICE_ID_IVSHMEM 0x1110
41
cd9953f7 42#define IVSHMEM_MAX_PEERS UINT16_MAX
6cbf4c8c
CM
43#define IVSHMEM_IOEVENTFD 0
44#define IVSHMEM_MSI 1
45
6cbf4c8c
CM
46#define IVSHMEM_REG_BAR_SIZE 0x100
47
a4fa93bf
MA
48#define IVSHMEM_DEBUG 0
49#define IVSHMEM_DPRINTF(fmt, ...) \
50 do { \
51 if (IVSHMEM_DEBUG) { \
52 printf("IVSHMEM: " fmt, ## __VA_ARGS__); \
53 } \
54 } while (0)
6cbf4c8c 55
5400c02b
MA
56#define TYPE_IVSHMEM_COMMON "ivshmem-common"
57#define IVSHMEM_COMMON(obj) \
58 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_COMMON)
59
60#define TYPE_IVSHMEM_PLAIN "ivshmem-plain"
61#define IVSHMEM_PLAIN(obj) \
62 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_PLAIN)
63
64#define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell"
65#define IVSHMEM_DOORBELL(obj) \
66 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_DOORBELL)
67
eb3fedf3
PC
68#define TYPE_IVSHMEM "ivshmem"
69#define IVSHMEM(obj) \
70 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM)
71
6cbf4c8c
CM
72typedef struct Peer {
73 int nb_eventfds;
563027cc 74 EventNotifier *eventfds;
6cbf4c8c
CM
75} Peer;
76
0f57350e 77typedef struct MSIVector {
6cbf4c8c 78 PCIDevice *pdev;
660c97ee 79 int virq;
0f57350e 80} MSIVector;
6cbf4c8c
CM
81
82typedef struct IVShmemState {
b7578eaa
AF
83 /*< private >*/
84 PCIDevice parent_obj;
85 /*< public >*/
86
ddc85284
MA
87 uint32_t features;
88
89 /* exactly one of these two may be set */
90 HostMemoryBackend *hostmem; /* with interrupts */
becdfa00 91 CharBackend server_chr; /* without interrupts */
ddc85284
MA
92
93 /* registers */
6cbf4c8c
CM
94 uint32_t intrmask;
95 uint32_t intrstatus;
ddc85284 96 int vm_id;
6cbf4c8c 97
ddc85284
MA
98 /* BARs */
99 MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */
c2d8019c
MA
100 MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */
101 MemoryRegion server_bar2; /* used with server_chr */
6cbf4c8c 102
ddc85284 103 /* interrupt support */
6cbf4c8c 104 Peer *peers;
cd9953f7 105 int nb_peers; /* space in @peers[] */
6cbf4c8c 106 uint32_t vectors;
0f57350e 107 MSIVector *msi_vectors;
ee276391
MA
108 uint64_t msg_buf; /* buffer for receiving server messages */
109 int msg_buffered_bytes; /* #bytes in @msg_buf */
6cbf4c8c 110
ddc85284 111 /* migration stuff */
2a845da7 112 OnOffAuto master;
38e0735e
AL
113 Error *migration_blocker;
114
5400c02b
MA
115 /* legacy cruft */
116 char *role;
117 char *shmobj;
118 char *sizearg;
119 size_t legacy_size;
120 uint32_t not_legacy_32bit;
6cbf4c8c
CM
121} IVShmemState;
122
123/* registers for the Inter-VM shared memory device */
124enum ivshmem_registers {
125 INTRMASK = 0,
126 INTRSTATUS = 4,
127 IVPOSITION = 8,
128 DOORBELL = 12,
129};
130
131static inline uint32_t ivshmem_has_feature(IVShmemState *ivs,
132 unsigned int feature) {
133 return (ivs->features & (1 << feature));
134}
135
2a845da7
MA
136static inline bool ivshmem_is_master(IVShmemState *s)
137{
138 assert(s->master != ON_OFF_AUTO_AUTO);
139 return s->master == ON_OFF_AUTO_ON;
140}
141
d8a5da07 142static void ivshmem_update_irq(IVShmemState *s)
6cbf4c8c 143{
b7578eaa 144 PCIDevice *d = PCI_DEVICE(s);
434ad76d 145 uint32_t isr = s->intrstatus & s->intrmask;
6cbf4c8c 146
5400c02b
MA
147 /*
148 * Do nothing unless the device actually uses INTx. Here's how
149 * the device variants signal interrupts, what they put in PCI
150 * config space:
151 * Device variant Interrupt Interrupt Pin MSI-X cap.
152 * ivshmem-plain none 0 no
153 * ivshmem-doorbell MSI-X 1 yes(1)
154 * ivshmem,msi=off INTx 1 no
155 * ivshmem,msi=on MSI-X 1(2) yes(1)
156 * (1) if guest enabled MSI-X
157 * (2) the device lies
158 * Leads to the condition for doing nothing:
159 */
160 if (ivshmem_has_feature(s, IVSHMEM_MSI)
161 || !d->config[PCI_INTERRUPT_PIN]) {
2d1d422d
MA
162 return;
163 }
164
6cbf4c8c
CM
165 /* don't print ISR resets */
166 if (isr) {
167 IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n",
dbc464d4 168 isr ? 1 : 0, s->intrstatus, s->intrmask);
6cbf4c8c
CM
169 }
170
434ad76d 171 pci_set_irq(d, isr != 0);
6cbf4c8c
CM
172}
173
174static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
175{
176 IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val);
177
178 s->intrmask = val;
d8a5da07 179 ivshmem_update_irq(s);
6cbf4c8c
CM
180}
181
182static uint32_t ivshmem_IntrMask_read(IVShmemState *s)
183{
184 uint32_t ret = s->intrmask;
185
186 IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret);
6cbf4c8c
CM
187 return ret;
188}
189
190static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val)
191{
192 IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val);
193
194 s->intrstatus = val;
d8a5da07 195 ivshmem_update_irq(s);
6cbf4c8c
CM
196}
197
198static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
199{
200 uint32_t ret = s->intrstatus;
201
202 /* reading ISR clears all interrupts */
203 s->intrstatus = 0;
d8a5da07 204 ivshmem_update_irq(s);
6cbf4c8c
CM
205 return ret;
206}
207
a8170e5e 208static void ivshmem_io_write(void *opaque, hwaddr addr,
cb06608e 209 uint64_t val, unsigned size)
6cbf4c8c
CM
210{
211 IVShmemState *s = opaque;
212
6cbf4c8c
CM
213 uint16_t dest = val >> 16;
214 uint16_t vector = val & 0xff;
215
216 addr &= 0xfc;
217
218 IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr);
219 switch (addr)
220 {
221 case INTRMASK:
222 ivshmem_IntrMask_write(s, val);
223 break;
224
225 case INTRSTATUS:
226 ivshmem_IntrStatus_write(s, val);
227 break;
228
229 case DOORBELL:
230 /* check that dest VM ID is reasonable */
95c8425c 231 if (dest >= s->nb_peers) {
6cbf4c8c
CM
232 IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest);
233 break;
234 }
235
236 /* check doorbell range */
1b27d7a1 237 if (vector < s->peers[dest].nb_eventfds) {
563027cc
PB
238 IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector);
239 event_notifier_set(&s->peers[dest].eventfds[vector]);
f59bb378
MAL
240 } else {
241 IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n",
242 vector, dest);
6cbf4c8c
CM
243 }
244 break;
245 default:
f59bb378 246 IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr);
6cbf4c8c
CM
247 }
248}
249
a8170e5e 250static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
cb06608e 251 unsigned size)
6cbf4c8c
CM
252{
253
254 IVShmemState *s = opaque;
255 uint32_t ret;
256
257 switch (addr)
258 {
259 case INTRMASK:
260 ret = ivshmem_IntrMask_read(s);
261 break;
262
263 case INTRSTATUS:
264 ret = ivshmem_IntrStatus_read(s);
265 break;
266
267 case IVPOSITION:
1309cf44 268 ret = s->vm_id;
6cbf4c8c
CM
269 break;
270
271 default:
272 IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr);
273 ret = 0;
274 }
275
276 return ret;
277}
278
cb06608e
AK
279static const MemoryRegionOps ivshmem_mmio_ops = {
280 .read = ivshmem_io_read,
281 .write = ivshmem_io_write,
282 .endianness = DEVICE_NATIVE_ENDIAN,
283 .impl = {
284 .min_access_size = 4,
285 .max_access_size = 4,
286 },
6cbf4c8c
CM
287};
288
9940c323
MAL
289static void ivshmem_vector_notify(void *opaque)
290{
0f57350e 291 MSIVector *entry = opaque;
6cbf4c8c 292 PCIDevice *pdev = entry->pdev;
5400c02b 293 IVShmemState *s = IVSHMEM_COMMON(pdev);
0f57350e 294 int vector = entry - s->msi_vectors;
9940c323
MAL
295 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
296
297 if (!event_notifier_test_and_clear(n)) {
298 return;
299 }
6cbf4c8c 300
d160f3f7 301 IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector);
9940c323 302 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8
MA
303 if (msix_enabled(pdev)) {
304 msix_notify(pdev, vector);
305 }
9940c323
MAL
306 } else {
307 ivshmem_IntrStatus_write(s, 1);
308 }
6cbf4c8c
CM
309}
310
660c97ee
MAL
311static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector,
312 MSIMessage msg)
313{
5400c02b 314 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
315 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
316 MSIVector *v = &s->msi_vectors[vector];
317 int ret;
318
319 IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector);
320
321 ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev);
322 if (ret < 0) {
323 return ret;
324 }
3f1fea0f 325 kvm_irqchip_commit_routes(kvm_state);
660c97ee
MAL
326
327 return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq);
328}
329
330static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector)
331{
5400c02b 332 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
333 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
334 int ret;
335
336 IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector);
337
338 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n,
339 s->msi_vectors[vector].virq);
340 if (ret != 0) {
341 error_report("remove_irqfd_notifier_gsi failed");
342 }
343}
344
345static void ivshmem_vector_poll(PCIDevice *dev,
346 unsigned int vector_start,
347 unsigned int vector_end)
348{
5400c02b 349 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
350 unsigned int vector;
351
352 IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end);
353
354 vector_end = MIN(vector_end, s->vectors);
355
356 for (vector = vector_start; vector < vector_end; vector++) {
357 EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector];
358
359 if (!msix_is_masked(dev, vector)) {
360 continue;
361 }
362
363 if (event_notifier_test_and_clear(notifier)) {
364 msix_set_pending(dev, vector);
365 }
366 }
367}
368
9940c323
MAL
369static void watch_vector_notifier(IVShmemState *s, EventNotifier *n,
370 int vector)
6cbf4c8c 371{
563027cc 372 int eventfd = event_notifier_get_fd(n);
6cbf4c8c 373
3c27969b 374 assert(!s->msi_vectors[vector].pdev);
9940c323 375 s->msi_vectors[vector].pdev = PCI_DEVICE(s);
6cbf4c8c 376
9940c323
MAL
377 qemu_set_fd_handler(eventfd, ivshmem_vector_notify,
378 NULL, &s->msi_vectors[vector]);
6cbf4c8c
CM
379}
380
563027cc
PB
381static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i)
382{
383 memory_region_add_eventfd(&s->ivshmem_mmio,
384 DOORBELL,
385 4,
386 true,
387 (posn << 16) | i,
753d5e14 388 &s->peers[posn].eventfds[i]);
563027cc
PB
389}
390
391static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i)
392{
393 memory_region_del_eventfd(&s->ivshmem_mmio,
394 DOORBELL,
395 4,
396 true,
397 (posn << 16) | i,
753d5e14 398 &s->peers[posn].eventfds[i]);
563027cc
PB
399}
400
f456179f 401static void close_peer_eventfds(IVShmemState *s, int posn)
6cbf4c8c 402{
f456179f 403 int i, n;
6cbf4c8c 404
9db51b4d 405 assert(posn >= 0 && posn < s->nb_peers);
f456179f 406 n = s->peers[posn].nb_eventfds;
6cbf4c8c 407
9db51b4d
MA
408 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
409 memory_region_transaction_begin();
410 for (i = 0; i < n; i++) {
411 ivshmem_del_eventfd(s, posn, i);
412 }
413 memory_region_transaction_commit();
b6a1f3a5 414 }
9db51b4d 415
f456179f 416 for (i = 0; i < n; i++) {
563027cc 417 event_notifier_cleanup(&s->peers[posn].eventfds[i]);
6cbf4c8c
CM
418 }
419
7267c094 420 g_free(s->peers[posn].eventfds);
6cbf4c8c
CM
421 s->peers[posn].nb_eventfds = 0;
422}
423
cd9953f7 424static void resize_peers(IVShmemState *s, int nb_peers)
34bc07c5 425{
cd9953f7
MA
426 int old_nb_peers = s->nb_peers;
427 int i;
6cbf4c8c 428
cd9953f7
MA
429 assert(nb_peers > old_nb_peers);
430 IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers);
6cbf4c8c 431
cd9953f7
MA
432 s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer));
433 s->nb_peers = nb_peers;
1300b273 434
cd9953f7
MA
435 for (i = old_nb_peers; i < nb_peers; i++) {
436 s->peers[i].eventfds = g_new0(EventNotifier, s->vectors);
437 s->peers[i].nb_eventfds = 0;
6cbf4c8c
CM
438 }
439}
440
1309cf44
MA
441static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector,
442 Error **errp)
660c97ee
MAL
443{
444 PCIDevice *pdev = PCI_DEVICE(s);
660c97ee
MAL
445 int ret;
446
447 IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector);
3c27969b 448 assert(!s->msi_vectors[vector].pdev);
660c97ee 449
d1f6af6a 450 ret = kvm_irqchip_add_msi_route(kvm_state, vector, pdev);
660c97ee 451 if (ret < 0) {
1309cf44
MA
452 error_setg(errp, "kvm_irqchip_add_msi_route failed");
453 return;
660c97ee
MAL
454 }
455
456 s->msi_vectors[vector].virq = ret;
457 s->msi_vectors[vector].pdev = pdev;
660c97ee
MAL
458}
459
1309cf44 460static void setup_interrupt(IVShmemState *s, int vector, Error **errp)
660c97ee
MAL
461{
462 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
463 bool with_irqfd = kvm_msi_via_irqfd_enabled() &&
464 ivshmem_has_feature(s, IVSHMEM_MSI);
465 PCIDevice *pdev = PCI_DEVICE(s);
1309cf44 466 Error *err = NULL;
660c97ee
MAL
467
468 IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector);
469
470 if (!with_irqfd) {
97553976 471 IVSHMEM_DPRINTF("with eventfd\n");
9940c323 472 watch_vector_notifier(s, n, vector);
660c97ee 473 } else if (msix_enabled(pdev)) {
97553976 474 IVSHMEM_DPRINTF("with irqfd\n");
1309cf44
MA
475 ivshmem_add_kvm_msi_virq(s, vector, &err);
476 if (err) {
477 error_propagate(errp, err);
660c97ee
MAL
478 return;
479 }
480
481 if (!msix_is_masked(pdev, vector)) {
482 kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL,
483 s->msi_vectors[vector].virq);
1309cf44 484 /* TODO handle error */
660c97ee
MAL
485 }
486 } else {
487 /* it will be delayed until msix is enabled, in write_config */
97553976 488 IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n");
660c97ee
MAL
489 }
490}
491
1309cf44 492static void process_msg_shmem(IVShmemState *s, int fd, Error **errp)
6cbf4c8c 493{
8381d89b 494 Error *local_err = NULL;
8baeb22b 495 struct stat buf;
5400c02b 496 size_t size;
6cbf4c8c 497
c2d8019c 498 if (s->ivshmem_bar2) {
1309cf44 499 error_setg(errp, "server sent unexpected shared memory message");
ca0b7566 500 close(fd);
0f14fd71 501 return;
a2e9011b
SH
502 }
503
8baeb22b
MA
504 if (fstat(fd, &buf) < 0) {
505 error_setg_errno(errp, errno,
506 "can't determine size of shared memory sent by server");
507 close(fd);
508 return;
509 }
510
5400c02b
MA
511 size = buf.st_size;
512
513 /* Legacy cruft */
514 if (s->legacy_size != SIZE_MAX) {
515 if (size < s->legacy_size) {
516 error_setg(errp, "server sent only %zd bytes of shared memory",
517 (size_t)buf.st_size);
518 close(fd);
519 return;
520 }
521 size = s->legacy_size;
cd9953f7
MA
522 }
523
ca0b7566 524 /* mmap the region and map into the BAR2 */
8381d89b
MAL
525 memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s),
526 "ivshmem.bar2", size, true, fd, &local_err);
527 if (local_err) {
528 error_propagate(errp, local_err);
ca0b7566 529 return;
6cbf4c8c 530 }
8381d89b 531
c2d8019c 532 s->ivshmem_bar2 = &s->server_bar2;
ca0b7566
MA
533}
534
1309cf44
MA
535static void process_msg_disconnect(IVShmemState *s, uint16_t posn,
536 Error **errp)
ca0b7566
MA
537{
538 IVSHMEM_DPRINTF("posn %d has gone away\n", posn);
9db51b4d 539 if (posn >= s->nb_peers || posn == s->vm_id) {
1309cf44 540 error_setg(errp, "invalid peer %d", posn);
9db51b4d
MA
541 return;
542 }
ca0b7566
MA
543 close_peer_eventfds(s, posn);
544}
6cbf4c8c 545
1309cf44
MA
546static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd,
547 Error **errp)
ca0b7566
MA
548{
549 Peer *peer = &s->peers[posn];
550 int vector;
9a2f0e64 551
ca0b7566
MA
552 /*
553 * The N-th connect message for this peer comes with the file
554 * descriptor for vector N-1. Count messages to find the vector.
555 */
556 if (peer->nb_eventfds >= s->vectors) {
1309cf44
MA
557 error_setg(errp, "Too many eventfd received, device has %d vectors",
558 s->vectors);
ca0b7566 559 close(fd);
6f8a16d5 560 return;
6cbf4c8c 561 }
ca0b7566 562 vector = peer->nb_eventfds++;
6cbf4c8c 563
ca0b7566
MA
564 IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd);
565 event_notifier_init_fd(&peer->eventfds[vector], fd);
566 fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */
945001a1 567
ca0b7566 568 if (posn == s->vm_id) {
1309cf44
MA
569 setup_interrupt(s, vector, errp);
570 /* TODO do we need to handle the error? */
ca0b7566 571 }
6cbf4c8c 572
ca0b7566
MA
573 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
574 ivshmem_add_eventfd(s, posn, vector);
575 }
576}
6cbf4c8c 577
1309cf44 578static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp)
ca0b7566
MA
579{
580 IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd);
6cbf4c8c 581
ca0b7566 582 if (msg < -1 || msg > IVSHMEM_MAX_PEERS) {
1309cf44 583 error_setg(errp, "server sent invalid message %" PRId64, msg);
ca0b7566 584 close(fd);
6cbf4c8c
CM
585 return;
586 }
587
ca0b7566 588 if (msg == -1) {
1309cf44 589 process_msg_shmem(s, fd, errp);
1ee57de4
MAL
590 return;
591 }
592
ca0b7566
MA
593 if (msg >= s->nb_peers) {
594 resize_peers(s, msg + 1);
595 }
6cbf4c8c 596
ca0b7566 597 if (fd >= 0) {
1309cf44 598 process_msg_connect(s, msg, fd, errp);
ca0b7566 599 } else {
1309cf44 600 process_msg_disconnect(s, msg, errp);
6cbf4c8c 601 }
ca0b7566 602}
6cbf4c8c 603
ee276391
MA
604static int ivshmem_can_receive(void *opaque)
605{
606 IVShmemState *s = opaque;
607
608 assert(s->msg_buffered_bytes < sizeof(s->msg_buf));
609 return sizeof(s->msg_buf) - s->msg_buffered_bytes;
610}
611
ca0b7566
MA
612static void ivshmem_read(void *opaque, const uint8_t *buf, int size)
613{
614 IVShmemState *s = opaque;
1309cf44 615 Error *err = NULL;
ca0b7566
MA
616 int fd;
617 int64_t msg;
618
ee276391
MA
619 assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf));
620 memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size);
621 s->msg_buffered_bytes += size;
622 if (s->msg_buffered_bytes < sizeof(s->msg_buf)) {
ca0b7566 623 return;
6cbf4c8c 624 }
ee276391
MA
625 msg = le64_to_cpu(s->msg_buf);
626 s->msg_buffered_bytes = 0;
ca0b7566 627
5345fdb4 628 fd = qemu_chr_fe_get_msgfd(&s->server_chr);
ca0b7566 629
1309cf44
MA
630 process_msg(s, msg, fd, &err);
631 if (err) {
632 error_report_err(err);
633 }
6cbf4c8c
CM
634}
635
1309cf44 636static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp)
5105b1d8 637{
3a55fc0f
MA
638 int64_t msg;
639 int n, ret;
640
641 n = 0;
642 do {
5345fdb4
MAL
643 ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n,
644 sizeof(msg) - n);
3a55fc0f 645 if (ret < 0 && ret != -EINTR) {
1309cf44 646 error_setg_errno(errp, -ret, "read from server failed");
3a55fc0f
MA
647 return INT64_MIN;
648 }
649 n += ret;
650 } while (n < sizeof(msg));
5105b1d8 651
5345fdb4 652 *pfd = qemu_chr_fe_get_msgfd(&s->server_chr);
3a55fc0f
MA
653 return msg;
654}
5105b1d8 655
1309cf44 656static void ivshmem_recv_setup(IVShmemState *s, Error **errp)
3a55fc0f 657{
1309cf44 658 Error *err = NULL;
3a55fc0f
MA
659 int64_t msg;
660 int fd;
661
1309cf44
MA
662 msg = ivshmem_recv_msg(s, &fd, &err);
663 if (err) {
664 error_propagate(errp, err);
665 return;
666 }
667 if (msg != IVSHMEM_PROTOCOL_VERSION) {
668 error_setg(errp, "server sent version %" PRId64 ", expecting %d",
669 msg, IVSHMEM_PROTOCOL_VERSION);
670 return;
671 }
672 if (fd != -1) {
673 error_setg(errp, "server sent invalid version message");
5105b1d8
DM
674 return;
675 }
676
a3feb086
MA
677 /*
678 * ivshmem-server sends the remaining initial messages in a fixed
679 * order, but the device has always accepted them in any order.
680 * Stay as compatible as practical, just in case people use
681 * servers that behave differently.
682 */
683
684 /*
685 * ivshmem_device_spec.txt has always required the ID message
686 * right here, and ivshmem-server has always complied. However,
687 * older versions of the device accepted it out of order, but
688 * broke when an interrupt setup message arrived before it.
689 */
690 msg = ivshmem_recv_msg(s, &fd, &err);
691 if (err) {
692 error_propagate(errp, err);
693 return;
694 }
695 if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) {
696 error_setg(errp, "server sent invalid ID message");
697 return;
698 }
699 s->vm_id = msg;
700
3a55fc0f
MA
701 /*
702 * Receive more messages until we got shared memory.
703 */
704 do {
1309cf44
MA
705 msg = ivshmem_recv_msg(s, &fd, &err);
706 if (err) {
707 error_propagate(errp, err);
708 return;
709 }
710 process_msg(s, msg, fd, &err);
711 if (err) {
712 error_propagate(errp, err);
713 return;
714 }
3a55fc0f 715 } while (msg != -1);
1309cf44
MA
716
717 /*
718 * This function must either map the shared memory or fail. The
719 * loop above ensures that: it terminates normally only after it
720 * successfully processed the server's shared memory message.
721 * Assert that actually mapped the shared memory:
722 */
c2d8019c 723 assert(s->ivshmem_bar2);
5105b1d8
DM
724}
725
4490c711
MT
726/* Select the MSI-X vectors used by device.
727 * ivshmem maps events to vectors statically, so
728 * we just enable all vectors on init and after reset. */
082751e8 729static void ivshmem_msix_vector_use(IVShmemState *s)
4490c711 730{
b7578eaa 731 PCIDevice *d = PCI_DEVICE(s);
4490c711
MT
732 int i;
733
4490c711 734 for (i = 0; i < s->vectors; i++) {
b7578eaa 735 msix_vector_use(d, i);
4490c711
MT
736 }
737}
738
6cbf4c8c
CM
739static void ivshmem_reset(DeviceState *d)
740{
5400c02b 741 IVShmemState *s = IVSHMEM_COMMON(d);
6cbf4c8c
CM
742
743 s->intrstatus = 0;
972ad215 744 s->intrmask = 0;
082751e8
MA
745 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
746 ivshmem_msix_vector_use(s);
747 }
6cbf4c8c
CM
748}
749
ee640c62 750static int ivshmem_setup_interrupts(IVShmemState *s, Error **errp)
4490c711 751{
fd47bfe5
MAL
752 /* allocate QEMU callback data for receiving interrupts */
753 s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector));
6cbf4c8c 754
fd47bfe5 755 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
ee640c62 756 if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1, errp)) {
fd47bfe5
MAL
757 return -1;
758 }
1116b539 759
fd47bfe5 760 IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
082751e8 761 ivshmem_msix_vector_use(s);
fd47bfe5 762 }
4490c711 763
d58d7e84 764 return 0;
6cbf4c8c
CM
765}
766
660c97ee
MAL
767static void ivshmem_enable_irqfd(IVShmemState *s)
768{
769 PCIDevice *pdev = PCI_DEVICE(s);
770 int i;
771
772 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
1309cf44
MA
773 Error *err = NULL;
774
775 ivshmem_add_kvm_msi_virq(s, i, &err);
776 if (err) {
777 error_report_err(err);
778 /* TODO do we need to handle the error? */
779 }
660c97ee
MAL
780 }
781
782 if (msix_set_vector_notifiers(pdev,
783 ivshmem_vector_unmask,
784 ivshmem_vector_mask,
785 ivshmem_vector_poll)) {
786 error_report("ivshmem: msix_set_vector_notifiers failed");
787 }
788}
789
790static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector)
791{
792 IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector);
793
794 if (s->msi_vectors[vector].pdev == NULL) {
795 return;
796 }
797
798 /* it was cleaned when masked in the frontend. */
799 kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq);
800
801 s->msi_vectors[vector].pdev = NULL;
802}
803
804static void ivshmem_disable_irqfd(IVShmemState *s)
805{
806 PCIDevice *pdev = PCI_DEVICE(s);
807 int i;
808
809 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
810 ivshmem_remove_kvm_msi_virq(s, i);
811 }
812
813 msix_unset_vector_notifiers(pdev);
814}
815
816static void ivshmem_write_config(PCIDevice *pdev, uint32_t address,
d58d7e84 817 uint32_t val, int len)
4490c711 818{
5400c02b 819 IVShmemState *s = IVSHMEM_COMMON(pdev);
660c97ee
MAL
820 int is_enabled, was_enabled = msix_enabled(pdev);
821
822 pci_default_write_config(pdev, address, val, len);
823 is_enabled = msix_enabled(pdev);
824
1309cf44 825 if (kvm_msi_via_irqfd_enabled()) {
660c97ee
MAL
826 if (!was_enabled && is_enabled) {
827 ivshmem_enable_irqfd(s);
828 } else if (was_enabled && !is_enabled) {
829 ivshmem_disable_irqfd(s);
830 }
831 }
4490c711
MT
832}
833
5400c02b 834static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
6cbf4c8c 835{
5400c02b 836 IVShmemState *s = IVSHMEM_COMMON(dev);
d855e275 837 Error *err = NULL;
6cbf4c8c 838 uint8_t *pci_conf;
9113e3f3
MAL
839 uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY |
840 PCI_BASE_ADDRESS_MEM_PREFETCH;
fe44dc91 841 Error *local_err = NULL;
6cbf4c8c 842
6cbf4c8c
CM
843 /* IRQFD requires MSI */
844 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) &&
845 !ivshmem_has_feature(s, IVSHMEM_MSI)) {
d58d7e84
MAL
846 error_setg(errp, "ioeventfd/irqfd requires MSI");
847 return;
6cbf4c8c
CM
848 }
849
b7578eaa 850 pci_conf = dev->config;
6cbf4c8c 851 pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
6cbf4c8c 852
3c161542 853 memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s,
cb06608e
AK
854 "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE);
855
6cbf4c8c 856 /* region for registers*/
b7578eaa 857 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
e824b2cc 858 &s->ivshmem_mmio);
cb06608e 859
b2b79a69 860 if (s->not_legacy_32bit) {
9113e3f3 861 attr |= PCI_BASE_ADDRESS_MEM_TYPE_64;
c08ba66f 862 }
6cbf4c8c 863
d9453c93 864 if (s->hostmem != NULL) {
d9453c93
MAL
865 IVSHMEM_DPRINTF("using hostmem\n");
866
c2d8019c
MA
867 s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem,
868 &error_abort);
5503e285 869 } else {
0ec7b3e7 870 Chardev *chr = qemu_chr_fe_get_driver(&s->server_chr);
5345fdb4 871 assert(chr);
6dc64780 872
6cbf4c8c 873 IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n",
5345fdb4 874 chr->filename);
6cbf4c8c 875
f456179f 876 /* we allocate enough space for 16 peers and grow as needed */
1300b273 877 resize_peers(s, 16);
6cbf4c8c 878
3a55fc0f
MA
879 /*
880 * Receive setup messages from server synchronously.
881 * Older versions did it asynchronously, but that creates a
882 * number of entertaining race conditions.
3a55fc0f 883 */
1309cf44
MA
884 ivshmem_recv_setup(s, &err);
885 if (err) {
886 error_propagate(errp, err);
887 return;
3a55fc0f
MA
888 }
889
62a830b6
MA
890 if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) {
891 error_setg(errp,
892 "master must connect to the server before any peers");
893 return;
894 }
895
5345fdb4 896 qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive,
81517ba3 897 ivshmem_read, NULL, NULL, s, NULL, true);
1309cf44 898
ee640c62
C
899 if (ivshmem_setup_interrupts(s, errp) < 0) {
900 error_prepend(errp, "Failed to initialize interrupts: ");
3a55fc0f
MA
901 return;
902 }
d855e275
MA
903 }
904
2a845da7
MA
905 if (s->master == ON_OFF_AUTO_AUTO) {
906 s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
907 }
908
909 if (!ivshmem_is_master(s)) {
d855e275
MA
910 error_setg(&s->migration_blocker,
911 "Migration is disabled when using feature 'peer mode' in device 'ivshmem'");
fe44dc91
AA
912 migrate_add_blocker(s->migration_blocker, &local_err);
913 if (local_err) {
914 error_propagate(errp, local_err);
915 error_free(s->migration_blocker);
916 return;
917 }
6cbf4c8c 918 }
fe44dc91
AA
919
920 vmstate_register_ram(s->ivshmem_bar2, DEVICE(s));
921 pci_register_bar(PCI_DEVICE(s), 2, attr, s->ivshmem_bar2);
6cbf4c8c
CM
922}
923
5400c02b
MA
924static void ivshmem_exit(PCIDevice *dev)
925{
926 IVShmemState *s = IVSHMEM_COMMON(dev);
f64a078d
MAL
927 int i;
928
38e0735e
AL
929 if (s->migration_blocker) {
930 migrate_del_blocker(s->migration_blocker);
931 error_free(s->migration_blocker);
932 }
933
c2d8019c 934 if (memory_region_is_mapped(s->ivshmem_bar2)) {
d9453c93 935 if (!s->hostmem) {
c2d8019c 936 void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2);
56a571d9 937 int fd;
d9453c93 938
5400c02b 939 if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) {
d9453c93
MAL
940 error_report("Failed to munmap shared memory %s",
941 strerror(errno));
942 }
56a571d9 943
4ff87573 944 fd = memory_region_get_fd(s->ivshmem_bar2);
c2d8019c 945 close(fd);
d9453c93 946 }
f64a078d 947
c2d8019c 948 vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev));
f64a078d
MAL
949 }
950
f64a078d
MAL
951 if (s->peers) {
952 for (i = 0; i < s->nb_peers; i++) {
f456179f 953 close_peer_eventfds(s, i);
f64a078d
MAL
954 }
955 g_free(s->peers);
956 }
957
958 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
959 msix_uninit_exclusive_bar(dev);
960 }
961
0f57350e 962 g_free(s->msi_vectors);
6cbf4c8c
CM
963}
964
1f8552df
MAL
965static int ivshmem_pre_load(void *opaque)
966{
967 IVShmemState *s = opaque;
968
2a845da7 969 if (!ivshmem_is_master(s)) {
1f8552df
MAL
970 error_report("'peer' devices are not migratable");
971 return -EINVAL;
972 }
973
974 return 0;
975}
976
977static int ivshmem_post_load(void *opaque, int version_id)
978{
979 IVShmemState *s = opaque;
980
981 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8 982 ivshmem_msix_vector_use(s);
1f8552df 983 }
1f8552df
MAL
984 return 0;
985}
986
5400c02b 987static void ivshmem_common_class_init(ObjectClass *klass, void *data)
40021f08 988{
39bffca2 989 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL
990 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
991
5400c02b
MA
992 k->realize = ivshmem_common_realize;
993 k->exit = ivshmem_exit;
d58d7e84 994 k->config_write = ivshmem_write_config;
b8ef62a9
PB
995 k->vendor_id = PCI_VENDOR_ID_IVSHMEM;
996 k->device_id = PCI_DEVICE_ID_IVSHMEM;
40021f08 997 k->class_id = PCI_CLASS_MEMORY_RAM;
5400c02b 998 k->revision = 1;
39bffca2 999 dc->reset = ivshmem_reset;
125ee0ed 1000 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
d383537d 1001 dc->desc = "Inter-VM shared memory";
40021f08
AL
1002}
1003
ddc85284
MA
1004static const TypeInfo ivshmem_common_info = {
1005 .name = TYPE_IVSHMEM_COMMON,
1006 .parent = TYPE_PCI_DEVICE,
1007 .instance_size = sizeof(IVShmemState),
1008 .abstract = true,
1009 .class_init = ivshmem_common_class_init,
1010};
5400c02b 1011
d9453c93
MAL
1012static void ivshmem_check_memdev_is_busy(Object *obj, const char *name,
1013 Object *val, Error **errp)
1014{
2aece63c 1015 if (host_memory_backend_is_mapped(MEMORY_BACKEND(val))) {
d9453c93
MAL
1016 char *path = object_get_canonical_path_component(val);
1017 error_setg(errp, "can't use already busy memdev: %s", path);
1018 g_free(path);
1019 } else {
1020 qdev_prop_allow_set_link_before_realize(obj, name, val, errp);
1021 }
1022}
1023
5400c02b
MA
1024static const VMStateDescription ivshmem_plain_vmsd = {
1025 .name = TYPE_IVSHMEM_PLAIN,
1026 .version_id = 0,
1027 .minimum_version_id = 0,
1028 .pre_load = ivshmem_pre_load,
1029 .post_load = ivshmem_post_load,
1030 .fields = (VMStateField[]) {
1031 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1032 VMSTATE_UINT32(intrstatus, IVShmemState),
1033 VMSTATE_UINT32(intrmask, IVShmemState),
1034 VMSTATE_END_OF_LIST()
1035 },
1036};
1037
1038static Property ivshmem_plain_properties[] = {
1039 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1040 DEFINE_PROP_END_OF_LIST(),
1041};
1042
1043static void ivshmem_plain_init(Object *obj)
1044{
1045 IVShmemState *s = IVSHMEM_PLAIN(obj);
1046
1047 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
1048 (Object **)&s->hostmem,
1049 ivshmem_check_memdev_is_busy,
1050 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1051 &error_abort);
b2b79a69 1052 s->not_legacy_32bit = 1;
5400c02b
MA
1053}
1054
6dc64780
MAL
1055static void ivshmem_plain_realize(PCIDevice *dev, Error **errp)
1056{
1057 IVShmemState *s = IVSHMEM_COMMON(dev);
1058
1059 if (!s->hostmem) {
1060 error_setg(errp, "You must specify a 'memdev'");
1061 return;
1062 }
1063
1064 ivshmem_common_realize(dev, errp);
2aece63c
XG
1065 host_memory_backend_set_mapped(s->hostmem, true);
1066}
1067
1068static void ivshmem_plain_exit(PCIDevice *pci_dev)
1069{
1070 IVShmemState *s = IVSHMEM_COMMON(pci_dev);
1071
1072 host_memory_backend_set_mapped(s->hostmem, false);
6dc64780
MAL
1073}
1074
5400c02b
MA
1075static void ivshmem_plain_class_init(ObjectClass *klass, void *data)
1076{
1077 DeviceClass *dc = DEVICE_CLASS(klass);
6dc64780 1078 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
5400c02b 1079
6dc64780 1080 k->realize = ivshmem_plain_realize;
2aece63c 1081 k->exit = ivshmem_plain_exit;
5400c02b
MA
1082 dc->props = ivshmem_plain_properties;
1083 dc->vmsd = &ivshmem_plain_vmsd;
1084}
1085
1086static const TypeInfo ivshmem_plain_info = {
1087 .name = TYPE_IVSHMEM_PLAIN,
1088 .parent = TYPE_IVSHMEM_COMMON,
1089 .instance_size = sizeof(IVShmemState),
1090 .instance_init = ivshmem_plain_init,
1091 .class_init = ivshmem_plain_class_init,
1092};
1093
1094static const VMStateDescription ivshmem_doorbell_vmsd = {
1095 .name = TYPE_IVSHMEM_DOORBELL,
1096 .version_id = 0,
1097 .minimum_version_id = 0,
1098 .pre_load = ivshmem_pre_load,
1099 .post_load = ivshmem_post_load,
1100 .fields = (VMStateField[]) {
1101 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1102 VMSTATE_MSIX(parent_obj, IVShmemState),
1103 VMSTATE_UINT32(intrstatus, IVShmemState),
1104 VMSTATE_UINT32(intrmask, IVShmemState),
1105 VMSTATE_END_OF_LIST()
1106 },
1107};
1108
1109static Property ivshmem_doorbell_properties[] = {
1110 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1111 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1112 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1113 true),
1114 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1115 DEFINE_PROP_END_OF_LIST(),
1116};
1117
1118static void ivshmem_doorbell_init(Object *obj)
1119{
1120 IVShmemState *s = IVSHMEM_DOORBELL(obj);
1121
1122 s->features |= (1 << IVSHMEM_MSI);
1123 s->legacy_size = SIZE_MAX; /* whatever the server sends */
b2b79a69 1124 s->not_legacy_32bit = 1;
5400c02b
MA
1125}
1126
6dc64780
MAL
1127static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp)
1128{
1129 IVShmemState *s = IVSHMEM_COMMON(dev);
1130
30650701 1131 if (!qemu_chr_fe_backend_connected(&s->server_chr)) {
6dc64780
MAL
1132 error_setg(errp, "You must specify a 'chardev'");
1133 return;
1134 }
1135
1136 ivshmem_common_realize(dev, errp);
1137}
1138
5400c02b
MA
1139static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data)
1140{
1141 DeviceClass *dc = DEVICE_CLASS(klass);
6dc64780 1142 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
5400c02b 1143
6dc64780 1144 k->realize = ivshmem_doorbell_realize;
5400c02b
MA
1145 dc->props = ivshmem_doorbell_properties;
1146 dc->vmsd = &ivshmem_doorbell_vmsd;
1147}
1148
1149static const TypeInfo ivshmem_doorbell_info = {
1150 .name = TYPE_IVSHMEM_DOORBELL,
1151 .parent = TYPE_IVSHMEM_COMMON,
1152 .instance_size = sizeof(IVShmemState),
1153 .instance_init = ivshmem_doorbell_init,
1154 .class_init = ivshmem_doorbell_class_init,
1155};
1156
ddc85284
MA
1157static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id)
1158{
1159 IVShmemState *s = opaque;
1160 PCIDevice *pdev = PCI_DEVICE(s);
1161 int ret;
1162
1163 IVSHMEM_DPRINTF("ivshmem_load_old\n");
1164
1165 if (version_id != 0) {
1166 return -EINVAL;
1167 }
1168
1169 ret = ivshmem_pre_load(s);
1170 if (ret) {
1171 return ret;
1172 }
1173
1174 ret = pci_device_load(pdev, f);
1175 if (ret) {
1176 return ret;
1177 }
1178
1179 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
1180 msix_load(pdev, f);
1181 ivshmem_msix_vector_use(s);
1182 } else {
1183 s->intrstatus = qemu_get_be32(f);
1184 s->intrmask = qemu_get_be32(f);
1185 }
1186
1187 return 0;
1188}
1189
1190static bool test_msix(void *opaque, int version_id)
1191{
1192 IVShmemState *s = opaque;
1193
1194 return ivshmem_has_feature(s, IVSHMEM_MSI);
1195}
1196
1197static bool test_no_msix(void *opaque, int version_id)
1198{
1199 return !test_msix(opaque, version_id);
1200}
1201
1202static const VMStateDescription ivshmem_vmsd = {
1203 .name = "ivshmem",
1204 .version_id = 1,
1205 .minimum_version_id = 1,
1206 .pre_load = ivshmem_pre_load,
1207 .post_load = ivshmem_post_load,
1208 .fields = (VMStateField[]) {
1209 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1210
1211 VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix),
1212 VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix),
1213 VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix),
1214
1215 VMSTATE_END_OF_LIST()
1216 },
1217 .load_state_old = ivshmem_load_old,
1218 .minimum_version_id_old = 0
1219};
1220
1221static Property ivshmem_properties[] = {
1222 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1223 DEFINE_PROP_STRING("size", IVShmemState, sizearg),
1224 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1225 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1226 false),
1227 DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true),
1228 DEFINE_PROP_STRING("shm", IVShmemState, shmobj),
1229 DEFINE_PROP_STRING("role", IVShmemState, role),
1230 DEFINE_PROP_UINT32("use64", IVShmemState, not_legacy_32bit, 1),
1231 DEFINE_PROP_END_OF_LIST(),
1232};
1233
1234static void desugar_shm(IVShmemState *s)
1235{
1236 Object *obj;
1237 char *path;
1238
1239 obj = object_new("memory-backend-file");
1240 path = g_strdup_printf("/dev/shm/%s", s->shmobj);
1241 object_property_set_str(obj, path, "mem-path", &error_abort);
1242 g_free(path);
1243 object_property_set_int(obj, s->legacy_size, "size", &error_abort);
1244 object_property_set_bool(obj, true, "share", &error_abort);
1245 object_property_add_child(OBJECT(s), "internal-shm-backend", obj,
1246 &error_abort);
1247 user_creatable_complete(obj, &error_abort);
1248 s->hostmem = MEMORY_BACKEND(obj);
1249}
1250
1251static void ivshmem_realize(PCIDevice *dev, Error **errp)
1252{
1253 IVShmemState *s = IVSHMEM_COMMON(dev);
1254
1255 if (!qtest_enabled()) {
1256 error_report("ivshmem is deprecated, please use ivshmem-plain"
1257 " or ivshmem-doorbell instead");
1258 }
1259
30650701 1260 if (qemu_chr_fe_backend_connected(&s->server_chr) + !!s->shmobj != 1) {
13fd2cb6 1261 error_setg(errp, "You must specify either 'shm' or 'chardev'");
ddc85284
MA
1262 return;
1263 }
1264
13fd2cb6 1265 if (s->sizearg == NULL) {
ddc85284
MA
1266 s->legacy_size = 4 << 20; /* 4 MB default */
1267 } else {
f17fd4fd 1268 int ret;
f46bfdbf 1269 uint64_t size;
f17fd4fd
MA
1270
1271 ret = qemu_strtosz_MiB(s->sizearg, NULL, &size);
1272 if (ret < 0 || (size_t)size != size || !is_power_of_2(size)) {
ddc85284
MA
1273 error_setg(errp, "Invalid size %s", s->sizearg);
1274 return;
1275 }
1276 s->legacy_size = size;
1277 }
1278
1279 /* check that role is reasonable */
1280 if (s->role) {
1281 if (strncmp(s->role, "peer", 5) == 0) {
1282 s->master = ON_OFF_AUTO_OFF;
1283 } else if (strncmp(s->role, "master", 7) == 0) {
1284 s->master = ON_OFF_AUTO_ON;
1285 } else {
1286 error_setg(errp, "'role' must be 'peer' or 'master'");
1287 return;
1288 }
1289 } else {
1290 s->master = ON_OFF_AUTO_AUTO;
1291 }
1292
1293 if (s->shmobj) {
1294 desugar_shm(s);
1295 }
1296
1297 /*
1298 * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a
1299 * bald-faced lie then. But it's a backwards compatible lie.
1300 */
1301 pci_config_set_interrupt_pin(dev->config, 1);
1302
1303 ivshmem_common_realize(dev, errp);
1304}
1305
ddc85284
MA
1306static void ivshmem_class_init(ObjectClass *klass, void *data)
1307{
1308 DeviceClass *dc = DEVICE_CLASS(klass);
1309 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1310
1311 k->realize = ivshmem_realize;
1312 k->revision = 0;
1313 dc->desc = "Inter-VM shared memory (legacy)";
1314 dc->props = ivshmem_properties;
1315 dc->vmsd = &ivshmem_vmsd;
1316}
1317
1318static const TypeInfo ivshmem_info = {
1319 .name = TYPE_IVSHMEM,
1320 .parent = TYPE_IVSHMEM_COMMON,
1321 .instance_size = sizeof(IVShmemState),
ddc85284
MA
1322 .class_init = ivshmem_class_init,
1323};
1324
83f7d43a 1325static void ivshmem_register_types(void)
6cbf4c8c 1326{
5400c02b
MA
1327 type_register_static(&ivshmem_common_info);
1328 type_register_static(&ivshmem_plain_info);
1329 type_register_static(&ivshmem_doorbell_info);
39bffca2 1330 type_register_static(&ivshmem_info);
6cbf4c8c
CM
1331}
1332
83f7d43a 1333type_init(ivshmem_register_types)
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