[qemu.git] / hw / wdt_i6300esb.c

/*
 * Virtual hardware watchdog.
 *
 * Copyright (C) 2009 Red Hat Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * By Richard W.M. Jones ([email protected]).
 */

#include <inttypes.h>

#include "qemu-common.h"
#include "qemu-timer.h"
#include "watchdog.h"
#include "hw.h"
#include "pci.h"

/*#define I6300ESB_DEBUG 1*/

#ifdef I6300ESB_DEBUG
#define i6300esb_debug(fs,...) \
    fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
#else
#define i6300esb_debug(fs,...)
#endif

/* PCI configuration registers */
#define ESB_CONFIG_REG  0x60            /* Config register                   */
#define ESB_LOCK_REG    0x68            /* WDT lock register                 */

/* Memory mapped registers (offset from base address) */
#define ESB_TIMER1_REG  0x00            /* Timer1 value after each reset     */
#define ESB_TIMER2_REG  0x04            /* Timer2 value after each reset     */
#define ESB_GINTSR_REG  0x08            /* General Interrupt Status Register */
#define ESB_RELOAD_REG  0x0c            /* Reload register                   */

/* Lock register bits */
#define ESB_WDT_FUNC    (0x01 << 2)   /* Watchdog functionality            */
#define ESB_WDT_ENABLE  (0x01 << 1)   /* Enable WDT                        */
#define ESB_WDT_LOCK    (0x01 << 0)   /* Lock (nowayout)                   */

/* Config register bits */
#define ESB_WDT_REBOOT  (0x01 << 5)   /* Enable reboot on timeout          */
#define ESB_WDT_FREQ    (0x01 << 2)   /* Decrement frequency               */
#define ESB_WDT_INTTYPE (0x11 << 0)   /* Interrupt type on timer1 timeout  */

/* Reload register bits */
#define ESB_WDT_RELOAD  (0x01 << 8)    /* prevent timeout                   */

/* Magic constants */
#define ESB_UNLOCK1     0x80            /* Step 1 to unlock reset registers  */
#define ESB_UNLOCK2     0x86            /* Step 2 to unlock reset registers  */

/* Device state. */
struct I6300State {
    PCIDevice dev;
    MemoryRegion io_mem;

    int reboot_enabled;         /* "Reboot" on timer expiry.  The real action
                                 * performed depends on the -watchdog-action
                                 * param passed on QEMU command line.
                                 */
    int clock_scale;            /* Clock scale. */
#define CLOCK_SCALE_1KHZ 0
#define CLOCK_SCALE_1MHZ 1

    int int_type;               /* Interrupt type generated. */
#define INT_TYPE_IRQ 0          /* APIC 1, INT 10 */
#define INT_TYPE_SMI 2
#define INT_TYPE_DISABLED 3

    int free_run;               /* If true, reload timer on expiry. */
    int locked;                 /* If true, enabled field cannot be changed. */
    int enabled;                /* If true, watchdog is enabled. */

    QEMUTimer *timer;           /* The actual watchdog timer. */

    uint32_t timer1_preload;    /* Values preloaded into timer1, timer2. */
    uint32_t timer2_preload;
    int stage;                  /* Stage (1 or 2). */

    int unlock_state;           /* Guest writes 0x80, 0x86 to unlock the
                                 * registers, and we transition through
                                 * states 0 -> 1 -> 2 when this happens.
                                 */

    int previous_reboot_flag;   /* If the watchdog caused the previous
                                 * reboot, this flag will be set.
                                 */
};

typedef struct I6300State I6300State;

/* This function is called when the watchdog has either been enabled
 * (hence it starts counting down) or has been keep-alived.
 */
static void i6300esb_restart_timer(I6300State *d, int stage)
{
    int64_t timeout;

    if (!d->enabled)
        return;

    d->stage = stage;

    if (d->stage <= 1)
        timeout = d->timer1_preload;
    else
        timeout = d->timer2_preload;

    if (d->clock_scale == CLOCK_SCALE_1KHZ)
        timeout <<= 15;
    else
        timeout <<= 5;

    /* Get the timeout in units of ticks_per_sec. */
    timeout = get_ticks_per_sec() * timeout / 33000000;

    i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);

    qemu_mod_timer(d->timer, qemu_get_clock_ns(vm_clock) + timeout);
}

/* This is called when the guest disables the watchdog. */
static void i6300esb_disable_timer(I6300State *d)
{
    i6300esb_debug("timer disabled\n");

    qemu_del_timer(d->timer);
}

static void i6300esb_reset(DeviceState *dev)
{
    PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
    I6300State *d = DO_UPCAST(I6300State, dev, pdev);

    i6300esb_debug("I6300State = %p\n", d);

    i6300esb_disable_timer(d);

    /* NB: Don't change d->previous_reboot_flag in this function. */

    d->reboot_enabled = 1;
    d->clock_scale = CLOCK_SCALE_1KHZ;
    d->int_type = INT_TYPE_IRQ;
    d->free_run = 0;
    d->locked = 0;
    d->enabled = 0;
    d->timer1_preload = 0xfffff;
    d->timer2_preload = 0xfffff;
    d->stage = 1;
    d->unlock_state = 0;
}

/* This function is called when the watchdog expires.  Note that
 * the hardware has two timers, and so expiry happens in two stages.
 * If d->stage == 1 then we perform the first stage action (usually,
 * sending an interrupt) and then restart the timer again for the
 * second stage.  If the second stage expires then the watchdog
 * really has run out.
 */
static void i6300esb_timer_expired(void *vp)
{
    I6300State *d = vp;

    i6300esb_debug("stage %d\n", d->stage);

    if (d->stage == 1) {
        /* What to do at the end of stage 1? */
        switch (d->int_type) {
        case INT_TYPE_IRQ:
            fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
            break;
        case INT_TYPE_SMI:
            fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
            break;
        }

        /* Start the second stage. */
        i6300esb_restart_timer(d, 2);
    } else {
        /* Second stage expired, reboot for real. */
        if (d->reboot_enabled) {
            d->previous_reboot_flag = 1;
            watchdog_perform_action(); /* This reboots, exits, etc */
            i6300esb_reset(&d->dev.qdev);
        }

        /* In "free running mode" we start stage 1 again. */
        if (d->free_run)
            i6300esb_restart_timer(d, 1);
    }
}

static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
                                  uint32_t data, int len)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    int old;

    i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
        d->clock_scale =
            (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
        d->int_type = (data & ESB_WDT_INTTYPE);
    } else if (addr == ESB_LOCK_REG && len == 1) {
        if (!d->locked) {
            d->locked = (data & ESB_WDT_LOCK) != 0;
            d->free_run = (data & ESB_WDT_FUNC) != 0;
            old = d->enabled;
            d->enabled = (data & ESB_WDT_ENABLE) != 0;
            if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
                i6300esb_restart_timer(d, 1);
            else if (!d->enabled)
                i6300esb_disable_timer(d);
        }
    } else {
        pci_default_write_config(dev, addr, data, len);
    }
}

static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    uint32_t data;

    i6300esb_debug ("addr = %x, len = %d\n", addr, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        data =
            (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
            (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
            d->int_type;
        return data;
    } else if (addr == ESB_LOCK_REG && len == 1) {
        data =
            (d->free_run ? ESB_WDT_FUNC : 0) |
            (d->locked ? ESB_WDT_LOCK : 0) |
            (d->enabled ? ESB_WDT_ENABLE : 0);
        return data;
    } else {
        return pci_default_read_config(dev, addr, len);
    }
}

static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
{
    i6300esb_debug ("addr = %x\n", (int) addr);

    return 0;
}

static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
{
    uint32_t data = 0;
    I6300State *d = vp;

    i6300esb_debug("addr = %x\n", (int) addr);

    if (addr == 0xc) {
        /* The previous reboot flag is really bit 9, but there is
         * a bug in the Linux driver where it thinks it's bit 12.
         * Set both.
         */
        data = d->previous_reboot_flag ? 0x1200 : 0;
    }

    return data;
}

static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
{
    i6300esb_debug("addr = %x\n", (int) addr);

    return 0;
}

static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
}

static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0xc) {
                if ((val & 0x100) != 0)
                    /* This is the "ping" from the userspace watchdog in
                     * the guest ...
                     */
                    i6300esb_restart_timer(d, 1);

                /* Setting bit 9 resets the previous reboot flag.
                 * There's a bug in the Linux driver where it sets
                 * bit 12 instead.
                 */
                if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
                    d->previous_reboot_flag = 0;
                }
            }

            d->unlock_state = 0;
        }
    }
}

static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0)
                d->timer1_preload = val & 0xfffff;
            else if (addr == 4)
                d->timer2_preload = val & 0xfffff;

            d->unlock_state = 0;
        }
    }
}

static const MemoryRegionOps i6300esb_ops = {
    .old_mmio = {
        .read = {
            i6300esb_mem_readb,
            i6300esb_mem_readw,
            i6300esb_mem_readl,
        },
        .write = {
            i6300esb_mem_writeb,
            i6300esb_mem_writew,
            i6300esb_mem_writel,
        },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_i6300esb = {
    .name = "i6300esb_wdt",
    .version_id = sizeof(I6300State),
    .minimum_version_id = sizeof(I6300State),
    .minimum_version_id_old = sizeof(I6300State),
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, I6300State),
        VMSTATE_INT32(reboot_enabled, I6300State),
        VMSTATE_INT32(clock_scale, I6300State),
        VMSTATE_INT32(int_type, I6300State),
        VMSTATE_INT32(free_run, I6300State),
        VMSTATE_INT32(locked, I6300State),
        VMSTATE_INT32(enabled, I6300State),
        VMSTATE_TIMER(timer, I6300State),
        VMSTATE_UINT32(timer1_preload, I6300State),
        VMSTATE_UINT32(timer2_preload, I6300State),
        VMSTATE_INT32(stage, I6300State),
        VMSTATE_INT32(unlock_state, I6300State),
        VMSTATE_INT32(previous_reboot_flag, I6300State),
        VMSTATE_END_OF_LIST()
    }
};

static int i6300esb_init(PCIDevice *dev)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);

    i6300esb_debug("I6300State = %p\n", d);

    d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
    d->previous_reboot_flag = 0;

    memory_region_init_io(&d->io_mem, &i6300esb_ops, d, "i6300esb", 0x10);
    pci_register_bar(&d->dev, 0, 0, &d->io_mem);
    /* qemu_register_coalesced_mmio (addr, 0x10); ? */

    return 0;
}

static int i6300esb_exit(PCIDevice *dev)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);

    memory_region_destroy(&d->io_mem);

    return 0;
}

static WatchdogTimerModel model = {
    .wdt_name = "i6300esb",
    .wdt_description = "Intel 6300ESB",
};

static PCIDeviceInfo i6300esb_info = {
    .qdev.name    = "i6300esb",
    .qdev.size    = sizeof(I6300State),
    .qdev.vmsd    = &vmstate_i6300esb,
    .qdev.reset   = i6300esb_reset,
    .config_read  = i6300esb_config_read,
    .config_write = i6300esb_config_write,
    .init         = i6300esb_init,
    .exit         = i6300esb_exit,
    .vendor_id    = PCI_VENDOR_ID_INTEL,
    .device_id    = PCI_DEVICE_ID_INTEL_ESB_9,
    .class_id     = PCI_CLASS_SYSTEM_OTHER,
};

static void i6300esb_register_devices(void)
{
    watchdog_add_model(&model);
    pci_qdev_register(&i6300esb_info);
}

device_init(i6300esb_register_devices);
Commit	Line	Data
9dd986cc RJ	1	/*
	2	* Virtual hardware watchdog.
	3	*
	4	* Copyright (C) 2009 Red Hat Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
8167ee88	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
9dd986cc RJ	18	*
	19	* By Richard W.M. Jones ([email protected]).
	20	*/
	21
	22	#include <inttypes.h>
	23
	24	#include "qemu-common.h"
	25	#include "qemu-timer.h"
	26	#include "watchdog.h"
	27	#include "hw.h"
9dd986cc RJ	28	#include "pci.h"
	29
	30	/#define I6300ESB_DEBUG 1/
	31
	32	#ifdef I6300ESB_DEBUG
	33	#define i6300esb_debug(fs,...) \
	34	fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
	35	#else
	36	#define i6300esb_debug(fs,...)
	37	#endif
	38
9dd986cc RJ	39	/* PCI configuration registers */
	40	#define ESB_CONFIG_REG 0x60 /* Config register */
	41	#define ESB_LOCK_REG 0x68 /* WDT lock register */
	42
	43	/* Memory mapped registers (offset from base address) */
	44	#define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
	45	#define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
	46	#define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
	47	#define ESB_RELOAD_REG 0x0c /* Reload register */
	48
	49	/* Lock register bits */
	50	#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
	51	#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
	52	#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
	53
	54	/* Config register bits */
	55	#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
	56	#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
	57	#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
	58
	59	/* Reload register bits */
	60	#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
	61
	62	/* Magic constants */
	63	#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
	64	#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
	65
	66	/* Device state. */
	67	struct I6300State {
9d472d51	68	PCIDevice dev;
d9c6ebd1	69	MemoryRegion io_mem;
9dd986cc RJ	70
	71	int reboot_enabled; /* "Reboot" on timer expiry. The real action
	72	* performed depends on the -watchdog-action
	73	* param passed on QEMU command line.
	74	*/
	75	int clock_scale; /* Clock scale. */
	76	#define CLOCK_SCALE_1KHZ 0
	77	#define CLOCK_SCALE_1MHZ 1
	78
	79	int int_type; /* Interrupt type generated. */
	80	#define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */
	81	#define INT_TYPE_SMI 2
	82	#define INT_TYPE_DISABLED 3
	83
	84	int free_run; /* If true, reload timer on expiry. */
	85	int locked; /* If true, enabled field cannot be changed. */
	86	int enabled; /* If true, watchdog is enabled. */
	87
	88	QEMUTimer timer; / The actual watchdog timer. */
	89
	90	uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */
	91	uint32_t timer2_preload;
	92	int stage; /* Stage (1 or 2). */
	93
	94	int unlock_state; /* Guest writes 0x80, 0x86 to unlock the
	95	* registers, and we transition through
	96	* states 0 -> 1 -> 2 when this happens.
	97	*/
	98
	99	int previous_reboot_flag; /* If the watchdog caused the previous
	100	* reboot, this flag will be set.
	101	*/
	102	};
	103
	104	typedef struct I6300State I6300State;
	105
	106	/* This function is called when the watchdog has either been enabled
	107	* (hence it starts counting down) or has been keep-alived.
	108	*/
	109	static void i6300esb_restart_timer(I6300State *d, int stage)
	110	{
	111	int64_t timeout;
	112
	113	if (!d->enabled)
	114	return;
	115
	116	d->stage = stage;
	117
	118	if (d->stage <= 1)
	119	timeout = d->timer1_preload;
	120	else
	121	timeout = d->timer2_preload;
	122
	123	if (d->clock_scale == CLOCK_SCALE_1KHZ)
	124	timeout <<= 15;
	125	else
	126	timeout <<= 5;
	127
	128	/* Get the timeout in units of ticks_per_sec. */
6ee093c9	129	timeout = get_ticks_per_sec() * timeout / 33000000;
9dd986cc RJ	130
	131	i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
	132
74475455	133	qemu_mod_timer(d->timer, qemu_get_clock_ns(vm_clock) + timeout);
9dd986cc RJ	134	}
	135
	136	/* This is called when the guest disables the watchdog. */
	137	static void i6300esb_disable_timer(I6300State *d)
	138	{
	139	i6300esb_debug("timer disabled\n");
	140
	141	qemu_del_timer(d->timer);
	142	}
	143
fa82e9c3	144	static void i6300esb_reset(DeviceState *dev)
9dd986cc	145	{
fa82e9c3 BK	146	PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
	147	I6300State *d = DO_UPCAST(I6300State, dev, pdev);
	148
	149	i6300esb_debug("I6300State = %p\n", d);
	150
9dd986cc	151	i6300esb_disable_timer(d);
fa82e9c3	152
36888c63 RJ	153	/* NB: Don't change d->previous_reboot_flag in this function. */
36888c63 RJ	154
fa82e9c3 BK	155	d->reboot_enabled = 1;
	156	d->clock_scale = CLOCK_SCALE_1KHZ;
	157	d->int_type = INT_TYPE_IRQ;
	158	d->free_run = 0;
	159	d->locked = 0;
	160	d->enabled = 0;
	161	d->timer1_preload = 0xfffff;
	162	d->timer2_preload = 0xfffff;
	163	d->stage = 1;
	164	d->unlock_state = 0;
9dd986cc RJ	165	}
	166
	167	/* This function is called when the watchdog expires. Note that
	168	* the hardware has two timers, and so expiry happens in two stages.
	169	* If d->stage == 1 then we perform the first stage action (usually,
	170	* sending an interrupt) and then restart the timer again for the
	171	* second stage. If the second stage expires then the watchdog
	172	* really has run out.
	173	*/
	174	static void i6300esb_timer_expired(void *vp)
	175	{
4f423e81	176	I6300State *d = vp;
9dd986cc RJ	177
	178	i6300esb_debug("stage %d\n", d->stage);
	179
	180	if (d->stage == 1) {
	181	/* What to do at the end of stage 1? */
	182	switch (d->int_type) {
	183	case INT_TYPE_IRQ:
	184	fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
	185	break;
	186	case INT_TYPE_SMI:
	187	fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
	188	break;
	189	}
	190
	191	/* Start the second stage. */
	192	i6300esb_restart_timer(d, 2);
	193	} else {
	194	/* Second stage expired, reboot for real. */
	195	if (d->reboot_enabled) {
	196	d->previous_reboot_flag = 1;
	197	watchdog_perform_action(); /* This reboots, exits, etc */
36888c63	198	i6300esb_reset(&d->dev.qdev);
9dd986cc RJ	199	}
	200
	201	/* In "free running mode" we start stage 1 again. */
	202	if (d->free_run)
	203	i6300esb_restart_timer(d, 1);
	204	}
	205	}
	206
	207	static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
	208	uint32_t data, int len)
	209	{
d03f09cc	210	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	211	int old;
	212
	213	i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
	214
	215	if (addr == ESB_CONFIG_REG && len == 2) {
	216	d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
	217	d->clock_scale =
	218	(data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
	219	d->int_type = (data & ESB_WDT_INTTYPE);
	220	} else if (addr == ESB_LOCK_REG && len == 1) {
	221	if (!d->locked) {
	222	d->locked = (data & ESB_WDT_LOCK) != 0;
	223	d->free_run = (data & ESB_WDT_FUNC) != 0;
	224	old = d->enabled;
	225	d->enabled = (data & ESB_WDT_ENABLE) != 0;
	226	if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
	227	i6300esb_restart_timer(d, 1);
	228	else if (!d->enabled)
	229	i6300esb_disable_timer(d);
	230	}
	231	} else {
	232	pci_default_write_config(dev, addr, data, len);
	233	}
	234	}
	235
	236	static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
	237	{
d03f09cc	238	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	239	uint32_t data;
	240
	241	i6300esb_debug ("addr = %x, len = %d\n", addr, len);
	242
	243	if (addr == ESB_CONFIG_REG && len == 2) {
	244	data =
	245	(d->reboot_enabled ? 0 : ESB_WDT_REBOOT) \|
	246	(d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) \|
	247	d->int_type;
	248	return data;
	249	} else if (addr == ESB_LOCK_REG && len == 1) {
	250	data =
	251	(d->free_run ? ESB_WDT_FUNC : 0) \|
	252	(d->locked ? ESB_WDT_LOCK : 0) \|
	253	(d->enabled ? ESB_WDT_ENABLE : 0);
	254	return data;
	255	} else {
	256	return pci_default_read_config(dev, addr, len);
	257	}
	258	}
	259
c227f099	260	static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
9dd986cc RJ	261	{
	262	i6300esb_debug ("addr = %x\n", (int) addr);
	263
	264	return 0;
	265	}
	266
c227f099	267	static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
9dd986cc RJ	268	{
9dd986cc RJ	269	uint32_t data = 0;
4f423e81	270	I6300State *d = vp;
9dd986cc RJ	271
	272	i6300esb_debug("addr = %x\n", (int) addr);
	273
	274	if (addr == 0xc) {
	275	/* The previous reboot flag is really bit 9, but there is
	276	* a bug in the Linux driver where it thinks it's bit 12.
	277	* Set both.
	278	*/
	279	data = d->previous_reboot_flag ? 0x1200 : 0;
	280	}
	281
	282	return data;
	283	}
	284
c227f099	285	static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
9dd986cc RJ	286	{
	287	i6300esb_debug("addr = %x\n", (int) addr);
	288
	289	return 0;
	290	}
	291
c227f099	292	static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	293	{
4f423e81	294	I6300State *d = vp;
9dd986cc RJ	295
	296	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	297
	298	if (addr == 0xc && val == 0x80)
	299	d->unlock_state = 1;
	300	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	301	d->unlock_state = 2;
	302	}
	303
c227f099	304	static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	305	{
4f423e81	306	I6300State *d = vp;
9dd986cc RJ	307
	308	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	309
	310	if (addr == 0xc && val == 0x80)
	311	d->unlock_state = 1;
	312	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	313	d->unlock_state = 2;
	314	else {
	315	if (d->unlock_state == 2) {
	316	if (addr == 0xc) {
	317	if ((val & 0x100) != 0)
	318	/* This is the "ping" from the userspace watchdog in
	319	* the guest ...
	320	*/
	321	i6300esb_restart_timer(d, 1);
	322
	323	/* Setting bit 9 resets the previous reboot flag.
	324	* There's a bug in the Linux driver where it sets
	325	* bit 12 instead.
	326	*/
	327	if ((val & 0x200) != 0 \|\| (val & 0x1000) != 0) {
	328	d->previous_reboot_flag = 0;
	329	}
	330	}
	331
	332	d->unlock_state = 0;
	333	}
	334	}
	335	}
	336
c227f099	337	static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	338	{
4f423e81	339	I6300State *d = vp;
9dd986cc RJ	340
	341	i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
	342
	343	if (addr == 0xc && val == 0x80)
	344	d->unlock_state = 1;
	345	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	346	d->unlock_state = 2;
	347	else {
	348	if (d->unlock_state == 2) {
	349	if (addr == 0)
	350	d->timer1_preload = val & 0xfffff;
	351	else if (addr == 4)
	352	d->timer2_preload = val & 0xfffff;
	353
	354	d->unlock_state = 0;
	355	}
	356	}
	357	}
	358
d9c6ebd1 AK	359	static const MemoryRegionOps i6300esb_ops = {
	360	.old_mmio = {
	361	.read = {
	362	i6300esb_mem_readb,
	363	i6300esb_mem_readw,
	364	i6300esb_mem_readl,
	365	},
	366	.write = {
	367	i6300esb_mem_writeb,
	368	i6300esb_mem_writew,
	369	i6300esb_mem_writel,
	370	},
	371	},
	372	.endianness = DEVICE_NATIVE_ENDIAN,
	373	};
	374
95c90a0e JQ	375	static const VMStateDescription vmstate_i6300esb = {
	376	.name = "i6300esb_wdt",
	377	.version_id = sizeof(I6300State),
	378	.minimum_version_id = sizeof(I6300State),
	379	.minimum_version_id_old = sizeof(I6300State),
	380	.fields = (VMStateField []) {
	381	VMSTATE_PCI_DEVICE(dev, I6300State),
	382	VMSTATE_INT32(reboot_enabled, I6300State),
	383	VMSTATE_INT32(clock_scale, I6300State),
	384	VMSTATE_INT32(int_type, I6300State),
	385	VMSTATE_INT32(free_run, I6300State),
	386	VMSTATE_INT32(locked, I6300State),
	387	VMSTATE_INT32(enabled, I6300State),
	388	VMSTATE_TIMER(timer, I6300State),
	389	VMSTATE_UINT32(timer1_preload, I6300State),
	390	VMSTATE_UINT32(timer2_preload, I6300State),
	391	VMSTATE_INT32(stage, I6300State),
	392	VMSTATE_INT32(unlock_state, I6300State),
	393	VMSTATE_INT32(previous_reboot_flag, I6300State),
	394	VMSTATE_END_OF_LIST()
	395	}
	396	};
9dd986cc	397
81a322d4	398	static int i6300esb_init(PCIDevice *dev)
9dd986cc	399	{
d03f09cc	400	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc	401
fa82e9c3 BK	402	i6300esb_debug("I6300State = %p\n", d);
fa82e9c3 BK	403
74475455	404	d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
36888c63	405	d->previous_reboot_flag = 0;
9dd986cc	406
d9c6ebd1	407	memory_region_init_io(&d->io_mem, &i6300esb_ops, d, "i6300esb", 0x10);
e824b2cc	408	pci_register_bar(&d->dev, 0, 0, &d->io_mem);
22f3647b	409	/* qemu_register_coalesced_mmio (addr, 0x10); ? */
9dd986cc	410
81a322d4	411	return 0;
9dd986cc RJ	412	}
9dd986cc RJ	413
d9c6ebd1 AK	414	static int i6300esb_exit(PCIDevice *dev)
	415	{
	416	I6300State *d = DO_UPCAST(I6300State, dev, dev);
	417
	418	memory_region_destroy(&d->io_mem);
	419
	420	return 0;
	421	}
	422
9dd986cc RJ	423	static WatchdogTimerModel model = {
	424	.wdt_name = "i6300esb",
	425	.wdt_description = "Intel 6300ESB",
9dd986cc RJ	426	};
9dd986cc RJ	427
09aaa160 MA	428	static PCIDeviceInfo i6300esb_info = {
	429	.qdev.name = "i6300esb",
	430	.qdev.size = sizeof(I6300State),
be73cfe2	431	.qdev.vmsd = &vmstate_i6300esb,
fa82e9c3	432	.qdev.reset = i6300esb_reset,
09aaa160 MA	433	.config_read = i6300esb_config_read,
	434	.config_write = i6300esb_config_write,
	435	.init = i6300esb_init,
d9c6ebd1	436	.exit = i6300esb_exit,
24b856ca IY	437	.vendor_id = PCI_VENDOR_ID_INTEL,
	438	.device_id = PCI_DEVICE_ID_INTEL_ESB_9,
	439	.class_id = PCI_CLASS_SYSTEM_OTHER,
09aaa160 MA	440	};
	441
	442	static void i6300esb_register_devices(void)
9dd986cc RJ	443	{
9dd986cc RJ	444	watchdog_add_model(&model);
09aaa160	445	pci_qdev_register(&i6300esb_info);
9dd986cc	446	}
09aaa160 MA	447
09aaa160 MA	448	device_init(i6300esb_register_devices);