[qemu.git] / hw / ide / microdrive.c

/*
 * QEMU IDE Emulation: microdrive (CF / PCMCIA)
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/i386/pc.h>
#include <hw/pcmcia.h>
#include "block/block.h"
#include "sysemu/dma.h"

#include <hw/ide/internal.h>

#define TYPE_MICRODRIVE "microdrive"
#define MICRODRIVE(obj) OBJECT_CHECK(MicroDriveState, (obj), TYPE_MICRODRIVE)

/***********************************************************/
/* CF-ATA Microdrive */

#define METADATA_SIZE	0x20

/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface.  */

typedef struct MicroDriveState {
    /*< private >*/
    PCMCIACardState parent_obj;
    /*< public >*/

    IDEBus bus;
    uint32_t attr_base;
    uint32_t io_base;

    /* Card state */
    uint8_t opt;
    uint8_t stat;
    uint8_t pins;

    uint8_t ctrl;
    uint16_t io;
    uint8_t cycle;
} MicroDriveState;

/* Register bitfields */
enum md_opt {
    OPT_MODE_MMAP	= 0,
    OPT_MODE_IOMAP16	= 1,
    OPT_MODE_IOMAP1	= 2,
    OPT_MODE_IOMAP2	= 3,
    OPT_MODE		= 0x3f,
    OPT_LEVIREQ		= 0x40,
    OPT_SRESET		= 0x80,
};
enum md_cstat {
    STAT_INT		= 0x02,
    STAT_PWRDWN		= 0x04,
    STAT_XE		= 0x10,
    STAT_IOIS8		= 0x20,
    STAT_SIGCHG		= 0x40,
    STAT_CHANGED	= 0x80,
};
enum md_pins {
    PINS_MRDY		= 0x02,
    PINS_CRDY		= 0x20,
};
enum md_ctrl {
    CTRL_IEN		= 0x02,
    CTRL_SRST		= 0x04,
};

static inline void md_interrupt_update(MicroDriveState *s)
{
    PCMCIACardState *card = PCMCIA_CARD(s);

    if (card->slot == NULL) {
        return;
    }

    qemu_set_irq(card->slot->irq,
                    !(s->stat & STAT_INT) &&	/* Inverted */
                    !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
                    !(s->opt & OPT_SRESET));
}

static void md_set_irq(void *opaque, int irq, int level)
{
    MicroDriveState *s = opaque;

    if (level) {
        s->stat |= STAT_INT;
    } else {
        s->stat &= ~STAT_INT;
    }

    md_interrupt_update(s);
}

static void md_reset(DeviceState *dev)
{
    MicroDriveState *s = MICRODRIVE(dev);

    s->opt = OPT_MODE_MMAP;
    s->stat = 0;
    s->pins = 0;
    s->cycle = 0;
    s->ctrl = 0;
    ide_bus_reset(&s->bus);
}

static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at)
{
    MicroDriveState *s = MICRODRIVE(card);
    PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);

    if (at < s->attr_base) {
        if (at < pcc->cis_len) {
            return pcc->cis[at];
        } else {
            return 0x00;
        }
    }

    at -= s->attr_base;

    switch (at) {
    case 0x00:	/* Configuration Option Register */
        return s->opt;
    case 0x02:	/* Card Configuration Status Register */
        if (s->ctrl & CTRL_IEN) {
            return s->stat & ~STAT_INT;
        } else {
            return s->stat;
        }
    case 0x04:	/* Pin Replacement Register */
        return (s->pins & PINS_CRDY) | 0x0c;
    case 0x06:	/* Socket and Copy Register */
        return 0x00;
#ifdef VERBOSE
    default:
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
#endif
    }

    return 0;
}

static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
{
    MicroDriveState *s = MICRODRIVE(card);

    at -= s->attr_base;

    switch (at) {
    case 0x00:	/* Configuration Option Register */
        s->opt = value & 0xcf;
        if (value & OPT_SRESET) {
            device_reset(DEVICE(s));
        }
        md_interrupt_update(s);
        break;
    case 0x02:	/* Card Configuration Status Register */
        if ((s->stat ^ value) & STAT_PWRDWN) {
            s->pins |= PINS_CRDY;
        }
        s->stat &= 0x82;
        s->stat |= value & 0x74;
        md_interrupt_update(s);
        /* Word 170 in Identify Device must be equal to STAT_XE */
        break;
    case 0x04:	/* Pin Replacement Register */
        s->pins &= PINS_CRDY;
        s->pins |= value & PINS_MRDY;
        break;
    case 0x06:	/* Socket and Copy Register */
        break;
    default:
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
    }
}

static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
{
    MicroDriveState *s = MICRODRIVE(card);
    IDEState *ifs;
    uint16_t ret;
    at -= s->io_base;

    switch (s->opt & OPT_MODE) {
    case OPT_MODE_MMAP:
        if ((at & ~0x3ff) == 0x400) {
            at = 0;
        }
        break;
    case OPT_MODE_IOMAP16:
        at &= 0xf;
        break;
    case OPT_MODE_IOMAP1:
        if ((at & ~0xf) == 0x3f0) {
            at -= 0x3e8;
        } else if ((at & ~0xf) == 0x1f0) {
            at -= 0x1f0;
        }
        break;
    case OPT_MODE_IOMAP2:
        if ((at & ~0xf) == 0x370) {
            at -= 0x368;
        } else if ((at & ~0xf) == 0x170) {
            at -= 0x170;
        }
    }

    switch (at) {
    case 0x0:	/* Even RD Data */
    case 0x8:
        return ide_data_readw(&s->bus, 0);

        /* TODO: 8-bit accesses */
        if (s->cycle) {
            ret = s->io >> 8;
        } else {
            s->io = ide_data_readw(&s->bus, 0);
            ret = s->io & 0xff;
        }
        s->cycle = !s->cycle;
        return ret;
    case 0x9:	/* Odd RD Data */
        return s->io >> 8;
    case 0xd:	/* Error */
        return ide_ioport_read(&s->bus, 0x1);
    case 0xe:	/* Alternate Status */
        ifs = idebus_active_if(&s->bus);
        if (ifs->bs) {
            return ifs->status;
        } else {
            return 0;
        }
    case 0xf:	/* Device Address */
        ifs = idebus_active_if(&s->bus);
        return 0xc2 | ((~ifs->select << 2) & 0x3c);
    default:
        return ide_ioport_read(&s->bus, at);
    }

    return 0;
}

static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
{
    MicroDriveState *s = MICRODRIVE(card);
    at -= s->io_base;

    switch (s->opt & OPT_MODE) {
    case OPT_MODE_MMAP:
        if ((at & ~0x3ff) == 0x400) {
            at = 0;
        }
        break;
    case OPT_MODE_IOMAP16:
        at &= 0xf;
        break;
    case OPT_MODE_IOMAP1:
        if ((at & ~0xf) == 0x3f0) {
            at -= 0x3e8;
        } else if ((at & ~0xf) == 0x1f0) {
            at -= 0x1f0;
        }
        break;
    case OPT_MODE_IOMAP2:
        if ((at & ~0xf) == 0x370) {
            at -= 0x368;
        } else if ((at & ~0xf) == 0x170) {
            at -= 0x170;
        }
    }

    switch (at) {
    case 0x0:	/* Even WR Data */
    case 0x8:
        ide_data_writew(&s->bus, 0, value);
        break;

        /* TODO: 8-bit accesses */
        if (s->cycle) {
            ide_data_writew(&s->bus, 0, s->io | (value << 8));
        } else {
            s->io = value & 0xff;
        }
        s->cycle = !s->cycle;
        break;
    case 0x9:
        s->io = value & 0xff;
        s->cycle = !s->cycle;
        break;
    case 0xd:	/* Features */
        ide_ioport_write(&s->bus, 0x1, value);
        break;
    case 0xe:	/* Device Control */
        s->ctrl = value;
        if (value & CTRL_SRST) {
            device_reset(DEVICE(s));
        }
        md_interrupt_update(s);
        break;
    default:
        if (s->stat & STAT_PWRDWN) {
            s->pins |= PINS_CRDY;
            s->stat &= ~STAT_PWRDWN;
        }
        ide_ioport_write(&s->bus, at, value);
    }
}

static const VMStateDescription vmstate_microdrive = {
    .name = "microdrive",
    .version_id = 3,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(opt, MicroDriveState),
        VMSTATE_UINT8(stat, MicroDriveState),
        VMSTATE_UINT8(pins, MicroDriveState),
        VMSTATE_UINT8(ctrl, MicroDriveState),
        VMSTATE_UINT16(io, MicroDriveState),
        VMSTATE_UINT8(cycle, MicroDriveState),
        VMSTATE_IDE_BUS(bus, MicroDriveState),
        VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
        VMSTATE_END_OF_LIST()
    }
};

static const uint8_t dscm1xxxx_cis[0x14a] = {
    [0x000] = CISTPL_DEVICE,	/* 5V Device Information */
    [0x002] = 0x03,		/* Tuple length = 4 bytes */
    [0x004] = 0xdb,		/* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
    [0x006] = 0x01,		/* Size = 2K bytes */
    [0x008] = CISTPL_ENDMARK,

    [0x00a] = CISTPL_DEVICE_OC,	/* Additional Device Information */
    [0x00c] = 0x04,		/* Tuple length = 4 byest */
    [0x00e] = 0x03,		/* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
    [0x010] = 0xdb,		/* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
    [0x012] = 0x01,		/* Size = 2K bytes */
    [0x014] = CISTPL_ENDMARK,

    [0x016] = CISTPL_JEDEC_C,	/* JEDEC ID */
    [0x018] = 0x02,		/* Tuple length = 2 bytes */
    [0x01a] = 0xdf,		/* PC Card ATA with no Vpp required */
    [0x01c] = 0x01,

    [0x01e] = CISTPL_MANFID,	/* Manufacture ID */
    [0x020] = 0x04,		/* Tuple length = 4 bytes */
    [0x022] = 0xa4,		/* TPLMID_MANF = 00a4 (IBM) */
    [0x024] = 0x00,
    [0x026] = 0x00,		/* PLMID_CARD = 0000 */
    [0x028] = 0x00,

    [0x02a] = CISTPL_VERS_1,	/* Level 1 Version */
    [0x02c] = 0x12,		/* Tuple length = 23 bytes */
    [0x02e] = 0x04,		/* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
    [0x030] = 0x01,		/* Minor Version = 1 */
    [0x032] = 'I',
    [0x034] = 'B',
    [0x036] = 'M',
    [0x038] = 0x00,
    [0x03a] = 'm',
    [0x03c] = 'i',
    [0x03e] = 'c',
    [0x040] = 'r',
    [0x042] = 'o',
    [0x044] = 'd',
    [0x046] = 'r',
    [0x048] = 'i',
    [0x04a] = 'v',
    [0x04c] = 'e',
    [0x04e] = 0x00,
    [0x050] = CISTPL_ENDMARK,

    [0x052] = CISTPL_FUNCID,	/* Function ID */
    [0x054] = 0x02,		/* Tuple length = 2 bytes */
    [0x056] = 0x04,		/* TPLFID_FUNCTION = Fixed Disk */
    [0x058] = 0x01,		/* TPLFID_SYSINIT: POST = 1, ROM = 0 */

    [0x05a] = CISTPL_FUNCE,	/* Function Extension */
    [0x05c] = 0x02,		/* Tuple length = 2 bytes */
    [0x05e] = 0x01,		/* TPLFE_TYPE = Disk Device Interface */
    [0x060] = 0x01,		/* TPLFE_DATA = PC Card ATA Interface */

    [0x062] = CISTPL_FUNCE,	/* Function Extension */
    [0x064] = 0x03,		/* Tuple length = 3 bytes */
    [0x066] = 0x02,		/* TPLFE_TYPE = Basic PC Card ATA Interface */
    [0x068] = 0x08,		/* TPLFE_DATA: Rotating, Unique, Single */
    [0x06a] = 0x0f,		/* TPLFE_DATA: Sleep, Standby, Idle, Auto */

    [0x06c] = CISTPL_CONFIG,	/* Configuration */
    [0x06e] = 0x05,		/* Tuple length = 5 bytes */
    [0x070] = 0x01,		/* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
    [0x072] = 0x07,		/* TPCC_LAST = 7 */
    [0x074] = 0x00,		/* TPCC_RADR = 0200 */
    [0x076] = 0x02,
    [0x078] = 0x0f,		/* TPCC_RMSK = 200, 202, 204, 206 */

    [0x07a] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x07c] = 0x0b,		/* Tuple length = 11 bytes */
    [0x07e] = 0xc0,		/* TPCE_INDX = Memory Mode, Default, Iface */
    [0x080] = 0xc0,		/* TPCE_IF = Memory, no BVDs, no WP, READY */
    [0x082] = 0xa1,		/* TPCE_FS = Vcc only, no I/O, Memory, Misc */
    [0x084] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x086] = 0x55,		/* NomV: 5.0 V */
    [0x088] = 0x4d,		/* MinV: 4.5 V */
    [0x08a] = 0x5d,		/* MaxV: 5.5 V */
    [0x08c] = 0x4e,		/* Peakl: 450 mA */
    [0x08e] = 0x08,		/* TPCE_MS = 1 window, 1 byte, Host address */
    [0x090] = 0x00,		/* Window descriptor: Window length = 0 */
    [0x092] = 0x20,		/* TPCE_MI: support power down mode, RW */

    [0x094] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x096] = 0x06,		/* Tuple length = 6 bytes */
    [0x098] = 0x00,		/* TPCE_INDX = Memory Mode, no Default */
    [0x09a] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x09c] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x09e] = 0xb5,		/* NomV: 3.3 V */
    [0x0a0] = 0x1e,
    [0x0a2] = 0x3e,		/* Peakl: 350 mA */

    [0x0a4] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0a6] = 0x0d,		/* Tuple length = 13 bytes */
    [0x0a8] = 0xc1,		/* TPCE_INDX = I/O and Memory Mode, Default */
    [0x0aa] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x0ac] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x0ae] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x0b0] = 0x55,		/* NomV: 5.0 V */
    [0x0b2] = 0x4d,		/* MinV: 4.5 V */
    [0x0b4] = 0x5d,		/* MaxV: 5.5 V */
    [0x0b6] = 0x4e,		/* Peakl: 450 mA */
    [0x0b8] = 0x64,		/* TPCE_IO = 16-byte boundary, 16/8 accesses */
    [0x0ba] = 0xf0,		/* TPCE_IR =  MASK, Level, Pulse, Share */
    [0x0bc] = 0xff,		/* IRQ0..IRQ7 supported */
    [0x0be] = 0xff,		/* IRQ8..IRQ15 supported */
    [0x0c0] = 0x20,		/* TPCE_MI = support power down mode */

    [0x0c2] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0c4] = 0x06,		/* Tuple length = 6 bytes */
    [0x0c6] = 0x01,		/* TPCE_INDX = I/O and Memory Mode */
    [0x0c8] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x0ca] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x0cc] = 0xb5,		/* NomV: 3.3 V */
    [0x0ce] = 0x1e,
    [0x0d0] = 0x3e,		/* Peakl: 350 mA */

    [0x0d2] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0d4] = 0x12,		/* Tuple length = 18 bytes */
    [0x0d6] = 0xc2,		/* TPCE_INDX = I/O Primary Mode */
    [0x0d8] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x0da] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x0dc] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x0de] = 0x55,		/* NomV: 5.0 V */
    [0x0e0] = 0x4d,		/* MinV: 4.5 V */
    [0x0e2] = 0x5d,		/* MaxV: 5.5 V */
    [0x0e4] = 0x4e,		/* Peakl: 450 mA */
    [0x0e6] = 0xea,		/* TPCE_IO = 1K boundary, 16/8 access, Range */
    [0x0e8] = 0x61,		/* Range: 2 fields, 2 bytes addr, 1 byte len */
    [0x0ea] = 0xf0,		/* Field 1 address = 0x01f0 */
    [0x0ec] = 0x01,
    [0x0ee] = 0x07,		/* Address block length = 8 */
    [0x0f0] = 0xf6,		/* Field 2 address = 0x03f6 */
    [0x0f2] = 0x03,
    [0x0f4] = 0x01,		/* Address block length = 2 */
    [0x0f6] = 0xee,		/* TPCE_IR = IRQ E, Level, Pulse, Share */
    [0x0f8] = 0x20,		/* TPCE_MI = support power down mode */

    [0x0fa] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0fc] = 0x06,		/* Tuple length = 6 bytes */
    [0x0fe] = 0x02,		/* TPCE_INDX = I/O Primary Mode, no Default */
    [0x100] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x102] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x104] = 0xb5,		/* NomV: 3.3 V */
    [0x106] = 0x1e,
    [0x108] = 0x3e,		/* Peakl: 350 mA */

    [0x10a] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x10c] = 0x12,		/* Tuple length = 18 bytes */
    [0x10e] = 0xc3,		/* TPCE_INDX = I/O Secondary Mode, Default */
    [0x110] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x112] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x114] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x116] = 0x55,		/* NomV: 5.0 V */
    [0x118] = 0x4d,		/* MinV: 4.5 V */
    [0x11a] = 0x5d,		/* MaxV: 5.5 V */
    [0x11c] = 0x4e,		/* Peakl: 450 mA */
    [0x11e] = 0xea,		/* TPCE_IO = 1K boundary, 16/8 access, Range */
    [0x120] = 0x61,		/* Range: 2 fields, 2 byte addr, 1 byte len */
    [0x122] = 0x70,		/* Field 1 address = 0x0170 */
    [0x124] = 0x01,
    [0x126] = 0x07,		/* Address block length = 8 */
    [0x128] = 0x76,		/* Field 2 address = 0x0376 */
    [0x12a] = 0x03,
    [0x12c] = 0x01,		/* Address block length = 2 */
    [0x12e] = 0xee,		/* TPCE_IR = IRQ E, Level, Pulse, Share */
    [0x130] = 0x20,		/* TPCE_MI = support power down mode */

    [0x132] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x134] = 0x06,		/* Tuple length = 6 bytes */
    [0x136] = 0x03,		/* TPCE_INDX = I/O Secondary Mode */
    [0x138] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x13a] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x13c] = 0xb5,		/* NomV: 3.3 V */
    [0x13e] = 0x1e,
    [0x140] = 0x3e,		/* Peakl: 350 mA */

    [0x142] = CISTPL_NO_LINK,	/* No Link */
    [0x144] = 0x00,		/* Tuple length = 0 bytes */

    [0x146] = CISTPL_END,	/* Tuple End */
};

#define TYPE_DSCM1XXXX "dscm1xxxx"

static int dscm1xxxx_attach(PCMCIACardState *card)
{
    MicroDriveState *md = MICRODRIVE(card);
    PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);

    md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
    md->io_base = 0x0;

    device_reset(DEVICE(md));
    md_interrupt_update(md);

    card->slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
    return 0;
}

static int dscm1xxxx_detach(PCMCIACardState *card)
{
    MicroDriveState *md = MICRODRIVE(card);

    device_reset(DEVICE(md));
    return 0;
}

PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo)
{
    MicroDriveState *md;

    md = MICRODRIVE(object_new(TYPE_DSCM1XXXX));
    qdev_init_nofail(DEVICE(md));

    if (dinfo != NULL) {
        ide_create_drive(&md->bus, 0, dinfo);
    }
    md->bus.ifs[0].drive_kind = IDE_CFATA;
    md->bus.ifs[0].mdata_size = METADATA_SIZE;
    md->bus.ifs[0].mdata_storage = g_malloc0(METADATA_SIZE);

    return PCMCIA_CARD(md);
}

static void dscm1xxxx_class_init(ObjectClass *oc, void *data)
{
    PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);

    pcc->cis = dscm1xxxx_cis;
    pcc->cis_len = sizeof(dscm1xxxx_cis);

    pcc->attach = dscm1xxxx_attach;
    pcc->detach = dscm1xxxx_detach;
}

static const TypeInfo dscm1xxxx_type_info = {
    .name = TYPE_DSCM1XXXX,
    .parent = TYPE_MICRODRIVE,
    .class_init = dscm1xxxx_class_init,
};

static void microdrive_realize(DeviceState *dev, Error **errp)
{
    MicroDriveState *md = MICRODRIVE(dev);

    ide_init2(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
}

static void microdrive_init(Object *obj)
{
    MicroDriveState *md = MICRODRIVE(obj);

    ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
}

static void microdrive_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);

    pcc->attr_read = md_attr_read;
    pcc->attr_write = md_attr_write;
    pcc->common_read = md_common_read;
    pcc->common_write = md_common_write;
    pcc->io_read = md_common_read;
    pcc->io_write = md_common_write;

    dc->realize = microdrive_realize;
    dc->reset = md_reset;
    dc->vmsd = &vmstate_microdrive;
}

static const TypeInfo microdrive_type_info = {
    .name = TYPE_MICRODRIVE,
    .parent = TYPE_PCMCIA_CARD,
    .instance_size = sizeof(MicroDriveState),
    .instance_init = microdrive_init,
    .abstract = true,
    .class_init = microdrive_class_init,
};

static void microdrive_register_types(void)
{
    type_register_static(&microdrive_type_info);
    type_register_static(&dscm1xxxx_type_info);
}

type_init(microdrive_register_types)
Commit	Line	Data
3f221c8d GH	1	/*
	2	* QEMU IDE Emulation: microdrive (CF / PCMCIA)
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787	25	#include <hw/hw.h>
0d09e41a	26	#include <hw/i386/pc.h>
59f2a787	27	#include <hw/pcmcia.h>
737e150e	28	#include "block/block.h"
9c17d615	29	#include "sysemu/dma.h"
59f2a787 GH	30
59f2a787 GH	31	#include <hw/ide/internal.h>
3f221c8d	32
d1f2c96a AF	33	#define TYPE_MICRODRIVE "microdrive"
	34	#define MICRODRIVE(obj) OBJECT_CHECK(MicroDriveState, (obj), TYPE_MICRODRIVE)
	35
3f221c8d GH	36	/***********************************************************/
	37	/* CF-ATA Microdrive */
	38
	39	#define METADATA_SIZE 0x20
	40
	41	/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
d1f2c96a AF	42
	43	typedef struct MicroDriveState {
	44	/< private >/
	45	PCMCIACardState parent_obj;
	46	/< public >/
	47
3f221c8d	48	IDEBus bus;
3f221c8d GH	49	uint32_t attr_base;
	50	uint32_t io_base;
	51
	52	/* Card state */
	53	uint8_t opt;
	54	uint8_t stat;
	55	uint8_t pins;
	56
	57	uint8_t ctrl;
	58	uint16_t io;
8a72f380	59	uint8_t cycle;
3f221c8d GH	60	} MicroDriveState;
	61
	62	/* Register bitfields */
	63	enum md_opt {
	64	OPT_MODE_MMAP = 0,
	65	OPT_MODE_IOMAP16 = 1,
	66	OPT_MODE_IOMAP1 = 2,
	67	OPT_MODE_IOMAP2 = 3,
	68	OPT_MODE = 0x3f,
	69	OPT_LEVIREQ = 0x40,
	70	OPT_SRESET = 0x80,
	71	};
	72	enum md_cstat {
	73	STAT_INT = 0x02,
	74	STAT_PWRDWN = 0x04,
	75	STAT_XE = 0x10,
	76	STAT_IOIS8 = 0x20,
	77	STAT_SIGCHG = 0x40,
	78	STAT_CHANGED = 0x80,
	79	};
	80	enum md_pins {
	81	PINS_MRDY = 0x02,
	82	PINS_CRDY = 0x20,
	83	};
	84	enum md_ctrl {
	85	CTRL_IEN = 0x02,
	86	CTRL_SRST = 0x04,
	87	};
	88
	89	static inline void md_interrupt_update(MicroDriveState *s)
	90	{
d1f2c96a AF	91	PCMCIACardState *card = PCMCIA_CARD(s);
	92
	93	if (card->slot == NULL) {
3f221c8d	94	return;
d1f2c96a	95	}
3f221c8d	96
d1f2c96a	97	qemu_set_irq(card->slot->irq,
3f221c8d GH	98	!(s->stat & STAT_INT) && /* Inverted */
	99	!(s->ctrl & (CTRL_IEN \| CTRL_SRST)) &&
	100	!(s->opt & OPT_SRESET));
	101	}
	102
	103	static void md_set_irq(void *opaque, int irq, int level)
	104	{
18c0fb30	105	MicroDriveState *s = opaque;
a6cb20fc AF	106
a6cb20fc AF	107	if (level) {
3f221c8d	108	s->stat \|= STAT_INT;
a6cb20fc	109	} else {
3f221c8d	110	s->stat &= ~STAT_INT;
a6cb20fc	111	}
3f221c8d GH	112
	113	md_interrupt_update(s);
	114	}
	115
d1f2c96a	116	static void md_reset(DeviceState *dev)
3f221c8d	117	{
d1f2c96a AF	118	MicroDriveState *s = MICRODRIVE(dev);
d1f2c96a AF	119
3f221c8d GH	120	s->opt = OPT_MODE_MMAP;
	121	s->stat = 0;
	122	s->pins = 0;
	123	s->cycle = 0;
	124	s->ctrl = 0;
4a643563	125	ide_bus_reset(&s->bus);
3f221c8d GH	126	}
3f221c8d GH	127
d1f2c96a	128	static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at)
3f221c8d	129	{
d1f2c96a AF	130	MicroDriveState *s = MICRODRIVE(card);
	131	PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
	132
3f221c8d	133	if (at < s->attr_base) {
d1f2c96a AF	134	if (at < pcc->cis_len) {
	135	return pcc->cis[at];
	136	} else {
3f221c8d	137	return 0x00;
d1f2c96a	138	}
3f221c8d GH	139	}
	140
	141	at -= s->attr_base;
	142
	143	switch (at) {
	144	case 0x00: /* Configuration Option Register */
	145	return s->opt;
	146	case 0x02: /* Card Configuration Status Register */
a6cb20fc	147	if (s->ctrl & CTRL_IEN) {
3f221c8d	148	return s->stat & ~STAT_INT;
a6cb20fc	149	} else {
3f221c8d	150	return s->stat;
a6cb20fc	151	}
3f221c8d GH	152	case 0x04: /* Pin Replacement Register */
	153	return (s->pins & PINS_CRDY) \| 0x0c;
	154	case 0x06: /* Socket and Copy Register */
	155	return 0x00;
	156	#ifdef VERBOSE
	157	default:
	158	printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
	159	#endif
	160	}
	161
	162	return 0;
	163	}
	164
d1f2c96a	165	static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
3f221c8d	166	{
d1f2c96a AF	167	MicroDriveState *s = MICRODRIVE(card);
d1f2c96a AF	168
3f221c8d GH	169	at -= s->attr_base;
	170
	171	switch (at) {
	172	case 0x00: /* Configuration Option Register */
	173	s->opt = value & 0xcf;
d1f2c96a AF	174	if (value & OPT_SRESET) {
	175	device_reset(DEVICE(s));
	176	}
3f221c8d GH	177	md_interrupt_update(s);
	178	break;
	179	case 0x02: /* Card Configuration Status Register */
a6cb20fc	180	if ((s->stat ^ value) & STAT_PWRDWN) {
3f221c8d	181	s->pins \|= PINS_CRDY;
a6cb20fc	182	}
3f221c8d GH	183	s->stat &= 0x82;
	184	s->stat \|= value & 0x74;
	185	md_interrupt_update(s);
	186	/* Word 170 in Identify Device must be equal to STAT_XE */
	187	break;
	188	case 0x04: /* Pin Replacement Register */
	189	s->pins &= PINS_CRDY;
	190	s->pins \|= value & PINS_MRDY;
	191	break;
	192	case 0x06: /* Socket and Copy Register */
	193	break;
	194	default:
	195	printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
	196	}
	197	}
	198
d1f2c96a	199	static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
3f221c8d	200	{
d1f2c96a	201	MicroDriveState *s = MICRODRIVE(card);
3f221c8d GH	202	IDEState *ifs;
	203	uint16_t ret;
	204	at -= s->io_base;
	205
	206	switch (s->opt & OPT_MODE) {
	207	case OPT_MODE_MMAP:
a6cb20fc	208	if ((at & ~0x3ff) == 0x400) {
3f221c8d	209	at = 0;
a6cb20fc	210	}
3f221c8d GH	211	break;
	212	case OPT_MODE_IOMAP16:
	213	at &= 0xf;
	214	break;
	215	case OPT_MODE_IOMAP1:
a6cb20fc	216	if ((at & ~0xf) == 0x3f0) {
3f221c8d	217	at -= 0x3e8;
a6cb20fc	218	} else if ((at & ~0xf) == 0x1f0) {
3f221c8d	219	at -= 0x1f0;
a6cb20fc	220	}
3f221c8d GH	221	break;
3f221c8d GH	222	case OPT_MODE_IOMAP2:
a6cb20fc	223	if ((at & ~0xf) == 0x370) {
3f221c8d	224	at -= 0x368;
a6cb20fc	225	} else if ((at & ~0xf) == 0x170) {
3f221c8d	226	at -= 0x170;
a6cb20fc	227	}
3f221c8d GH	228	}
	229
	230	switch (at) {
	231	case 0x0: /* Even RD Data */
	232	case 0x8:
	233	return ide_data_readw(&s->bus, 0);
	234
	235	/* TODO: 8-bit accesses */
a6cb20fc	236	if (s->cycle) {
3f221c8d	237	ret = s->io >> 8;
a6cb20fc	238	} else {
3f221c8d GH	239	s->io = ide_data_readw(&s->bus, 0);
	240	ret = s->io & 0xff;
	241	}
	242	s->cycle = !s->cycle;
	243	return ret;
	244	case 0x9: /* Odd RD Data */
	245	return s->io >> 8;
	246	case 0xd: /* Error */
	247	return ide_ioport_read(&s->bus, 0x1);
	248	case 0xe: /* Alternate Status */
	249	ifs = idebus_active_if(&s->bus);
a6cb20fc	250	if (ifs->bs) {
3f221c8d	251	return ifs->status;
a6cb20fc	252	} else {
3f221c8d	253	return 0;
a6cb20fc	254	}
3f221c8d GH	255	case 0xf: /* Device Address */
	256	ifs = idebus_active_if(&s->bus);
	257	return 0xc2 \| ((~ifs->select << 2) & 0x3c);
	258	default:
	259	return ide_ioport_read(&s->bus, at);
	260	}
	261
	262	return 0;
	263	}
	264
d1f2c96a	265	static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
3f221c8d	266	{
d1f2c96a	267	MicroDriveState *s = MICRODRIVE(card);
3f221c8d GH	268	at -= s->io_base;
	269
	270	switch (s->opt & OPT_MODE) {
	271	case OPT_MODE_MMAP:
a6cb20fc	272	if ((at & ~0x3ff) == 0x400) {
3f221c8d	273	at = 0;
a6cb20fc	274	}
3f221c8d GH	275	break;
	276	case OPT_MODE_IOMAP16:
	277	at &= 0xf;
	278	break;
	279	case OPT_MODE_IOMAP1:
a6cb20fc	280	if ((at & ~0xf) == 0x3f0) {
3f221c8d	281	at -= 0x3e8;
a6cb20fc	282	} else if ((at & ~0xf) == 0x1f0) {
3f221c8d	283	at -= 0x1f0;
a6cb20fc	284	}
3f221c8d GH	285	break;
3f221c8d GH	286	case OPT_MODE_IOMAP2:
a6cb20fc	287	if ((at & ~0xf) == 0x370) {
3f221c8d	288	at -= 0x368;
a6cb20fc	289	} else if ((at & ~0xf) == 0x170) {
3f221c8d	290	at -= 0x170;
a6cb20fc	291	}
3f221c8d GH	292	}
	293
	294	switch (at) {
	295	case 0x0: /* Even WR Data */
	296	case 0x8:
	297	ide_data_writew(&s->bus, 0, value);
	298	break;
	299
	300	/* TODO: 8-bit accesses */
a6cb20fc	301	if (s->cycle) {
3f221c8d	302	ide_data_writew(&s->bus, 0, s->io \| (value << 8));
a6cb20fc	303	} else {
3f221c8d	304	s->io = value & 0xff;
a6cb20fc	305	}
3f221c8d GH	306	s->cycle = !s->cycle;
	307	break;
	308	case 0x9:
	309	s->io = value & 0xff;
	310	s->cycle = !s->cycle;
	311	break;
	312	case 0xd: /* Features */
	313	ide_ioport_write(&s->bus, 0x1, value);
	314	break;
	315	case 0xe: /* Device Control */
	316	s->ctrl = value;
d1f2c96a AF	317	if (value & CTRL_SRST) {
	318	device_reset(DEVICE(s));
	319	}
3f221c8d GH	320	md_interrupt_update(s);
	321	break;
	322	default:
	323	if (s->stat & STAT_PWRDWN) {
	324	s->pins \|= PINS_CRDY;
	325	s->stat &= ~STAT_PWRDWN;
	326	}
	327	ide_ioport_write(&s->bus, at, value);
	328	}
	329	}
	330
d05ac8fa	331	static const VMStateDescription vmstate_microdrive = {
5f637ce0 JQ	332	.name = "microdrive",
	333	.version_id = 3,
	334	.minimum_version_id = 0,
35d08458	335	.fields = (VMStateField[]) {
5f637ce0 JQ	336	VMSTATE_UINT8(opt, MicroDriveState),
	337	VMSTATE_UINT8(stat, MicroDriveState),
	338	VMSTATE_UINT8(pins, MicroDriveState),
	339	VMSTATE_UINT8(ctrl, MicroDriveState),
	340	VMSTATE_UINT16(io, MicroDriveState),
	341	VMSTATE_UINT8(cycle, MicroDriveState),
	342	VMSTATE_IDE_BUS(bus, MicroDriveState),
	343	VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
	344	VMSTATE_END_OF_LIST()
	345	}
	346	};
3f221c8d GH	347
	348	static const uint8_t dscm1xxxx_cis[0x14a] = {
	349	[0x000] = CISTPL_DEVICE, /* 5V Device Information */
	350	[0x002] = 0x03, /* Tuple length = 4 bytes */
	351	[0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
	352	[0x006] = 0x01, /* Size = 2K bytes */
	353	[0x008] = CISTPL_ENDMARK,
	354
	355	[0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
	356	[0x00c] = 0x04, /* Tuple length = 4 byest */
	357	[0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
	358	[0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
	359	[0x012] = 0x01, /* Size = 2K bytes */
	360	[0x014] = CISTPL_ENDMARK,
	361
	362	[0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
	363	[0x018] = 0x02, /* Tuple length = 2 bytes */
	364	[0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
	365	[0x01c] = 0x01,
	366
	367	[0x01e] = CISTPL_MANFID, /* Manufacture ID */
	368	[0x020] = 0x04, /* Tuple length = 4 bytes */
	369	[0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
	370	[0x024] = 0x00,
	371	[0x026] = 0x00, /* PLMID_CARD = 0000 */
	372	[0x028] = 0x00,
	373
	374	[0x02a] = CISTPL_VERS_1, /* Level 1 Version */
	375	[0x02c] = 0x12, /* Tuple length = 23 bytes */
	376	[0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
	377	[0x030] = 0x01, /* Minor Version = 1 */
	378	[0x032] = 'I',
	379	[0x034] = 'B',
	380	[0x036] = 'M',
	381	[0x038] = 0x00,
	382	[0x03a] = 'm',
	383	[0x03c] = 'i',
	384	[0x03e] = 'c',
	385	[0x040] = 'r',
	386	[0x042] = 'o',
	387	[0x044] = 'd',
	388	[0x046] = 'r',
	389	[0x048] = 'i',
	390	[0x04a] = 'v',
	391	[0x04c] = 'e',
	392	[0x04e] = 0x00,
	393	[0x050] = CISTPL_ENDMARK,
	394
	395	[0x052] = CISTPL_FUNCID, /* Function ID */
	396	[0x054] = 0x02, /* Tuple length = 2 bytes */
	397	[0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
	398	[0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
	399
	400	[0x05a] = CISTPL_FUNCE, /* Function Extension */
	401	[0x05c] = 0x02, /* Tuple length = 2 bytes */
	402	[0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
	403	[0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
	404
	405	[0x062] = CISTPL_FUNCE, /* Function Extension */
	406	[0x064] = 0x03, /* Tuple length = 3 bytes */
	407	[0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
	408	[0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
	409	[0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
	410
411	[0x06c] = CISTPL_CONFIG, /* Configuration */
412	[0x06e] = 0x05, /* Tuple length = 5 bytes */
413	[0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
414	[0x072] = 0x07, /* TPCC_LAST = 7 */
415	[0x074] = 0x00, /* TPCC_RADR = 0200 */
416	[0x076] = 0x02,
417	[0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
418
419	[0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
420	[0x07c] = 0x0b, /* Tuple length = 11 bytes */
421	[0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
422	[0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
423	[0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
424	[0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
425	[0x086] = 0x55, /* NomV: 5.0 V */
426	[0x088] = 0x4d, /* MinV: 4.5 V */
427	[0x08a] = 0x5d, /* MaxV: 5.5 V */
428	[0x08c] = 0x4e, /* Peakl: 450 mA */
429	[0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
430	[0x090] = 0x00, /* Window descriptor: Window length = 0 */
431	[0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
432
433	[0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
434	[0x096] = 0x06, /* Tuple length = 6 bytes */
435	[0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
436	[0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
437	[0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
438	[0x09e] = 0xb5, /* NomV: 3.3 V */
439	[0x0a0] = 0x1e,
440	[0x0a2] = 0x3e, /* Peakl: 350 mA */
441
442	[0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
443	[0x0a6] = 0x0d, /* Tuple length = 13 bytes */
444	[0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
445	[0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
446	[0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
447	[0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
448	[0x0b0] = 0x55, /* NomV: 5.0 V */
449	[0x0b2] = 0x4d, /* MinV: 4.5 V */
450	[0x0b4] = 0x5d, /* MaxV: 5.5 V */
451	[0x0b6] = 0x4e, /* Peakl: 450 mA */
452	[0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
453	[0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
454	[0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
455	[0x0be] = 0xff, /* IRQ8..IRQ15 supported */
456	[0x0c0] = 0x20, /* TPCE_MI = support power down mode */
457
458	[0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
459	[0x0c4] = 0x06, /* Tuple length = 6 bytes */
460	[0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
461	[0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
462	[0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
463	[0x0cc] = 0xb5, /* NomV: 3.3 V */
464	[0x0ce] = 0x1e,
465	[0x0d0] = 0x3e, /* Peakl: 350 mA */
466
467	[0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
468	[0x0d4] = 0x12, /* Tuple length = 18 bytes */
469	[0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
470	[0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
471	[0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
472	[0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
473	[0x0de] = 0x55, /* NomV: 5.0 V */
474	[0x0e0] = 0x4d, /* MinV: 4.5 V */
475	[0x0e2] = 0x5d, /* MaxV: 5.5 V */
476	[0x0e4] = 0x4e, /* Peakl: 450 mA */
477	[0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
478	[0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
479	[0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
480	[0x0ec] = 0x01,
481	[0x0ee] = 0x07, /* Address block length = 8 */
482	[0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
483	[0x0f2] = 0x03,
484	[0x0f4] = 0x01, /* Address block length = 2 */
485	[0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
486	[0x0f8] = 0x20, /* TPCE_MI = support power down mode */
487
488	[0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
489	[0x0fc] = 0x06, /* Tuple length = 6 bytes */
490	[0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
491	[0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
492	[0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
493	[0x104] = 0xb5, /* NomV: 3.3 V */
494	[0x106] = 0x1e,
495	[0x108] = 0x3e, /* Peakl: 350 mA */
496
497	[0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
498	[0x10c] = 0x12, /* Tuple length = 18 bytes */
499	[0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
500	[0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
501	[0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
502	[0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
503	[0x116] = 0x55, /* NomV: 5.0 V */
504	[0x118] = 0x4d, /* MinV: 4.5 V */
505	[0x11a] = 0x5d, /* MaxV: 5.5 V */
506	[0x11c] = 0x4e, /* Peakl: 450 mA */
507	[0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
508	[0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
509	[0x122] = 0x70, /* Field 1 address = 0x0170 */
510	[0x124] = 0x01,
511	[0x126] = 0x07, /* Address block length = 8 */
512	[0x128] = 0x76, /* Field 2 address = 0x0376 */
513	[0x12a] = 0x03,
514	[0x12c] = 0x01, /* Address block length = 2 */
515	[0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
516	[0x130] = 0x20, /* TPCE_MI = support power down mode */
517
518	[0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
519	[0x134] = 0x06, /* Tuple length = 6 bytes */
520	[0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
521	[0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
522	[0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
523	[0x13c] = 0xb5, /* NomV: 3.3 V */
524	[0x13e] = 0x1e,
525	[0x140] = 0x3e, /* Peakl: 350 mA */
526
527	[0x142] = CISTPL_NO_LINK, /* No Link */
528	[0x144] = 0x00, /* Tuple length = 0 bytes */
529
530	[0x146] = CISTPL_END, /* Tuple End */
531	};
532
d1f2c96a AF	533	#define TYPE_DSCM1XXXX "dscm1xxxx"
	534
	535	static int dscm1xxxx_attach(PCMCIACardState *card)
3f221c8d	536	{
d1f2c96a AF	537	MicroDriveState *md = MICRODRIVE(card);
	538	PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
	539
	540	md->attr_base = pcc->cis[0x74] \| (pcc->cis[0x76] << 8);
3f221c8d GH	541	md->io_base = 0x0;
3f221c8d GH	542
d1f2c96a	543	device_reset(DEVICE(md));
3f221c8d GH	544	md_interrupt_update(md);
3f221c8d GH	545
d1f2c96a	546	card->slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
3f221c8d GH	547	return 0;
	548	}
	549
d1f2c96a	550	static int dscm1xxxx_detach(PCMCIACardState *card)
3f221c8d	551	{
d1f2c96a AF	552	MicroDriveState *md = MICRODRIVE(card);
	553
	554	device_reset(DEVICE(md));
3f221c8d GH	555	return 0;
	556	}
	557
d1f2c96a	558	PCMCIACardState dscm1xxxx_init(DriveInfo dinfo)
3f221c8d	559	{
a6cb20fc AF	560	MicroDriveState *md;
	561
	562	md = MICRODRIVE(object_new(TYPE_DSCM1XXXX));
	563	qdev_init_nofail(DEVICE(md));
d1f2c96a AF	564
	565	if (dinfo != NULL) {
	566	ide_create_drive(&md->bus, 0, dinfo);
	567	}
cd8722bb	568	md->bus.ifs[0].drive_kind = IDE_CFATA;
3f221c8d	569	md->bus.ifs[0].mdata_size = METADATA_SIZE;
d4df3dbc	570	md->bus.ifs[0].mdata_storage = g_malloc0(METADATA_SIZE);
3f221c8d	571
a6cb20fc	572	return PCMCIA_CARD(md);
d1f2c96a AF	573	}
	574
	575	static void dscm1xxxx_class_init(ObjectClass oc, void data)
	576	{
	577	PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
	578
	579	pcc->cis = dscm1xxxx_cis;
	580	pcc->cis_len = sizeof(dscm1xxxx_cis);
	581
	582	pcc->attach = dscm1xxxx_attach;
	583	pcc->detach = dscm1xxxx_detach;
	584	}
	585
	586	static const TypeInfo dscm1xxxx_type_info = {
	587	.name = TYPE_DSCM1XXXX,
	588	.parent = TYPE_MICRODRIVE,
	589	.class_init = dscm1xxxx_class_init,
	590	};
	591
	592	static void microdrive_realize(DeviceState dev, Error *errp)
	593	{
	594	MicroDriveState *md = MICRODRIVE(dev);
	595
f3c7d038	596	ide_init2(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
d1f2c96a AF	597	}
	598
	599	static void microdrive_init(Object *obj)
	600	{
	601	MicroDriveState *md = MICRODRIVE(obj);
	602
	603	ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
	604	}
3f221c8d	605
d1f2c96a AF	606	static void microdrive_class_init(ObjectClass oc, void data)
	607	{
	608	DeviceClass *dc = DEVICE_CLASS(oc);
	609	PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
	610
	611	pcc->attr_read = md_attr_read;
	612	pcc->attr_write = md_attr_write;
	613	pcc->common_read = md_common_read;
	614	pcc->common_write = md_common_write;
	615	pcc->io_read = md_common_read;
	616	pcc->io_write = md_common_write;
	617
	618	dc->realize = microdrive_realize;
	619	dc->reset = md_reset;
	620	dc->vmsd = &vmstate_microdrive;
3f221c8d	621	}
d1f2c96a AF	622
	623	static const TypeInfo microdrive_type_info = {
	624	.name = TYPE_MICRODRIVE,
	625	.parent = TYPE_PCMCIA_CARD,
	626	.instance_size = sizeof(MicroDriveState),
	627	.instance_init = microdrive_init,
	628	.abstract = true,
	629	.class_init = microdrive_class_init,
	630	};
	631
	632	static void microdrive_register_types(void)
	633	{
	634	type_register_static(&microdrive_type_info);
	635	type_register_static(&dscm1xxxx_type_info);
	636	}
	637
	638	type_init(microdrive_register_types)