[qemu.git] / hw / ide-microdrive.c

/*
 * QEMU IDE Emulation: microdrive (CF / PCMCIA)
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pc.h"
#include "block.h"
#include "block_int.h"
#include "sysemu.h"
#include "dma.h"
#include "ide-internal.h"
#include "pcmcia.h"

/***********************************************************/
/* CF-ATA Microdrive */

#define METADATA_SIZE	0x20

/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface.  */
typedef struct {
    IDEBus bus;
    PCMCIACardState card;
    uint32_t attr_base;
    uint32_t io_base;

    /* Card state */
    uint8_t opt;
    uint8_t stat;
    uint8_t pins;

    uint8_t ctrl;
    uint16_t io;
    int cycle;
} MicroDriveState;

/* Register bitfields */
enum md_opt {
    OPT_MODE_MMAP	= 0,
    OPT_MODE_IOMAP16	= 1,
    OPT_MODE_IOMAP1	= 2,
    OPT_MODE_IOMAP2	= 3,
    OPT_MODE		= 0x3f,
    OPT_LEVIREQ		= 0x40,
    OPT_SRESET		= 0x80,
};
enum md_cstat {
    STAT_INT		= 0x02,
    STAT_PWRDWN		= 0x04,
    STAT_XE		= 0x10,
    STAT_IOIS8		= 0x20,
    STAT_SIGCHG		= 0x40,
    STAT_CHANGED	= 0x80,
};
enum md_pins {
    PINS_MRDY		= 0x02,
    PINS_CRDY		= 0x20,
};
enum md_ctrl {
    CTRL_IEN		= 0x02,
    CTRL_SRST		= 0x04,
};

static inline void md_interrupt_update(MicroDriveState *s)
{
    if (!s->card.slot)
        return;

    qemu_set_irq(s->card.slot->irq,
                    !(s->stat & STAT_INT) &&	/* Inverted */
                    !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
                    !(s->opt & OPT_SRESET));
}

static void md_set_irq(void *opaque, int irq, int level)
{
    MicroDriveState *s = (MicroDriveState *) opaque;
    if (level)
        s->stat |= STAT_INT;
    else
        s->stat &= ~STAT_INT;

    md_interrupt_update(s);
}

static void md_reset(MicroDriveState *s)
{
    s->opt = OPT_MODE_MMAP;
    s->stat = 0;
    s->pins = 0;
    s->cycle = 0;
    s->ctrl = 0;
    ide_reset(s->bus.ifs);
}

static uint8_t md_attr_read(void *opaque, uint32_t at)
{
    MicroDriveState *s = (MicroDriveState *) opaque;
    if (at < s->attr_base) {
        if (at < s->card.cis_len)
            return s->card.cis[at];
        else
            return 0x00;
    }

    at -= s->attr_base;

    switch (at) {
    case 0x00:	/* Configuration Option Register */
        return s->opt;
    case 0x02:	/* Card Configuration Status Register */
        if (s->ctrl & CTRL_IEN)
            return s->stat & ~STAT_INT;
        else
            return s->stat;
    case 0x04:	/* Pin Replacement Register */
        return (s->pins & PINS_CRDY) | 0x0c;
    case 0x06:	/* Socket and Copy Register */
        return 0x00;
#ifdef VERBOSE
    default:
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
#endif
    }

    return 0;
}

static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
{
    MicroDriveState *s = (MicroDriveState *) opaque;
    at -= s->attr_base;

    switch (at) {
    case 0x00:	/* Configuration Option Register */
        s->opt = value & 0xcf;
        if (value & OPT_SRESET)
            md_reset(s);
        md_interrupt_update(s);
        break;
    case 0x02:	/* Card Configuration Status Register */
        if ((s->stat ^ value) & STAT_PWRDWN)
            s->pins |= PINS_CRDY;
        s->stat &= 0x82;
        s->stat |= value & 0x74;
        md_interrupt_update(s);
        /* Word 170 in Identify Device must be equal to STAT_XE */
        break;
    case 0x04:	/* Pin Replacement Register */
        s->pins &= PINS_CRDY;
        s->pins |= value & PINS_MRDY;
        break;
    case 0x06:	/* Socket and Copy Register */
        break;
    default:
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
    }
}

static uint16_t md_common_read(void *opaque, uint32_t at)
{
    MicroDriveState *s = (MicroDriveState *) opaque;
    IDEState *ifs;
    uint16_t ret;
    at -= s->io_base;

    switch (s->opt & OPT_MODE) {
    case OPT_MODE_MMAP:
        if ((at & ~0x3ff) == 0x400)
            at = 0;
        break;
    case OPT_MODE_IOMAP16:
        at &= 0xf;
        break;
    case OPT_MODE_IOMAP1:
        if ((at & ~0xf) == 0x3f0)
            at -= 0x3e8;
        else if ((at & ~0xf) == 0x1f0)
            at -= 0x1f0;
        break;
    case OPT_MODE_IOMAP2:
        if ((at & ~0xf) == 0x370)
            at -= 0x368;
        else if ((at & ~0xf) == 0x170)
            at -= 0x170;
    }

    switch (at) {
    case 0x0:	/* Even RD Data */
    case 0x8:
        return ide_data_readw(&s->bus, 0);

        /* TODO: 8-bit accesses */
        if (s->cycle)
            ret = s->io >> 8;
        else {
            s->io = ide_data_readw(&s->bus, 0);
            ret = s->io & 0xff;
        }
        s->cycle = !s->cycle;
        return ret;
    case 0x9:	/* Odd RD Data */
        return s->io >> 8;
    case 0xd:	/* Error */
        return ide_ioport_read(&s->bus, 0x1);
    case 0xe:	/* Alternate Status */
        ifs = idebus_active_if(&s->bus);
        if (ifs->bs)
            return ifs->status;
        else
            return 0;
    case 0xf:	/* Device Address */
        ifs = idebus_active_if(&s->bus);
        return 0xc2 | ((~ifs->select << 2) & 0x3c);
    default:
        return ide_ioport_read(&s->bus, at);
    }

    return 0;
}

static void md_common_write(void *opaque, uint32_t at, uint16_t value)
{
    MicroDriveState *s = (MicroDriveState *) opaque;
    at -= s->io_base;

    switch (s->opt & OPT_MODE) {
    case OPT_MODE_MMAP:
        if ((at & ~0x3ff) == 0x400)
            at = 0;
        break;
    case OPT_MODE_IOMAP16:
        at &= 0xf;
        break;
    case OPT_MODE_IOMAP1:
        if ((at & ~0xf) == 0x3f0)
            at -= 0x3e8;
        else if ((at & ~0xf) == 0x1f0)
            at -= 0x1f0;
        break;
    case OPT_MODE_IOMAP2:
        if ((at & ~0xf) == 0x370)
            at -= 0x368;
        else if ((at & ~0xf) == 0x170)
            at -= 0x170;
    }

    switch (at) {
    case 0x0:	/* Even WR Data */
    case 0x8:
        ide_data_writew(&s->bus, 0, value);
        break;

        /* TODO: 8-bit accesses */
        if (s->cycle)
            ide_data_writew(&s->bus, 0, s->io | (value << 8));
        else
            s->io = value & 0xff;
        s->cycle = !s->cycle;
        break;
    case 0x9:
        s->io = value & 0xff;
        s->cycle = !s->cycle;
        break;
    case 0xd:	/* Features */
        ide_ioport_write(&s->bus, 0x1, value);
        break;
    case 0xe:	/* Device Control */
        s->ctrl = value;
        if (value & CTRL_SRST)
            md_reset(s);
        md_interrupt_update(s);
        break;
    default:
        if (s->stat & STAT_PWRDWN) {
            s->pins |= PINS_CRDY;
            s->stat &= ~STAT_PWRDWN;
        }
        ide_ioport_write(&s->bus, at, value);
    }
}

static void md_save(QEMUFile *f, void *opaque)
{
    MicroDriveState *s = (MicroDriveState *) opaque;
    int i;

    qemu_put_8s(f, &s->opt);
    qemu_put_8s(f, &s->stat);
    qemu_put_8s(f, &s->pins);

    qemu_put_8s(f, &s->ctrl);
    qemu_put_be16s(f, &s->io);
    qemu_put_byte(f, s->cycle);

    idebus_save(f, &s->bus);

    for (i = 0; i < 2; i ++)
        ide_save(f, &s->bus.ifs[i]);
}

static int md_load(QEMUFile *f, void *opaque, int version_id)
{
    MicroDriveState *s = (MicroDriveState *) opaque;
    int i;

    if (version_id != 0 && version_id != 3)
        return -EINVAL;

    qemu_get_8s(f, &s->opt);
    qemu_get_8s(f, &s->stat);
    qemu_get_8s(f, &s->pins);

    qemu_get_8s(f, &s->ctrl);
    qemu_get_be16s(f, &s->io);
    s->cycle = qemu_get_byte(f);

    idebus_load(f, &s->bus, version_id);

    for (i = 0; i < 2; i ++)
        ide_load(f, &s->bus.ifs[i], version_id);

    return 0;
}

static const uint8_t dscm1xxxx_cis[0x14a] = {
    [0x000] = CISTPL_DEVICE,	/* 5V Device Information */
    [0x002] = 0x03,		/* Tuple length = 4 bytes */
    [0x004] = 0xdb,		/* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
    [0x006] = 0x01,		/* Size = 2K bytes */
    [0x008] = CISTPL_ENDMARK,

    [0x00a] = CISTPL_DEVICE_OC,	/* Additional Device Information */
    [0x00c] = 0x04,		/* Tuple length = 4 byest */
    [0x00e] = 0x03,		/* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
    [0x010] = 0xdb,		/* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
    [0x012] = 0x01,		/* Size = 2K bytes */
    [0x014] = CISTPL_ENDMARK,

    [0x016] = CISTPL_JEDEC_C,	/* JEDEC ID */
    [0x018] = 0x02,		/* Tuple length = 2 bytes */
    [0x01a] = 0xdf,		/* PC Card ATA with no Vpp required */
    [0x01c] = 0x01,

    [0x01e] = CISTPL_MANFID,	/* Manufacture ID */
    [0x020] = 0x04,		/* Tuple length = 4 bytes */
    [0x022] = 0xa4,		/* TPLMID_MANF = 00a4 (IBM) */
    [0x024] = 0x00,
    [0x026] = 0x00,		/* PLMID_CARD = 0000 */
    [0x028] = 0x00,

    [0x02a] = CISTPL_VERS_1,	/* Level 1 Version */
    [0x02c] = 0x12,		/* Tuple length = 23 bytes */
    [0x02e] = 0x04,		/* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
    [0x030] = 0x01,		/* Minor Version = 1 */
    [0x032] = 'I',
    [0x034] = 'B',
    [0x036] = 'M',
    [0x038] = 0x00,
    [0x03a] = 'm',
    [0x03c] = 'i',
    [0x03e] = 'c',
    [0x040] = 'r',
    [0x042] = 'o',
    [0x044] = 'd',
    [0x046] = 'r',
    [0x048] = 'i',
    [0x04a] = 'v',
    [0x04c] = 'e',
    [0x04e] = 0x00,
    [0x050] = CISTPL_ENDMARK,

    [0x052] = CISTPL_FUNCID,	/* Function ID */
    [0x054] = 0x02,		/* Tuple length = 2 bytes */
    [0x056] = 0x04,		/* TPLFID_FUNCTION = Fixed Disk */
    [0x058] = 0x01,		/* TPLFID_SYSINIT: POST = 1, ROM = 0 */

    [0x05a] = CISTPL_FUNCE,	/* Function Extension */
    [0x05c] = 0x02,		/* Tuple length = 2 bytes */
    [0x05e] = 0x01,		/* TPLFE_TYPE = Disk Device Interface */
    [0x060] = 0x01,		/* TPLFE_DATA = PC Card ATA Interface */

    [0x062] = CISTPL_FUNCE,	/* Function Extension */
    [0x064] = 0x03,		/* Tuple length = 3 bytes */
    [0x066] = 0x02,		/* TPLFE_TYPE = Basic PC Card ATA Interface */
    [0x068] = 0x08,		/* TPLFE_DATA: Rotating, Unique, Single */
    [0x06a] = 0x0f,		/* TPLFE_DATA: Sleep, Standby, Idle, Auto */

    [0x06c] = CISTPL_CONFIG,	/* Configuration */
    [0x06e] = 0x05,		/* Tuple length = 5 bytes */
    [0x070] = 0x01,		/* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
    [0x072] = 0x07,		/* TPCC_LAST = 7 */
    [0x074] = 0x00,		/* TPCC_RADR = 0200 */
    [0x076] = 0x02,
    [0x078] = 0x0f,		/* TPCC_RMSK = 200, 202, 204, 206 */

    [0x07a] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x07c] = 0x0b,		/* Tuple length = 11 bytes */
    [0x07e] = 0xc0,		/* TPCE_INDX = Memory Mode, Default, Iface */
    [0x080] = 0xc0,		/* TPCE_IF = Memory, no BVDs, no WP, READY */
    [0x082] = 0xa1,		/* TPCE_FS = Vcc only, no I/O, Memory, Misc */
    [0x084] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x086] = 0x55,		/* NomV: 5.0 V */
    [0x088] = 0x4d,		/* MinV: 4.5 V */
    [0x08a] = 0x5d,		/* MaxV: 5.5 V */
    [0x08c] = 0x4e,		/* Peakl: 450 mA */
    [0x08e] = 0x08,		/* TPCE_MS = 1 window, 1 byte, Host address */
    [0x090] = 0x00,		/* Window descriptor: Window length = 0 */
    [0x092] = 0x20,		/* TPCE_MI: support power down mode, RW */

    [0x094] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x096] = 0x06,		/* Tuple length = 6 bytes */
    [0x098] = 0x00,		/* TPCE_INDX = Memory Mode, no Default */
    [0x09a] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x09c] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x09e] = 0xb5,		/* NomV: 3.3 V */
    [0x0a0] = 0x1e,
    [0x0a2] = 0x3e,		/* Peakl: 350 mA */

    [0x0a4] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0a6] = 0x0d,		/* Tuple length = 13 bytes */
    [0x0a8] = 0xc1,		/* TPCE_INDX = I/O and Memory Mode, Default */
    [0x0aa] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x0ac] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x0ae] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x0b0] = 0x55,		/* NomV: 5.0 V */
    [0x0b2] = 0x4d,		/* MinV: 4.5 V */
    [0x0b4] = 0x5d,		/* MaxV: 5.5 V */
    [0x0b6] = 0x4e,		/* Peakl: 450 mA */
    [0x0b8] = 0x64,		/* TPCE_IO = 16-byte boundary, 16/8 accesses */
    [0x0ba] = 0xf0,		/* TPCE_IR =  MASK, Level, Pulse, Share */
    [0x0bc] = 0xff,		/* IRQ0..IRQ7 supported */
    [0x0be] = 0xff,		/* IRQ8..IRQ15 supported */
    [0x0c0] = 0x20,		/* TPCE_MI = support power down mode */

    [0x0c2] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0c4] = 0x06,		/* Tuple length = 6 bytes */
    [0x0c6] = 0x01,		/* TPCE_INDX = I/O and Memory Mode */
    [0x0c8] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x0ca] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x0cc] = 0xb5,		/* NomV: 3.3 V */
    [0x0ce] = 0x1e,
    [0x0d0] = 0x3e,		/* Peakl: 350 mA */

    [0x0d2] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0d4] = 0x12,		/* Tuple length = 18 bytes */
    [0x0d6] = 0xc2,		/* TPCE_INDX = I/O Primary Mode */
    [0x0d8] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x0da] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x0dc] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x0de] = 0x55,		/* NomV: 5.0 V */
    [0x0e0] = 0x4d,		/* MinV: 4.5 V */
    [0x0e2] = 0x5d,		/* MaxV: 5.5 V */
    [0x0e4] = 0x4e,		/* Peakl: 450 mA */
    [0x0e6] = 0xea,		/* TPCE_IO = 1K boundary, 16/8 access, Range */
    [0x0e8] = 0x61,		/* Range: 2 fields, 2 bytes addr, 1 byte len */
    [0x0ea] = 0xf0,		/* Field 1 address = 0x01f0 */
    [0x0ec] = 0x01,
    [0x0ee] = 0x07,		/* Address block length = 8 */
    [0x0f0] = 0xf6,		/* Field 2 address = 0x03f6 */
    [0x0f2] = 0x03,
    [0x0f4] = 0x01,		/* Address block length = 2 */
    [0x0f6] = 0xee,		/* TPCE_IR = IRQ E, Level, Pulse, Share */
    [0x0f8] = 0x20,		/* TPCE_MI = support power down mode */

    [0x0fa] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0fc] = 0x06,		/* Tuple length = 6 bytes */
    [0x0fe] = 0x02,		/* TPCE_INDX = I/O Primary Mode, no Default */
    [0x100] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x102] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x104] = 0xb5,		/* NomV: 3.3 V */
    [0x106] = 0x1e,
    [0x108] = 0x3e,		/* Peakl: 350 mA */

    [0x10a] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x10c] = 0x12,		/* Tuple length = 18 bytes */
    [0x10e] = 0xc3,		/* TPCE_INDX = I/O Secondary Mode, Default */
    [0x110] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x112] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x114] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x116] = 0x55,		/* NomV: 5.0 V */
    [0x118] = 0x4d,		/* MinV: 4.5 V */
    [0x11a] = 0x5d,		/* MaxV: 5.5 V */
    [0x11c] = 0x4e,		/* Peakl: 450 mA */
    [0x11e] = 0xea,		/* TPCE_IO = 1K boundary, 16/8 access, Range */
    [0x120] = 0x61,		/* Range: 2 fields, 2 byte addr, 1 byte len */
    [0x122] = 0x70,		/* Field 1 address = 0x0170 */
    [0x124] = 0x01,
    [0x126] = 0x07,		/* Address block length = 8 */
    [0x128] = 0x76,		/* Field 2 address = 0x0376 */
    [0x12a] = 0x03,
    [0x12c] = 0x01,		/* Address block length = 2 */
    [0x12e] = 0xee,		/* TPCE_IR = IRQ E, Level, Pulse, Share */
    [0x130] = 0x20,		/* TPCE_MI = support power down mode */

    [0x132] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x134] = 0x06,		/* Tuple length = 6 bytes */
    [0x136] = 0x03,		/* TPCE_INDX = I/O Secondary Mode */
    [0x138] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x13a] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x13c] = 0xb5,		/* NomV: 3.3 V */
    [0x13e] = 0x1e,
    [0x140] = 0x3e,		/* Peakl: 350 mA */

    [0x142] = CISTPL_NO_LINK,	/* No Link */
    [0x144] = 0x00,		/* Tuple length = 0 bytes */

    [0x146] = CISTPL_END,	/* Tuple End */
};

static int dscm1xxxx_attach(void *opaque)
{
    MicroDriveState *md = (MicroDriveState *) opaque;
    md->card.attr_read = md_attr_read;
    md->card.attr_write = md_attr_write;
    md->card.common_read = md_common_read;
    md->card.common_write = md_common_write;
    md->card.io_read = md_common_read;
    md->card.io_write = md_common_write;

    md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
    md->io_base = 0x0;

    md_reset(md);
    md_interrupt_update(md);

    md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
    return 0;
}

static int dscm1xxxx_detach(void *opaque)
{
    MicroDriveState *md = (MicroDriveState *) opaque;
    md_reset(md);
    return 0;
}

PCMCIACardState *dscm1xxxx_init(BlockDriverState *bdrv)
{
    MicroDriveState *md = (MicroDriveState *) qemu_mallocz(sizeof(MicroDriveState));
    md->card.state = md;
    md->card.attach = dscm1xxxx_attach;
    md->card.detach = dscm1xxxx_detach;
    md->card.cis = dscm1xxxx_cis;
    md->card.cis_len = sizeof(dscm1xxxx_cis);

    ide_init2(&md->bus, bdrv, NULL, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
    md->bus.ifs[0].is_cf = 1;
    md->bus.ifs[0].mdata_size = METADATA_SIZE;
    md->bus.ifs[0].mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);

    register_savevm("microdrive", -1, 3, md_save, md_load, md);

    return &md->card;
}
Commit	Line	Data
3f221c8d GH	1	/*
	2	* QEMU IDE Emulation: microdrive (CF / PCMCIA)
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "hw.h"
	26	#include "pc.h"
	27	#include "block.h"
	28	#include "block_int.h"
	29	#include "sysemu.h"
	30	#include "dma.h"
	31	#include "ide-internal.h"
	32	#include "pcmcia.h"
	33
	34	/***********************************************************/
	35	/* CF-ATA Microdrive */
	36
	37	#define METADATA_SIZE 0x20
	38
	39	/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
	40	typedef struct {
	41	IDEBus bus;
	42	PCMCIACardState card;
	43	uint32_t attr_base;
	44	uint32_t io_base;
	45
	46	/* Card state */
	47	uint8_t opt;
	48	uint8_t stat;
	49	uint8_t pins;
	50
	51	uint8_t ctrl;
	52	uint16_t io;
	53	int cycle;
	54	} MicroDriveState;
	55
	56	/* Register bitfields */
	57	enum md_opt {
	58	OPT_MODE_MMAP = 0,
	59	OPT_MODE_IOMAP16 = 1,
	60	OPT_MODE_IOMAP1 = 2,
	61	OPT_MODE_IOMAP2 = 3,
	62	OPT_MODE = 0x3f,
	63	OPT_LEVIREQ = 0x40,
	64	OPT_SRESET = 0x80,
65	};
66	enum md_cstat {
67	STAT_INT = 0x02,
68	STAT_PWRDWN = 0x04,
69	STAT_XE = 0x10,
70	STAT_IOIS8 = 0x20,
71	STAT_SIGCHG = 0x40,
72	STAT_CHANGED = 0x80,
73	};
74	enum md_pins {
75	PINS_MRDY = 0x02,
76	PINS_CRDY = 0x20,
77	};
78	enum md_ctrl {
79	CTRL_IEN = 0x02,
80	CTRL_SRST = 0x04,
81	};
82
83	static inline void md_interrupt_update(MicroDriveState *s)
84	{
85	if (!s->card.slot)
86	return;
87
88	qemu_set_irq(s->card.slot->irq,
89	!(s->stat & STAT_INT) && /* Inverted */
90	!(s->ctrl & (CTRL_IEN \| CTRL_SRST)) &&
91	!(s->opt & OPT_SRESET));
92	}
93
94	static void md_set_irq(void *opaque, int irq, int level)
95	{
96	MicroDriveState s = (MicroDriveState ) opaque;
97	if (level)
98	s->stat \|= STAT_INT;
99	else
100	s->stat &= ~STAT_INT;
101
102	md_interrupt_update(s);
103	}
104
105	static void md_reset(MicroDriveState *s)
106	{
107	s->opt = OPT_MODE_MMAP;
108	s->stat = 0;
109	s->pins = 0;
110	s->cycle = 0;
111	s->ctrl = 0;
112	ide_reset(s->bus.ifs);
113	}
114
115	static uint8_t md_attr_read(void *opaque, uint32_t at)
116	{
117	MicroDriveState s = (MicroDriveState ) opaque;
118	if (at < s->attr_base) {
119	if (at < s->card.cis_len)
120	return s->card.cis[at];
121	else
122	return 0x00;
123	}
124
125	at -= s->attr_base;
126
127	switch (at) {
128	case 0x00: /* Configuration Option Register */
129	return s->opt;
130	case 0x02: /* Card Configuration Status Register */
131	if (s->ctrl & CTRL_IEN)
132	return s->stat & ~STAT_INT;
133	else
134	return s->stat;
135	case 0x04: /* Pin Replacement Register */
136	return (s->pins & PINS_CRDY) \| 0x0c;
137	case 0x06: /* Socket and Copy Register */
138	return 0x00;
139	#ifdef VERBOSE
140	default:
141	printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
142	#endif
143	}
144
145	return 0;
146	}
147
148	static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
149	{
150	MicroDriveState s = (MicroDriveState ) opaque;
151	at -= s->attr_base;
152
153	switch (at) {
154	case 0x00: /* Configuration Option Register */
155	s->opt = value & 0xcf;
156	if (value & OPT_SRESET)
157	md_reset(s);
158	md_interrupt_update(s);
159	break;
160	case 0x02: /* Card Configuration Status Register */
161	if ((s->stat ^ value) & STAT_PWRDWN)
162	s->pins \|= PINS_CRDY;
163	s->stat &= 0x82;
164	s->stat \|= value & 0x74;
165	md_interrupt_update(s);
166	/* Word 170 in Identify Device must be equal to STAT_XE */
167	break;
168	case 0x04: /* Pin Replacement Register */
169	s->pins &= PINS_CRDY;
170	s->pins \|= value & PINS_MRDY;
171	break;
172	case 0x06: /* Socket and Copy Register */
173	break;
174	default:
175	printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
176	}
177	}
178
179	static uint16_t md_common_read(void *opaque, uint32_t at)
180	{
181	MicroDriveState s = (MicroDriveState ) opaque;
182	IDEState *ifs;
183	uint16_t ret;
184	at -= s->io_base;
185
186	switch (s->opt & OPT_MODE) {
187	case OPT_MODE_MMAP:
188	if ((at & ~0x3ff) == 0x400)
189	at = 0;
190	break;
191	case OPT_MODE_IOMAP16:
192	at &= 0xf;
193	break;
194	case OPT_MODE_IOMAP1:
195	if ((at & ~0xf) == 0x3f0)
196	at -= 0x3e8;
197	else if ((at & ~0xf) == 0x1f0)
198	at -= 0x1f0;
199	break;
200	case OPT_MODE_IOMAP2:
201	if ((at & ~0xf) == 0x370)
202	at -= 0x368;
203	else if ((at & ~0xf) == 0x170)
204	at -= 0x170;
205	}
206
207	switch (at) {
208	case 0x0: /* Even RD Data */
209	case 0x8:
210	return ide_data_readw(&s->bus, 0);
211
212	/* TODO: 8-bit accesses */
213	if (s->cycle)
214	ret = s->io >> 8;
215	else {
216	s->io = ide_data_readw(&s->bus, 0);
217	ret = s->io & 0xff;
218	}
219	s->cycle = !s->cycle;
220	return ret;
221	case 0x9: /* Odd RD Data */
222	return s->io >> 8;
223	case 0xd: /* Error */
224	return ide_ioport_read(&s->bus, 0x1);
225	case 0xe: /* Alternate Status */
226	ifs = idebus_active_if(&s->bus);
227	if (ifs->bs)
228	return ifs->status;
229	else
230	return 0;
231	case 0xf: /* Device Address */
232	ifs = idebus_active_if(&s->bus);
233	return 0xc2 \| ((~ifs->select << 2) & 0x3c);
234	default:
235	return ide_ioport_read(&s->bus, at);
236	}
237
238	return 0;
239	}
240
241	static void md_common_write(void *opaque, uint32_t at, uint16_t value)
242	{
243	MicroDriveState s = (MicroDriveState ) opaque;
244	at -= s->io_base;
245
246	switch (s->opt & OPT_MODE) {
247	case OPT_MODE_MMAP:
248	if ((at & ~0x3ff) == 0x400)
249	at = 0;
250	break;
251	case OPT_MODE_IOMAP16:
252	at &= 0xf;
253	break;
254	case OPT_MODE_IOMAP1:
255	if ((at & ~0xf) == 0x3f0)
256	at -= 0x3e8;
257	else if ((at & ~0xf) == 0x1f0)
258	at -= 0x1f0;
259	break;
260	case OPT_MODE_IOMAP2:
261	if ((at & ~0xf) == 0x370)
262	at -= 0x368;
263	else if ((at & ~0xf) == 0x170)
264	at -= 0x170;
265	}
266
267	switch (at) {
268	case 0x0: /* Even WR Data */
269	case 0x8:
270	ide_data_writew(&s->bus, 0, value);
271	break;
272
273	/* TODO: 8-bit accesses */
274	if (s->cycle)
275	ide_data_writew(&s->bus, 0, s->io \| (value << 8));
276	else
277	s->io = value & 0xff;
278	s->cycle = !s->cycle;
279	break;
280	case 0x9:
281	s->io = value & 0xff;
282	s->cycle = !s->cycle;
283	break;
284	case 0xd: /* Features */
285	ide_ioport_write(&s->bus, 0x1, value);
286	break;
287	case 0xe: /* Device Control */
288	s->ctrl = value;
289	if (value & CTRL_SRST)
290	md_reset(s);
291	md_interrupt_update(s);
292	break;
293	default:
294	if (s->stat & STAT_PWRDWN) {
295	s->pins \|= PINS_CRDY;
296	s->stat &= ~STAT_PWRDWN;
297	}
298	ide_ioport_write(&s->bus, at, value);
299	}
300	}
301
302	static void md_save(QEMUFile f, void opaque)
303	{
304	MicroDriveState s = (MicroDriveState ) opaque;
305	int i;
306
307	qemu_put_8s(f, &s->opt);
308	qemu_put_8s(f, &s->stat);
309	qemu_put_8s(f, &s->pins);
310
311	qemu_put_8s(f, &s->ctrl);
312	qemu_put_be16s(f, &s->io);
313	qemu_put_byte(f, s->cycle);
314
315	idebus_save(f, &s->bus);
316
317	for (i = 0; i < 2; i ++)
318	ide_save(f, &s->bus.ifs[i]);
319	}
320
321	static int md_load(QEMUFile f, void opaque, int version_id)
322	{
323	MicroDriveState s = (MicroDriveState ) opaque;
324	int i;
325
326	if (version_id != 0 && version_id != 3)
327	return -EINVAL;
328
329	qemu_get_8s(f, &s->opt);
330	qemu_get_8s(f, &s->stat);
331	qemu_get_8s(f, &s->pins);
332
333	qemu_get_8s(f, &s->ctrl);
334	qemu_get_be16s(f, &s->io);
335	s->cycle = qemu_get_byte(f);
336
337	idebus_load(f, &s->bus, version_id);
338
339	for (i = 0; i < 2; i ++)
340	ide_load(f, &s->bus.ifs[i], version_id);
341
342	return 0;
343	}
344
345	static const uint8_t dscm1xxxx_cis[0x14a] = {
346	[0x000] = CISTPL_DEVICE, /* 5V Device Information */
347	[0x002] = 0x03, /* Tuple length = 4 bytes */
348	[0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
349	[0x006] = 0x01, /* Size = 2K bytes */
350	[0x008] = CISTPL_ENDMARK,
351
352	[0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
353	[0x00c] = 0x04, /* Tuple length = 4 byest */
354	[0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
355	[0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
356	[0x012] = 0x01, /* Size = 2K bytes */
357	[0x014] = CISTPL_ENDMARK,
358
359	[0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
360	[0x018] = 0x02, /* Tuple length = 2 bytes */
361	[0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
362	[0x01c] = 0x01,
363
364	[0x01e] = CISTPL_MANFID, /* Manufacture ID */
365	[0x020] = 0x04, /* Tuple length = 4 bytes */
366	[0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
367	[0x024] = 0x00,
368	[0x026] = 0x00, /* PLMID_CARD = 0000 */
369	[0x028] = 0x00,
370
371	[0x02a] = CISTPL_VERS_1, /* Level 1 Version */
372	[0x02c] = 0x12, /* Tuple length = 23 bytes */
373	[0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
374	[0x030] = 0x01, /* Minor Version = 1 */
375	[0x032] = 'I',
376	[0x034] = 'B',
377	[0x036] = 'M',
378	[0x038] = 0x00,
379	[0x03a] = 'm',
380	[0x03c] = 'i',
381	[0x03e] = 'c',
382	[0x040] = 'r',
383	[0x042] = 'o',
384	[0x044] = 'd',
385	[0x046] = 'r',
386	[0x048] = 'i',
387	[0x04a] = 'v',
388	[0x04c] = 'e',
389	[0x04e] = 0x00,
390	[0x050] = CISTPL_ENDMARK,
391
392	[0x052] = CISTPL_FUNCID, /* Function ID */
393	[0x054] = 0x02, /* Tuple length = 2 bytes */
394	[0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
395	[0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
396
397	[0x05a] = CISTPL_FUNCE, /* Function Extension */
398	[0x05c] = 0x02, /* Tuple length = 2 bytes */
399	[0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
400	[0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
401
402	[0x062] = CISTPL_FUNCE, /* Function Extension */
403	[0x064] = 0x03, /* Tuple length = 3 bytes */
404	[0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
405	[0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
406	[0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
407
408	[0x06c] = CISTPL_CONFIG, /* Configuration */
409	[0x06e] = 0x05, /* Tuple length = 5 bytes */
410	[0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
411	[0x072] = 0x07, /* TPCC_LAST = 7 */
412	[0x074] = 0x00, /* TPCC_RADR = 0200 */
413	[0x076] = 0x02,
414	[0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
415
416	[0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
417	[0x07c] = 0x0b, /* Tuple length = 11 bytes */
418	[0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
419	[0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
420	[0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
421	[0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
422	[0x086] = 0x55, /* NomV: 5.0 V */
423	[0x088] = 0x4d, /* MinV: 4.5 V */
424	[0x08a] = 0x5d, /* MaxV: 5.5 V */
425	[0x08c] = 0x4e, /* Peakl: 450 mA */
426	[0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
427	[0x090] = 0x00, /* Window descriptor: Window length = 0 */
428	[0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
429
430	[0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
431	[0x096] = 0x06, /* Tuple length = 6 bytes */
432	[0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
433	[0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
434	[0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
435	[0x09e] = 0xb5, /* NomV: 3.3 V */
436	[0x0a0] = 0x1e,
437	[0x0a2] = 0x3e, /* Peakl: 350 mA */
438
439	[0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
440	[0x0a6] = 0x0d, /* Tuple length = 13 bytes */
441	[0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
442	[0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
443	[0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
444	[0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
445	[0x0b0] = 0x55, /* NomV: 5.0 V */
446	[0x0b2] = 0x4d, /* MinV: 4.5 V */
447	[0x0b4] = 0x5d, /* MaxV: 5.5 V */
448	[0x0b6] = 0x4e, /* Peakl: 450 mA */
449	[0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
450	[0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
451	[0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
452	[0x0be] = 0xff, /* IRQ8..IRQ15 supported */
453	[0x0c0] = 0x20, /* TPCE_MI = support power down mode */
454
455	[0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
456	[0x0c4] = 0x06, /* Tuple length = 6 bytes */
457	[0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
458	[0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
459	[0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
460	[0x0cc] = 0xb5, /* NomV: 3.3 V */
461	[0x0ce] = 0x1e,
462	[0x0d0] = 0x3e, /* Peakl: 350 mA */
463
464	[0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
465	[0x0d4] = 0x12, /* Tuple length = 18 bytes */
466	[0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
467	[0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
468	[0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
469	[0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
470	[0x0de] = 0x55, /* NomV: 5.0 V */
471	[0x0e0] = 0x4d, /* MinV: 4.5 V */
472	[0x0e2] = 0x5d, /* MaxV: 5.5 V */
473	[0x0e4] = 0x4e, /* Peakl: 450 mA */
474	[0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
475	[0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
476	[0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
477	[0x0ec] = 0x01,
478	[0x0ee] = 0x07, /* Address block length = 8 */
479	[0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
480	[0x0f2] = 0x03,
481	[0x0f4] = 0x01, /* Address block length = 2 */
482	[0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
483	[0x0f8] = 0x20, /* TPCE_MI = support power down mode */
484
485	[0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
486	[0x0fc] = 0x06, /* Tuple length = 6 bytes */
487	[0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
488	[0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
489	[0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
490	[0x104] = 0xb5, /* NomV: 3.3 V */
491	[0x106] = 0x1e,
492	[0x108] = 0x3e, /* Peakl: 350 mA */
493
494	[0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
495	[0x10c] = 0x12, /* Tuple length = 18 bytes */
496	[0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
497	[0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
498	[0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
499	[0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
500	[0x116] = 0x55, /* NomV: 5.0 V */
501	[0x118] = 0x4d, /* MinV: 4.5 V */
502	[0x11a] = 0x5d, /* MaxV: 5.5 V */
503	[0x11c] = 0x4e, /* Peakl: 450 mA */
504	[0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
505	[0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
506	[0x122] = 0x70, /* Field 1 address = 0x0170 */
507	[0x124] = 0x01,
508	[0x126] = 0x07, /* Address block length = 8 */
509	[0x128] = 0x76, /* Field 2 address = 0x0376 */
510	[0x12a] = 0x03,
511	[0x12c] = 0x01, /* Address block length = 2 */
512	[0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
513	[0x130] = 0x20, /* TPCE_MI = support power down mode */
514
515	[0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
516	[0x134] = 0x06, /* Tuple length = 6 bytes */
517	[0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
518	[0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
519	[0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
520	[0x13c] = 0xb5, /* NomV: 3.3 V */
521	[0x13e] = 0x1e,
522	[0x140] = 0x3e, /* Peakl: 350 mA */
523
524	[0x142] = CISTPL_NO_LINK, /* No Link */
525	[0x144] = 0x00, /* Tuple length = 0 bytes */
526
527	[0x146] = CISTPL_END, /* Tuple End */
528	};
529
530	static int dscm1xxxx_attach(void *opaque)
531	{
532	MicroDriveState md = (MicroDriveState ) opaque;
533	md->card.attr_read = md_attr_read;
534	md->card.attr_write = md_attr_write;
535	md->card.common_read = md_common_read;
536	md->card.common_write = md_common_write;
537	md->card.io_read = md_common_read;
538	md->card.io_write = md_common_write;
539
540	md->attr_base = md->card.cis[0x74] \| (md->card.cis[0x76] << 8);
541	md->io_base = 0x0;
542
543	md_reset(md);
544	md_interrupt_update(md);
545
546	md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
547	return 0;
548	}
549
550	static int dscm1xxxx_detach(void *opaque)
551	{
552	MicroDriveState md = (MicroDriveState ) opaque;
553	md_reset(md);
554	return 0;
555	}
556
557	PCMCIACardState dscm1xxxx_init(BlockDriverState bdrv)
558	{
559	MicroDriveState md = (MicroDriveState ) qemu_mallocz(sizeof(MicroDriveState));
560	md->card.state = md;
561	md->card.attach = dscm1xxxx_attach;
562	md->card.detach = dscm1xxxx_detach;
563	md->card.cis = dscm1xxxx_cis;
564	md->card.cis_len = sizeof(dscm1xxxx_cis);
565
566	ide_init2(&md->bus, bdrv, NULL, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
567	md->bus.ifs[0].is_cf = 1;
568	md->bus.ifs[0].mdata_size = METADATA_SIZE;
569	md->bus.ifs[0].mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
570
571	register_savevm("microdrive", -1, 3, md_save, md_load, md);
572
573	return &md->card;
574	}