[qemu.git] / hw / ide / microdrive.c

/*
 * QEMU IDE Emulation: microdrive (CF / PCMCIA)
 *
 * Copyright (c) 2003 Fabrice Bellard
 * Copyright (c) 2006 Openedhand Ltd.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <hw/hw.h>
#include <hw/i386/pc.h>
#include <hw/pcmcia.h>
#include "block/block.h"
#include "sysemu/dma.h"

#include <hw/ide/internal.h>

#define TYPE_MICRODRIVE "microdrive"
#define MICRODRIVE(obj) OBJECT_CHECK(MicroDriveState, (obj), TYPE_MICRODRIVE)

/***********************************************************/
/* CF-ATA Microdrive */

#define METADATA_SIZE	0x20

/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface.  */

typedef struct MicroDriveState {
    /*< private >*/
    PCMCIACardState parent_obj;
    /*< public >*/

    IDEBus bus;
    uint32_t attr_base;
    uint32_t io_base;

    /* Card state */
    uint8_t opt;
    uint8_t stat;
    uint8_t pins;

    uint8_t ctrl;
    uint16_t io;
    uint8_t cycle;
} MicroDriveState;

/* Register bitfields */
enum md_opt {
    OPT_MODE_MMAP	= 0,
    OPT_MODE_IOMAP16	= 1,
    OPT_MODE_IOMAP1	= 2,
    OPT_MODE_IOMAP2	= 3,
    OPT_MODE		= 0x3f,
    OPT_LEVIREQ		= 0x40,
    OPT_SRESET		= 0x80,
};
enum md_cstat {
    STAT_INT		= 0x02,
    STAT_PWRDWN		= 0x04,
    STAT_XE		= 0x10,
    STAT_IOIS8		= 0x20,
    STAT_SIGCHG		= 0x40,
    STAT_CHANGED	= 0x80,
};
enum md_pins {
    PINS_MRDY		= 0x02,
    PINS_CRDY		= 0x20,
};
enum md_ctrl {
    CTRL_IEN		= 0x02,
    CTRL_SRST		= 0x04,
};

static inline void md_interrupt_update(MicroDriveState *s)
{
    PCMCIACardState *card = PCMCIA_CARD(s);

    if (card->slot == NULL) {
        return;
    }

    qemu_set_irq(card->slot->irq,
                    !(s->stat & STAT_INT) &&	/* Inverted */
                    !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
                    !(s->opt & OPT_SRESET));
}

static void md_set_irq(void *opaque, int irq, int level)
{
    MicroDriveState *s = opaque;
    if (level)
        s->stat |= STAT_INT;
    else
        s->stat &= ~STAT_INT;

    md_interrupt_update(s);
}

static void md_reset(DeviceState *dev)
{
    MicroDriveState *s = MICRODRIVE(dev);

    s->opt = OPT_MODE_MMAP;
    s->stat = 0;
    s->pins = 0;
    s->cycle = 0;
    s->ctrl = 0;
    ide_bus_reset(&s->bus);
}

static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at)
{
    MicroDriveState *s = MICRODRIVE(card);
    PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);

    if (at < s->attr_base) {
        if (at < pcc->cis_len) {
            return pcc->cis[at];
        } else {
            return 0x00;
        }
    }

    at -= s->attr_base;

    switch (at) {
    case 0x00:	/* Configuration Option Register */
        return s->opt;
    case 0x02:	/* Card Configuration Status Register */
        if (s->ctrl & CTRL_IEN)
            return s->stat & ~STAT_INT;
        else
            return s->stat;
    case 0x04:	/* Pin Replacement Register */
        return (s->pins & PINS_CRDY) | 0x0c;
    case 0x06:	/* Socket and Copy Register */
        return 0x00;
#ifdef VERBOSE
    default:
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
#endif
    }

    return 0;
}

static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
{
    MicroDriveState *s = MICRODRIVE(card);

    at -= s->attr_base;

    switch (at) {
    case 0x00:	/* Configuration Option Register */
        s->opt = value & 0xcf;
        if (value & OPT_SRESET) {
            device_reset(DEVICE(s));
        }
        md_interrupt_update(s);
        break;
    case 0x02:	/* Card Configuration Status Register */
        if ((s->stat ^ value) & STAT_PWRDWN)
            s->pins |= PINS_CRDY;
        s->stat &= 0x82;
        s->stat |= value & 0x74;
        md_interrupt_update(s);
        /* Word 170 in Identify Device must be equal to STAT_XE */
        break;
    case 0x04:	/* Pin Replacement Register */
        s->pins &= PINS_CRDY;
        s->pins |= value & PINS_MRDY;
        break;
    case 0x06:	/* Socket and Copy Register */
        break;
    default:
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
    }
}

static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
{
    MicroDriveState *s = MICRODRIVE(card);
    IDEState *ifs;
    uint16_t ret;
    at -= s->io_base;

    switch (s->opt & OPT_MODE) {
    case OPT_MODE_MMAP:
        if ((at & ~0x3ff) == 0x400)
            at = 0;
        break;
    case OPT_MODE_IOMAP16:
        at &= 0xf;
        break;
    case OPT_MODE_IOMAP1:
        if ((at & ~0xf) == 0x3f0)
            at -= 0x3e8;
        else if ((at & ~0xf) == 0x1f0)
            at -= 0x1f0;
        break;
    case OPT_MODE_IOMAP2:
        if ((at & ~0xf) == 0x370)
            at -= 0x368;
        else if ((at & ~0xf) == 0x170)
            at -= 0x170;
    }

    switch (at) {
    case 0x0:	/* Even RD Data */
    case 0x8:
        return ide_data_readw(&s->bus, 0);

        /* TODO: 8-bit accesses */
        if (s->cycle)
            ret = s->io >> 8;
        else {
            s->io = ide_data_readw(&s->bus, 0);
            ret = s->io & 0xff;
        }
        s->cycle = !s->cycle;
        return ret;
    case 0x9:	/* Odd RD Data */
        return s->io >> 8;
    case 0xd:	/* Error */
        return ide_ioport_read(&s->bus, 0x1);
    case 0xe:	/* Alternate Status */
        ifs = idebus_active_if(&s->bus);
        if (ifs->bs)
            return ifs->status;
        else
            return 0;
    case 0xf:	/* Device Address */
        ifs = idebus_active_if(&s->bus);
        return 0xc2 | ((~ifs->select << 2) & 0x3c);
    default:
        return ide_ioport_read(&s->bus, at);
    }

    return 0;
}

static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
{
    MicroDriveState *s = MICRODRIVE(card);
    at -= s->io_base;

    switch (s->opt & OPT_MODE) {
    case OPT_MODE_MMAP:
        if ((at & ~0x3ff) == 0x400)
            at = 0;
        break;
    case OPT_MODE_IOMAP16:
        at &= 0xf;
        break;
    case OPT_MODE_IOMAP1:
        if ((at & ~0xf) == 0x3f0)
            at -= 0x3e8;
        else if ((at & ~0xf) == 0x1f0)
            at -= 0x1f0;
        break;
    case OPT_MODE_IOMAP2:
        if ((at & ~0xf) == 0x370)
            at -= 0x368;
        else if ((at & ~0xf) == 0x170)
            at -= 0x170;
    }

    switch (at) {
    case 0x0:	/* Even WR Data */
    case 0x8:
        ide_data_writew(&s->bus, 0, value);
        break;

        /* TODO: 8-bit accesses */
        if (s->cycle)
            ide_data_writew(&s->bus, 0, s->io | (value << 8));
        else
            s->io = value & 0xff;
        s->cycle = !s->cycle;
        break;
    case 0x9:
        s->io = value & 0xff;
        s->cycle = !s->cycle;
        break;
    case 0xd:	/* Features */
        ide_ioport_write(&s->bus, 0x1, value);
        break;
    case 0xe:	/* Device Control */
        s->ctrl = value;
        if (value & CTRL_SRST) {
            device_reset(DEVICE(s));
        }
        md_interrupt_update(s);
        break;
    default:
        if (s->stat & STAT_PWRDWN) {
            s->pins |= PINS_CRDY;
            s->stat &= ~STAT_PWRDWN;
        }
        ide_ioport_write(&s->bus, at, value);
    }
}

static const VMStateDescription vmstate_microdrive = {
    .name = "microdrive",
    .version_id = 3,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField []) {
        VMSTATE_UINT8(opt, MicroDriveState),
        VMSTATE_UINT8(stat, MicroDriveState),
        VMSTATE_UINT8(pins, MicroDriveState),
        VMSTATE_UINT8(ctrl, MicroDriveState),
        VMSTATE_UINT16(io, MicroDriveState),
        VMSTATE_UINT8(cycle, MicroDriveState),
        VMSTATE_IDE_BUS(bus, MicroDriveState),
        VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
        VMSTATE_END_OF_LIST()
    }
};

static const uint8_t dscm1xxxx_cis[0x14a] = {
    [0x000] = CISTPL_DEVICE,	/* 5V Device Information */
    [0x002] = 0x03,		/* Tuple length = 4 bytes */
    [0x004] = 0xdb,		/* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
    [0x006] = 0x01,		/* Size = 2K bytes */
    [0x008] = CISTPL_ENDMARK,

    [0x00a] = CISTPL_DEVICE_OC,	/* Additional Device Information */
    [0x00c] = 0x04,		/* Tuple length = 4 byest */
    [0x00e] = 0x03,		/* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
    [0x010] = 0xdb,		/* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
    [0x012] = 0x01,		/* Size = 2K bytes */
    [0x014] = CISTPL_ENDMARK,

    [0x016] = CISTPL_JEDEC_C,	/* JEDEC ID */
    [0x018] = 0x02,		/* Tuple length = 2 bytes */
    [0x01a] = 0xdf,		/* PC Card ATA with no Vpp required */
    [0x01c] = 0x01,

    [0x01e] = CISTPL_MANFID,	/* Manufacture ID */
    [0x020] = 0x04,		/* Tuple length = 4 bytes */
    [0x022] = 0xa4,		/* TPLMID_MANF = 00a4 (IBM) */
    [0x024] = 0x00,
    [0x026] = 0x00,		/* PLMID_CARD = 0000 */
    [0x028] = 0x00,

    [0x02a] = CISTPL_VERS_1,	/* Level 1 Version */
    [0x02c] = 0x12,		/* Tuple length = 23 bytes */
    [0x02e] = 0x04,		/* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
    [0x030] = 0x01,		/* Minor Version = 1 */
    [0x032] = 'I',
    [0x034] = 'B',
    [0x036] = 'M',
    [0x038] = 0x00,
    [0x03a] = 'm',
    [0x03c] = 'i',
    [0x03e] = 'c',
    [0x040] = 'r',
    [0x042] = 'o',
    [0x044] = 'd',
    [0x046] = 'r',
    [0x048] = 'i',
    [0x04a] = 'v',
    [0x04c] = 'e',
    [0x04e] = 0x00,
    [0x050] = CISTPL_ENDMARK,

    [0x052] = CISTPL_FUNCID,	/* Function ID */
    [0x054] = 0x02,		/* Tuple length = 2 bytes */
    [0x056] = 0x04,		/* TPLFID_FUNCTION = Fixed Disk */
    [0x058] = 0x01,		/* TPLFID_SYSINIT: POST = 1, ROM = 0 */

    [0x05a] = CISTPL_FUNCE,	/* Function Extension */
    [0x05c] = 0x02,		/* Tuple length = 2 bytes */
    [0x05e] = 0x01,		/* TPLFE_TYPE = Disk Device Interface */
    [0x060] = 0x01,		/* TPLFE_DATA = PC Card ATA Interface */

    [0x062] = CISTPL_FUNCE,	/* Function Extension */
    [0x064] = 0x03,		/* Tuple length = 3 bytes */
    [0x066] = 0x02,		/* TPLFE_TYPE = Basic PC Card ATA Interface */
    [0x068] = 0x08,		/* TPLFE_DATA: Rotating, Unique, Single */
    [0x06a] = 0x0f,		/* TPLFE_DATA: Sleep, Standby, Idle, Auto */

    [0x06c] = CISTPL_CONFIG,	/* Configuration */
    [0x06e] = 0x05,		/* Tuple length = 5 bytes */
    [0x070] = 0x01,		/* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
    [0x072] = 0x07,		/* TPCC_LAST = 7 */
    [0x074] = 0x00,		/* TPCC_RADR = 0200 */
    [0x076] = 0x02,
    [0x078] = 0x0f,		/* TPCC_RMSK = 200, 202, 204, 206 */

    [0x07a] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x07c] = 0x0b,		/* Tuple length = 11 bytes */
    [0x07e] = 0xc0,		/* TPCE_INDX = Memory Mode, Default, Iface */
    [0x080] = 0xc0,		/* TPCE_IF = Memory, no BVDs, no WP, READY */
    [0x082] = 0xa1,		/* TPCE_FS = Vcc only, no I/O, Memory, Misc */
    [0x084] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x086] = 0x55,		/* NomV: 5.0 V */
    [0x088] = 0x4d,		/* MinV: 4.5 V */
    [0x08a] = 0x5d,		/* MaxV: 5.5 V */
    [0x08c] = 0x4e,		/* Peakl: 450 mA */
    [0x08e] = 0x08,		/* TPCE_MS = 1 window, 1 byte, Host address */
    [0x090] = 0x00,		/* Window descriptor: Window length = 0 */
    [0x092] = 0x20,		/* TPCE_MI: support power down mode, RW */

    [0x094] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x096] = 0x06,		/* Tuple length = 6 bytes */
    [0x098] = 0x00,		/* TPCE_INDX = Memory Mode, no Default */
    [0x09a] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x09c] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x09e] = 0xb5,		/* NomV: 3.3 V */
    [0x0a0] = 0x1e,
    [0x0a2] = 0x3e,		/* Peakl: 350 mA */

    [0x0a4] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0a6] = 0x0d,		/* Tuple length = 13 bytes */
    [0x0a8] = 0xc1,		/* TPCE_INDX = I/O and Memory Mode, Default */
    [0x0aa] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x0ac] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x0ae] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x0b0] = 0x55,		/* NomV: 5.0 V */
    [0x0b2] = 0x4d,		/* MinV: 4.5 V */
    [0x0b4] = 0x5d,		/* MaxV: 5.5 V */
    [0x0b6] = 0x4e,		/* Peakl: 450 mA */
    [0x0b8] = 0x64,		/* TPCE_IO = 16-byte boundary, 16/8 accesses */
    [0x0ba] = 0xf0,		/* TPCE_IR =  MASK, Level, Pulse, Share */
    [0x0bc] = 0xff,		/* IRQ0..IRQ7 supported */
    [0x0be] = 0xff,		/* IRQ8..IRQ15 supported */
    [0x0c0] = 0x20,		/* TPCE_MI = support power down mode */

    [0x0c2] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0c4] = 0x06,		/* Tuple length = 6 bytes */
    [0x0c6] = 0x01,		/* TPCE_INDX = I/O and Memory Mode */
    [0x0c8] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x0ca] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x0cc] = 0xb5,		/* NomV: 3.3 V */
    [0x0ce] = 0x1e,
    [0x0d0] = 0x3e,		/* Peakl: 350 mA */

    [0x0d2] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0d4] = 0x12,		/* Tuple length = 18 bytes */
    [0x0d6] = 0xc2,		/* TPCE_INDX = I/O Primary Mode */
    [0x0d8] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x0da] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x0dc] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x0de] = 0x55,		/* NomV: 5.0 V */
    [0x0e0] = 0x4d,		/* MinV: 4.5 V */
    [0x0e2] = 0x5d,		/* MaxV: 5.5 V */
    [0x0e4] = 0x4e,		/* Peakl: 450 mA */
    [0x0e6] = 0xea,		/* TPCE_IO = 1K boundary, 16/8 access, Range */
    [0x0e8] = 0x61,		/* Range: 2 fields, 2 bytes addr, 1 byte len */
    [0x0ea] = 0xf0,		/* Field 1 address = 0x01f0 */
    [0x0ec] = 0x01,
    [0x0ee] = 0x07,		/* Address block length = 8 */
    [0x0f0] = 0xf6,		/* Field 2 address = 0x03f6 */
    [0x0f2] = 0x03,
    [0x0f4] = 0x01,		/* Address block length = 2 */
    [0x0f6] = 0xee,		/* TPCE_IR = IRQ E, Level, Pulse, Share */
    [0x0f8] = 0x20,		/* TPCE_MI = support power down mode */

    [0x0fa] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x0fc] = 0x06,		/* Tuple length = 6 bytes */
    [0x0fe] = 0x02,		/* TPCE_INDX = I/O Primary Mode, no Default */
    [0x100] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x102] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x104] = 0xb5,		/* NomV: 3.3 V */
    [0x106] = 0x1e,
    [0x108] = 0x3e,		/* Peakl: 350 mA */

    [0x10a] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x10c] = 0x12,		/* Tuple length = 18 bytes */
    [0x10e] = 0xc3,		/* TPCE_INDX = I/O Secondary Mode, Default */
    [0x110] = 0x41,		/* TPCE_IF = I/O and Memory, no BVD, no WP */
    [0x112] = 0x99,		/* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
    [0x114] = 0x27,		/* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
    [0x116] = 0x55,		/* NomV: 5.0 V */
    [0x118] = 0x4d,		/* MinV: 4.5 V */
    [0x11a] = 0x5d,		/* MaxV: 5.5 V */
    [0x11c] = 0x4e,		/* Peakl: 450 mA */
    [0x11e] = 0xea,		/* TPCE_IO = 1K boundary, 16/8 access, Range */
    [0x120] = 0x61,		/* Range: 2 fields, 2 byte addr, 1 byte len */
    [0x122] = 0x70,		/* Field 1 address = 0x0170 */
    [0x124] = 0x01,
    [0x126] = 0x07,		/* Address block length = 8 */
    [0x128] = 0x76,		/* Field 2 address = 0x0376 */
    [0x12a] = 0x03,
    [0x12c] = 0x01,		/* Address block length = 2 */
    [0x12e] = 0xee,		/* TPCE_IR = IRQ E, Level, Pulse, Share */
    [0x130] = 0x20,		/* TPCE_MI = support power down mode */

    [0x132] = CISTPL_CFTABLE_ENTRY,	/* 16-bit PC Card Configuration */
    [0x134] = 0x06,		/* Tuple length = 6 bytes */
    [0x136] = 0x03,		/* TPCE_INDX = I/O Secondary Mode */
    [0x138] = 0x01,		/* TPCE_FS = Vcc only, no I/O, no Memory */
    [0x13a] = 0x21,		/* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
    [0x13c] = 0xb5,		/* NomV: 3.3 V */
    [0x13e] = 0x1e,
    [0x140] = 0x3e,		/* Peakl: 350 mA */

    [0x142] = CISTPL_NO_LINK,	/* No Link */
    [0x144] = 0x00,		/* Tuple length = 0 bytes */

    [0x146] = CISTPL_END,	/* Tuple End */
};

#define TYPE_DSCM1XXXX "dscm1xxxx"

static int dscm1xxxx_attach(PCMCIACardState *card)
{
    MicroDriveState *md = MICRODRIVE(card);
    PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);

    md->attr_base = pcc->cis[0x74] | (pcc->cis[0x76] << 8);
    md->io_base = 0x0;

    device_reset(DEVICE(md));
    md_interrupt_update(md);

    card->slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
    return 0;
}

static int dscm1xxxx_detach(PCMCIACardState *card)
{
    MicroDriveState *md = MICRODRIVE(card);

    device_reset(DEVICE(md));
    return 0;
}

PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo)
{
    MicroDriveState *md = MICRODRIVE(object_new(TYPE_DSCM1XXXX));
    PCMCIACardState *card = PCMCIA_CARD(md);

    if (dinfo != NULL) {
        ide_create_drive(&md->bus, 0, dinfo);
    }
    md->bus.ifs[0].drive_kind = IDE_CFATA;
    md->bus.ifs[0].mdata_size = METADATA_SIZE;
    md->bus.ifs[0].mdata_storage = (uint8_t *) g_malloc0(METADATA_SIZE);

    return card;
}

static void dscm1xxxx_class_init(ObjectClass *oc, void *data)
{
    PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);

    pcc->cis = dscm1xxxx_cis;
    pcc->cis_len = sizeof(dscm1xxxx_cis);

    pcc->attach = dscm1xxxx_attach;
    pcc->detach = dscm1xxxx_detach;
}

static const TypeInfo dscm1xxxx_type_info = {
    .name = TYPE_DSCM1XXXX,
    .parent = TYPE_MICRODRIVE,
    .class_init = dscm1xxxx_class_init,
};

static void microdrive_realize(DeviceState *dev, Error **errp)
{
    MicroDriveState *md = MICRODRIVE(dev);

    ide_init2(&md->bus, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
}

static void microdrive_init(Object *obj)
{
    MicroDriveState *md = MICRODRIVE(obj);

    ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
}

static void microdrive_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);

    pcc->attr_read = md_attr_read;
    pcc->attr_write = md_attr_write;
    pcc->common_read = md_common_read;
    pcc->common_write = md_common_write;
    pcc->io_read = md_common_read;
    pcc->io_write = md_common_write;

    dc->realize = microdrive_realize;
    dc->reset = md_reset;
    dc->vmsd = &vmstate_microdrive;
}

static const TypeInfo microdrive_type_info = {
    .name = TYPE_MICRODRIVE,
    .parent = TYPE_PCMCIA_CARD,
    .instance_size = sizeof(MicroDriveState),
    .instance_init = microdrive_init,
    .abstract = true,
    .class_init = microdrive_class_init,
};

static void microdrive_register_types(void)
{
    type_register_static(&microdrive_type_info);
    type_register_static(&dscm1xxxx_type_info);
}

type_init(microdrive_register_types)
Commit	Line	Data
3f221c8d GH	1	/*
	2	* QEMU IDE Emulation: microdrive (CF / PCMCIA)
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	* Copyright (c) 2006 Openedhand Ltd.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
59f2a787	25	#include <hw/hw.h>
0d09e41a	26	#include <hw/i386/pc.h>
59f2a787	27	#include <hw/pcmcia.h>
737e150e	28	#include "block/block.h"
9c17d615	29	#include "sysemu/dma.h"
59f2a787 GH	30
59f2a787 GH	31	#include <hw/ide/internal.h>
3f221c8d	32
d1f2c96a AF	33	#define TYPE_MICRODRIVE "microdrive"
	34	#define MICRODRIVE(obj) OBJECT_CHECK(MicroDriveState, (obj), TYPE_MICRODRIVE)
	35
3f221c8d GH	36	/***********************************************************/
	37	/* CF-ATA Microdrive */
	38
	39	#define METADATA_SIZE 0x20
	40
	41	/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface. */
d1f2c96a AF	42
	43	typedef struct MicroDriveState {
	44	/< private >/
	45	PCMCIACardState parent_obj;
	46	/< public >/
	47
3f221c8d	48	IDEBus bus;
3f221c8d GH	49	uint32_t attr_base;
	50	uint32_t io_base;
	51
	52	/* Card state */
	53	uint8_t opt;
	54	uint8_t stat;
	55	uint8_t pins;
	56
	57	uint8_t ctrl;
	58	uint16_t io;
8a72f380	59	uint8_t cycle;
3f221c8d GH	60	} MicroDriveState;
	61
	62	/* Register bitfields */
	63	enum md_opt {
	64	OPT_MODE_MMAP = 0,
	65	OPT_MODE_IOMAP16 = 1,
	66	OPT_MODE_IOMAP1 = 2,
	67	OPT_MODE_IOMAP2 = 3,
	68	OPT_MODE = 0x3f,
	69	OPT_LEVIREQ = 0x40,
	70	OPT_SRESET = 0x80,
	71	};
	72	enum md_cstat {
	73	STAT_INT = 0x02,
	74	STAT_PWRDWN = 0x04,
	75	STAT_XE = 0x10,
	76	STAT_IOIS8 = 0x20,
	77	STAT_SIGCHG = 0x40,
	78	STAT_CHANGED = 0x80,
	79	};
	80	enum md_pins {
	81	PINS_MRDY = 0x02,
	82	PINS_CRDY = 0x20,
	83	};
	84	enum md_ctrl {
	85	CTRL_IEN = 0x02,
	86	CTRL_SRST = 0x04,
	87	};
	88
	89	static inline void md_interrupt_update(MicroDriveState *s)
	90	{
d1f2c96a AF	91	PCMCIACardState *card = PCMCIA_CARD(s);
	92
	93	if (card->slot == NULL) {
3f221c8d	94	return;
d1f2c96a	95	}
3f221c8d	96
d1f2c96a	97	qemu_set_irq(card->slot->irq,
3f221c8d GH	98	!(s->stat & STAT_INT) && /* Inverted */
	99	!(s->ctrl & (CTRL_IEN \| CTRL_SRST)) &&
	100	!(s->opt & OPT_SRESET));
	101	}
	102
	103	static void md_set_irq(void *opaque, int irq, int level)
	104	{
18c0fb30	105	MicroDriveState *s = opaque;
3f221c8d GH	106	if (level)
	107	s->stat \|= STAT_INT;
	108	else
	109	s->stat &= ~STAT_INT;
	110
	111	md_interrupt_update(s);
	112	}
	113
d1f2c96a	114	static void md_reset(DeviceState *dev)
3f221c8d	115	{
d1f2c96a AF	116	MicroDriveState *s = MICRODRIVE(dev);
d1f2c96a AF	117
3f221c8d GH	118	s->opt = OPT_MODE_MMAP;
	119	s->stat = 0;
	120	s->pins = 0;
	121	s->cycle = 0;
	122	s->ctrl = 0;
4a643563	123	ide_bus_reset(&s->bus);
3f221c8d GH	124	}
3f221c8d GH	125
d1f2c96a	126	static uint8_t md_attr_read(PCMCIACardState *card, uint32_t at)
3f221c8d	127	{
d1f2c96a AF	128	MicroDriveState *s = MICRODRIVE(card);
	129	PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
	130
3f221c8d	131	if (at < s->attr_base) {
d1f2c96a AF	132	if (at < pcc->cis_len) {
	133	return pcc->cis[at];
	134	} else {
3f221c8d	135	return 0x00;
d1f2c96a	136	}
3f221c8d GH	137	}
	138
	139	at -= s->attr_base;
	140
	141	switch (at) {
	142	case 0x00: /* Configuration Option Register */
	143	return s->opt;
	144	case 0x02: /* Card Configuration Status Register */
	145	if (s->ctrl & CTRL_IEN)
	146	return s->stat & ~STAT_INT;
	147	else
	148	return s->stat;
	149	case 0x04: /* Pin Replacement Register */
	150	return (s->pins & PINS_CRDY) \| 0x0c;
	151	case 0x06: /* Socket and Copy Register */
	152	return 0x00;
	153	#ifdef VERBOSE
	154	default:
	155	printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
	156	#endif
	157	}
	158
	159	return 0;
	160	}
	161
d1f2c96a	162	static void md_attr_write(PCMCIACardState *card, uint32_t at, uint8_t value)
3f221c8d	163	{
d1f2c96a AF	164	MicroDriveState *s = MICRODRIVE(card);
d1f2c96a AF	165
3f221c8d GH	166	at -= s->attr_base;
	167
	168	switch (at) {
	169	case 0x00: /* Configuration Option Register */
	170	s->opt = value & 0xcf;
d1f2c96a AF	171	if (value & OPT_SRESET) {
	172	device_reset(DEVICE(s));
	173	}
3f221c8d GH	174	md_interrupt_update(s);
	175	break;
	176	case 0x02: /* Card Configuration Status Register */
	177	if ((s->stat ^ value) & STAT_PWRDWN)
	178	s->pins \|= PINS_CRDY;
	179	s->stat &= 0x82;
	180	s->stat \|= value & 0x74;
	181	md_interrupt_update(s);
	182	/* Word 170 in Identify Device must be equal to STAT_XE */
	183	break;
	184	case 0x04: /* Pin Replacement Register */
	185	s->pins &= PINS_CRDY;
	186	s->pins \|= value & PINS_MRDY;
	187	break;
	188	case 0x06: /* Socket and Copy Register */
	189	break;
	190	default:
	191	printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
	192	}
	193	}
	194
d1f2c96a	195	static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
3f221c8d	196	{
d1f2c96a	197	MicroDriveState *s = MICRODRIVE(card);
3f221c8d GH	198	IDEState *ifs;
	199	uint16_t ret;
	200	at -= s->io_base;
	201
	202	switch (s->opt & OPT_MODE) {
	203	case OPT_MODE_MMAP:
	204	if ((at & ~0x3ff) == 0x400)
	205	at = 0;
	206	break;
	207	case OPT_MODE_IOMAP16:
	208	at &= 0xf;
	209	break;
	210	case OPT_MODE_IOMAP1:
	211	if ((at & ~0xf) == 0x3f0)
	212	at -= 0x3e8;
	213	else if ((at & ~0xf) == 0x1f0)
	214	at -= 0x1f0;
	215	break;
	216	case OPT_MODE_IOMAP2:
	217	if ((at & ~0xf) == 0x370)
	218	at -= 0x368;
	219	else if ((at & ~0xf) == 0x170)
	220	at -= 0x170;
	221	}
	222
	223	switch (at) {
	224	case 0x0: /* Even RD Data */
	225	case 0x8:
	226	return ide_data_readw(&s->bus, 0);
	227
	228	/* TODO: 8-bit accesses */
	229	if (s->cycle)
	230	ret = s->io >> 8;
	231	else {
	232	s->io = ide_data_readw(&s->bus, 0);
	233	ret = s->io & 0xff;
	234	}
	235	s->cycle = !s->cycle;
	236	return ret;
	237	case 0x9: /* Odd RD Data */
	238	return s->io >> 8;
	239	case 0xd: /* Error */
	240	return ide_ioport_read(&s->bus, 0x1);
	241	case 0xe: /* Alternate Status */
	242	ifs = idebus_active_if(&s->bus);
	243	if (ifs->bs)
	244	return ifs->status;
	245	else
	246	return 0;
	247	case 0xf: /* Device Address */
	248	ifs = idebus_active_if(&s->bus);
	249	return 0xc2 \| ((~ifs->select << 2) & 0x3c);
	250	default:
	251	return ide_ioport_read(&s->bus, at);
	252	}
	253
	254	return 0;
	255	}
	256
d1f2c96a	257	static void md_common_write(PCMCIACardState *card, uint32_t at, uint16_t value)
3f221c8d	258	{
d1f2c96a	259	MicroDriveState *s = MICRODRIVE(card);
3f221c8d GH	260	at -= s->io_base;
	261
	262	switch (s->opt & OPT_MODE) {
	263	case OPT_MODE_MMAP:
	264	if ((at & ~0x3ff) == 0x400)
	265	at = 0;
	266	break;
	267	case OPT_MODE_IOMAP16:
	268	at &= 0xf;
	269	break;
	270	case OPT_MODE_IOMAP1:
	271	if ((at & ~0xf) == 0x3f0)
	272	at -= 0x3e8;
	273	else if ((at & ~0xf) == 0x1f0)
	274	at -= 0x1f0;
	275	break;
	276	case OPT_MODE_IOMAP2:
	277	if ((at & ~0xf) == 0x370)
	278	at -= 0x368;
	279	else if ((at & ~0xf) == 0x170)
	280	at -= 0x170;
	281	}
	282
	283	switch (at) {
	284	case 0x0: /* Even WR Data */
	285	case 0x8:
	286	ide_data_writew(&s->bus, 0, value);
	287	break;
	288
	289	/* TODO: 8-bit accesses */
	290	if (s->cycle)
	291	ide_data_writew(&s->bus, 0, s->io \| (value << 8));
	292	else
	293	s->io = value & 0xff;
	294	s->cycle = !s->cycle;
	295	break;
	296	case 0x9:
	297	s->io = value & 0xff;
	298	s->cycle = !s->cycle;
	299	break;
	300	case 0xd: /* Features */
	301	ide_ioport_write(&s->bus, 0x1, value);
	302	break;
	303	case 0xe: /* Device Control */
	304	s->ctrl = value;
d1f2c96a AF	305	if (value & CTRL_SRST) {
	306	device_reset(DEVICE(s));
	307	}
3f221c8d GH	308	md_interrupt_update(s);
	309	break;
	310	default:
	311	if (s->stat & STAT_PWRDWN) {
	312	s->pins \|= PINS_CRDY;
	313	s->stat &= ~STAT_PWRDWN;
	314	}
	315	ide_ioport_write(&s->bus, at, value);
	316	}
	317	}
	318
d05ac8fa	319	static const VMStateDescription vmstate_microdrive = {
5f637ce0 JQ	320	.name = "microdrive",
	321	.version_id = 3,
	322	.minimum_version_id = 0,
	323	.minimum_version_id_old = 0,
	324	.fields = (VMStateField []) {
	325	VMSTATE_UINT8(opt, MicroDriveState),
	326	VMSTATE_UINT8(stat, MicroDriveState),
	327	VMSTATE_UINT8(pins, MicroDriveState),
	328	VMSTATE_UINT8(ctrl, MicroDriveState),
	329	VMSTATE_UINT16(io, MicroDriveState),
	330	VMSTATE_UINT8(cycle, MicroDriveState),
	331	VMSTATE_IDE_BUS(bus, MicroDriveState),
	332	VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
	333	VMSTATE_END_OF_LIST()
	334	}
	335	};
3f221c8d GH	336
	337	static const uint8_t dscm1xxxx_cis[0x14a] = {
	338	[0x000] = CISTPL_DEVICE, /* 5V Device Information */
	339	[0x002] = 0x03, /* Tuple length = 4 bytes */
	340	[0x004] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
	341	[0x006] = 0x01, /* Size = 2K bytes */
	342	[0x008] = CISTPL_ENDMARK,
	343
	344	[0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
	345	[0x00c] = 0x04, /* Tuple length = 4 byest */
	346	[0x00e] = 0x03, /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
	347	[0x010] = 0xdb, /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
	348	[0x012] = 0x01, /* Size = 2K bytes */
	349	[0x014] = CISTPL_ENDMARK,
	350
	351	[0x016] = CISTPL_JEDEC_C, /* JEDEC ID */
	352	[0x018] = 0x02, /* Tuple length = 2 bytes */
	353	[0x01a] = 0xdf, /* PC Card ATA with no Vpp required */
	354	[0x01c] = 0x01,
	355
	356	[0x01e] = CISTPL_MANFID, /* Manufacture ID */
	357	[0x020] = 0x04, /* Tuple length = 4 bytes */
	358	[0x022] = 0xa4, /* TPLMID_MANF = 00a4 (IBM) */
	359	[0x024] = 0x00,
	360	[0x026] = 0x00, /* PLMID_CARD = 0000 */
	361	[0x028] = 0x00,
	362
	363	[0x02a] = CISTPL_VERS_1, /* Level 1 Version */
	364	[0x02c] = 0x12, /* Tuple length = 23 bytes */
	365	[0x02e] = 0x04, /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
	366	[0x030] = 0x01, /* Minor Version = 1 */
	367	[0x032] = 'I',
	368	[0x034] = 'B',
	369	[0x036] = 'M',
	370	[0x038] = 0x00,
	371	[0x03a] = 'm',
	372	[0x03c] = 'i',
	373	[0x03e] = 'c',
	374	[0x040] = 'r',
	375	[0x042] = 'o',
	376	[0x044] = 'd',
	377	[0x046] = 'r',
	378	[0x048] = 'i',
	379	[0x04a] = 'v',
	380	[0x04c] = 'e',
	381	[0x04e] = 0x00,
	382	[0x050] = CISTPL_ENDMARK,
	383
	384	[0x052] = CISTPL_FUNCID, /* Function ID */
	385	[0x054] = 0x02, /* Tuple length = 2 bytes */
	386	[0x056] = 0x04, /* TPLFID_FUNCTION = Fixed Disk */
	387	[0x058] = 0x01, /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
	388
	389	[0x05a] = CISTPL_FUNCE, /* Function Extension */
	390	[0x05c] = 0x02, /* Tuple length = 2 bytes */
	391	[0x05e] = 0x01, /* TPLFE_TYPE = Disk Device Interface */
	392	[0x060] = 0x01, /* TPLFE_DATA = PC Card ATA Interface */
	393
	394	[0x062] = CISTPL_FUNCE, /* Function Extension */
	395	[0x064] = 0x03, /* Tuple length = 3 bytes */
	396	[0x066] = 0x02, /* TPLFE_TYPE = Basic PC Card ATA Interface */
	397	[0x068] = 0x08, /* TPLFE_DATA: Rotating, Unique, Single */
	398	[0x06a] = 0x0f, /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
	399
400	[0x06c] = CISTPL_CONFIG, /* Configuration */
401	[0x06e] = 0x05, /* Tuple length = 5 bytes */
402	[0x070] = 0x01, /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
403	[0x072] = 0x07, /* TPCC_LAST = 7 */
404	[0x074] = 0x00, /* TPCC_RADR = 0200 */
405	[0x076] = 0x02,
406	[0x078] = 0x0f, /* TPCC_RMSK = 200, 202, 204, 206 */
407
408	[0x07a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
409	[0x07c] = 0x0b, /* Tuple length = 11 bytes */
410	[0x07e] = 0xc0, /* TPCE_INDX = Memory Mode, Default, Iface */
411	[0x080] = 0xc0, /* TPCE_IF = Memory, no BVDs, no WP, READY */
412	[0x082] = 0xa1, /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
413	[0x084] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
414	[0x086] = 0x55, /* NomV: 5.0 V */
415	[0x088] = 0x4d, /* MinV: 4.5 V */
416	[0x08a] = 0x5d, /* MaxV: 5.5 V */
417	[0x08c] = 0x4e, /* Peakl: 450 mA */
418	[0x08e] = 0x08, /* TPCE_MS = 1 window, 1 byte, Host address */
419	[0x090] = 0x00, /* Window descriptor: Window length = 0 */
420	[0x092] = 0x20, /* TPCE_MI: support power down mode, RW */
421
422	[0x094] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
423	[0x096] = 0x06, /* Tuple length = 6 bytes */
424	[0x098] = 0x00, /* TPCE_INDX = Memory Mode, no Default */
425	[0x09a] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
426	[0x09c] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
427	[0x09e] = 0xb5, /* NomV: 3.3 V */
428	[0x0a0] = 0x1e,
429	[0x0a2] = 0x3e, /* Peakl: 350 mA */
430
431	[0x0a4] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
432	[0x0a6] = 0x0d, /* Tuple length = 13 bytes */
433	[0x0a8] = 0xc1, /* TPCE_INDX = I/O and Memory Mode, Default */
434	[0x0aa] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
435	[0x0ac] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
436	[0x0ae] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
437	[0x0b0] = 0x55, /* NomV: 5.0 V */
438	[0x0b2] = 0x4d, /* MinV: 4.5 V */
439	[0x0b4] = 0x5d, /* MaxV: 5.5 V */
440	[0x0b6] = 0x4e, /* Peakl: 450 mA */
441	[0x0b8] = 0x64, /* TPCE_IO = 16-byte boundary, 16/8 accesses */
442	[0x0ba] = 0xf0, /* TPCE_IR = MASK, Level, Pulse, Share */
443	[0x0bc] = 0xff, /* IRQ0..IRQ7 supported */
444	[0x0be] = 0xff, /* IRQ8..IRQ15 supported */
445	[0x0c0] = 0x20, /* TPCE_MI = support power down mode */
446
447	[0x0c2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
448	[0x0c4] = 0x06, /* Tuple length = 6 bytes */
449	[0x0c6] = 0x01, /* TPCE_INDX = I/O and Memory Mode */
450	[0x0c8] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
451	[0x0ca] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
452	[0x0cc] = 0xb5, /* NomV: 3.3 V */
453	[0x0ce] = 0x1e,
454	[0x0d0] = 0x3e, /* Peakl: 350 mA */
455
456	[0x0d2] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
457	[0x0d4] = 0x12, /* Tuple length = 18 bytes */
458	[0x0d6] = 0xc2, /* TPCE_INDX = I/O Primary Mode */
459	[0x0d8] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
460	[0x0da] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
461	[0x0dc] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
462	[0x0de] = 0x55, /* NomV: 5.0 V */
463	[0x0e0] = 0x4d, /* MinV: 4.5 V */
464	[0x0e2] = 0x5d, /* MaxV: 5.5 V */
465	[0x0e4] = 0x4e, /* Peakl: 450 mA */
466	[0x0e6] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
467	[0x0e8] = 0x61, /* Range: 2 fields, 2 bytes addr, 1 byte len */
468	[0x0ea] = 0xf0, /* Field 1 address = 0x01f0 */
469	[0x0ec] = 0x01,
470	[0x0ee] = 0x07, /* Address block length = 8 */
471	[0x0f0] = 0xf6, /* Field 2 address = 0x03f6 */
472	[0x0f2] = 0x03,
473	[0x0f4] = 0x01, /* Address block length = 2 */
474	[0x0f6] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
475	[0x0f8] = 0x20, /* TPCE_MI = support power down mode */
476
477	[0x0fa] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
478	[0x0fc] = 0x06, /* Tuple length = 6 bytes */
479	[0x0fe] = 0x02, /* TPCE_INDX = I/O Primary Mode, no Default */
480	[0x100] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
481	[0x102] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
482	[0x104] = 0xb5, /* NomV: 3.3 V */
483	[0x106] = 0x1e,
484	[0x108] = 0x3e, /* Peakl: 350 mA */
485
486	[0x10a] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
487	[0x10c] = 0x12, /* Tuple length = 18 bytes */
488	[0x10e] = 0xc3, /* TPCE_INDX = I/O Secondary Mode, Default */
489	[0x110] = 0x41, /* TPCE_IF = I/O and Memory, no BVD, no WP */
490	[0x112] = 0x99, /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
491	[0x114] = 0x27, /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
492	[0x116] = 0x55, /* NomV: 5.0 V */
493	[0x118] = 0x4d, /* MinV: 4.5 V */
494	[0x11a] = 0x5d, /* MaxV: 5.5 V */
495	[0x11c] = 0x4e, /* Peakl: 450 mA */
496	[0x11e] = 0xea, /* TPCE_IO = 1K boundary, 16/8 access, Range */
497	[0x120] = 0x61, /* Range: 2 fields, 2 byte addr, 1 byte len */
498	[0x122] = 0x70, /* Field 1 address = 0x0170 */
499	[0x124] = 0x01,
500	[0x126] = 0x07, /* Address block length = 8 */
501	[0x128] = 0x76, /* Field 2 address = 0x0376 */
502	[0x12a] = 0x03,
503	[0x12c] = 0x01, /* Address block length = 2 */
504	[0x12e] = 0xee, /* TPCE_IR = IRQ E, Level, Pulse, Share */
505	[0x130] = 0x20, /* TPCE_MI = support power down mode */
506
507	[0x132] = CISTPL_CFTABLE_ENTRY, /* 16-bit PC Card Configuration */
508	[0x134] = 0x06, /* Tuple length = 6 bytes */
509	[0x136] = 0x03, /* TPCE_INDX = I/O Secondary Mode */
510	[0x138] = 0x01, /* TPCE_FS = Vcc only, no I/O, no Memory */
511	[0x13a] = 0x21, /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
512	[0x13c] = 0xb5, /* NomV: 3.3 V */
513	[0x13e] = 0x1e,
514	[0x140] = 0x3e, /* Peakl: 350 mA */
515
516	[0x142] = CISTPL_NO_LINK, /* No Link */
517	[0x144] = 0x00, /* Tuple length = 0 bytes */
518
519	[0x146] = CISTPL_END, /* Tuple End */
520	};
521
d1f2c96a AF	522	#define TYPE_DSCM1XXXX "dscm1xxxx"
	523
	524	static int dscm1xxxx_attach(PCMCIACardState *card)
3f221c8d	525	{
d1f2c96a AF	526	MicroDriveState *md = MICRODRIVE(card);
	527	PCMCIACardClass *pcc = PCMCIA_CARD_GET_CLASS(card);
	528
	529	md->attr_base = pcc->cis[0x74] \| (pcc->cis[0x76] << 8);
3f221c8d GH	530	md->io_base = 0x0;
3f221c8d GH	531
d1f2c96a	532	device_reset(DEVICE(md));
3f221c8d GH	533	md_interrupt_update(md);
3f221c8d GH	534
d1f2c96a	535	card->slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
3f221c8d GH	536	return 0;
	537	}
	538
d1f2c96a	539	static int dscm1xxxx_detach(PCMCIACardState *card)
3f221c8d	540	{
d1f2c96a AF	541	MicroDriveState *md = MICRODRIVE(card);
	542
	543	device_reset(DEVICE(md));
3f221c8d GH	544	return 0;
	545	}
	546
d1f2c96a	547	PCMCIACardState dscm1xxxx_init(DriveInfo dinfo)
3f221c8d	548	{
d1f2c96a AF	549	MicroDriveState *md = MICRODRIVE(object_new(TYPE_DSCM1XXXX));
	550	PCMCIACardState *card = PCMCIA_CARD(md);
	551
	552	if (dinfo != NULL) {
	553	ide_create_drive(&md->bus, 0, dinfo);
	554	}
cd8722bb	555	md->bus.ifs[0].drive_kind = IDE_CFATA;
3f221c8d	556	md->bus.ifs[0].mdata_size = METADATA_SIZE;
7267c094	557	md->bus.ifs[0].mdata_storage = (uint8_t *) g_malloc0(METADATA_SIZE);
3f221c8d	558
d1f2c96a AF	559	return card;
	560	}
	561
	562	static void dscm1xxxx_class_init(ObjectClass oc, void data)
	563	{
	564	PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
	565
	566	pcc->cis = dscm1xxxx_cis;
	567	pcc->cis_len = sizeof(dscm1xxxx_cis);
	568
	569	pcc->attach = dscm1xxxx_attach;
	570	pcc->detach = dscm1xxxx_detach;
	571	}
	572
	573	static const TypeInfo dscm1xxxx_type_info = {
	574	.name = TYPE_DSCM1XXXX,
	575	.parent = TYPE_MICRODRIVE,
	576	.class_init = dscm1xxxx_class_init,
	577	};
	578
	579	static void microdrive_realize(DeviceState dev, Error *errp)
	580	{
	581	MicroDriveState *md = MICRODRIVE(dev);
	582
	583	ide_init2(&md->bus, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
	584	}
	585
	586	static void microdrive_init(Object *obj)
	587	{
	588	MicroDriveState *md = MICRODRIVE(obj);
	589
	590	ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
	591	}
3f221c8d	592
d1f2c96a AF	593	static void microdrive_class_init(ObjectClass oc, void data)
	594	{
	595	DeviceClass *dc = DEVICE_CLASS(oc);
	596	PCMCIACardClass *pcc = PCMCIA_CARD_CLASS(oc);
	597
	598	pcc->attr_read = md_attr_read;
	599	pcc->attr_write = md_attr_write;
	600	pcc->common_read = md_common_read;
	601	pcc->common_write = md_common_write;
	602	pcc->io_read = md_common_read;
	603	pcc->io_write = md_common_write;
	604
	605	dc->realize = microdrive_realize;
	606	dc->reset = md_reset;
	607	dc->vmsd = &vmstate_microdrive;
3f221c8d	608	}
d1f2c96a AF	609
	610	static const TypeInfo microdrive_type_info = {
	611	.name = TYPE_MICRODRIVE,
	612	.parent = TYPE_PCMCIA_CARD,
	613	.instance_size = sizeof(MicroDriveState),
	614	.instance_init = microdrive_init,
	615	.abstract = true,
	616	.class_init = microdrive_class_init,
	617	};
	618
	619	static void microdrive_register_types(void)
	620	{
	621	type_register_static(&microdrive_type_info);
	622	type_register_static(&dscm1xxxx_type_info);
	623	}
	624
	625	type_init(microdrive_register_types)