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Add and use #defines for PCI device classes
[qemu.git] / hw / vmware_vga.c
CommitLineData
d34cab9f
TS		 1/*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <[email protected]>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b
PB		 24#include "hw.h"
25#include "console.h"
26#include "pci.h"
d34cab9f
TS		 27
28#define VERBOSE
29#define EMBED_STDVGA
30#undef DIRECT_VRAM
31#define HW_RECT_ACCEL
32#define HW_FILL_ACCEL
33#define HW_MOUSE_ACCEL
34
35#ifdef EMBED_STDVGA
36# include "vga_int.h"
37#endif
38
39struct vmsvga_state_s {
40#ifdef EMBED_STDVGA
41 VGA_STATE_COMMON
42#endif
43
44 int width;
45 int height;
46 int invalidated;
47 int depth;
48 int bypp;
49 int enable;
50 int config;
51 struct {
52 int id;
53 int x;
54 int y;
55 int on;
56 } cursor;
57
58#ifndef EMBED_STDVGA
59 DisplayState *ds;
60 int vram_size;
6f9bc132 61 ram_addr_t vram_offset;
d34cab9f
TS		 62#endif
63 uint8_t *vram;
3016d80b 64 target_phys_addr_t vram_base;
d34cab9f
TS		 65
66 int index;
67 int scratch_size;
68 uint32_t *scratch;
69 int new_width;
70 int new_height;
71 uint32_t guest;
72 uint32_t svgaid;
73 uint32_t wred;
74 uint32_t wgreen;
75 uint32_t wblue;
76 int syncing;
77 int fb_size;
78
79 union {
80 uint32_t *fifo;
81 struct __attribute__((__packed__)) {
82 uint32_t min;
83 uint32_t max;
84 uint32_t next_cmd;
85 uint32_t stop;
86 /* Add registers here when adding capabilities. */
87 uint32_t fifo[0];
88 } *cmd;
89 };
90
91#define REDRAW_FIFO_LEN 512
92 struct vmsvga_rect_s {
93 int x, y, w, h;
94 } redraw_fifo[REDRAW_FIFO_LEN];
95 int redraw_fifo_first, redraw_fifo_last;
96};
97
98struct pci_vmsvga_state_s {
99 PCIDevice card;
100 struct vmsvga_state_s chip;
101};
102
103#define SVGA_MAGIC 0x900000UL
104#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
105#define SVGA_ID_0 SVGA_MAKE_ID(0)
106#define SVGA_ID_1 SVGA_MAKE_ID(1)
107#define SVGA_ID_2 SVGA_MAKE_ID(2)
108
109#define SVGA_LEGACY_BASE_PORT 0x4560
110#define SVGA_INDEX_PORT 0x0
111#define SVGA_VALUE_PORT 0x1
112#define SVGA_BIOS_PORT 0x2
113
114#define SVGA_VERSION_2
115
116#ifdef SVGA_VERSION_2
117# define SVGA_ID SVGA_ID_2
118# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
119# define SVGA_IO_MUL 1
120# define SVGA_FIFO_SIZE 0x10000
1f72aae5 121# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 122# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
123#else
124# define SVGA_ID SVGA_ID_1
125# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
126# define SVGA_IO_MUL 4
127# define SVGA_FIFO_SIZE 0x10000
1f72aae5 128# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 129# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
130#endif
131
132enum {
133 /* ID 0, 1 and 2 registers */
134 SVGA_REG_ID = 0,
135 SVGA_REG_ENABLE = 1,
136 SVGA_REG_WIDTH = 2,
137 SVGA_REG_HEIGHT = 3,
138 SVGA_REG_MAX_WIDTH = 4,
139 SVGA_REG_MAX_HEIGHT = 5,
140 SVGA_REG_DEPTH = 6,
141 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
142 SVGA_REG_PSEUDOCOLOR = 8,
143 SVGA_REG_RED_MASK = 9,
144 SVGA_REG_GREEN_MASK = 10,
145 SVGA_REG_BLUE_MASK = 11,
146 SVGA_REG_BYTES_PER_LINE = 12,
147 SVGA_REG_FB_START = 13,
148 SVGA_REG_FB_OFFSET = 14,
149 SVGA_REG_VRAM_SIZE = 15,
150 SVGA_REG_FB_SIZE = 16,
151
152 /* ID 1 and 2 registers */
153 SVGA_REG_CAPABILITIES = 17,
154 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
155 SVGA_REG_MEM_SIZE = 19,
156 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
157 SVGA_REG_SYNC = 21, /* Write to force synchronization */
158 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
159 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
160 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
161 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
162 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
163 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
164 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
165 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
166 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
167 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
168 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
169
170 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
171 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
172 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
173};
174
175#define SVGA_CAP_NONE 0
176#define SVGA_CAP_RECT_FILL (1 << 0)
177#define SVGA_CAP_RECT_COPY (1 << 1)
178#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
179#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
180#define SVGA_CAP_RASTER_OP (1 << 4)
181#define SVGA_CAP_CURSOR (1 << 5)
182#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
183#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
184#define SVGA_CAP_8BIT_EMULATION (1 << 8)
185#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
186#define SVGA_CAP_GLYPH (1 << 10)
187#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
188#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
189#define SVGA_CAP_ALPHA_BLEND (1 << 13)
190#define SVGA_CAP_3D (1 << 14)
191#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
192#define SVGA_CAP_MULTIMON (1 << 16)
193#define SVGA_CAP_PITCHLOCK (1 << 17)
194
195/*
196 * FIFO offsets (seen as an array of 32-bit words)
197 */
198enum {
199 /*
200 * The original defined FIFO offsets
201 */
202 SVGA_FIFO_MIN = 0,
203 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
204 SVGA_FIFO_NEXT_CMD,
205 SVGA_FIFO_STOP,
206
207 /*
208 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
209 */
210 SVGA_FIFO_CAPABILITIES = 4,
211 SVGA_FIFO_FLAGS,
212 SVGA_FIFO_FENCE,
213 SVGA_FIFO_3D_HWVERSION,
214 SVGA_FIFO_PITCHLOCK,
215};
216
217#define SVGA_FIFO_CAP_NONE 0
218#define SVGA_FIFO_CAP_FENCE (1 << 0)
219#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
220#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
221
222#define SVGA_FIFO_FLAG_NONE 0
223#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
224
225/* These values can probably be changed arbitrarily. */
226#define SVGA_SCRATCH_SIZE 0x8000
227#define SVGA_MAX_WIDTH 2360
228#define SVGA_MAX_HEIGHT 1770
229
230#ifdef VERBOSE
231# define GUEST_OS_BASE 0x5001
232static const char *vmsvga_guest_id[] = {
f707cfba
AZ		 233 [0x00 ... 0x15] = "an unknown OS",
234 [0x00] = "Dos",
235 [0x01] = "Windows 3.1",
236 [0x02] = "Windows 95",
237 [0x03] = "Windows 98",
238 [0x04] = "Windows ME",
239 [0x05] = "Windows NT",
240 [0x06] = "Windows 2000",
241 [0x07] = "Linux",
242 [0x08] = "OS/2",
243 [0x0a] = "BSD",
244 [0x0b] = "Whistler",
245 [0x15] = "Windows 2003",
d34cab9f
TS		 246};
247#endif
248
249enum {
250 SVGA_CMD_INVALID_CMD = 0,
251 SVGA_CMD_UPDATE = 1,
252 SVGA_CMD_RECT_FILL = 2,
253 SVGA_CMD_RECT_COPY = 3,
254 SVGA_CMD_DEFINE_BITMAP = 4,
255 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
256 SVGA_CMD_DEFINE_PIXMAP = 6,
257 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
258 SVGA_CMD_RECT_BITMAP_FILL = 8,
259 SVGA_CMD_RECT_PIXMAP_FILL = 9,
260 SVGA_CMD_RECT_BITMAP_COPY = 10,
261 SVGA_CMD_RECT_PIXMAP_COPY = 11,
262 SVGA_CMD_FREE_OBJECT = 12,
263 SVGA_CMD_RECT_ROP_FILL = 13,
264 SVGA_CMD_RECT_ROP_COPY = 14,
265 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
266 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
267 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
268 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
269 SVGA_CMD_DEFINE_CURSOR = 19,
270 SVGA_CMD_DISPLAY_CURSOR = 20,
271 SVGA_CMD_MOVE_CURSOR = 21,
272 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
273 SVGA_CMD_DRAW_GLYPH = 23,
274 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
275 SVGA_CMD_UPDATE_VERBOSE = 25,
276 SVGA_CMD_SURFACE_FILL = 26,
277 SVGA_CMD_SURFACE_COPY = 27,
278 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
279 SVGA_CMD_FRONT_ROP_FILL = 29,
280 SVGA_CMD_FENCE = 30,
281};
282
283/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
284enum {
285 SVGA_CURSOR_ON_HIDE = 0,
286 SVGA_CURSOR_ON_SHOW = 1,
287 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
288 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
289};
290
291static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
292 int x, int y, int w, int h)
293{
294#ifndef DIRECT_VRAM
a8fbaf96
AZ		 295 int line;
296 int bypl;
297 int width;
298 int start;
299 uint8_t *src;
300 uint8_t *dst;
301
302 if (x + w > s->width) {
303 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
304 __FUNCTION__, x, w);
305 x = MIN(x, s->width);
306 w = s->width - x;
307 }
308
309 if (y + h > s->height) {
310 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
311 __FUNCTION__, y, h);
312 y = MIN(y, s->height);
313 h = s->height - y;
314 }
315
316 line = h;
317 bypl = s->bypp * s->width;
318 width = s->bypp * w;
319 start = s->bypp * x + bypl * y;
320 src = s->vram + start;
0e1f5a0c 321 dst = ds_get_data(s->ds) + start;
d34cab9f
TS		 322
323 for (; line > 0; line --, src += bypl, dst += bypl)
324 memcpy(dst, src, width);
325#endif
326
327 dpy_update(s->ds, x, y, w, h);
328}
329
330static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
331{
332#ifndef DIRECT_VRAM
0e1f5a0c 333 memcpy(ds_get_data(s->ds), s->vram, s->bypp * s->width * s->height);
d34cab9f
TS		 334#endif
335
336 dpy_update(s->ds, 0, 0, s->width, s->height);
337}
338
339#ifdef DIRECT_VRAM
340# define vmsvga_update_rect_delayed vmsvga_update_rect
341#else
342static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
343 int x, int y, int w, int h)
344{
345 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
346 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
347 rect->x = x;
348 rect->y = y;
349 rect->w = w;
350 rect->h = h;
351}
352#endif
353
354static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
355{
356 struct vmsvga_rect_s *rect;
357 if (s->invalidated) {
358 s->redraw_fifo_first = s->redraw_fifo_last;
359 return;
360 }
361 /* Overlapping region updates can be optimised out here - if someone
362 * knows a smart algorithm to do that, please share. */
363 while (s->redraw_fifo_first != s->redraw_fifo_last) {
364 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
365 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
366 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
367 }
368}
369
370#ifdef HW_RECT_ACCEL
371static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
372 int x0, int y0, int x1, int y1, int w, int h)
373{
374# ifdef DIRECT_VRAM
0e1f5a0c 375 uint8_t *vram = ds_get_data(s->ds);
d34cab9f
TS		 376# else
377 uint8_t *vram = s->vram;
378# endif
379 int bypl = s->bypp * s->width;
380 int width = s->bypp * w;
381 int line = h;
382 uint8_t *ptr[2];
383
384# ifdef DIRECT_VRAM
385 if (s->ds->dpy_copy)
3023f332 386 qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
d34cab9f
TS		 387 else
388# endif
389 {
390 if (y1 > y0) {
391 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
392 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
393 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
394 memmove(ptr[1], ptr[0], width);
395 } else {
396 ptr[0] = vram + s->bypp * x0 + bypl * y0;
397 ptr[1] = vram + s->bypp * x1 + bypl * y1;
398 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
399 memmove(ptr[1], ptr[0], width);
400 }
401 }
402
403 vmsvga_update_rect_delayed(s, x1, y1, w, h);
404}
405#endif
406
407#ifdef HW_FILL_ACCEL
408static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
409 uint32_t c, int x, int y, int w, int h)
410{
411# ifdef DIRECT_VRAM
0e1f5a0c 412 uint8_t *vram = ds_get_data(s->ds);
d34cab9f
TS		 413# else
414 uint8_t *vram = s->vram;
415# endif
416 int bypp = s->bypp;
417 int bypl = bypp * s->width;
418 int width = bypp * w;
419 int line = h;
420 int column;
421 uint8_t *fst = vram + bypp * x + bypl * y;
422 uint8_t *dst;
423 uint8_t *src;
424 uint8_t col[4];
425
426# ifdef DIRECT_VRAM
427 if (s->ds->dpy_fill)
428 s->ds->dpy_fill(s->ds, x, y, w, h, c);
429 else
430# endif
431 {
432 col[0] = c;
433 col[1] = c >> 8;
434 col[2] = c >> 16;
435 col[3] = c >> 24;
436
437 if (line --) {
438 dst = fst;
439 src = col;
440 for (column = width; column > 0; column --) {
441 *(dst ++) = *(src ++);
442 if (src - col == bypp)
443 src = col;
444 }
445 dst = fst;
446 for (; line > 0; line --) {
447 dst += bypl;
448 memcpy(dst, fst, width);
449 }
450 }
451 }
452
453 vmsvga_update_rect_delayed(s, x, y, w, h);
454}
455#endif
456
457struct vmsvga_cursor_definition_s {
458 int width;
459 int height;
460 int id;
461 int bpp;
462 int hot_x;
463 int hot_y;
464 uint32_t mask[1024];
465 uint32_t image[1024];
466};
467
468#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
469#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
470
471#ifdef HW_MOUSE_ACCEL
472static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
473 struct vmsvga_cursor_definition_s *c)
474{
475 int i;
476 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
477 c->mask[i] = ~c->mask[i];
478
479 if (s->ds->cursor_define)
480 s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
481 (uint8_t *) c->image, (uint8_t *) c->mask);
482}
483#endif
484
ff9cf2cb
AZ		 485#define CMD(f) le32_to_cpu(s->cmd->f)
486
d34cab9f
TS		 487static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
488{
489 if (!s->config || !s->enable)
f707cfba 490 return 1;
d34cab9f
TS		 491 return (s->cmd->next_cmd == s->cmd->stop);
492}
493
ff9cf2cb 494static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
d34cab9f 495{
ff9cf2cb
AZ		 496 uint32_t cmd = s->fifo[CMD(stop) >> 2];
497 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
498 if (CMD(stop) >= CMD(max))
d34cab9f
TS		 499 s->cmd->stop = s->cmd->min;
500 return cmd;
501}
502
ff9cf2cb
AZ		 503static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
504{
505 return le32_to_cpu(vmsvga_fifo_read_raw(s));
506}
507
d34cab9f
TS		 508static void vmsvga_fifo_run(struct vmsvga_state_s *s)
509{
510 uint32_t cmd, colour;
511 int args = 0;
512 int x, y, dx, dy, width, height;
513 struct vmsvga_cursor_definition_s cursor;
514 while (!vmsvga_fifo_empty(s))
515 switch (cmd = vmsvga_fifo_read(s)) {
516 case SVGA_CMD_UPDATE:
517 case SVGA_CMD_UPDATE_VERBOSE:
518 x = vmsvga_fifo_read(s);
519 y = vmsvga_fifo_read(s);
520 width = vmsvga_fifo_read(s);
521 height = vmsvga_fifo_read(s);
522 vmsvga_update_rect_delayed(s, x, y, width, height);
523 break;
524
525 case SVGA_CMD_RECT_FILL:
526 colour = vmsvga_fifo_read(s);
527 x = vmsvga_fifo_read(s);
528 y = vmsvga_fifo_read(s);
529 width = vmsvga_fifo_read(s);
530 height = vmsvga_fifo_read(s);
531#ifdef HW_FILL_ACCEL
532 vmsvga_fill_rect(s, colour, x, y, width, height);
533 break;
534#else
535 goto badcmd;
536#endif
537
538 case SVGA_CMD_RECT_COPY:
539 x = vmsvga_fifo_read(s);
540 y = vmsvga_fifo_read(s);
541 dx = vmsvga_fifo_read(s);
542 dy = vmsvga_fifo_read(s);
543 width = vmsvga_fifo_read(s);
544 height = vmsvga_fifo_read(s);
545#ifdef HW_RECT_ACCEL
546 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
547 break;
548#else
549 goto badcmd;
550#endif
551
552 case SVGA_CMD_DEFINE_CURSOR:
553 cursor.id = vmsvga_fifo_read(s);
554 cursor.hot_x = vmsvga_fifo_read(s);
555 cursor.hot_y = vmsvga_fifo_read(s);
556 cursor.width = x = vmsvga_fifo_read(s);
557 cursor.height = y = vmsvga_fifo_read(s);
558 vmsvga_fifo_read(s);
559 cursor.bpp = vmsvga_fifo_read(s);
560 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
ff9cf2cb 561 cursor.mask[args] = vmsvga_fifo_read_raw(s);
d34cab9f 562 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
ff9cf2cb 563 cursor.image[args] = vmsvga_fifo_read_raw(s);
d34cab9f
TS		 564#ifdef HW_MOUSE_ACCEL
565 vmsvga_cursor_define(s, &cursor);
566 break;
567#else
568 args = 0;
569 goto badcmd;
570#endif
571
572 /*
573 * Other commands that we at least know the number of arguments
574 * for so we can avoid FIFO desync if driver uses them illegally.
575 */
576 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
577 vmsvga_fifo_read(s);
578 vmsvga_fifo_read(s);
579 vmsvga_fifo_read(s);
580 x = vmsvga_fifo_read(s);
581 y = vmsvga_fifo_read(s);
582 args = x * y;
583 goto badcmd;
584 case SVGA_CMD_RECT_ROP_FILL:
585 args = 6;
586 goto badcmd;
587 case SVGA_CMD_RECT_ROP_COPY:
588 args = 7;
589 goto badcmd;
590 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
591 vmsvga_fifo_read(s);
592 vmsvga_fifo_read(s);
593 args = 7 + (vmsvga_fifo_read(s) >> 2);
594 goto badcmd;
595 case SVGA_CMD_SURFACE_ALPHA_BLEND:
596 args = 12;
597 goto badcmd;
598
599 /*
600 * Other commands that are not listed as depending on any
601 * CAPABILITIES bits, but are not described in the README either.
602 */
603 case SVGA_CMD_SURFACE_FILL:
604 case SVGA_CMD_SURFACE_COPY:
605 case SVGA_CMD_FRONT_ROP_FILL:
606 case SVGA_CMD_FENCE:
607 case SVGA_CMD_INVALID_CMD:
608 break; /* Nop */
609
610 default:
611 badcmd:
612 while (args --)
613 vmsvga_fifo_read(s);
614 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
615 __FUNCTION__, cmd);
616 break;
617 }
618
619 s->syncing = 0;
620}
621
622static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
623{
624 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
625 return s->index;
626}
627
628static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
629{
630 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
631 s->index = index;
632}
633
634static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
635{
636 uint32_t caps;
637 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
638 switch (s->index) {
639 case SVGA_REG_ID:
640 return s->svgaid;
641
642 case SVGA_REG_ENABLE:
643 return s->enable;
644
645 case SVGA_REG_WIDTH:
646 return s->width;
647
648 case SVGA_REG_HEIGHT:
649 return s->height;
650
651 case SVGA_REG_MAX_WIDTH:
652 return SVGA_MAX_WIDTH;
653
654 case SVGA_REG_MAX_HEIGHT:
f707cfba 655 return SVGA_MAX_HEIGHT;
d34cab9f
TS		 656
657 case SVGA_REG_DEPTH:
658 return s->depth;
659
660 case SVGA_REG_BITS_PER_PIXEL:
661 return (s->depth + 7) & ~7;
662
663 case SVGA_REG_PSEUDOCOLOR:
664 return 0x0;
665
666 case SVGA_REG_RED_MASK:
667 return s->wred;
668 case SVGA_REG_GREEN_MASK:
669 return s->wgreen;
670 case SVGA_REG_BLUE_MASK:
671 return s->wblue;
672
673 case SVGA_REG_BYTES_PER_LINE:
674 return ((s->depth + 7) >> 3) * s->new_width;
675
676 case SVGA_REG_FB_START:
3016d80b 677 return s->vram_base;
d34cab9f
TS		 678
679 case SVGA_REG_FB_OFFSET:
680 return 0x0;
681
682 case SVGA_REG_VRAM_SIZE:
683 return s->vram_size - SVGA_FIFO_SIZE;
684
685 case SVGA_REG_FB_SIZE:
686 return s->fb_size;
687
688 case SVGA_REG_CAPABILITIES:
689 caps = SVGA_CAP_NONE;
690#ifdef HW_RECT_ACCEL
691 caps |= SVGA_CAP_RECT_COPY;
692#endif
693#ifdef HW_FILL_ACCEL
694 caps |= SVGA_CAP_RECT_FILL;
695#endif
696#ifdef HW_MOUSE_ACCEL
697 if (s->ds->mouse_set)
698 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
699 SVGA_CAP_CURSOR_BYPASS;
700#endif
701 return caps;
702
703 case SVGA_REG_MEM_START:
3016d80b 704 return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
d34cab9f
TS		 705
706 case SVGA_REG_MEM_SIZE:
707 return SVGA_FIFO_SIZE;
708
709 case SVGA_REG_CONFIG_DONE:
710 return s->config;
711
712 case SVGA_REG_SYNC:
713 case SVGA_REG_BUSY:
714 return s->syncing;
715
716 case SVGA_REG_GUEST_ID:
717 return s->guest;
718
719 case SVGA_REG_CURSOR_ID:
720 return s->cursor.id;
721
722 case SVGA_REG_CURSOR_X:
723 return s->cursor.x;
724
725 case SVGA_REG_CURSOR_Y:
726 return s->cursor.x;
727
728 case SVGA_REG_CURSOR_ON:
729 return s->cursor.on;
730
731 case SVGA_REG_HOST_BITS_PER_PIXEL:
732 return (s->depth + 7) & ~7;
733
734 case SVGA_REG_SCRATCH_SIZE:
735 return s->scratch_size;
736
737 case SVGA_REG_MEM_REGS:
738 case SVGA_REG_NUM_DISPLAYS:
739 case SVGA_REG_PITCHLOCK:
740 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
741 return 0;
742
743 default:
744 if (s->index >= SVGA_SCRATCH_BASE &&
745 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
746 return s->scratch[s->index - SVGA_SCRATCH_BASE];
747 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
748 }
749
750 return 0;
751}
752
753static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
754{
755 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
756 switch (s->index) {
757 case SVGA_REG_ID:
758 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
759 s->svgaid = value;
760 break;
761
762 case SVGA_REG_ENABLE:
f707cfba
AZ		 763 s->enable = value;
764 s->config &= !!value;
d34cab9f
TS		 765 s->width = -1;
766 s->height = -1;
767 s->invalidated = 1;
768#ifdef EMBED_STDVGA
769 s->invalidate(opaque);
770#endif
771 if (s->enable)
772 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
773 break;
774
775 case SVGA_REG_WIDTH:
776 s->new_width = value;
777 s->invalidated = 1;
778 break;
779
780 case SVGA_REG_HEIGHT:
781 s->new_height = value;
782 s->invalidated = 1;
783 break;
784
785 case SVGA_REG_DEPTH:
786 case SVGA_REG_BITS_PER_PIXEL:
787 if (value != s->depth) {
788 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
789 s->config = 0;
790 }
791 break;
792
793 case SVGA_REG_CONFIG_DONE:
794 if (value) {
795 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
796 /* Check range and alignment. */
ff9cf2cb
AZ		 797 if ((CMD(min) | CMD(max) |
798 CMD(next_cmd) | CMD(stop)) & 3)
d34cab9f 799 break;
ff9cf2cb 800 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
d34cab9f 801 break;
ff9cf2cb 802 if (CMD(max) > SVGA_FIFO_SIZE)
d34cab9f 803 break;
ff9cf2cb 804 if (CMD(max) < CMD(min) + 10 * 1024)
d34cab9f
TS		 805 break;
806 }
f707cfba 807 s->config = !!value;
d34cab9f
TS		 808 break;
809
810 case SVGA_REG_SYNC:
811 s->syncing = 1;
812 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
813 break;
814
815 case SVGA_REG_GUEST_ID:
816 s->guest = value;
817#ifdef VERBOSE
818 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
b1503cda 819 ARRAY_SIZE(vmsvga_guest_id))
d34cab9f
TS		 820 printf("%s: guest runs %s.\n", __FUNCTION__,
821 vmsvga_guest_id[value - GUEST_OS_BASE]);
822#endif
823 break;
824
825 case SVGA_REG_CURSOR_ID:
826 s->cursor.id = value;
827 break;
828
829 case SVGA_REG_CURSOR_X:
830 s->cursor.x = value;
831 break;
832
833 case SVGA_REG_CURSOR_Y:
834 s->cursor.y = value;
835 break;
836
837 case SVGA_REG_CURSOR_ON:
838 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
839 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
840#ifdef HW_MOUSE_ACCEL
841 if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
842 s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
843#endif
844 break;
845
846 case SVGA_REG_MEM_REGS:
847 case SVGA_REG_NUM_DISPLAYS:
848 case SVGA_REG_PITCHLOCK:
849 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
850 break;
851
852 default:
853 if (s->index >= SVGA_SCRATCH_BASE &&
854 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
855 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
856 break;
857 }
858 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
859 }
860}
861
862static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
863{
864 printf("%s: what are we supposed to return?\n", __FUNCTION__);
865 return 0xcafe;
866}
867
868static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
869{
870 printf("%s: what are we supposed to do with (%08x)?\n",
871 __FUNCTION__, data);
872}
873
874static inline void vmsvga_size(struct vmsvga_state_s *s)
875{
876 if (s->new_width != s->width || s->new_height != s->height) {
877 s->width = s->new_width;
878 s->height = s->new_height;
3023f332 879 qemu_console_resize(s->ds, s->width, s->height);
d34cab9f
TS		 880 s->invalidated = 1;
881 }
882}
883
884static void vmsvga_update_display(void *opaque)
885{
886 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
887 if (!s->enable) {
888#ifdef EMBED_STDVGA
889 s->update(opaque);
890#endif
891 return;
892 }
893
894 vmsvga_size(s);
895
896 vmsvga_fifo_run(s);
897 vmsvga_update_rect_flush(s);
898
899 /*
900 * Is it more efficient to look at vram VGA-dirty bits or wait
901 * for the driver to issue SVGA_CMD_UPDATE?
902 */
903 if (s->invalidated) {
904 s->invalidated = 0;
905 vmsvga_update_screen(s);
906 }
907}
908
909static void vmsvga_reset(struct vmsvga_state_s *s)
910{
911 s->index = 0;
912 s->enable = 0;
913 s->config = 0;
914 s->width = -1;
915 s->height = -1;
916 s->svgaid = SVGA_ID;
3023f332 917 s->depth = 24;
d34cab9f
TS		 918 s->bypp = (s->depth + 7) >> 3;
919 s->cursor.on = 0;
920 s->redraw_fifo_first = 0;
921 s->redraw_fifo_last = 0;
922 switch (s->depth) {
923 case 8:
924 s->wred = 0x00000007;
925 s->wgreen = 0x00000038;
926 s->wblue = 0x000000c0;
927 break;
928 case 15:
929 s->wred = 0x0000001f;
930 s->wgreen = 0x000003e0;
931 s->wblue = 0x00007c00;
932 break;
933 case 16:
934 s->wred = 0x0000001f;
935 s->wgreen = 0x000007e0;
936 s->wblue = 0x0000f800;
937 break;
938 case 24:
f707cfba 939 s->wred = 0x00ff0000;
d34cab9f 940 s->wgreen = 0x0000ff00;
f707cfba 941 s->wblue = 0x000000ff;
d34cab9f
TS		 942 break;
943 case 32:
f707cfba 944 s->wred = 0x00ff0000;
d34cab9f 945 s->wgreen = 0x0000ff00;
f707cfba 946 s->wblue = 0x000000ff;
d34cab9f
TS		 947 break;
948 }
949 s->syncing = 0;
950}
951
952static void vmsvga_invalidate_display(void *opaque)
953{
954 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
955 if (!s->enable) {
956#ifdef EMBED_STDVGA
957 s->invalidate(opaque);
958#endif
959 return;
960 }
961
962 s->invalidated = 1;
963}
964
f707cfba
AZ		 965/* save the vga display in a PPM image even if no display is
966 available */
d34cab9f
TS		 967static void vmsvga_screen_dump(void *opaque, const char *filename)
968{
969 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
970 if (!s->enable) {
971#ifdef EMBED_STDVGA
972 s->screen_dump(opaque, filename);
973#endif
974 return;
975 }
976
f707cfba 977 if (s->depth == 32) {
e07d630a
AL		 978 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
979 s->height, 32, ds_get_linesize(s->ds), s->vram);
980 ppm_save(filename, ds);
981 qemu_free(ds);
f707cfba 982 }
d34cab9f
TS		 983}
984
4d3b6f6e
AZ		 985static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
986{
987 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
988
989 if (s->text_update)
990 s->text_update(opaque, chardata);
991}
992
d34cab9f
TS		 993#ifdef DIRECT_VRAM
994static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
995{
996 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
d34cab9f 997 if (addr < s->fb_size)
0e1f5a0c 998 return *(uint8_t *) (ds_get_data(s->ds) + addr);
d34cab9f
TS		 999 else
1000 return *(uint8_t *) (s->vram + addr);
1001}
1002
1003static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
1004{
1005 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
d34cab9f 1006 if (addr < s->fb_size)
0e1f5a0c 1007 return *(uint16_t *) (ds_get_data(s->ds) + addr);
d34cab9f
TS		 1008 else
1009 return *(uint16_t *) (s->vram + addr);
1010}
1011
1012static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1013{
1014 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
d34cab9f 1015 if (addr < s->fb_size)
0e1f5a0c 1016 return *(uint32_t *) (ds_get_data(s->ds) + addr);
d34cab9f
TS		 1017 else
1018 return *(uint32_t *) (s->vram + addr);
1019}
1020
1021static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1022 uint32_t value)
1023{
1024 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
d34cab9f 1025 if (addr < s->fb_size)
0e1f5a0c 1026 *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f
TS		 1027 else
1028 *(uint8_t *) (s->vram + addr) = value;
1029}
1030
1031static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1032 uint32_t value)
1033{
1034 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
d34cab9f 1035 if (addr < s->fb_size)
0e1f5a0c 1036 *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f
TS		 1037 else
1038 *(uint16_t *) (s->vram + addr) = value;
1039}
1040
1041static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1042 uint32_t value)
1043{
1044 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
d34cab9f 1045 if (addr < s->fb_size)
0e1f5a0c 1046 *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f
TS		 1047 else
1048 *(uint32_t *) (s->vram + addr) = value;
1049}
1050
1051static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1052 vmsvga_vram_readb,
1053 vmsvga_vram_readw,
1054 vmsvga_vram_readl,
1055};
1056
1057static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1058 vmsvga_vram_writeb,
1059 vmsvga_vram_writew,
1060 vmsvga_vram_writel,
1061};
1062#endif
1063
1064static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1065{
bee8d684
TS		 1066 qemu_put_be32(f, s->depth);
1067 qemu_put_be32(f, s->enable);
1068 qemu_put_be32(f, s->config);
1069 qemu_put_be32(f, s->cursor.id);
1070 qemu_put_be32(f, s->cursor.x);
1071 qemu_put_be32(f, s->cursor.y);
1072 qemu_put_be32(f, s->cursor.on);
1073 qemu_put_be32(f, s->index);
d34cab9f 1074 qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
bee8d684
TS		 1075 qemu_put_be32(f, s->new_width);
1076 qemu_put_be32(f, s->new_height);
d34cab9f
TS		 1077 qemu_put_be32s(f, &s->guest);
1078 qemu_put_be32s(f, &s->svgaid);
bee8d684
TS		 1079 qemu_put_be32(f, s->syncing);
1080 qemu_put_be32(f, s->fb_size);
d34cab9f
TS		 1081}
1082
1083static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1084{
1085 int depth;
bee8d684
TS		 1086 depth=qemu_get_be32(f);
1087 s->enable=qemu_get_be32(f);
1088 s->config=qemu_get_be32(f);
1089 s->cursor.id=qemu_get_be32(f);
1090 s->cursor.x=qemu_get_be32(f);
1091 s->cursor.y=qemu_get_be32(f);
1092 s->cursor.on=qemu_get_be32(f);
1093 s->index=qemu_get_be32(f);
d34cab9f 1094 qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
bee8d684
TS		 1095 s->new_width=qemu_get_be32(f);
1096 s->new_height=qemu_get_be32(f);
d34cab9f
TS		 1097 qemu_get_be32s(f, &s->guest);
1098 qemu_get_be32s(f, &s->svgaid);
bee8d684
TS		 1099 s->syncing=qemu_get_be32(f);
1100 s->fb_size=qemu_get_be32(f);
d34cab9f
TS		 1101
1102 if (s->enable && depth != s->depth) {
1103 printf("%s: need colour depth of %i bits to resume operation.\n",
1104 __FUNCTION__, depth);
1105 return -EINVAL;
1106 }
1107
1108 s->invalidated = 1;
1109 if (s->config)
1110 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1111
1112 return 0;
1113}
1114
3023f332 1115static void vmsvga_init(struct vmsvga_state_s *s,
d34cab9f
TS		 1116 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1117 int vga_ram_size)
1118{
d34cab9f
TS		 1119 s->vram = vga_ram_base;
1120 s->vram_size = vga_ram_size;
6f9bc132 1121 s->vram_offset = vga_ram_offset;
d34cab9f
TS		 1122
1123 s->scratch_size = SVGA_SCRATCH_SIZE;
1124 s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1125
1126 vmsvga_reset(s);
1127
d34cab9f 1128#ifdef EMBED_STDVGA
3023f332 1129 vga_common_init((VGAState *) s,
d34cab9f
TS		 1130 vga_ram_base, vga_ram_offset, vga_ram_size);
1131 vga_init((VGAState *) s);
1132#endif
e93a5f4f 1133
3023f332
AL		 1134 s->ds = graphic_console_init(vmsvga_update_display,
1135 vmsvga_invalidate_display,
1136 vmsvga_screen_dump,
1137 vmsvga_text_update, s);
931ea435
AZ		 1138
1139#ifdef CONFIG_BOCHS_VBE
1140 /* XXX: use optimized standard vga accesses */
1141 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
1142 vga_ram_size, vga_ram_offset);
1143#endif
d34cab9f
TS		 1144}
1145
1146static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1147{
1148 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1149 pci_device_save(&s->card, f);
1150 vmsvga_save(&s->chip, f);
1151}
1152
1153static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1154{
1155 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1156 int ret;
1157
1158 ret = pci_device_load(&s->card, f);
1159 if (ret < 0)
1160 return ret;
1161
1162 ret = vmsvga_load(&s->chip, f);
1163 if (ret < 0)
1164 return ret;
1165
1166 return 0;
1167}
1168
1492a3c4
AZ		 1169static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1170 uint32_t addr, uint32_t size, int type)
1171{
1172 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1173 struct vmsvga_state_s *s = &d->chip;
1174
1175 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1176 1, 4, vmsvga_index_read, s);
1177 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1178 1, 4, vmsvga_index_write, s);
1179 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1180 1, 4, vmsvga_value_read, s);
1181 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1182 1, 4, vmsvga_value_write, s);
1183 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1184 1, 4, vmsvga_bios_read, s);
1185 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1186 1, 4, vmsvga_bios_write, s);
1187}
1188
3016d80b
AZ		 1189static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1190 uint32_t addr, uint32_t size, int type)
1191{
1192 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1193 struct vmsvga_state_s *s = &d->chip;
ff9cf2cb 1194 ram_addr_t iomemtype;
3016d80b
AZ		 1195
1196 s->vram_base = addr;
1197#ifdef DIRECT_VRAM
1198 iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1199 vmsvga_vram_write, s);
1200#else
6f9bc132 1201 iomemtype = s->vram_offset | IO_MEM_RAM;
3016d80b
AZ		 1202#endif
1203 cpu_register_physical_memory(s->vram_base, s->vram_size,
1204 iomemtype);
1205}
1206
d34cab9f
TS		 1207#define PCI_CLASS_HEADERTYPE_00h 0x00
1208
3023f332 1209void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
d34cab9f
TS		 1210 unsigned long vga_ram_offset, int vga_ram_size)
1211{
1212 struct pci_vmsvga_state_s *s;
1213
1214 /* Setup PCI configuration */
1215 s = (struct pci_vmsvga_state_s *)
1216 pci_register_device(bus, "QEMUware SVGA",
1217 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
deb54399
AL		 1218 pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
1219 pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
d34cab9f 1220 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
173a543b 1221 pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
d34cab9f
TS		 1222 s->card.config[0x0c] = 0x08; /* Cache line size */
1223 s->card.config[0x0d] = 0x40; /* Latency timer */
1224 s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
d34cab9f
TS		 1225 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1226 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1227 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1228 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1229 s->card.config[0x3c] = 0xff; /* End */
1230
1492a3c4
AZ		 1231 pci_register_io_region(&s->card, 0, 0x10,
1232 PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
2408b77b 1233 pci_register_io_region(&s->card, 1, vga_ram_size,
3016d80b 1234 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
1492a3c4 1235
3023f332 1236 vmsvga_init(&s->chip, vga_ram_base, vga_ram_offset, vga_ram_size);
d34cab9f
TS		 1237
1238 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1239}
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