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[qemu.git] / hw / vmware_vga.c
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d34cab9f
TS		 1/*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <[email protected]>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b
PB		 24#include "hw.h"
25#include "console.h"
26#include "pci.h"
d34cab9f
TS		 27
28#define VERBOSE
29#define EMBED_STDVGA
30#undef DIRECT_VRAM
31#define HW_RECT_ACCEL
32#define HW_FILL_ACCEL
33#define HW_MOUSE_ACCEL
34
35#ifdef EMBED_STDVGA
36# include "vga_int.h"
37#endif
38
39struct vmsvga_state_s {
40#ifdef EMBED_STDVGA
41 VGA_STATE_COMMON
42#endif
43
44 int width;
45 int height;
46 int invalidated;
47 int depth;
48 int bypp;
49 int enable;
50 int config;
51 struct {
52 int id;
53 int x;
54 int y;
55 int on;
56 } cursor;
57
58#ifndef EMBED_STDVGA
59 DisplayState *ds;
60 int vram_size;
61#endif
62 uint8_t *vram;
3016d80b 63 target_phys_addr_t vram_base;
d34cab9f
TS		 64
65 int index;
66 int scratch_size;
67 uint32_t *scratch;
68 int new_width;
69 int new_height;
70 uint32_t guest;
71 uint32_t svgaid;
72 uint32_t wred;
73 uint32_t wgreen;
74 uint32_t wblue;
75 int syncing;
76 int fb_size;
77
78 union {
79 uint32_t *fifo;
80 struct __attribute__((__packed__)) {
81 uint32_t min;
82 uint32_t max;
83 uint32_t next_cmd;
84 uint32_t stop;
85 /* Add registers here when adding capabilities. */
86 uint32_t fifo[0];
87 } *cmd;
88 };
89
90#define REDRAW_FIFO_LEN 512
91 struct vmsvga_rect_s {
92 int x, y, w, h;
93 } redraw_fifo[REDRAW_FIFO_LEN];
94 int redraw_fifo_first, redraw_fifo_last;
95};
96
97struct pci_vmsvga_state_s {
98 PCIDevice card;
99 struct vmsvga_state_s chip;
100};
101
102#define SVGA_MAGIC 0x900000UL
103#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
104#define SVGA_ID_0 SVGA_MAKE_ID(0)
105#define SVGA_ID_1 SVGA_MAKE_ID(1)
106#define SVGA_ID_2 SVGA_MAKE_ID(2)
107
108#define SVGA_LEGACY_BASE_PORT 0x4560
109#define SVGA_INDEX_PORT 0x0
110#define SVGA_VALUE_PORT 0x1
111#define SVGA_BIOS_PORT 0x2
112
113#define SVGA_VERSION_2
114
115#ifdef SVGA_VERSION_2
116# define SVGA_ID SVGA_ID_2
117# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
118# define SVGA_IO_MUL 1
119# define SVGA_FIFO_SIZE 0x10000
1f72aae5 120# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 121# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
122#else
123# define SVGA_ID SVGA_ID_1
124# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
125# define SVGA_IO_MUL 4
126# define SVGA_FIFO_SIZE 0x10000
1f72aae5 127# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 128# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
129#endif
130
131enum {
132 /* ID 0, 1 and 2 registers */
133 SVGA_REG_ID = 0,
134 SVGA_REG_ENABLE = 1,
135 SVGA_REG_WIDTH = 2,
136 SVGA_REG_HEIGHT = 3,
137 SVGA_REG_MAX_WIDTH = 4,
138 SVGA_REG_MAX_HEIGHT = 5,
139 SVGA_REG_DEPTH = 6,
140 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
141 SVGA_REG_PSEUDOCOLOR = 8,
142 SVGA_REG_RED_MASK = 9,
143 SVGA_REG_GREEN_MASK = 10,
144 SVGA_REG_BLUE_MASK = 11,
145 SVGA_REG_BYTES_PER_LINE = 12,
146 SVGA_REG_FB_START = 13,
147 SVGA_REG_FB_OFFSET = 14,
148 SVGA_REG_VRAM_SIZE = 15,
149 SVGA_REG_FB_SIZE = 16,
150
151 /* ID 1 and 2 registers */
152 SVGA_REG_CAPABILITIES = 17,
153 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
154 SVGA_REG_MEM_SIZE = 19,
155 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
156 SVGA_REG_SYNC = 21, /* Write to force synchronization */
157 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
158 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
159 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
160 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
161 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
162 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
163 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
164 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
165 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
166 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
167 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
168
169 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
170 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
171 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
172};
173
174#define SVGA_CAP_NONE 0
175#define SVGA_CAP_RECT_FILL (1 << 0)
176#define SVGA_CAP_RECT_COPY (1 << 1)
177#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
178#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
179#define SVGA_CAP_RASTER_OP (1 << 4)
180#define SVGA_CAP_CURSOR (1 << 5)
181#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
182#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
183#define SVGA_CAP_8BIT_EMULATION (1 << 8)
184#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
185#define SVGA_CAP_GLYPH (1 << 10)
186#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
187#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
188#define SVGA_CAP_ALPHA_BLEND (1 << 13)
189#define SVGA_CAP_3D (1 << 14)
190#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
191#define SVGA_CAP_MULTIMON (1 << 16)
192#define SVGA_CAP_PITCHLOCK (1 << 17)
193
194/*
195 * FIFO offsets (seen as an array of 32-bit words)
196 */
197enum {
198 /*
199 * The original defined FIFO offsets
200 */
201 SVGA_FIFO_MIN = 0,
202 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
203 SVGA_FIFO_NEXT_CMD,
204 SVGA_FIFO_STOP,
205
206 /*
207 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
208 */
209 SVGA_FIFO_CAPABILITIES = 4,
210 SVGA_FIFO_FLAGS,
211 SVGA_FIFO_FENCE,
212 SVGA_FIFO_3D_HWVERSION,
213 SVGA_FIFO_PITCHLOCK,
214};
215
216#define SVGA_FIFO_CAP_NONE 0
217#define SVGA_FIFO_CAP_FENCE (1 << 0)
218#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
219#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
220
221#define SVGA_FIFO_FLAG_NONE 0
222#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
223
224/* These values can probably be changed arbitrarily. */
225#define SVGA_SCRATCH_SIZE 0x8000
226#define SVGA_MAX_WIDTH 2360
227#define SVGA_MAX_HEIGHT 1770
228
229#ifdef VERBOSE
230# define GUEST_OS_BASE 0x5001
231static const char *vmsvga_guest_id[] = {
f707cfba
AZ		 232 [0x00 ... 0x15] = "an unknown OS",
233 [0x00] = "Dos",
234 [0x01] = "Windows 3.1",
235 [0x02] = "Windows 95",
236 [0x03] = "Windows 98",
237 [0x04] = "Windows ME",
238 [0x05] = "Windows NT",
239 [0x06] = "Windows 2000",
240 [0x07] = "Linux",
241 [0x08] = "OS/2",
242 [0x0a] = "BSD",
243 [0x0b] = "Whistler",
244 [0x15] = "Windows 2003",
d34cab9f
TS		 245};
246#endif
247
248enum {
249 SVGA_CMD_INVALID_CMD = 0,
250 SVGA_CMD_UPDATE = 1,
251 SVGA_CMD_RECT_FILL = 2,
252 SVGA_CMD_RECT_COPY = 3,
253 SVGA_CMD_DEFINE_BITMAP = 4,
254 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
255 SVGA_CMD_DEFINE_PIXMAP = 6,
256 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
257 SVGA_CMD_RECT_BITMAP_FILL = 8,
258 SVGA_CMD_RECT_PIXMAP_FILL = 9,
259 SVGA_CMD_RECT_BITMAP_COPY = 10,
260 SVGA_CMD_RECT_PIXMAP_COPY = 11,
261 SVGA_CMD_FREE_OBJECT = 12,
262 SVGA_CMD_RECT_ROP_FILL = 13,
263 SVGA_CMD_RECT_ROP_COPY = 14,
264 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
265 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
266 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
267 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
268 SVGA_CMD_DEFINE_CURSOR = 19,
269 SVGA_CMD_DISPLAY_CURSOR = 20,
270 SVGA_CMD_MOVE_CURSOR = 21,
271 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
272 SVGA_CMD_DRAW_GLYPH = 23,
273 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
274 SVGA_CMD_UPDATE_VERBOSE = 25,
275 SVGA_CMD_SURFACE_FILL = 26,
276 SVGA_CMD_SURFACE_COPY = 27,
277 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
278 SVGA_CMD_FRONT_ROP_FILL = 29,
279 SVGA_CMD_FENCE = 30,
280};
281
282/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
283enum {
284 SVGA_CURSOR_ON_HIDE = 0,
285 SVGA_CURSOR_ON_SHOW = 1,
286 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
287 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
288};
289
290static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
291 int x, int y, int w, int h)
292{
293#ifndef DIRECT_VRAM
a8fbaf96
AZ		 294 int line;
295 int bypl;
296 int width;
297 int start;
298 uint8_t *src;
299 uint8_t *dst;
300
301 if (x + w > s->width) {
302 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
303 __FUNCTION__, x, w);
304 x = MIN(x, s->width);
305 w = s->width - x;
306 }
307
308 if (y + h > s->height) {
309 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
310 __FUNCTION__, y, h);
311 y = MIN(y, s->height);
312 h = s->height - y;
313 }
314
315 line = h;
316 bypl = s->bypp * s->width;
317 width = s->bypp * w;
318 start = s->bypp * x + bypl * y;
319 src = s->vram + start;
320 dst = s->ds->data + start;
d34cab9f
TS		 321
322 for (; line > 0; line --, src += bypl, dst += bypl)
323 memcpy(dst, src, width);
324#endif
325
326 dpy_update(s->ds, x, y, w, h);
327}
328
329static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
330{
331#ifndef DIRECT_VRAM
332 memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
333#endif
334
335 dpy_update(s->ds, 0, 0, s->width, s->height);
336}
337
338#ifdef DIRECT_VRAM
339# define vmsvga_update_rect_delayed vmsvga_update_rect
340#else
341static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
342 int x, int y, int w, int h)
343{
344 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
345 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
346 rect->x = x;
347 rect->y = y;
348 rect->w = w;
349 rect->h = h;
350}
351#endif
352
353static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
354{
355 struct vmsvga_rect_s *rect;
356 if (s->invalidated) {
357 s->redraw_fifo_first = s->redraw_fifo_last;
358 return;
359 }
360 /* Overlapping region updates can be optimised out here - if someone
361 * knows a smart algorithm to do that, please share. */
362 while (s->redraw_fifo_first != s->redraw_fifo_last) {
363 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
364 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
365 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
366 }
367}
368
369#ifdef HW_RECT_ACCEL
370static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
371 int x0, int y0, int x1, int y1, int w, int h)
372{
373# ifdef DIRECT_VRAM
374 uint8_t *vram = s->ds->data;
375# else
376 uint8_t *vram = s->vram;
377# endif
378 int bypl = s->bypp * s->width;
379 int width = s->bypp * w;
380 int line = h;
381 uint8_t *ptr[2];
382
383# ifdef DIRECT_VRAM
384 if (s->ds->dpy_copy)
385 s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
386 else
387# endif
388 {
389 if (y1 > y0) {
390 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
391 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
392 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
393 memmove(ptr[1], ptr[0], width);
394 } else {
395 ptr[0] = vram + s->bypp * x0 + bypl * y0;
396 ptr[1] = vram + s->bypp * x1 + bypl * y1;
397 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
398 memmove(ptr[1], ptr[0], width);
399 }
400 }
401
402 vmsvga_update_rect_delayed(s, x1, y1, w, h);
403}
404#endif
405
406#ifdef HW_FILL_ACCEL
407static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
408 uint32_t c, int x, int y, int w, int h)
409{
410# ifdef DIRECT_VRAM
411 uint8_t *vram = s->ds->data;
412# else
413 uint8_t *vram = s->vram;
414# endif
415 int bypp = s->bypp;
416 int bypl = bypp * s->width;
417 int width = bypp * w;
418 int line = h;
419 int column;
420 uint8_t *fst = vram + bypp * x + bypl * y;
421 uint8_t *dst;
422 uint8_t *src;
423 uint8_t col[4];
424
425# ifdef DIRECT_VRAM
426 if (s->ds->dpy_fill)
427 s->ds->dpy_fill(s->ds, x, y, w, h, c);
428 else
429# endif
430 {
431 col[0] = c;
432 col[1] = c >> 8;
433 col[2] = c >> 16;
434 col[3] = c >> 24;
435
436 if (line --) {
437 dst = fst;
438 src = col;
439 for (column = width; column > 0; column --) {
440 *(dst ++) = *(src ++);
441 if (src - col == bypp)
442 src = col;
443 }
444 dst = fst;
445 for (; line > 0; line --) {
446 dst += bypl;
447 memcpy(dst, fst, width);
448 }
449 }
450 }
451
452 vmsvga_update_rect_delayed(s, x, y, w, h);
453}
454#endif
455
456struct vmsvga_cursor_definition_s {
457 int width;
458 int height;
459 int id;
460 int bpp;
461 int hot_x;
462 int hot_y;
463 uint32_t mask[1024];
464 uint32_t image[1024];
465};
466
467#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
468#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
469
470#ifdef HW_MOUSE_ACCEL
471static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
472 struct vmsvga_cursor_definition_s *c)
473{
474 int i;
475 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
476 c->mask[i] = ~c->mask[i];
477
478 if (s->ds->cursor_define)
479 s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
480 (uint8_t *) c->image, (uint8_t *) c->mask);
481}
482#endif
483
484static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
485{
486 if (!s->config || !s->enable)
f707cfba 487 return 1;
d34cab9f
TS		 488 return (s->cmd->next_cmd == s->cmd->stop);
489}
490
491static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
492{
493 uint32_t cmd = s->fifo[s->cmd->stop >> 2];
494 s->cmd->stop += 4;
495 if (s->cmd->stop >= s->cmd->max)
496 s->cmd->stop = s->cmd->min;
497 return cmd;
498}
499
500static void vmsvga_fifo_run(struct vmsvga_state_s *s)
501{
502 uint32_t cmd, colour;
503 int args = 0;
504 int x, y, dx, dy, width, height;
505 struct vmsvga_cursor_definition_s cursor;
506 while (!vmsvga_fifo_empty(s))
507 switch (cmd = vmsvga_fifo_read(s)) {
508 case SVGA_CMD_UPDATE:
509 case SVGA_CMD_UPDATE_VERBOSE:
510 x = vmsvga_fifo_read(s);
511 y = vmsvga_fifo_read(s);
512 width = vmsvga_fifo_read(s);
513 height = vmsvga_fifo_read(s);
514 vmsvga_update_rect_delayed(s, x, y, width, height);
515 break;
516
517 case SVGA_CMD_RECT_FILL:
518 colour = vmsvga_fifo_read(s);
519 x = vmsvga_fifo_read(s);
520 y = vmsvga_fifo_read(s);
521 width = vmsvga_fifo_read(s);
522 height = vmsvga_fifo_read(s);
523#ifdef HW_FILL_ACCEL
524 vmsvga_fill_rect(s, colour, x, y, width, height);
525 break;
526#else
527 goto badcmd;
528#endif
529
530 case SVGA_CMD_RECT_COPY:
531 x = vmsvga_fifo_read(s);
532 y = vmsvga_fifo_read(s);
533 dx = vmsvga_fifo_read(s);
534 dy = vmsvga_fifo_read(s);
535 width = vmsvga_fifo_read(s);
536 height = vmsvga_fifo_read(s);
537#ifdef HW_RECT_ACCEL
538 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
539 break;
540#else
541 goto badcmd;
542#endif
543
544 case SVGA_CMD_DEFINE_CURSOR:
545 cursor.id = vmsvga_fifo_read(s);
546 cursor.hot_x = vmsvga_fifo_read(s);
547 cursor.hot_y = vmsvga_fifo_read(s);
548 cursor.width = x = vmsvga_fifo_read(s);
549 cursor.height = y = vmsvga_fifo_read(s);
550 vmsvga_fifo_read(s);
551 cursor.bpp = vmsvga_fifo_read(s);
552 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
553 cursor.mask[args] = vmsvga_fifo_read(s);
554 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
555 cursor.image[args] = vmsvga_fifo_read(s);
556#ifdef HW_MOUSE_ACCEL
557 vmsvga_cursor_define(s, &cursor);
558 break;
559#else
560 args = 0;
561 goto badcmd;
562#endif
563
564 /*
565 * Other commands that we at least know the number of arguments
566 * for so we can avoid FIFO desync if driver uses them illegally.
567 */
568 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
569 vmsvga_fifo_read(s);
570 vmsvga_fifo_read(s);
571 vmsvga_fifo_read(s);
572 x = vmsvga_fifo_read(s);
573 y = vmsvga_fifo_read(s);
574 args = x * y;
575 goto badcmd;
576 case SVGA_CMD_RECT_ROP_FILL:
577 args = 6;
578 goto badcmd;
579 case SVGA_CMD_RECT_ROP_COPY:
580 args = 7;
581 goto badcmd;
582 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
583 vmsvga_fifo_read(s);
584 vmsvga_fifo_read(s);
585 args = 7 + (vmsvga_fifo_read(s) >> 2);
586 goto badcmd;
587 case SVGA_CMD_SURFACE_ALPHA_BLEND:
588 args = 12;
589 goto badcmd;
590
591 /*
592 * Other commands that are not listed as depending on any
593 * CAPABILITIES bits, but are not described in the README either.
594 */
595 case SVGA_CMD_SURFACE_FILL:
596 case SVGA_CMD_SURFACE_COPY:
597 case SVGA_CMD_FRONT_ROP_FILL:
598 case SVGA_CMD_FENCE:
599 case SVGA_CMD_INVALID_CMD:
600 break; /* Nop */
601
602 default:
603 badcmd:
604 while (args --)
605 vmsvga_fifo_read(s);
606 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
607 __FUNCTION__, cmd);
608 break;
609 }
610
611 s->syncing = 0;
612}
613
614static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
615{
616 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
617 return s->index;
618}
619
620static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
621{
622 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
623 s->index = index;
624}
625
626static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
627{
628 uint32_t caps;
629 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
630 switch (s->index) {
631 case SVGA_REG_ID:
632 return s->svgaid;
633
634 case SVGA_REG_ENABLE:
635 return s->enable;
636
637 case SVGA_REG_WIDTH:
638 return s->width;
639
640 case SVGA_REG_HEIGHT:
641 return s->height;
642
643 case SVGA_REG_MAX_WIDTH:
644 return SVGA_MAX_WIDTH;
645
646 case SVGA_REG_MAX_HEIGHT:
f707cfba 647 return SVGA_MAX_HEIGHT;
d34cab9f
TS		 648
649 case SVGA_REG_DEPTH:
650 return s->depth;
651
652 case SVGA_REG_BITS_PER_PIXEL:
653 return (s->depth + 7) & ~7;
654
655 case SVGA_REG_PSEUDOCOLOR:
656 return 0x0;
657
658 case SVGA_REG_RED_MASK:
659 return s->wred;
660 case SVGA_REG_GREEN_MASK:
661 return s->wgreen;
662 case SVGA_REG_BLUE_MASK:
663 return s->wblue;
664
665 case SVGA_REG_BYTES_PER_LINE:
666 return ((s->depth + 7) >> 3) * s->new_width;
667
668 case SVGA_REG_FB_START:
3016d80b 669 return s->vram_base;
d34cab9f
TS		 670
671 case SVGA_REG_FB_OFFSET:
672 return 0x0;
673
674 case SVGA_REG_VRAM_SIZE:
675 return s->vram_size - SVGA_FIFO_SIZE;
676
677 case SVGA_REG_FB_SIZE:
678 return s->fb_size;
679
680 case SVGA_REG_CAPABILITIES:
681 caps = SVGA_CAP_NONE;
682#ifdef HW_RECT_ACCEL
683 caps |= SVGA_CAP_RECT_COPY;
684#endif
685#ifdef HW_FILL_ACCEL
686 caps |= SVGA_CAP_RECT_FILL;
687#endif
688#ifdef HW_MOUSE_ACCEL
689 if (s->ds->mouse_set)
690 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
691 SVGA_CAP_CURSOR_BYPASS;
692#endif
693 return caps;
694
695 case SVGA_REG_MEM_START:
3016d80b 696 return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
d34cab9f
TS		 697
698 case SVGA_REG_MEM_SIZE:
699 return SVGA_FIFO_SIZE;
700
701 case SVGA_REG_CONFIG_DONE:
702 return s->config;
703
704 case SVGA_REG_SYNC:
705 case SVGA_REG_BUSY:
706 return s->syncing;
707
708 case SVGA_REG_GUEST_ID:
709 return s->guest;
710
711 case SVGA_REG_CURSOR_ID:
712 return s->cursor.id;
713
714 case SVGA_REG_CURSOR_X:
715 return s->cursor.x;
716
717 case SVGA_REG_CURSOR_Y:
718 return s->cursor.x;
719
720 case SVGA_REG_CURSOR_ON:
721 return s->cursor.on;
722
723 case SVGA_REG_HOST_BITS_PER_PIXEL:
724 return (s->depth + 7) & ~7;
725
726 case SVGA_REG_SCRATCH_SIZE:
727 return s->scratch_size;
728
729 case SVGA_REG_MEM_REGS:
730 case SVGA_REG_NUM_DISPLAYS:
731 case SVGA_REG_PITCHLOCK:
732 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
733 return 0;
734
735 default:
736 if (s->index >= SVGA_SCRATCH_BASE &&
737 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
738 return s->scratch[s->index - SVGA_SCRATCH_BASE];
739 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
740 }
741
742 return 0;
743}
744
745static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
746{
747 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
748 switch (s->index) {
749 case SVGA_REG_ID:
750 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
751 s->svgaid = value;
752 break;
753
754 case SVGA_REG_ENABLE:
f707cfba
AZ		 755 s->enable = value;
756 s->config &= !!value;
d34cab9f
TS		 757 s->width = -1;
758 s->height = -1;
759 s->invalidated = 1;
760#ifdef EMBED_STDVGA
761 s->invalidate(opaque);
762#endif
763 if (s->enable)
764 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
765 break;
766
767 case SVGA_REG_WIDTH:
768 s->new_width = value;
769 s->invalidated = 1;
770 break;
771
772 case SVGA_REG_HEIGHT:
773 s->new_height = value;
774 s->invalidated = 1;
775 break;
776
777 case SVGA_REG_DEPTH:
778 case SVGA_REG_BITS_PER_PIXEL:
779 if (value != s->depth) {
780 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
781 s->config = 0;
782 }
783 break;
784
785 case SVGA_REG_CONFIG_DONE:
786 if (value) {
787 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
788 /* Check range and alignment. */
789 if ((s->cmd->min | s->cmd->max |
790 s->cmd->next_cmd | s->cmd->stop) & 3)
791 break;
792 if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
793 break;
794 if (s->cmd->max > SVGA_FIFO_SIZE)
795 break;
796 if (s->cmd->max < s->cmd->min + 10 * 1024)
797 break;
798 }
f707cfba 799 s->config = !!value;
d34cab9f
TS		 800 break;
801
802 case SVGA_REG_SYNC:
803 s->syncing = 1;
804 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
805 break;
806
807 case SVGA_REG_GUEST_ID:
808 s->guest = value;
809#ifdef VERBOSE
810 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
811 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
812 printf("%s: guest runs %s.\n", __FUNCTION__,
813 vmsvga_guest_id[value - GUEST_OS_BASE]);
814#endif
815 break;
816
817 case SVGA_REG_CURSOR_ID:
818 s->cursor.id = value;
819 break;
820
821 case SVGA_REG_CURSOR_X:
822 s->cursor.x = value;
823 break;
824
825 case SVGA_REG_CURSOR_Y:
826 s->cursor.y = value;
827 break;
828
829 case SVGA_REG_CURSOR_ON:
830 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
831 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
832#ifdef HW_MOUSE_ACCEL
833 if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
834 s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
835#endif
836 break;
837
838 case SVGA_REG_MEM_REGS:
839 case SVGA_REG_NUM_DISPLAYS:
840 case SVGA_REG_PITCHLOCK:
841 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
842 break;
843
844 default:
845 if (s->index >= SVGA_SCRATCH_BASE &&
846 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
847 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
848 break;
849 }
850 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
851 }
852}
853
854static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
855{
856 printf("%s: what are we supposed to return?\n", __FUNCTION__);
857 return 0xcafe;
858}
859
860static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
861{
862 printf("%s: what are we supposed to do with (%08x)?\n",
863 __FUNCTION__, data);
864}
865
866static inline void vmsvga_size(struct vmsvga_state_s *s)
867{
868 if (s->new_width != s->width || s->new_height != s->height) {
869 s->width = s->new_width;
870 s->height = s->new_height;
871 dpy_resize(s->ds, s->width, s->height);
872 s->invalidated = 1;
873 }
874}
875
876static void vmsvga_update_display(void *opaque)
877{
878 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
879 if (!s->enable) {
880#ifdef EMBED_STDVGA
881 s->update(opaque);
882#endif
883 return;
884 }
885
886 vmsvga_size(s);
887
888 vmsvga_fifo_run(s);
889 vmsvga_update_rect_flush(s);
890
891 /*
892 * Is it more efficient to look at vram VGA-dirty bits or wait
893 * for the driver to issue SVGA_CMD_UPDATE?
894 */
895 if (s->invalidated) {
896 s->invalidated = 0;
897 vmsvga_update_screen(s);
898 }
899}
900
901static void vmsvga_reset(struct vmsvga_state_s *s)
902{
903 s->index = 0;
904 s->enable = 0;
905 s->config = 0;
906 s->width = -1;
907 s->height = -1;
908 s->svgaid = SVGA_ID;
909 s->depth = s->ds->depth ? s->ds->depth : 24;
910 s->bypp = (s->depth + 7) >> 3;
911 s->cursor.on = 0;
912 s->redraw_fifo_first = 0;
913 s->redraw_fifo_last = 0;
914 switch (s->depth) {
915 case 8:
916 s->wred = 0x00000007;
917 s->wgreen = 0x00000038;
918 s->wblue = 0x000000c0;
919 break;
920 case 15:
921 s->wred = 0x0000001f;
922 s->wgreen = 0x000003e0;
923 s->wblue = 0x00007c00;
924 break;
925 case 16:
926 s->wred = 0x0000001f;
927 s->wgreen = 0x000007e0;
928 s->wblue = 0x0000f800;
929 break;
930 case 24:
f707cfba 931 s->wred = 0x00ff0000;
d34cab9f 932 s->wgreen = 0x0000ff00;
f707cfba 933 s->wblue = 0x000000ff;
d34cab9f
TS		 934 break;
935 case 32:
f707cfba 936 s->wred = 0x00ff0000;
d34cab9f 937 s->wgreen = 0x0000ff00;
f707cfba 938 s->wblue = 0x000000ff;
d34cab9f
TS		 939 break;
940 }
941 s->syncing = 0;
942}
943
944static void vmsvga_invalidate_display(void *opaque)
945{
946 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
947 if (!s->enable) {
948#ifdef EMBED_STDVGA
949 s->invalidate(opaque);
950#endif
951 return;
952 }
953
954 s->invalidated = 1;
955}
956
f707cfba
AZ		 957/* save the vga display in a PPM image even if no display is
958 available */
d34cab9f
TS		 959static void vmsvga_screen_dump(void *opaque, const char *filename)
960{
961 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
962 if (!s->enable) {
963#ifdef EMBED_STDVGA
964 s->screen_dump(opaque, filename);
965#endif
966 return;
967 }
968
f707cfba
AZ		 969 if (s->depth == 32) {
970 ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
971 }
d34cab9f
TS		 972}
973
4d3b6f6e
AZ		 974static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
975{
976 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
977
978 if (s->text_update)
979 s->text_update(opaque, chardata);
980}
981
d34cab9f
TS		 982#ifdef DIRECT_VRAM
983static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
984{
985 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
3016d80b 986 addr -= s->vram_base;
d34cab9f
TS		 987 if (addr < s->fb_size)
988 return *(uint8_t *) (s->ds->data + addr);
989 else
990 return *(uint8_t *) (s->vram + addr);
991}
992
993static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
994{
995 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
3016d80b 996 addr -= s->vram_base;
d34cab9f
TS		 997 if (addr < s->fb_size)
998 return *(uint16_t *) (s->ds->data + addr);
999 else
1000 return *(uint16_t *) (s->vram + addr);
1001}
1002
1003static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1004{
1005 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
3016d80b 1006 addr -= s->vram_base;
d34cab9f
TS		 1007 if (addr < s->fb_size)
1008 return *(uint32_t *) (s->ds->data + addr);
1009 else
1010 return *(uint32_t *) (s->vram + addr);
1011}
1012
1013static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1014 uint32_t value)
1015{
1016 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
3016d80b 1017 addr -= s->vram_base;
d34cab9f
TS		 1018 if (addr < s->fb_size)
1019 *(uint8_t *) (s->ds->data + addr) = value;
1020 else
1021 *(uint8_t *) (s->vram + addr) = value;
1022}
1023
1024static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1025 uint32_t value)
1026{
1027 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
3016d80b 1028 addr -= s->vram_base;
d34cab9f
TS		 1029 if (addr < s->fb_size)
1030 *(uint16_t *) (s->ds->data + addr) = value;
1031 else
1032 *(uint16_t *) (s->vram + addr) = value;
1033}
1034
1035static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1036 uint32_t value)
1037{
1038 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
3016d80b 1039 addr -= s->vram_base;
d34cab9f
TS		 1040 if (addr < s->fb_size)
1041 *(uint32_t *) (s->ds->data + addr) = value;
1042 else
1043 *(uint32_t *) (s->vram + addr) = value;
1044}
1045
1046static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1047 vmsvga_vram_readb,
1048 vmsvga_vram_readw,
1049 vmsvga_vram_readl,
1050};
1051
1052static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1053 vmsvga_vram_writeb,
1054 vmsvga_vram_writew,
1055 vmsvga_vram_writel,
1056};
1057#endif
1058
1059static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1060{
bee8d684
TS		 1061 qemu_put_be32(f, s->depth);
1062 qemu_put_be32(f, s->enable);
1063 qemu_put_be32(f, s->config);
1064 qemu_put_be32(f, s->cursor.id);
1065 qemu_put_be32(f, s->cursor.x);
1066 qemu_put_be32(f, s->cursor.y);
1067 qemu_put_be32(f, s->cursor.on);
1068 qemu_put_be32(f, s->index);
d34cab9f 1069 qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
bee8d684
TS		 1070 qemu_put_be32(f, s->new_width);
1071 qemu_put_be32(f, s->new_height);
d34cab9f
TS		 1072 qemu_put_be32s(f, &s->guest);
1073 qemu_put_be32s(f, &s->svgaid);
bee8d684
TS		 1074 qemu_put_be32(f, s->syncing);
1075 qemu_put_be32(f, s->fb_size);
d34cab9f
TS		 1076}
1077
1078static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1079{
1080 int depth;
bee8d684
TS		 1081 depth=qemu_get_be32(f);
1082 s->enable=qemu_get_be32(f);
1083 s->config=qemu_get_be32(f);
1084 s->cursor.id=qemu_get_be32(f);
1085 s->cursor.x=qemu_get_be32(f);
1086 s->cursor.y=qemu_get_be32(f);
1087 s->cursor.on=qemu_get_be32(f);
1088 s->index=qemu_get_be32(f);
d34cab9f 1089 qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
bee8d684
TS		 1090 s->new_width=qemu_get_be32(f);
1091 s->new_height=qemu_get_be32(f);
d34cab9f
TS		 1092 qemu_get_be32s(f, &s->guest);
1093 qemu_get_be32s(f, &s->svgaid);
bee8d684
TS		 1094 s->syncing=qemu_get_be32(f);
1095 s->fb_size=qemu_get_be32(f);
d34cab9f
TS		 1096
1097 if (s->enable && depth != s->depth) {
1098 printf("%s: need colour depth of %i bits to resume operation.\n",
1099 __FUNCTION__, depth);
1100 return -EINVAL;
1101 }
1102
1103 s->invalidated = 1;
1104 if (s->config)
1105 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1106
1107 return 0;
1108}
1109
1110static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1111 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1112 int vga_ram_size)
1113{
d34cab9f
TS		 1114 s->ds = ds;
1115 s->vram = vga_ram_base;
1116 s->vram_size = vga_ram_size;
1117
1118 s->scratch_size = SVGA_SCRATCH_SIZE;
1119 s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1120
1121 vmsvga_reset(s);
1122
d34cab9f 1123 graphic_console_init(ds, vmsvga_update_display,
4d3b6f6e
AZ		 1124 vmsvga_invalidate_display, vmsvga_screen_dump,
1125 vmsvga_text_update, s);
d34cab9f
TS		 1126
1127#ifdef EMBED_STDVGA
1128 vga_common_init((VGAState *) s, ds,
1129 vga_ram_base, vga_ram_offset, vga_ram_size);
1130 vga_init((VGAState *) s);
1131#endif
1132}
1133
1134static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1135{
1136 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1137 pci_device_save(&s->card, f);
1138 vmsvga_save(&s->chip, f);
1139}
1140
1141static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1142{
1143 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1144 int ret;
1145
1146 ret = pci_device_load(&s->card, f);
1147 if (ret < 0)
1148 return ret;
1149
1150 ret = vmsvga_load(&s->chip, f);
1151 if (ret < 0)
1152 return ret;
1153
1154 return 0;
1155}
1156
1492a3c4
AZ		 1157static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1158 uint32_t addr, uint32_t size, int type)
1159{
1160 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1161 struct vmsvga_state_s *s = &d->chip;
1162
1163 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1164 1, 4, vmsvga_index_read, s);
1165 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1166 1, 4, vmsvga_index_write, s);
1167 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1168 1, 4, vmsvga_value_read, s);
1169 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1170 1, 4, vmsvga_value_write, s);
1171 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1172 1, 4, vmsvga_bios_read, s);
1173 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1174 1, 4, vmsvga_bios_write, s);
1175}
1176
3016d80b
AZ		 1177static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1178 uint32_t addr, uint32_t size, int type)
1179{
1180 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1181 struct vmsvga_state_s *s = &d->chip;
1182 int iomemtype;
1183
1184 s->vram_base = addr;
1185#ifdef DIRECT_VRAM
1186 iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1187 vmsvga_vram_write, s);
1188#else
1189 iomemtype = 0 | IO_MEM_RAM;
1190#endif
1191 cpu_register_physical_memory(s->vram_base, s->vram_size,
1192 iomemtype);
1193}
1194
d34cab9f
TS		 1195#define PCI_VENDOR_ID_VMWARE 0x15ad
1196#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
1197#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
1198#define PCI_DEVICE_ID_VMWARE_NET 0x0720
1199#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
1200#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
1201#define PCI_CLASS_BASE_DISPLAY 0x03
1202#define PCI_CLASS_SUB_VGA 0x00
1203#define PCI_CLASS_HEADERTYPE_00h 0x00
1204
1205void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1206 unsigned long vga_ram_offset, int vga_ram_size)
1207{
1208 struct pci_vmsvga_state_s *s;
1209
1210 /* Setup PCI configuration */
1211 s = (struct pci_vmsvga_state_s *)
1212 pci_register_device(bus, "QEMUware SVGA",
1213 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1214 s->card.config[PCI_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
1215 s->card.config[PCI_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8;
1216 s->card.config[PCI_DEVICE_ID] = SVGA_PCI_DEVICE_ID & 0xff;
1217 s->card.config[PCI_DEVICE_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
1218 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
1219 s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA;
1220 s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY;
1221 s->card.config[0x0c] = 0x08; /* Cache line size */
1222 s->card.config[0x0d] = 0x40; /* Latency timer */
1223 s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
1224 s->card.config[0x10] = ((SVGA_IO_BASE >> 0) & 0xff) | 1;
1225 s->card.config[0x11] = (SVGA_IO_BASE >> 8) & 0xff;
1226 s->card.config[0x12] = (SVGA_IO_BASE >> 16) & 0xff;
1227 s->card.config[0x13] = (SVGA_IO_BASE >> 24) & 0xff;
1228 s->card.config[0x18] = (SVGA_MEM_BASE >> 0) & 0xff;
1229 s->card.config[0x19] = (SVGA_MEM_BASE >> 8) & 0xff;
1230 s->card.config[0x1a] = (SVGA_MEM_BASE >> 16) & 0xff;
1231 s->card.config[0x1b] = (SVGA_MEM_BASE >> 24) & 0xff;
1232 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1233 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1234 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1235 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1236 s->card.config[0x3c] = 0xff; /* End */
1237
1492a3c4
AZ		 1238 pci_register_io_region(&s->card, 0, 0x10,
1239 PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
2408b77b 1240 pci_register_io_region(&s->card, 1, vga_ram_size,
3016d80b 1241 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
1492a3c4 1242
d34cab9f
TS		 1243 vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1244
1245 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1246}
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