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Correct qemu-img usage hint (Andreas Färber).
[qemu.git] / hw / vmware_vga.c
CommitLineData
d34cab9f
TS		 1/*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <[email protected]>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b
PB		 24#include "hw.h"
25#include "console.h"
26#include "pci.h"
d34cab9f
TS		 27
28#define VERBOSE
29#define EMBED_STDVGA
30#undef DIRECT_VRAM
31#define HW_RECT_ACCEL
32#define HW_FILL_ACCEL
33#define HW_MOUSE_ACCEL
34
35#ifdef EMBED_STDVGA
36# include "vga_int.h"
37#endif
38
39struct vmsvga_state_s {
40#ifdef EMBED_STDVGA
41 VGA_STATE_COMMON
42#endif
43
44 int width;
45 int height;
46 int invalidated;
47 int depth;
48 int bypp;
49 int enable;
50 int config;
51 struct {
52 int id;
53 int x;
54 int y;
55 int on;
56 } cursor;
57
58#ifndef EMBED_STDVGA
59 DisplayState *ds;
60 int vram_size;
61#endif
62 uint8_t *vram;
63
64 int index;
65 int scratch_size;
66 uint32_t *scratch;
67 int new_width;
68 int new_height;
69 uint32_t guest;
70 uint32_t svgaid;
71 uint32_t wred;
72 uint32_t wgreen;
73 uint32_t wblue;
74 int syncing;
75 int fb_size;
76
77 union {
78 uint32_t *fifo;
79 struct __attribute__((__packed__)) {
80 uint32_t min;
81 uint32_t max;
82 uint32_t next_cmd;
83 uint32_t stop;
84 /* Add registers here when adding capabilities. */
85 uint32_t fifo[0];
86 } *cmd;
87 };
88
89#define REDRAW_FIFO_LEN 512
90 struct vmsvga_rect_s {
91 int x, y, w, h;
92 } redraw_fifo[REDRAW_FIFO_LEN];
93 int redraw_fifo_first, redraw_fifo_last;
94};
95
96struct pci_vmsvga_state_s {
97 PCIDevice card;
98 struct vmsvga_state_s chip;
99};
100
101#define SVGA_MAGIC 0x900000UL
102#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
103#define SVGA_ID_0 SVGA_MAKE_ID(0)
104#define SVGA_ID_1 SVGA_MAKE_ID(1)
105#define SVGA_ID_2 SVGA_MAKE_ID(2)
106
107#define SVGA_LEGACY_BASE_PORT 0x4560
108#define SVGA_INDEX_PORT 0x0
109#define SVGA_VALUE_PORT 0x1
110#define SVGA_BIOS_PORT 0x2
111
112#define SVGA_VERSION_2
113
114#ifdef SVGA_VERSION_2
115# define SVGA_ID SVGA_ID_2
116# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
117# define SVGA_IO_MUL 1
118# define SVGA_FIFO_SIZE 0x10000
1f72aae5 119# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 120# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
121#else
122# define SVGA_ID SVGA_ID_1
123# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
124# define SVGA_IO_MUL 4
125# define SVGA_FIFO_SIZE 0x10000
1f72aae5 126# define SVGA_MEM_BASE 0xe0000000
d34cab9f
TS		 127# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
128#endif
129
130enum {
131 /* ID 0, 1 and 2 registers */
132 SVGA_REG_ID = 0,
133 SVGA_REG_ENABLE = 1,
134 SVGA_REG_WIDTH = 2,
135 SVGA_REG_HEIGHT = 3,
136 SVGA_REG_MAX_WIDTH = 4,
137 SVGA_REG_MAX_HEIGHT = 5,
138 SVGA_REG_DEPTH = 6,
139 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
140 SVGA_REG_PSEUDOCOLOR = 8,
141 SVGA_REG_RED_MASK = 9,
142 SVGA_REG_GREEN_MASK = 10,
143 SVGA_REG_BLUE_MASK = 11,
144 SVGA_REG_BYTES_PER_LINE = 12,
145 SVGA_REG_FB_START = 13,
146 SVGA_REG_FB_OFFSET = 14,
147 SVGA_REG_VRAM_SIZE = 15,
148 SVGA_REG_FB_SIZE = 16,
149
150 /* ID 1 and 2 registers */
151 SVGA_REG_CAPABILITIES = 17,
152 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
153 SVGA_REG_MEM_SIZE = 19,
154 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
155 SVGA_REG_SYNC = 21, /* Write to force synchronization */
156 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
157 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
158 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
159 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
160 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
161 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
162 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
163 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
164 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
165 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
166 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
167
168 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
169 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
170 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
171};
172
173#define SVGA_CAP_NONE 0
174#define SVGA_CAP_RECT_FILL (1 << 0)
175#define SVGA_CAP_RECT_COPY (1 << 1)
176#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
177#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
178#define SVGA_CAP_RASTER_OP (1 << 4)
179#define SVGA_CAP_CURSOR (1 << 5)
180#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
181#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
182#define SVGA_CAP_8BIT_EMULATION (1 << 8)
183#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
184#define SVGA_CAP_GLYPH (1 << 10)
185#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
186#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
187#define SVGA_CAP_ALPHA_BLEND (1 << 13)
188#define SVGA_CAP_3D (1 << 14)
189#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
190#define SVGA_CAP_MULTIMON (1 << 16)
191#define SVGA_CAP_PITCHLOCK (1 << 17)
192
193/*
194 * FIFO offsets (seen as an array of 32-bit words)
195 */
196enum {
197 /*
198 * The original defined FIFO offsets
199 */
200 SVGA_FIFO_MIN = 0,
201 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
202 SVGA_FIFO_NEXT_CMD,
203 SVGA_FIFO_STOP,
204
205 /*
206 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
207 */
208 SVGA_FIFO_CAPABILITIES = 4,
209 SVGA_FIFO_FLAGS,
210 SVGA_FIFO_FENCE,
211 SVGA_FIFO_3D_HWVERSION,
212 SVGA_FIFO_PITCHLOCK,
213};
214
215#define SVGA_FIFO_CAP_NONE 0
216#define SVGA_FIFO_CAP_FENCE (1 << 0)
217#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
218#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
219
220#define SVGA_FIFO_FLAG_NONE 0
221#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
222
223/* These values can probably be changed arbitrarily. */
224#define SVGA_SCRATCH_SIZE 0x8000
225#define SVGA_MAX_WIDTH 2360
226#define SVGA_MAX_HEIGHT 1770
227
228#ifdef VERBOSE
229# define GUEST_OS_BASE 0x5001
230static const char *vmsvga_guest_id[] = {
f707cfba
AZ		 231 [0x00 ... 0x15] = "an unknown OS",
232 [0x00] = "Dos",
233 [0x01] = "Windows 3.1",
234 [0x02] = "Windows 95",
235 [0x03] = "Windows 98",
236 [0x04] = "Windows ME",
237 [0x05] = "Windows NT",
238 [0x06] = "Windows 2000",
239 [0x07] = "Linux",
240 [0x08] = "OS/2",
241 [0x0a] = "BSD",
242 [0x0b] = "Whistler",
243 [0x15] = "Windows 2003",
d34cab9f
TS		 244};
245#endif
246
247enum {
248 SVGA_CMD_INVALID_CMD = 0,
249 SVGA_CMD_UPDATE = 1,
250 SVGA_CMD_RECT_FILL = 2,
251 SVGA_CMD_RECT_COPY = 3,
252 SVGA_CMD_DEFINE_BITMAP = 4,
253 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
254 SVGA_CMD_DEFINE_PIXMAP = 6,
255 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
256 SVGA_CMD_RECT_BITMAP_FILL = 8,
257 SVGA_CMD_RECT_PIXMAP_FILL = 9,
258 SVGA_CMD_RECT_BITMAP_COPY = 10,
259 SVGA_CMD_RECT_PIXMAP_COPY = 11,
260 SVGA_CMD_FREE_OBJECT = 12,
261 SVGA_CMD_RECT_ROP_FILL = 13,
262 SVGA_CMD_RECT_ROP_COPY = 14,
263 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
264 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
265 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
266 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
267 SVGA_CMD_DEFINE_CURSOR = 19,
268 SVGA_CMD_DISPLAY_CURSOR = 20,
269 SVGA_CMD_MOVE_CURSOR = 21,
270 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
271 SVGA_CMD_DRAW_GLYPH = 23,
272 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
273 SVGA_CMD_UPDATE_VERBOSE = 25,
274 SVGA_CMD_SURFACE_FILL = 26,
275 SVGA_CMD_SURFACE_COPY = 27,
276 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
277 SVGA_CMD_FRONT_ROP_FILL = 29,
278 SVGA_CMD_FENCE = 30,
279};
280
281/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
282enum {
283 SVGA_CURSOR_ON_HIDE = 0,
284 SVGA_CURSOR_ON_SHOW = 1,
285 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
286 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
287};
288
289static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
290 int x, int y, int w, int h)
291{
292#ifndef DIRECT_VRAM
293 int line = h;
294 int bypl = s->bypp * s->width;
295 int width = s->bypp * w;
296 int start = s->bypp * x + bypl * y;
297 uint8_t *src = s->vram + start;
298 uint8_t *dst = s->ds->data + start;
299
300 for (; line > 0; line --, src += bypl, dst += bypl)
301 memcpy(dst, src, width);
302#endif
303
304 dpy_update(s->ds, x, y, w, h);
305}
306
307static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
308{
309#ifndef DIRECT_VRAM
310 memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
311#endif
312
313 dpy_update(s->ds, 0, 0, s->width, s->height);
314}
315
316#ifdef DIRECT_VRAM
317# define vmsvga_update_rect_delayed vmsvga_update_rect
318#else
319static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
320 int x, int y, int w, int h)
321{
322 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
323 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
324 rect->x = x;
325 rect->y = y;
326 rect->w = w;
327 rect->h = h;
328}
329#endif
330
331static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
332{
333 struct vmsvga_rect_s *rect;
334 if (s->invalidated) {
335 s->redraw_fifo_first = s->redraw_fifo_last;
336 return;
337 }
338 /* Overlapping region updates can be optimised out here - if someone
339 * knows a smart algorithm to do that, please share. */
340 while (s->redraw_fifo_first != s->redraw_fifo_last) {
341 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
342 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
343 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
344 }
345}
346
347#ifdef HW_RECT_ACCEL
348static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
349 int x0, int y0, int x1, int y1, int w, int h)
350{
351# ifdef DIRECT_VRAM
352 uint8_t *vram = s->ds->data;
353# else
354 uint8_t *vram = s->vram;
355# endif
356 int bypl = s->bypp * s->width;
357 int width = s->bypp * w;
358 int line = h;
359 uint8_t *ptr[2];
360
361# ifdef DIRECT_VRAM
362 if (s->ds->dpy_copy)
363 s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
364 else
365# endif
366 {
367 if (y1 > y0) {
368 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
369 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
370 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
371 memmove(ptr[1], ptr[0], width);
372 } else {
373 ptr[0] = vram + s->bypp * x0 + bypl * y0;
374 ptr[1] = vram + s->bypp * x1 + bypl * y1;
375 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
376 memmove(ptr[1], ptr[0], width);
377 }
378 }
379
380 vmsvga_update_rect_delayed(s, x1, y1, w, h);
381}
382#endif
383
384#ifdef HW_FILL_ACCEL
385static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
386 uint32_t c, int x, int y, int w, int h)
387{
388# ifdef DIRECT_VRAM
389 uint8_t *vram = s->ds->data;
390# else
391 uint8_t *vram = s->vram;
392# endif
393 int bypp = s->bypp;
394 int bypl = bypp * s->width;
395 int width = bypp * w;
396 int line = h;
397 int column;
398 uint8_t *fst = vram + bypp * x + bypl * y;
399 uint8_t *dst;
400 uint8_t *src;
401 uint8_t col[4];
402
403# ifdef DIRECT_VRAM
404 if (s->ds->dpy_fill)
405 s->ds->dpy_fill(s->ds, x, y, w, h, c);
406 else
407# endif
408 {
409 col[0] = c;
410 col[1] = c >> 8;
411 col[2] = c >> 16;
412 col[3] = c >> 24;
413
414 if (line --) {
415 dst = fst;
416 src = col;
417 for (column = width; column > 0; column --) {
418 *(dst ++) = *(src ++);
419 if (src - col == bypp)
420 src = col;
421 }
422 dst = fst;
423 for (; line > 0; line --) {
424 dst += bypl;
425 memcpy(dst, fst, width);
426 }
427 }
428 }
429
430 vmsvga_update_rect_delayed(s, x, y, w, h);
431}
432#endif
433
434struct vmsvga_cursor_definition_s {
435 int width;
436 int height;
437 int id;
438 int bpp;
439 int hot_x;
440 int hot_y;
441 uint32_t mask[1024];
442 uint32_t image[1024];
443};
444
445#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
446#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
447
448#ifdef HW_MOUSE_ACCEL
449static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
450 struct vmsvga_cursor_definition_s *c)
451{
452 int i;
453 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
454 c->mask[i] = ~c->mask[i];
455
456 if (s->ds->cursor_define)
457 s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
458 (uint8_t *) c->image, (uint8_t *) c->mask);
459}
460#endif
461
462static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
463{
464 if (!s->config || !s->enable)
f707cfba 465 return 1;
d34cab9f
TS		 466 return (s->cmd->next_cmd == s->cmd->stop);
467}
468
469static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
470{
471 uint32_t cmd = s->fifo[s->cmd->stop >> 2];
472 s->cmd->stop += 4;
473 if (s->cmd->stop >= s->cmd->max)
474 s->cmd->stop = s->cmd->min;
475 return cmd;
476}
477
478static void vmsvga_fifo_run(struct vmsvga_state_s *s)
479{
480 uint32_t cmd, colour;
481 int args = 0;
482 int x, y, dx, dy, width, height;
483 struct vmsvga_cursor_definition_s cursor;
484 while (!vmsvga_fifo_empty(s))
485 switch (cmd = vmsvga_fifo_read(s)) {
486 case SVGA_CMD_UPDATE:
487 case SVGA_CMD_UPDATE_VERBOSE:
488 x = vmsvga_fifo_read(s);
489 y = vmsvga_fifo_read(s);
490 width = vmsvga_fifo_read(s);
491 height = vmsvga_fifo_read(s);
492 vmsvga_update_rect_delayed(s, x, y, width, height);
493 break;
494
495 case SVGA_CMD_RECT_FILL:
496 colour = vmsvga_fifo_read(s);
497 x = vmsvga_fifo_read(s);
498 y = vmsvga_fifo_read(s);
499 width = vmsvga_fifo_read(s);
500 height = vmsvga_fifo_read(s);
501#ifdef HW_FILL_ACCEL
502 vmsvga_fill_rect(s, colour, x, y, width, height);
503 break;
504#else
505 goto badcmd;
506#endif
507
508 case SVGA_CMD_RECT_COPY:
509 x = vmsvga_fifo_read(s);
510 y = vmsvga_fifo_read(s);
511 dx = vmsvga_fifo_read(s);
512 dy = vmsvga_fifo_read(s);
513 width = vmsvga_fifo_read(s);
514 height = vmsvga_fifo_read(s);
515#ifdef HW_RECT_ACCEL
516 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
517 break;
518#else
519 goto badcmd;
520#endif
521
522 case SVGA_CMD_DEFINE_CURSOR:
523 cursor.id = vmsvga_fifo_read(s);
524 cursor.hot_x = vmsvga_fifo_read(s);
525 cursor.hot_y = vmsvga_fifo_read(s);
526 cursor.width = x = vmsvga_fifo_read(s);
527 cursor.height = y = vmsvga_fifo_read(s);
528 vmsvga_fifo_read(s);
529 cursor.bpp = vmsvga_fifo_read(s);
530 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
531 cursor.mask[args] = vmsvga_fifo_read(s);
532 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
533 cursor.image[args] = vmsvga_fifo_read(s);
534#ifdef HW_MOUSE_ACCEL
535 vmsvga_cursor_define(s, &cursor);
536 break;
537#else
538 args = 0;
539 goto badcmd;
540#endif
541
542 /*
543 * Other commands that we at least know the number of arguments
544 * for so we can avoid FIFO desync if driver uses them illegally.
545 */
546 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
547 vmsvga_fifo_read(s);
548 vmsvga_fifo_read(s);
549 vmsvga_fifo_read(s);
550 x = vmsvga_fifo_read(s);
551 y = vmsvga_fifo_read(s);
552 args = x * y;
553 goto badcmd;
554 case SVGA_CMD_RECT_ROP_FILL:
555 args = 6;
556 goto badcmd;
557 case SVGA_CMD_RECT_ROP_COPY:
558 args = 7;
559 goto badcmd;
560 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
561 vmsvga_fifo_read(s);
562 vmsvga_fifo_read(s);
563 args = 7 + (vmsvga_fifo_read(s) >> 2);
564 goto badcmd;
565 case SVGA_CMD_SURFACE_ALPHA_BLEND:
566 args = 12;
567 goto badcmd;
568
569 /*
570 * Other commands that are not listed as depending on any
571 * CAPABILITIES bits, but are not described in the README either.
572 */
573 case SVGA_CMD_SURFACE_FILL:
574 case SVGA_CMD_SURFACE_COPY:
575 case SVGA_CMD_FRONT_ROP_FILL:
576 case SVGA_CMD_FENCE:
577 case SVGA_CMD_INVALID_CMD:
578 break; /* Nop */
579
580 default:
581 badcmd:
582 while (args --)
583 vmsvga_fifo_read(s);
584 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
585 __FUNCTION__, cmd);
586 break;
587 }
588
589 s->syncing = 0;
590}
591
592static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
593{
594 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
595 return s->index;
596}
597
598static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
599{
600 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
601 s->index = index;
602}
603
604static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
605{
606 uint32_t caps;
607 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
608 switch (s->index) {
609 case SVGA_REG_ID:
610 return s->svgaid;
611
612 case SVGA_REG_ENABLE:
613 return s->enable;
614
615 case SVGA_REG_WIDTH:
616 return s->width;
617
618 case SVGA_REG_HEIGHT:
619 return s->height;
620
621 case SVGA_REG_MAX_WIDTH:
622 return SVGA_MAX_WIDTH;
623
624 case SVGA_REG_MAX_HEIGHT:
f707cfba 625 return SVGA_MAX_HEIGHT;
d34cab9f
TS		 626
627 case SVGA_REG_DEPTH:
628 return s->depth;
629
630 case SVGA_REG_BITS_PER_PIXEL:
631 return (s->depth + 7) & ~7;
632
633 case SVGA_REG_PSEUDOCOLOR:
634 return 0x0;
635
636 case SVGA_REG_RED_MASK:
637 return s->wred;
638 case SVGA_REG_GREEN_MASK:
639 return s->wgreen;
640 case SVGA_REG_BLUE_MASK:
641 return s->wblue;
642
643 case SVGA_REG_BYTES_PER_LINE:
644 return ((s->depth + 7) >> 3) * s->new_width;
645
646 case SVGA_REG_FB_START:
647 return SVGA_MEM_BASE;
648
649 case SVGA_REG_FB_OFFSET:
650 return 0x0;
651
652 case SVGA_REG_VRAM_SIZE:
653 return s->vram_size - SVGA_FIFO_SIZE;
654
655 case SVGA_REG_FB_SIZE:
656 return s->fb_size;
657
658 case SVGA_REG_CAPABILITIES:
659 caps = SVGA_CAP_NONE;
660#ifdef HW_RECT_ACCEL
661 caps |= SVGA_CAP_RECT_COPY;
662#endif
663#ifdef HW_FILL_ACCEL
664 caps |= SVGA_CAP_RECT_FILL;
665#endif
666#ifdef HW_MOUSE_ACCEL
667 if (s->ds->mouse_set)
668 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
669 SVGA_CAP_CURSOR_BYPASS;
670#endif
671 return caps;
672
673 case SVGA_REG_MEM_START:
674 return SVGA_MEM_BASE + s->vram_size - SVGA_FIFO_SIZE;
675
676 case SVGA_REG_MEM_SIZE:
677 return SVGA_FIFO_SIZE;
678
679 case SVGA_REG_CONFIG_DONE:
680 return s->config;
681
682 case SVGA_REG_SYNC:
683 case SVGA_REG_BUSY:
684 return s->syncing;
685
686 case SVGA_REG_GUEST_ID:
687 return s->guest;
688
689 case SVGA_REG_CURSOR_ID:
690 return s->cursor.id;
691
692 case SVGA_REG_CURSOR_X:
693 return s->cursor.x;
694
695 case SVGA_REG_CURSOR_Y:
696 return s->cursor.x;
697
698 case SVGA_REG_CURSOR_ON:
699 return s->cursor.on;
700
701 case SVGA_REG_HOST_BITS_PER_PIXEL:
702 return (s->depth + 7) & ~7;
703
704 case SVGA_REG_SCRATCH_SIZE:
705 return s->scratch_size;
706
707 case SVGA_REG_MEM_REGS:
708 case SVGA_REG_NUM_DISPLAYS:
709 case SVGA_REG_PITCHLOCK:
710 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
711 return 0;
712
713 default:
714 if (s->index >= SVGA_SCRATCH_BASE &&
715 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
716 return s->scratch[s->index - SVGA_SCRATCH_BASE];
717 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
718 }
719
720 return 0;
721}
722
723static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
724{
725 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
726 switch (s->index) {
727 case SVGA_REG_ID:
728 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
729 s->svgaid = value;
730 break;
731
732 case SVGA_REG_ENABLE:
f707cfba
AZ		 733 s->enable = value;
734 s->config &= !!value;
d34cab9f
TS		 735 s->width = -1;
736 s->height = -1;
737 s->invalidated = 1;
738#ifdef EMBED_STDVGA
739 s->invalidate(opaque);
740#endif
741 if (s->enable)
742 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
743 break;
744
745 case SVGA_REG_WIDTH:
746 s->new_width = value;
747 s->invalidated = 1;
748 break;
749
750 case SVGA_REG_HEIGHT:
751 s->new_height = value;
752 s->invalidated = 1;
753 break;
754
755 case SVGA_REG_DEPTH:
756 case SVGA_REG_BITS_PER_PIXEL:
757 if (value != s->depth) {
758 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
759 s->config = 0;
760 }
761 break;
762
763 case SVGA_REG_CONFIG_DONE:
764 if (value) {
765 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
766 /* Check range and alignment. */
767 if ((s->cmd->min | s->cmd->max |
768 s->cmd->next_cmd | s->cmd->stop) & 3)
769 break;
770 if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
771 break;
772 if (s->cmd->max > SVGA_FIFO_SIZE)
773 break;
774 if (s->cmd->max < s->cmd->min + 10 * 1024)
775 break;
776 }
f707cfba 777 s->config = !!value;
d34cab9f
TS		 778 break;
779
780 case SVGA_REG_SYNC:
781 s->syncing = 1;
782 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
783 break;
784
785 case SVGA_REG_GUEST_ID:
786 s->guest = value;
787#ifdef VERBOSE
788 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
789 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
790 printf("%s: guest runs %s.\n", __FUNCTION__,
791 vmsvga_guest_id[value - GUEST_OS_BASE]);
792#endif
793 break;
794
795 case SVGA_REG_CURSOR_ID:
796 s->cursor.id = value;
797 break;
798
799 case SVGA_REG_CURSOR_X:
800 s->cursor.x = value;
801 break;
802
803 case SVGA_REG_CURSOR_Y:
804 s->cursor.y = value;
805 break;
806
807 case SVGA_REG_CURSOR_ON:
808 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
809 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
810#ifdef HW_MOUSE_ACCEL
811 if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
812 s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
813#endif
814 break;
815
816 case SVGA_REG_MEM_REGS:
817 case SVGA_REG_NUM_DISPLAYS:
818 case SVGA_REG_PITCHLOCK:
819 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
820 break;
821
822 default:
823 if (s->index >= SVGA_SCRATCH_BASE &&
824 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
825 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
826 break;
827 }
828 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
829 }
830}
831
832static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
833{
834 printf("%s: what are we supposed to return?\n", __FUNCTION__);
835 return 0xcafe;
836}
837
838static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
839{
840 printf("%s: what are we supposed to do with (%08x)?\n",
841 __FUNCTION__, data);
842}
843
844static inline void vmsvga_size(struct vmsvga_state_s *s)
845{
846 if (s->new_width != s->width || s->new_height != s->height) {
847 s->width = s->new_width;
848 s->height = s->new_height;
849 dpy_resize(s->ds, s->width, s->height);
850 s->invalidated = 1;
851 }
852}
853
854static void vmsvga_update_display(void *opaque)
855{
856 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
857 if (!s->enable) {
858#ifdef EMBED_STDVGA
859 s->update(opaque);
860#endif
861 return;
862 }
863
864 vmsvga_size(s);
865
866 vmsvga_fifo_run(s);
867 vmsvga_update_rect_flush(s);
868
869 /*
870 * Is it more efficient to look at vram VGA-dirty bits or wait
871 * for the driver to issue SVGA_CMD_UPDATE?
872 */
873 if (s->invalidated) {
874 s->invalidated = 0;
875 vmsvga_update_screen(s);
876 }
877}
878
879static void vmsvga_reset(struct vmsvga_state_s *s)
880{
881 s->index = 0;
882 s->enable = 0;
883 s->config = 0;
884 s->width = -1;
885 s->height = -1;
886 s->svgaid = SVGA_ID;
887 s->depth = s->ds->depth ? s->ds->depth : 24;
888 s->bypp = (s->depth + 7) >> 3;
889 s->cursor.on = 0;
890 s->redraw_fifo_first = 0;
891 s->redraw_fifo_last = 0;
892 switch (s->depth) {
893 case 8:
894 s->wred = 0x00000007;
895 s->wgreen = 0x00000038;
896 s->wblue = 0x000000c0;
897 break;
898 case 15:
899 s->wred = 0x0000001f;
900 s->wgreen = 0x000003e0;
901 s->wblue = 0x00007c00;
902 break;
903 case 16:
904 s->wred = 0x0000001f;
905 s->wgreen = 0x000007e0;
906 s->wblue = 0x0000f800;
907 break;
908 case 24:
f707cfba 909 s->wred = 0x00ff0000;
d34cab9f 910 s->wgreen = 0x0000ff00;
f707cfba 911 s->wblue = 0x000000ff;
d34cab9f
TS		 912 break;
913 case 32:
f707cfba 914 s->wred = 0x00ff0000;
d34cab9f 915 s->wgreen = 0x0000ff00;
f707cfba 916 s->wblue = 0x000000ff;
d34cab9f
TS		 917 break;
918 }
919 s->syncing = 0;
920}
921
922static void vmsvga_invalidate_display(void *opaque)
923{
924 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
925 if (!s->enable) {
926#ifdef EMBED_STDVGA
927 s->invalidate(opaque);
928#endif
929 return;
930 }
931
932 s->invalidated = 1;
933}
934
f707cfba
AZ		 935/* save the vga display in a PPM image even if no display is
936 available */
d34cab9f
TS		 937static void vmsvga_screen_dump(void *opaque, const char *filename)
938{
939 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
940 if (!s->enable) {
941#ifdef EMBED_STDVGA
942 s->screen_dump(opaque, filename);
943#endif
944 return;
945 }
946
f707cfba
AZ		 947 if (s->depth == 32) {
948 ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
949 }
d34cab9f
TS		 950}
951
952#ifdef DIRECT_VRAM
953static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
954{
955 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
956 addr -= SVGA_MEM_BASE;
957 if (addr < s->fb_size)
958 return *(uint8_t *) (s->ds->data + addr);
959 else
960 return *(uint8_t *) (s->vram + addr);
961}
962
963static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
964{
965 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
966 addr -= SVGA_MEM_BASE;
967 if (addr < s->fb_size)
968 return *(uint16_t *) (s->ds->data + addr);
969 else
970 return *(uint16_t *) (s->vram + addr);
971}
972
973static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
974{
975 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
976 addr -= SVGA_MEM_BASE;
977 if (addr < s->fb_size)
978 return *(uint32_t *) (s->ds->data + addr);
979 else
980 return *(uint32_t *) (s->vram + addr);
981}
982
983static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
984 uint32_t value)
985{
986 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
987 addr -= SVGA_MEM_BASE;
988 if (addr < s->fb_size)
989 *(uint8_t *) (s->ds->data + addr) = value;
990 else
991 *(uint8_t *) (s->vram + addr) = value;
992}
993
994static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
995 uint32_t value)
996{
997 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
998 addr -= SVGA_MEM_BASE;
999 if (addr < s->fb_size)
1000 *(uint16_t *) (s->ds->data + addr) = value;
1001 else
1002 *(uint16_t *) (s->vram + addr) = value;
1003}
1004
1005static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1006 uint32_t value)
1007{
1008 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1009 addr -= SVGA_MEM_BASE;
1010 if (addr < s->fb_size)
1011 *(uint32_t *) (s->ds->data + addr) = value;
1012 else
1013 *(uint32_t *) (s->vram + addr) = value;
1014}
1015
1016static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1017 vmsvga_vram_readb,
1018 vmsvga_vram_readw,
1019 vmsvga_vram_readl,
1020};
1021
1022static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1023 vmsvga_vram_writeb,
1024 vmsvga_vram_writew,
1025 vmsvga_vram_writel,
1026};
1027#endif
1028
1029static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1030{
bee8d684
TS		 1031 qemu_put_be32(f, s->depth);
1032 qemu_put_be32(f, s->enable);
1033 qemu_put_be32(f, s->config);
1034 qemu_put_be32(f, s->cursor.id);
1035 qemu_put_be32(f, s->cursor.x);
1036 qemu_put_be32(f, s->cursor.y);
1037 qemu_put_be32(f, s->cursor.on);
1038 qemu_put_be32(f, s->index);
d34cab9f 1039 qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
bee8d684
TS		 1040 qemu_put_be32(f, s->new_width);
1041 qemu_put_be32(f, s->new_height);
d34cab9f
TS		 1042 qemu_put_be32s(f, &s->guest);
1043 qemu_put_be32s(f, &s->svgaid);
bee8d684
TS		 1044 qemu_put_be32(f, s->syncing);
1045 qemu_put_be32(f, s->fb_size);
d34cab9f
TS		 1046}
1047
1048static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1049{
1050 int depth;
bee8d684
TS		 1051 depth=qemu_get_be32(f);
1052 s->enable=qemu_get_be32(f);
1053 s->config=qemu_get_be32(f);
1054 s->cursor.id=qemu_get_be32(f);
1055 s->cursor.x=qemu_get_be32(f);
1056 s->cursor.y=qemu_get_be32(f);
1057 s->cursor.on=qemu_get_be32(f);
1058 s->index=qemu_get_be32(f);
d34cab9f 1059 qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
bee8d684
TS		 1060 s->new_width=qemu_get_be32(f);
1061 s->new_height=qemu_get_be32(f);
d34cab9f
TS		 1062 qemu_get_be32s(f, &s->guest);
1063 qemu_get_be32s(f, &s->svgaid);
bee8d684
TS		 1064 s->syncing=qemu_get_be32(f);
1065 s->fb_size=qemu_get_be32(f);
d34cab9f
TS		 1066
1067 if (s->enable && depth != s->depth) {
1068 printf("%s: need colour depth of %i bits to resume operation.\n",
1069 __FUNCTION__, depth);
1070 return -EINVAL;
1071 }
1072
1073 s->invalidated = 1;
1074 if (s->config)
1075 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1076
1077 return 0;
1078}
1079
1080static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1081 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1082 int vga_ram_size)
1083{
1084 int iomemtype;
1085 s->ds = ds;
1086 s->vram = vga_ram_base;
1087 s->vram_size = vga_ram_size;
1088
1089 s->scratch_size = SVGA_SCRATCH_SIZE;
1090 s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1091
1092 vmsvga_reset(s);
1093
1094#ifdef DIRECT_VRAM
1095 iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1096 vmsvga_vram_write, s);
1097#else
1098 iomemtype = vga_ram_offset | IO_MEM_RAM;
1099#endif
1100 cpu_register_physical_memory(SVGA_MEM_BASE, vga_ram_size,
1101 iomemtype);
1102
d34cab9f
TS		 1103 graphic_console_init(ds, vmsvga_update_display,
1104 vmsvga_invalidate_display, vmsvga_screen_dump, s);
1105
1106#ifdef EMBED_STDVGA
1107 vga_common_init((VGAState *) s, ds,
1108 vga_ram_base, vga_ram_offset, vga_ram_size);
1109 vga_init((VGAState *) s);
1110#endif
1111}
1112
1113static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1114{
1115 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1116 pci_device_save(&s->card, f);
1117 vmsvga_save(&s->chip, f);
1118}
1119
1120static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1121{
1122 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1123 int ret;
1124
1125 ret = pci_device_load(&s->card, f);
1126 if (ret < 0)
1127 return ret;
1128
1129 ret = vmsvga_load(&s->chip, f);
1130 if (ret < 0)
1131 return ret;
1132
1133 return 0;
1134}
1135
1492a3c4
AZ		 1136static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1137 uint32_t addr, uint32_t size, int type)
1138{
1139 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1140 struct vmsvga_state_s *s = &d->chip;
1141
1142 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1143 1, 4, vmsvga_index_read, s);
1144 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1145 1, 4, vmsvga_index_write, s);
1146 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1147 1, 4, vmsvga_value_read, s);
1148 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1149 1, 4, vmsvga_value_write, s);
1150 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1151 1, 4, vmsvga_bios_read, s);
1152 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1153 1, 4, vmsvga_bios_write, s);
1154}
1155
d34cab9f
TS		 1156#define PCI_VENDOR_ID_VMWARE 0x15ad
1157#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
1158#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
1159#define PCI_DEVICE_ID_VMWARE_NET 0x0720
1160#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
1161#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
1162#define PCI_CLASS_BASE_DISPLAY 0x03
1163#define PCI_CLASS_SUB_VGA 0x00
1164#define PCI_CLASS_HEADERTYPE_00h 0x00
1165
1166void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1167 unsigned long vga_ram_offset, int vga_ram_size)
1168{
1169 struct pci_vmsvga_state_s *s;
1170
1171 /* Setup PCI configuration */
1172 s = (struct pci_vmsvga_state_s *)
1173 pci_register_device(bus, "QEMUware SVGA",
1174 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1175 s->card.config[PCI_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
1176 s->card.config[PCI_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8;
1177 s->card.config[PCI_DEVICE_ID] = SVGA_PCI_DEVICE_ID & 0xff;
1178 s->card.config[PCI_DEVICE_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
1179 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
1180 s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA;
1181 s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY;
1182 s->card.config[0x0c] = 0x08; /* Cache line size */
1183 s->card.config[0x0d] = 0x40; /* Latency timer */
1184 s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
1185 s->card.config[0x10] = ((SVGA_IO_BASE >> 0) & 0xff) | 1;
1186 s->card.config[0x11] = (SVGA_IO_BASE >> 8) & 0xff;
1187 s->card.config[0x12] = (SVGA_IO_BASE >> 16) & 0xff;
1188 s->card.config[0x13] = (SVGA_IO_BASE >> 24) & 0xff;
1189 s->card.config[0x18] = (SVGA_MEM_BASE >> 0) & 0xff;
1190 s->card.config[0x19] = (SVGA_MEM_BASE >> 8) & 0xff;
1191 s->card.config[0x1a] = (SVGA_MEM_BASE >> 16) & 0xff;
1192 s->card.config[0x1b] = (SVGA_MEM_BASE >> 24) & 0xff;
1193 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1194 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1195 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1196 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1197 s->card.config[0x3c] = 0xff; /* End */
1198
1492a3c4
AZ		 1199 pci_register_io_region(&s->card, 0, 0x10,
1200 PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1201
d34cab9f
TS		 1202 vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1203
1204 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1205}
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