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[qemu.git] / hw / audio / intel-hda.c
CommitLineData
d61a4ce8
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
6086a565 20#include "qemu/osdep.h"
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
23#include "hw/pci/msi.h"
1de7afc9 24#include "qemu/timer.h"
0d09e41a 25#include "hw/audio/audio.h"
47b43a1f
PB		 26#include "intel-hda.h"
27#include "intel-hda-defs.h"
9c17d615 28#include "sysemu/dma.h"
bda8d9b8 29#include "qapi/error.h"
d61a4ce8
GH		 30
31/* --------------------------------------------------------------------- */
32/* hda bus */
33
3cb75a7c
PB		 34static Property hda_props[] = {
35 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
36 DEFINE_PROP_END_OF_LIST()
37};
38
0d936928
AL		 39static const TypeInfo hda_codec_bus_info = {
40 .name = TYPE_HDA_BUS,
41 .parent = TYPE_BUS,
42 .instance_size = sizeof(HDACodecBus),
d61a4ce8
GH		 43};
44
ab809e84 45void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
d61a4ce8
GH		 46 hda_codec_response_func response,
47 hda_codec_xfer_func xfer)
48{
fb17dfe0 49 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
d61a4ce8
GH		 50 bus->response = response;
51 bus->xfer = xfer;
52}
53
bda8d9b8 54static void hda_codec_dev_realize(DeviceState *qdev, Error **errp)
d61a4ce8 55{
e19202af
XZ		 56 HDACodecBus *bus = HDA_BUS(qdev->parent_bus);
57 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
dbaa7904 58 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
d61a4ce8 59
d61a4ce8
GH		 60 if (dev->cad == -1) {
61 dev->cad = bus->next_cad;
62 }
df0db221 63 if (dev->cad >= 15) {
bda8d9b8
XZ		 64 error_setg(errp, "HDA audio codec address is full");
65 return;
df0db221 66 }
d61a4ce8 67 bus->next_cad = dev->cad + 1;
bda8d9b8
XZ		 68 if (cdc->init(dev) != 0) {
69 error_setg(errp, "HDA audio init failed");
70 }
d61a4ce8
GH		 71}
72
8ac55351 73static void hda_codec_dev_unrealize(DeviceState *qdev, Error **errp)
dc4b9240 74{
e19202af 75 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
dbaa7904 76 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
dc4b9240 77
dbaa7904
AL		 78 if (cdc->exit) {
79 cdc->exit(dev);
dc4b9240 80 }
dc4b9240
GH		 81}
82
d61a4ce8
GH		 83HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
84{
0866aca1 85 BusChild *kid;
d61a4ce8
GH		 86 HDACodecDevice *cdev;
87
0866aca1
AL		 88 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
89 DeviceState *qdev = kid->child;
e19202af 90 cdev = HDA_CODEC_DEVICE(qdev);
d61a4ce8
GH		 91 if (cdev->cad == cad) {
92 return cdev;
93 }
94 }
95 return NULL;
96}
97
98void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
99{
e19202af 100 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
d61a4ce8
GH		 101 bus->response(dev, solicited, response);
102}
103
104bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
105 uint8_t *buf, uint32_t len)
106{
e19202af 107 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
d61a4ce8
GH		 108 return bus->xfer(dev, stnr, output, buf, len);
109}
110
111/* --------------------------------------------------------------------- */
112/* intel hda emulation */
113
114typedef struct IntelHDAStream IntelHDAStream;
115typedef struct IntelHDAState IntelHDAState;
116typedef struct IntelHDAReg IntelHDAReg;
117
118typedef struct bpl {
119 uint64_t addr;
120 uint32_t len;
121 uint32_t flags;
122} bpl;
123
124struct IntelHDAStream {
125 /* registers */
126 uint32_t ctl;
127 uint32_t lpib;
128 uint32_t cbl;
129 uint32_t lvi;
130 uint32_t fmt;
131 uint32_t bdlp_lbase;
132 uint32_t bdlp_ubase;
133
134 /* state */
135 bpl *bpl;
136 uint32_t bentries;
137 uint32_t bsize, be, bp;
138};
139
140struct IntelHDAState {
141 PCIDevice pci;
142 const char *name;
143 HDACodecBus codecs;
144
145 /* registers */
146 uint32_t g_ctl;
147 uint32_t wake_en;
148 uint32_t state_sts;
149 uint32_t int_ctl;
150 uint32_t int_sts;
151 uint32_t wall_clk;
152
153 uint32_t corb_lbase;
154 uint32_t corb_ubase;
155 uint32_t corb_rp;
156 uint32_t corb_wp;
157 uint32_t corb_ctl;
158 uint32_t corb_sts;
159 uint32_t corb_size;
160
161 uint32_t rirb_lbase;
162 uint32_t rirb_ubase;
163 uint32_t rirb_wp;
164 uint32_t rirb_cnt;
165 uint32_t rirb_ctl;
166 uint32_t rirb_sts;
167 uint32_t rirb_size;
168
169 uint32_t dp_lbase;
170 uint32_t dp_ubase;
171
172 uint32_t icw;
173 uint32_t irr;
174 uint32_t ics;
175
176 /* streams */
177 IntelHDAStream st[8];
178
179 /* state */
234bbdf1 180 MemoryRegion mmio;
d61a4ce8
GH		 181 uint32_t rirb_count;
182 int64_t wall_base_ns;
183
184 /* debug logging */
185 const IntelHDAReg *last_reg;
186 uint32_t last_val;
187 uint32_t last_write;
188 uint32_t last_sec;
189 uint32_t repeat_count;
190
191 /* properties */
192 uint32_t debug;
c0f2abff 193 OnOffAuto msi;
d209c744 194 bool old_msi_addr;
d61a4ce8
GH		 195};
196
062db740
PC		 197#define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
198
52bb7c6a
PC		 199#define INTEL_HDA(obj) \
200 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
201
d61a4ce8
GH		 202struct IntelHDAReg {
203 const char *name; /* register name */
204 uint32_t size; /* size in bytes */
205 uint32_t reset; /* reset value */
206 uint32_t wmask; /* write mask */
207 uint32_t wclear; /* write 1 to clear bits */
208 uint32_t offset; /* location in IntelHDAState */
209 uint32_t shift; /* byte access entries for dwords */
210 uint32_t stream;
211 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
212 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
213};
214
215static void intel_hda_reset(DeviceState *dev);
216
217/* --------------------------------------------------------------------- */
218
a8170e5e 219static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
d61a4ce8 220{
9be38598 221 return ((uint64_t)ubase << 32) | lbase;
d61a4ce8
GH		 222}
223
d61a4ce8
GH		 224static void intel_hda_update_int_sts(IntelHDAState *d)
225{
226 uint32_t sts = 0;
227 uint32_t i;
228
229 /* update controller status */
230 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
231 sts |= (1 << 30);
232 }
233 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
234 sts |= (1 << 30);
235 }
af93485c 236 if (d->state_sts & d->wake_en) {
d61a4ce8
GH		 237 sts |= (1 << 30);
238 }
239
240 /* update stream status */
241 for (i = 0; i < 8; i++) {
242 /* buffer completion interrupt */
243 if (d->st[i].ctl & (1 << 26)) {
244 sts |= (1 << i);
245 }
246 }
247
248 /* update global status */
249 if (sts & d->int_ctl) {
b1fe60cd 250 sts |= (1U << 31);
d61a4ce8
GH		 251 }
252
253 d->int_sts = sts;
254}
255
256static void intel_hda_update_irq(IntelHDAState *d)
257{
c0f2abff 258 bool msi = msi_enabled(&d->pci);
d61a4ce8
GH		 259 int level;
260
261 intel_hda_update_int_sts(d);
b1fe60cd 262 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
d61a4ce8
GH		 263 level = 1;
264 } else {
265 level = 0;
266 }
17786d52
GH		 267 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
268 level, msi ? "msi" : "intx");
269 if (msi) {
270 if (level) {
271 msi_notify(&d->pci, 0);
272 }
273 } else {
9e64f8a3 274 pci_set_irq(&d->pci, level);
17786d52 275 }
d61a4ce8
GH		 276}
277
278static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
279{
280 uint32_t cad, nid, data;
281 HDACodecDevice *codec;
dbaa7904 282 HDACodecDeviceClass *cdc;
d61a4ce8
GH		 283
284 cad = (verb >> 28) & 0x0f;
285 if (verb & (1 << 27)) {
286 /* indirect node addressing, not specified in HDA 1.0 */
287 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
288 return -1;
289 }
290 nid = (verb >> 20) & 0x7f;
291 data = verb & 0xfffff;
292
293 codec = hda_codec_find(&d->codecs, cad);
294 if (codec == NULL) {
295 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
296 return -1;
297 }
dbaa7904
AL		 298 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
299 cdc->command(codec, nid, data);
d61a4ce8
GH		 300 return 0;
301}
302
303static void intel_hda_corb_run(IntelHDAState *d)
304{
a8170e5e 305 hwaddr addr;
d61a4ce8
GH		 306 uint32_t rp, verb;
307
308 if (d->ics & ICH6_IRS_BUSY) {
309 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
310 intel_hda_send_command(d, d->icw);
311 return;
312 }
313
314 for (;;) {
315 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
316 dprint(d, 2, "%s: !run\n", __FUNCTION__);
317 return;
318 }
319 if ((d->corb_rp & 0xff) == d->corb_wp) {
320 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
321 return;
322 }
323 if (d->rirb_count == d->rirb_cnt) {
324 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
325 return;
326 }
327
328 rp = (d->corb_rp + 1) & 0xff;
329 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
fa0ce55c 330 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
d61a4ce8
GH		 331 d->corb_rp = rp;
332
333 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
334 intel_hda_send_command(d, verb);
335 }
336}
337
338static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
339{
e19202af 340 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
d61a4ce8 341 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
a8170e5e 342 hwaddr addr;
d61a4ce8
GH		 343 uint32_t wp, ex;
344
345 if (d->ics & ICH6_IRS_BUSY) {
346 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
347 __FUNCTION__, response, dev->cad);
348 d->irr = response;
349 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
350 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
351 return;
352 }
353
354 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
355 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
356 return;
357 }
358
359 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
360 wp = (d->rirb_wp + 1) & 0xff;
361 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
fa0ce55c
DG		 362 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
363 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
d61a4ce8
GH		 364 d->rirb_wp = wp;
365
366 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
367 __FUNCTION__, wp, response, ex);
368
369 d->rirb_count++;
370 if (d->rirb_count == d->rirb_cnt) {
371 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
372 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
373 d->rirb_sts |= ICH6_RBSTS_IRQ;
374 intel_hda_update_irq(d);
375 }
376 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
377 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
378 d->rirb_count, d->rirb_cnt);
379 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
380 d->rirb_sts |= ICH6_RBSTS_IRQ;
381 intel_hda_update_irq(d);
382 }
383 }
384}
385
386static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
387 uint8_t *buf, uint32_t len)
388{
e19202af 389 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
d61a4ce8 390 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
a8170e5e 391 hwaddr addr;
d61a4ce8 392 uint32_t s, copy, left;
36ac4ad3 393 IntelHDAStream *st;
d61a4ce8
GH		 394 bool irq = false;
395
36ac4ad3
MAL		 396 st = output ? d->st + 4 : d->st;
397 for (s = 0; s < 4; s++) {
398 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
399 st = st + s;
d61a4ce8
GH		 400 break;
401 }
402 }
18ebcc86 403 if (s == 4) {
d61a4ce8
GH		 404 return false;
405 }
406 if (st->bpl == NULL) {
407 return false;
408 }
409 if (st->ctl & (1 << 26)) {
410 /*
411 * Wait with the next DMA xfer until the guest
412 * has acked the buffer completion interrupt
413 */
414 return false;
415 }
416
417 left = len;
0c0fc2b5
PP		 418 s = st->bentries;
419 while (left > 0 && s-- > 0) {
d61a4ce8
GH		 420 copy = left;
421 if (copy > st->bsize - st->lpib)
422 copy = st->bsize - st->lpib;
423 if (copy > st->bpl[st->be].len - st->bp)
424 copy = st->bpl[st->be].len - st->bp;
425
426 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
427 st->be, st->bp, st->bpl[st->be].len, copy);
428
fa0ce55c 429 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
d61a4ce8
GH		 430 st->lpib += copy;
431 st->bp += copy;
432 buf += copy;
433 left -= copy;
434
435 if (st->bpl[st->be].len == st->bp) {
436 /* bpl entry filled */
437 if (st->bpl[st->be].flags & 0x01) {
438 irq = true;
439 }
440 st->bp = 0;
441 st->be++;
442 if (st->be == st->bentries) {
443 /* bpl wrap around */
444 st->be = 0;
445 st->lpib = 0;
446 }
447 }
448 }
449 if (d->dp_lbase & 0x01) {
d58ce68a 450 s = st - d->st;
d61a4ce8 451 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
fa0ce55c 452 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
d61a4ce8
GH		 453 }
454 dprint(d, 3, "dma: --\n");
455
456 if (irq) {
457 st->ctl |= (1 << 26); /* buffer completion interrupt */
458 intel_hda_update_irq(d);
459 }
460 return true;
461}
462
463static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
464{
a8170e5e 465 hwaddr addr;
d61a4ce8
GH		 466 uint8_t buf[16];
467 uint32_t i;
468
469 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
470 st->bentries = st->lvi +1;
7267c094
AL		 471 g_free(st->bpl);
472 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
d61a4ce8 473 for (i = 0; i < st->bentries; i++, addr += 16) {
fa0ce55c 474 pci_dma_read(&d->pci, addr, buf, 16);
d61a4ce8
GH		 475 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
476 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
477 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
478 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
479 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
480 }
481
482 st->bsize = st->cbl;
483 st->lpib = 0;
484 st->be = 0;
485 st->bp = 0;
486}
487
ba43d289 488static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
d61a4ce8 489{
0866aca1 490 BusChild *kid;
d61a4ce8
GH		 491 HDACodecDevice *cdev;
492
0866aca1
AL		 493 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
494 DeviceState *qdev = kid->child;
dbaa7904
AL		 495 HDACodecDeviceClass *cdc;
496
e19202af 497 cdev = HDA_CODEC_DEVICE(qdev);
dbaa7904
AL		 498 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
499 if (cdc->stream) {
500 cdc->stream(cdev, stream, running, output);
d61a4ce8
GH		 501 }
502 }
503}
504
505/* --------------------------------------------------------------------- */
506
507static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
508{
509 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
52bb7c6a 510 intel_hda_reset(DEVICE(d));
d61a4ce8
GH		 511 }
512}
513
6a0d02f5
GH		 514static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
515{
516 intel_hda_update_irq(d);
517}
518
d61a4ce8
GH		 519static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
520{
521 intel_hda_update_irq(d);
522}
523
524static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
525{
526 intel_hda_update_irq(d);
527}
528
529static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
530{
531 int64_t ns;
532
bc72ad67 533 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
d61a4ce8
GH		 534 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
535}
536
537static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
538{
539 intel_hda_corb_run(d);
540}
541
542static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
543{
544 intel_hda_corb_run(d);
545}
546
547static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
548{
549 if (d->rirb_wp & ICH6_RIRBWP_RST) {
550 d->rirb_wp = 0;
551 }
552}
553
554static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
555{
556 intel_hda_update_irq(d);
557
558 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
559 /* cleared ICH6_RBSTS_IRQ */
560 d->rirb_count = 0;
561 intel_hda_corb_run(d);
562 }
563}
564
565static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
566{
567 if (d->ics & ICH6_IRS_BUSY) {
568 intel_hda_corb_run(d);
569 }
570}
571
572static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
573{
ba43d289 574 bool output = reg->stream >= 4;
d61a4ce8
GH		 575 IntelHDAStream *st = d->st + reg->stream;
576
577 if (st->ctl & 0x01) {
578 /* reset */
579 dprint(d, 1, "st #%d: reset\n", reg->stream);
a2554a33 580 st->ctl = SD_STS_FIFO_READY << 24;
d61a4ce8
GH		 581 }
582 if ((st->ctl & 0x02) != (old & 0x02)) {
583 uint32_t stnr = (st->ctl >> 20) & 0x0f;
584 /* run bit flipped */
585 if (st->ctl & 0x02) {
586 /* start */
587 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
588 reg->stream, stnr, st->cbl);
589 intel_hda_parse_bdl(d, st);
ba43d289 590 intel_hda_notify_codecs(d, stnr, true, output);
d61a4ce8
GH		 591 } else {
592 /* stop */
593 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
ba43d289 594 intel_hda_notify_codecs(d, stnr, false, output);
d61a4ce8
GH		 595 }
596 }
597 intel_hda_update_irq(d);
598}
599
600/* --------------------------------------------------------------------- */
601
602#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
603
604static const struct IntelHDAReg regtab[] = {
605 /* global */
606 [ ICH6_REG_GCAP ] = {
607 .name = "GCAP",
608 .size = 2,
609 .reset = 0x4401,
610 },
611 [ ICH6_REG_VMIN ] = {
612 .name = "VMIN",
613 .size = 1,
614 },
615 [ ICH6_REG_VMAJ ] = {
616 .name = "VMAJ",
617 .size = 1,
618 .reset = 1,
619 },
620 [ ICH6_REG_OUTPAY ] = {
621 .name = "OUTPAY",
622 .size = 2,
623 .reset = 0x3c,
624 },
625 [ ICH6_REG_INPAY ] = {
626 .name = "INPAY",
627 .size = 2,
628 .reset = 0x1d,
629 },
630 [ ICH6_REG_GCTL ] = {
631 .name = "GCTL",
632 .size = 4,
633 .wmask = 0x0103,
634 .offset = offsetof(IntelHDAState, g_ctl),
635 .whandler = intel_hda_set_g_ctl,
636 },
637 [ ICH6_REG_WAKEEN ] = {
638 .name = "WAKEEN",
639 .size = 2,
df0db221 640 .wmask = 0x7fff,
d61a4ce8 641 .offset = offsetof(IntelHDAState, wake_en),
6a0d02f5 642 .whandler = intel_hda_set_wake_en,
d61a4ce8
GH		 643 },
644 [ ICH6_REG_STATESTS ] = {
645 .name = "STATESTS",
646 .size = 2,
df0db221
GH		 647 .wmask = 0x7fff,
648 .wclear = 0x7fff,
d61a4ce8
GH		 649 .offset = offsetof(IntelHDAState, state_sts),
650 .whandler = intel_hda_set_state_sts,
651 },
652
653 /* interrupts */
654 [ ICH6_REG_INTCTL ] = {
655 .name = "INTCTL",
656 .size = 4,
657 .wmask = 0xc00000ff,
658 .offset = offsetof(IntelHDAState, int_ctl),
659 .whandler = intel_hda_set_int_ctl,
660 },
661 [ ICH6_REG_INTSTS ] = {
662 .name = "INTSTS",
663 .size = 4,
664 .wmask = 0xc00000ff,
665 .wclear = 0xc00000ff,
666 .offset = offsetof(IntelHDAState, int_sts),
667 },
668
669 /* misc */
670 [ ICH6_REG_WALLCLK ] = {
671 .name = "WALLCLK",
672 .size = 4,
673 .offset = offsetof(IntelHDAState, wall_clk),
674 .rhandler = intel_hda_get_wall_clk,
675 },
676 [ ICH6_REG_WALLCLK + 0x2000 ] = {
677 .name = "WALLCLK(alias)",
678 .size = 4,
679 .offset = offsetof(IntelHDAState, wall_clk),
680 .rhandler = intel_hda_get_wall_clk,
681 },
682
683 /* dma engine */
684 [ ICH6_REG_CORBLBASE ] = {
685 .name = "CORBLBASE",
686 .size = 4,
687 .wmask = 0xffffff80,
688 .offset = offsetof(IntelHDAState, corb_lbase),
689 },
690 [ ICH6_REG_CORBUBASE ] = {
691 .name = "CORBUBASE",
692 .size = 4,
693 .wmask = 0xffffffff,
694 .offset = offsetof(IntelHDAState, corb_ubase),
695 },
696 [ ICH6_REG_CORBWP ] = {
697 .name = "CORBWP",
698 .size = 2,
699 .wmask = 0xff,
700 .offset = offsetof(IntelHDAState, corb_wp),
701 .whandler = intel_hda_set_corb_wp,
702 },
703 [ ICH6_REG_CORBRP ] = {
704 .name = "CORBRP",
705 .size = 2,
706 .wmask = 0x80ff,
707 .offset = offsetof(IntelHDAState, corb_rp),
708 },
709 [ ICH6_REG_CORBCTL ] = {
710 .name = "CORBCTL",
711 .size = 1,
712 .wmask = 0x03,
713 .offset = offsetof(IntelHDAState, corb_ctl),
714 .whandler = intel_hda_set_corb_ctl,
715 },
716 [ ICH6_REG_CORBSTS ] = {
717 .name = "CORBSTS",
718 .size = 1,
719 .wmask = 0x01,
720 .wclear = 0x01,
721 .offset = offsetof(IntelHDAState, corb_sts),
722 },
723 [ ICH6_REG_CORBSIZE ] = {
724 .name = "CORBSIZE",
725 .size = 1,
726 .reset = 0x42,
727 .offset = offsetof(IntelHDAState, corb_size),
728 },
729 [ ICH6_REG_RIRBLBASE ] = {
730 .name = "RIRBLBASE",
731 .size = 4,
732 .wmask = 0xffffff80,
733 .offset = offsetof(IntelHDAState, rirb_lbase),
734 },
735 [ ICH6_REG_RIRBUBASE ] = {
736 .name = "RIRBUBASE",
737 .size = 4,
738 .wmask = 0xffffffff,
739 .offset = offsetof(IntelHDAState, rirb_ubase),
740 },
741 [ ICH6_REG_RIRBWP ] = {
742 .name = "RIRBWP",
743 .size = 2,
744 .wmask = 0x8000,
745 .offset = offsetof(IntelHDAState, rirb_wp),
746 .whandler = intel_hda_set_rirb_wp,
747 },
748 [ ICH6_REG_RINTCNT ] = {
749 .name = "RINTCNT",
750 .size = 2,
751 .wmask = 0xff,
752 .offset = offsetof(IntelHDAState, rirb_cnt),
753 },
754 [ ICH6_REG_RIRBCTL ] = {
755 .name = "RIRBCTL",
756 .size = 1,
757 .wmask = 0x07,
758 .offset = offsetof(IntelHDAState, rirb_ctl),
759 },
760 [ ICH6_REG_RIRBSTS ] = {
761 .name = "RIRBSTS",
762 .size = 1,
763 .wmask = 0x05,
764 .wclear = 0x05,
765 .offset = offsetof(IntelHDAState, rirb_sts),
766 .whandler = intel_hda_set_rirb_sts,
767 },
768 [ ICH6_REG_RIRBSIZE ] = {
769 .name = "RIRBSIZE",
770 .size = 1,
771 .reset = 0x42,
772 .offset = offsetof(IntelHDAState, rirb_size),
773 },
774
775 [ ICH6_REG_DPLBASE ] = {
776 .name = "DPLBASE",
777 .size = 4,
778 .wmask = 0xffffff81,
779 .offset = offsetof(IntelHDAState, dp_lbase),
780 },
781 [ ICH6_REG_DPUBASE ] = {
782 .name = "DPUBASE",
783 .size = 4,
784 .wmask = 0xffffffff,
785 .offset = offsetof(IntelHDAState, dp_ubase),
786 },
787
788 [ ICH6_REG_IC ] = {
789 .name = "ICW",
790 .size = 4,
791 .wmask = 0xffffffff,
792 .offset = offsetof(IntelHDAState, icw),
793 },
794 [ ICH6_REG_IR ] = {
795 .name = "IRR",
796 .size = 4,
797 .offset = offsetof(IntelHDAState, irr),
798 },
799 [ ICH6_REG_IRS ] = {
800 .name = "ICS",
801 .size = 2,
802 .wmask = 0x0003,
803 .wclear = 0x0002,
804 .offset = offsetof(IntelHDAState, ics),
805 .whandler = intel_hda_set_ics,
806 },
807
808#define HDA_STREAM(_t, _i) \
809 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
810 .stream = _i, \
811 .name = _t stringify(_i) " CTL", \
812 .size = 4, \
813 .wmask = 0x1cff001f, \
814 .offset = offsetof(IntelHDAState, st[_i].ctl), \
815 .whandler = intel_hda_set_st_ctl, \
816 }, \
817 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
818 .stream = _i, \
819 .name = _t stringify(_i) " CTL(stnr)", \
820 .size = 1, \
821 .shift = 16, \
822 .wmask = 0x00ff0000, \
823 .offset = offsetof(IntelHDAState, st[_i].ctl), \
824 .whandler = intel_hda_set_st_ctl, \
825 }, \
826 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
827 .stream = _i, \
828 .name = _t stringify(_i) " CTL(sts)", \
829 .size = 1, \
830 .shift = 24, \
831 .wmask = 0x1c000000, \
832 .wclear = 0x1c000000, \
833 .offset = offsetof(IntelHDAState, st[_i].ctl), \
834 .whandler = intel_hda_set_st_ctl, \
a2554a33 835 .reset = SD_STS_FIFO_READY << 24 \
d61a4ce8
GH		 836 }, \
837 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
838 .stream = _i, \
839 .name = _t stringify(_i) " LPIB", \
840 .size = 4, \
841 .offset = offsetof(IntelHDAState, st[_i].lpib), \
842 }, \
843 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
844 .stream = _i, \
845 .name = _t stringify(_i) " LPIB(alias)", \
846 .size = 4, \
847 .offset = offsetof(IntelHDAState, st[_i].lpib), \
848 }, \
849 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
850 .stream = _i, \
851 .name = _t stringify(_i) " CBL", \
852 .size = 4, \
853 .wmask = 0xffffffff, \
854 .offset = offsetof(IntelHDAState, st[_i].cbl), \
855 }, \
856 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
857 .stream = _i, \
858 .name = _t stringify(_i) " LVI", \
859 .size = 2, \
860 .wmask = 0x00ff, \
861 .offset = offsetof(IntelHDAState, st[_i].lvi), \
862 }, \
863 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
864 .stream = _i, \
865 .name = _t stringify(_i) " FIFOS", \
866 .size = 2, \
867 .reset = HDA_BUFFER_SIZE, \
868 }, \
869 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
870 .stream = _i, \
871 .name = _t stringify(_i) " FMT", \
872 .size = 2, \
873 .wmask = 0x7f7f, \
874 .offset = offsetof(IntelHDAState, st[_i].fmt), \
875 }, \
876 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
877 .stream = _i, \
878 .name = _t stringify(_i) " BDLPL", \
879 .size = 4, \
880 .wmask = 0xffffff80, \
881 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
882 }, \
883 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
884 .stream = _i, \
885 .name = _t stringify(_i) " BDLPU", \
886 .size = 4, \
887 .wmask = 0xffffffff, \
888 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
889 }, \
890
891 HDA_STREAM("IN", 0)
892 HDA_STREAM("IN", 1)
893 HDA_STREAM("IN", 2)
894 HDA_STREAM("IN", 3)
895
896 HDA_STREAM("OUT", 4)
897 HDA_STREAM("OUT", 5)
898 HDA_STREAM("OUT", 6)
899 HDA_STREAM("OUT", 7)
900
901};
902
a8170e5e 903static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
d61a4ce8
GH		 904{
905 const IntelHDAReg *reg;
906
dff7424d 907 if (addr >= ARRAY_SIZE(regtab)) {
d61a4ce8
GH		 908 goto noreg;
909 }
910 reg = regtab+addr;
911 if (reg->name == NULL) {
912 goto noreg;
913 }
914 return reg;
915
916noreg:
917 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
918 return NULL;
919}
920
921static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
922{
923 uint8_t *addr = (void*)d;
924
925 addr += reg->offset;
926 return (uint32_t*)addr;
927}
928
929static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
930 uint32_t wmask)
931{
932 uint32_t *addr;
933 uint32_t old;
934
935 if (!reg) {
936 return;
937 }
938
939 if (d->debug) {
940 time_t now = time(NULL);
941 if (d->last_write && d->last_reg == reg && d->last_val == val) {
942 d->repeat_count++;
943 if (d->last_sec != now) {
944 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
945 d->last_sec = now;
946 d->repeat_count = 0;
947 }
948 } else {
949 if (d->repeat_count) {
950 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
951 }
952 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
953 d->last_write = 1;
954 d->last_reg = reg;
955 d->last_val = val;
956 d->last_sec = now;
957 d->repeat_count = 0;
958 }
959 }
960 assert(reg->offset != 0);
961
962 addr = intel_hda_reg_addr(d, reg);
963 old = *addr;
964
965 if (reg->shift) {
966 val <<= reg->shift;
967 wmask <<= reg->shift;
968 }
969 wmask &= reg->wmask;
970 *addr &= ~wmask;
971 *addr |= wmask & val;
972 *addr &= ~(val & reg->wclear);
973
974 if (reg->whandler) {
975 reg->whandler(d, reg, old);
976 }
977}
978
979static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
980 uint32_t rmask)
981{
982 uint32_t *addr, ret;
983
984 if (!reg) {
985 return 0;
986 }
987
988 if (reg->rhandler) {
989 reg->rhandler(d, reg);
990 }
991
992 if (reg->offset == 0) {
993 /* constant read-only register */
994 ret = reg->reset;
995 } else {
996 addr = intel_hda_reg_addr(d, reg);
997 ret = *addr;
998 if (reg->shift) {
999 ret >>= reg->shift;
1000 }
1001 ret &= rmask;
1002 }
1003 if (d->debug) {
1004 time_t now = time(NULL);
1005 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1006 d->repeat_count++;
1007 if (d->last_sec != now) {
1008 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1009 d->last_sec = now;
1010 d->repeat_count = 0;
1011 }
1012 } else {
1013 if (d->repeat_count) {
1014 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1015 }
1016 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1017 d->last_write = 0;
1018 d->last_reg = reg;
1019 d->last_val = ret;
1020 d->last_sec = now;
1021 d->repeat_count = 0;
1022 }
1023 }
1024 return ret;
1025}
1026
1027static void intel_hda_regs_reset(IntelHDAState *d)
1028{
1029 uint32_t *addr;
1030 int i;
1031
dff7424d 1032 for (i = 0; i < ARRAY_SIZE(regtab); i++) {
d61a4ce8
GH		 1033 if (regtab[i].name == NULL) {
1034 continue;
1035 }
1036 if (regtab[i].offset == 0) {
1037 continue;
1038 }
1039 addr = intel_hda_reg_addr(d, regtab + i);
1040 *addr = regtab[i].reset;
1041 }
1042}
1043
1044/* --------------------------------------------------------------------- */
1045
a8170e5e 1046static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1047{
1048 IntelHDAState *d = opaque;
1049 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1050
1051 intel_hda_reg_write(d, reg, val, 0xff);
1052}
1053
a8170e5e 1054static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1055{
1056 IntelHDAState *d = opaque;
1057 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1058
1059 intel_hda_reg_write(d, reg, val, 0xffff);
1060}
1061
a8170e5e 1062static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1063{
1064 IntelHDAState *d = opaque;
1065 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1066
1067 intel_hda_reg_write(d, reg, val, 0xffffffff);
1068}
1069
a8170e5e 1070static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
d61a4ce8
GH		 1071{
1072 IntelHDAState *d = opaque;
1073 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1074
1075 return intel_hda_reg_read(d, reg, 0xff);
1076}
1077
a8170e5e 1078static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
d61a4ce8
GH		 1079{
1080 IntelHDAState *d = opaque;
1081 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1082
1083 return intel_hda_reg_read(d, reg, 0xffff);
1084}
1085
a8170e5e 1086static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
d61a4ce8
GH		 1087{
1088 IntelHDAState *d = opaque;
1089 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1090
1091 return intel_hda_reg_read(d, reg, 0xffffffff);
1092}
1093
234bbdf1
AK		 1094static const MemoryRegionOps intel_hda_mmio_ops = {
1095 .old_mmio = {
1096 .read = {
1097 intel_hda_mmio_readb,
1098 intel_hda_mmio_readw,
1099 intel_hda_mmio_readl,
1100 },
1101 .write = {
1102 intel_hda_mmio_writeb,
1103 intel_hda_mmio_writew,
1104 intel_hda_mmio_writel,
1105 },
1106 },
1107 .endianness = DEVICE_NATIVE_ENDIAN,
d61a4ce8
GH		 1108};
1109
d61a4ce8
GH		 1110/* --------------------------------------------------------------------- */
1111
1112static void intel_hda_reset(DeviceState *dev)
1113{
0866aca1 1114 BusChild *kid;
52bb7c6a 1115 IntelHDAState *d = INTEL_HDA(dev);
d61a4ce8
GH		 1116 HDACodecDevice *cdev;
1117
1118 intel_hda_regs_reset(d);
bc72ad67 1119 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
d61a4ce8
GH		 1120
1121 /* reset codecs */
0866aca1
AL		 1122 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1123 DeviceState *qdev = kid->child;
e19202af 1124 cdev = HDA_CODEC_DEVICE(qdev);
94afdadc 1125 device_reset(DEVICE(cdev));
d61a4ce8
GH		 1126 d->state_sts |= (1 << cdev->cad);
1127 }
1128 intel_hda_update_irq(d);
1129}
1130
9af21dbe 1131static void intel_hda_realize(PCIDevice *pci, Error **errp)
d61a4ce8 1132{
52bb7c6a 1133 IntelHDAState *d = INTEL_HDA(pci);
d61a4ce8 1134 uint8_t *conf = d->pci.config;
1108b2f8
C		 1135 Error *err = NULL;
1136 int ret;
d61a4ce8 1137
f79f2bfc 1138 d->name = object_get_typename(OBJECT(d));
d61a4ce8 1139
d61a4ce8
GH		 1140 pci_config_set_interrupt_pin(conf, 1);
1141
1142 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1143 conf[0x40] = 0x01;
1144
1108b2f8
C		 1145 if (d->msi != ON_OFF_AUTO_OFF) {
1146 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60,
1147 1, true, false, &err);
1148 /* Any error other than -ENOTSUP(board's MSI support is broken)
1149 * is a programming error */
1150 assert(!ret || ret == -ENOTSUP);
1151 if (ret && d->msi == ON_OFF_AUTO_ON) {
1152 /* Can't satisfy user's explicit msi=on request, fail */
1153 error_append_hint(&err, "You have to use msi=auto (default) or "
1154 "msi=off with this machine type.\n");
1155 error_propagate(errp, err);
1156 return;
1157 }
1158 assert(!err || d->msi == ON_OFF_AUTO_AUTO);
1159 /* With msi=auto, we fall back to MSI off silently */
1160 error_free(err);
1161 }
1162
64bde0f3 1163 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
234bbdf1 1164 "intel-hda", 0x4000);
e824b2cc 1165 pci_register_bar(&d->pci, 0, 0, &d->mmio);
d61a4ce8 1166
ab809e84 1167 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
d61a4ce8 1168 intel_hda_response, intel_hda_xfer);
d61a4ce8
GH		 1169}
1170
f90c2bcd 1171static void intel_hda_exit(PCIDevice *pci)
dc4b9240 1172{
52bb7c6a 1173 IntelHDAState *d = INTEL_HDA(pci);
dc4b9240 1174
45fe15c2 1175 msi_uninit(&d->pci);
dc4b9240
GH		 1176}
1177
d61a4ce8
GH		 1178static int intel_hda_post_load(void *opaque, int version)
1179{
1180 IntelHDAState* d = opaque;
1181 int i;
1182
1183 dprint(d, 1, "%s\n", __FUNCTION__);
1184 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1185 if (d->st[i].ctl & 0x02) {
1186 intel_hda_parse_bdl(d, &d->st[i]);
1187 }
1188 }
1189 intel_hda_update_irq(d);
1190 return 0;
1191}
1192
1193static const VMStateDescription vmstate_intel_hda_stream = {
1194 .name = "intel-hda-stream",
1195 .version_id = 1,
d49805ae 1196 .fields = (VMStateField[]) {
d61a4ce8
GH		 1197 VMSTATE_UINT32(ctl, IntelHDAStream),
1198 VMSTATE_UINT32(lpib, IntelHDAStream),
1199 VMSTATE_UINT32(cbl, IntelHDAStream),
1200 VMSTATE_UINT32(lvi, IntelHDAStream),
1201 VMSTATE_UINT32(fmt, IntelHDAStream),
1202 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1203 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1204 VMSTATE_END_OF_LIST()
1205 }
1206};
1207
1208static const VMStateDescription vmstate_intel_hda = {
1209 .name = "intel-hda",
1210 .version_id = 1,
1211 .post_load = intel_hda_post_load,
d49805ae 1212 .fields = (VMStateField[]) {
d61a4ce8
GH		 1213 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1214
1215 /* registers */
1216 VMSTATE_UINT32(g_ctl, IntelHDAState),
1217 VMSTATE_UINT32(wake_en, IntelHDAState),
1218 VMSTATE_UINT32(state_sts, IntelHDAState),
1219 VMSTATE_UINT32(int_ctl, IntelHDAState),
1220 VMSTATE_UINT32(int_sts, IntelHDAState),
1221 VMSTATE_UINT32(wall_clk, IntelHDAState),
1222 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1223 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1224 VMSTATE_UINT32(corb_rp, IntelHDAState),
1225 VMSTATE_UINT32(corb_wp, IntelHDAState),
1226 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1227 VMSTATE_UINT32(corb_sts, IntelHDAState),
1228 VMSTATE_UINT32(corb_size, IntelHDAState),
1229 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1230 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1231 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1232 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1233 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1234 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1235 VMSTATE_UINT32(rirb_size, IntelHDAState),
1236 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1237 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1238 VMSTATE_UINT32(icw, IntelHDAState),
1239 VMSTATE_UINT32(irr, IntelHDAState),
1240 VMSTATE_UINT32(ics, IntelHDAState),
1241 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1242 vmstate_intel_hda_stream,
1243 IntelHDAStream),
1244
1245 /* additional state info */
1246 VMSTATE_UINT32(rirb_count, IntelHDAState),
1247 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1248
1249 VMSTATE_END_OF_LIST()
1250 }
1251};
1252
40021f08
AL		 1253static Property intel_hda_properties[] = {
1254 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
c0f2abff 1255 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
d209c744 1256 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
40021f08
AL		 1257 DEFINE_PROP_END_OF_LIST(),
1258};
1259
062db740 1260static void intel_hda_class_init(ObjectClass *klass, void *data)
40021f08 1261{
39bffca2 1262 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1263 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1264
9af21dbe 1265 k->realize = intel_hda_realize;
40021f08 1266 k->exit = intel_hda_exit;
40021f08 1267 k->vendor_id = PCI_VENDOR_ID_INTEL;
40021f08 1268 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
39bffca2
AL		 1269 dc->reset = intel_hda_reset;
1270 dc->vmsd = &vmstate_intel_hda;
1271 dc->props = intel_hda_properties;
40021f08
AL		 1272}
1273
8b07eaa1
GH		 1274static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1275{
1276 DeviceClass *dc = DEVICE_CLASS(klass);
1277 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1278
8b07eaa1
GH		 1279 k->device_id = 0x2668;
1280 k->revision = 1;
125ee0ed 1281 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
8b07eaa1
GH		 1282 dc->desc = "Intel HD Audio Controller (ich6)";
1283}
1284
1285static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1286{
1287 DeviceClass *dc = DEVICE_CLASS(klass);
1288 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1289
8b07eaa1
GH		 1290 k->device_id = 0x293e;
1291 k->revision = 3;
125ee0ed 1292 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
8b07eaa1
GH		 1293 dc->desc = "Intel HD Audio Controller (ich9)";
1294}
1295
062db740
PC		 1296static const TypeInfo intel_hda_info = {
1297 .name = TYPE_INTEL_HDA_GENERIC,
39bffca2
AL		 1298 .parent = TYPE_PCI_DEVICE,
1299 .instance_size = sizeof(IntelHDAState),
062db740
PC		 1300 .class_init = intel_hda_class_init,
1301 .abstract = true,
1302};
1303
1304static const TypeInfo intel_hda_info_ich6 = {
1305 .name = "intel-hda",
1306 .parent = TYPE_INTEL_HDA_GENERIC,
8b07eaa1
GH		 1307 .class_init = intel_hda_class_init_ich6,
1308};
1309
e2848a78 1310static const TypeInfo intel_hda_info_ich9 = {
8b07eaa1 1311 .name = "ich9-intel-hda",
062db740 1312 .parent = TYPE_INTEL_HDA_GENERIC,
8b07eaa1 1313 .class_init = intel_hda_class_init_ich9,
40021f08
AL		 1314};
1315
39bffca2
AL		 1316static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1317{
1318 DeviceClass *k = DEVICE_CLASS(klass);
bda8d9b8 1319 k->realize = hda_codec_dev_realize;
8ac55351 1320 k->unrealize = hda_codec_dev_unrealize;
125ee0ed 1321 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
0d936928 1322 k->bus_type = TYPE_HDA_BUS;
bce54474 1323 k->props = hda_props;
39bffca2
AL		 1324}
1325
8c43a6f0 1326static const TypeInfo hda_codec_device_type_info = {
40021f08
AL		 1327 .name = TYPE_HDA_CODEC_DEVICE,
1328 .parent = TYPE_DEVICE,
1329 .instance_size = sizeof(HDACodecDevice),
1330 .abstract = true,
1331 .class_size = sizeof(HDACodecDeviceClass),
39bffca2 1332 .class_init = hda_codec_device_class_init,
d61a4ce8
GH		 1333};
1334
d61a4ce8
GH		 1335/*
1336 * create intel hda controller with codec attached to it,
1337 * so '-soundhw hda' works.
1338 */
36cd6f6f 1339static int intel_hda_and_codec_init(PCIBus *bus)
d61a4ce8 1340{
52bb7c6a 1341 DeviceState *controller;
d61a4ce8
GH		 1342 BusState *hdabus;
1343 DeviceState *codec;
1344
52bb7c6a
PC		 1345 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1346 hdabus = QLIST_FIRST(&controller->child_bus);
d61a4ce8
GH		 1347 codec = qdev_create(hdabus, "hda-duplex");
1348 qdev_init_nofail(codec);
1349 return 0;
1350}
1351
36cd6f6f
PB		 1352static void intel_hda_register_types(void)
1353{
1354 type_register_static(&hda_codec_bus_info);
062db740 1355 type_register_static(&intel_hda_info);
36cd6f6f
PB		 1356 type_register_static(&intel_hda_info_ich6);
1357 type_register_static(&intel_hda_info_ich9);
1358 type_register_static(&hda_codec_device_type_info);
1359 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1360}
1361
1362type_init(intel_hda_register_types)
Empty description
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