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error: Remove unnecessary local_err variables
[qemu.git] / hw / audio / intel-hda.c
CommitLineData
d61a4ce8
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
6086a565 20#include "qemu/osdep.h"
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
23#include "hw/pci/msi.h"
1de7afc9 24#include "qemu/timer.h"
0d09e41a 25#include "hw/audio/audio.h"
47b43a1f
PB		 26#include "intel-hda.h"
27#include "intel-hda-defs.h"
9c17d615 28#include "sysemu/dma.h"
bda8d9b8 29#include "qapi/error.h"
d61a4ce8
GH		 30
31/* --------------------------------------------------------------------- */
32/* hda bus */
33
3cb75a7c
PB		 34static Property hda_props[] = {
35 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
36 DEFINE_PROP_END_OF_LIST()
37};
38
0d936928
AL		 39static const TypeInfo hda_codec_bus_info = {
40 .name = TYPE_HDA_BUS,
41 .parent = TYPE_BUS,
42 .instance_size = sizeof(HDACodecBus),
d61a4ce8
GH		 43};
44
ab809e84 45void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
d61a4ce8
GH		 46 hda_codec_response_func response,
47 hda_codec_xfer_func xfer)
48{
fb17dfe0 49 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
d61a4ce8
GH		 50 bus->response = response;
51 bus->xfer = xfer;
52}
53
bda8d9b8 54static void hda_codec_dev_realize(DeviceState *qdev, Error **errp)
d61a4ce8 55{
e19202af
XZ		 56 HDACodecBus *bus = HDA_BUS(qdev->parent_bus);
57 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
dbaa7904 58 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
d61a4ce8 59
d61a4ce8
GH		 60 if (dev->cad == -1) {
61 dev->cad = bus->next_cad;
62 }
df0db221 63 if (dev->cad >= 15) {
bda8d9b8
XZ		 64 error_setg(errp, "HDA audio codec address is full");
65 return;
df0db221 66 }
d61a4ce8 67 bus->next_cad = dev->cad + 1;
bda8d9b8
XZ		 68 if (cdc->init(dev) != 0) {
69 error_setg(errp, "HDA audio init failed");
70 }
d61a4ce8
GH		 71}
72
dc4b9240
GH		 73static int hda_codec_dev_exit(DeviceState *qdev)
74{
e19202af 75 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
dbaa7904 76 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
dc4b9240 77
dbaa7904
AL		 78 if (cdc->exit) {
79 cdc->exit(dev);
dc4b9240
GH		 80 }
81 return 0;
82}
83
d61a4ce8
GH		 84HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
85{
0866aca1 86 BusChild *kid;
d61a4ce8
GH		 87 HDACodecDevice *cdev;
88
0866aca1
AL		 89 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
90 DeviceState *qdev = kid->child;
e19202af 91 cdev = HDA_CODEC_DEVICE(qdev);
d61a4ce8
GH		 92 if (cdev->cad == cad) {
93 return cdev;
94 }
95 }
96 return NULL;
97}
98
99void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
100{
e19202af 101 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
d61a4ce8
GH		 102 bus->response(dev, solicited, response);
103}
104
105bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
106 uint8_t *buf, uint32_t len)
107{
e19202af 108 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
d61a4ce8
GH		 109 return bus->xfer(dev, stnr, output, buf, len);
110}
111
112/* --------------------------------------------------------------------- */
113/* intel hda emulation */
114
115typedef struct IntelHDAStream IntelHDAStream;
116typedef struct IntelHDAState IntelHDAState;
117typedef struct IntelHDAReg IntelHDAReg;
118
119typedef struct bpl {
120 uint64_t addr;
121 uint32_t len;
122 uint32_t flags;
123} bpl;
124
125struct IntelHDAStream {
126 /* registers */
127 uint32_t ctl;
128 uint32_t lpib;
129 uint32_t cbl;
130 uint32_t lvi;
131 uint32_t fmt;
132 uint32_t bdlp_lbase;
133 uint32_t bdlp_ubase;
134
135 /* state */
136 bpl *bpl;
137 uint32_t bentries;
138 uint32_t bsize, be, bp;
139};
140
141struct IntelHDAState {
142 PCIDevice pci;
143 const char *name;
144 HDACodecBus codecs;
145
146 /* registers */
147 uint32_t g_ctl;
148 uint32_t wake_en;
149 uint32_t state_sts;
150 uint32_t int_ctl;
151 uint32_t int_sts;
152 uint32_t wall_clk;
153
154 uint32_t corb_lbase;
155 uint32_t corb_ubase;
156 uint32_t corb_rp;
157 uint32_t corb_wp;
158 uint32_t corb_ctl;
159 uint32_t corb_sts;
160 uint32_t corb_size;
161
162 uint32_t rirb_lbase;
163 uint32_t rirb_ubase;
164 uint32_t rirb_wp;
165 uint32_t rirb_cnt;
166 uint32_t rirb_ctl;
167 uint32_t rirb_sts;
168 uint32_t rirb_size;
169
170 uint32_t dp_lbase;
171 uint32_t dp_ubase;
172
173 uint32_t icw;
174 uint32_t irr;
175 uint32_t ics;
176
177 /* streams */
178 IntelHDAStream st[8];
179
180 /* state */
234bbdf1 181 MemoryRegion mmio;
d61a4ce8
GH		 182 uint32_t rirb_count;
183 int64_t wall_base_ns;
184
185 /* debug logging */
186 const IntelHDAReg *last_reg;
187 uint32_t last_val;
188 uint32_t last_write;
189 uint32_t last_sec;
190 uint32_t repeat_count;
191
192 /* properties */
193 uint32_t debug;
17786d52 194 uint32_t msi;
d209c744 195 bool old_msi_addr;
d61a4ce8
GH		 196};
197
062db740
PC		 198#define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
199
52bb7c6a
PC		 200#define INTEL_HDA(obj) \
201 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
202
d61a4ce8
GH		 203struct IntelHDAReg {
204 const char *name; /* register name */
205 uint32_t size; /* size in bytes */
206 uint32_t reset; /* reset value */
207 uint32_t wmask; /* write mask */
208 uint32_t wclear; /* write 1 to clear bits */
209 uint32_t offset; /* location in IntelHDAState */
210 uint32_t shift; /* byte access entries for dwords */
211 uint32_t stream;
212 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
213 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
214};
215
216static void intel_hda_reset(DeviceState *dev);
217
218/* --------------------------------------------------------------------- */
219
a8170e5e 220static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
d61a4ce8 221{
a8170e5e 222 hwaddr addr;
d61a4ce8 223
4be403c8 224 addr = ((uint64_t)ubase << 32) | lbase;
d61a4ce8
GH		 225 return addr;
226}
227
d61a4ce8
GH		 228static void intel_hda_update_int_sts(IntelHDAState *d)
229{
230 uint32_t sts = 0;
231 uint32_t i;
232
233 /* update controller status */
234 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
235 sts |= (1 << 30);
236 }
237 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
238 sts |= (1 << 30);
239 }
af93485c 240 if (d->state_sts & d->wake_en) {
d61a4ce8
GH		 241 sts |= (1 << 30);
242 }
243
244 /* update stream status */
245 for (i = 0; i < 8; i++) {
246 /* buffer completion interrupt */
247 if (d->st[i].ctl & (1 << 26)) {
248 sts |= (1 << i);
249 }
250 }
251
252 /* update global status */
253 if (sts & d->int_ctl) {
b1fe60cd 254 sts |= (1U << 31);
d61a4ce8
GH		 255 }
256
257 d->int_sts = sts;
258}
259
260static void intel_hda_update_irq(IntelHDAState *d)
261{
17786d52 262 int msi = d->msi && msi_enabled(&d->pci);
d61a4ce8
GH		 263 int level;
264
265 intel_hda_update_int_sts(d);
b1fe60cd 266 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
d61a4ce8
GH		 267 level = 1;
268 } else {
269 level = 0;
270 }
17786d52
GH		 271 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
272 level, msi ? "msi" : "intx");
273 if (msi) {
274 if (level) {
275 msi_notify(&d->pci, 0);
276 }
277 } else {
9e64f8a3 278 pci_set_irq(&d->pci, level);
17786d52 279 }
d61a4ce8
GH		 280}
281
282static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
283{
284 uint32_t cad, nid, data;
285 HDACodecDevice *codec;
dbaa7904 286 HDACodecDeviceClass *cdc;
d61a4ce8
GH		 287
288 cad = (verb >> 28) & 0x0f;
289 if (verb & (1 << 27)) {
290 /* indirect node addressing, not specified in HDA 1.0 */
291 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
292 return -1;
293 }
294 nid = (verb >> 20) & 0x7f;
295 data = verb & 0xfffff;
296
297 codec = hda_codec_find(&d->codecs, cad);
298 if (codec == NULL) {
299 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
300 return -1;
301 }
dbaa7904
AL		 302 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
303 cdc->command(codec, nid, data);
d61a4ce8
GH		 304 return 0;
305}
306
307static void intel_hda_corb_run(IntelHDAState *d)
308{
a8170e5e 309 hwaddr addr;
d61a4ce8
GH		 310 uint32_t rp, verb;
311
312 if (d->ics & ICH6_IRS_BUSY) {
313 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
314 intel_hda_send_command(d, d->icw);
315 return;
316 }
317
318 for (;;) {
319 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
320 dprint(d, 2, "%s: !run\n", __FUNCTION__);
321 return;
322 }
323 if ((d->corb_rp & 0xff) == d->corb_wp) {
324 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
325 return;
326 }
327 if (d->rirb_count == d->rirb_cnt) {
328 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
329 return;
330 }
331
332 rp = (d->corb_rp + 1) & 0xff;
333 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
fa0ce55c 334 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
d61a4ce8
GH		 335 d->corb_rp = rp;
336
337 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
338 intel_hda_send_command(d, verb);
339 }
340}
341
342static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
343{
e19202af 344 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
d61a4ce8 345 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
a8170e5e 346 hwaddr addr;
d61a4ce8
GH		 347 uint32_t wp, ex;
348
349 if (d->ics & ICH6_IRS_BUSY) {
350 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
351 __FUNCTION__, response, dev->cad);
352 d->irr = response;
353 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
354 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
355 return;
356 }
357
358 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
359 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
360 return;
361 }
362
363 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
364 wp = (d->rirb_wp + 1) & 0xff;
365 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
fa0ce55c
DG		 366 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
367 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
d61a4ce8
GH		 368 d->rirb_wp = wp;
369
370 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
371 __FUNCTION__, wp, response, ex);
372
373 d->rirb_count++;
374 if (d->rirb_count == d->rirb_cnt) {
375 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
376 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
377 d->rirb_sts |= ICH6_RBSTS_IRQ;
378 intel_hda_update_irq(d);
379 }
380 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
381 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
382 d->rirb_count, d->rirb_cnt);
383 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
384 d->rirb_sts |= ICH6_RBSTS_IRQ;
385 intel_hda_update_irq(d);
386 }
387 }
388}
389
390static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
391 uint8_t *buf, uint32_t len)
392{
e19202af 393 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
d61a4ce8 394 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
a8170e5e 395 hwaddr addr;
d61a4ce8 396 uint32_t s, copy, left;
36ac4ad3 397 IntelHDAStream *st;
d61a4ce8
GH		 398 bool irq = false;
399
36ac4ad3
MAL		 400 st = output ? d->st + 4 : d->st;
401 for (s = 0; s < 4; s++) {
402 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
403 st = st + s;
d61a4ce8
GH		 404 break;
405 }
406 }
18ebcc86 407 if (s == 4) {
d61a4ce8
GH		 408 return false;
409 }
410 if (st->bpl == NULL) {
411 return false;
412 }
413 if (st->ctl & (1 << 26)) {
414 /*
415 * Wait with the next DMA xfer until the guest
416 * has acked the buffer completion interrupt
417 */
418 return false;
419 }
420
421 left = len;
422 while (left > 0) {
423 copy = left;
424 if (copy > st->bsize - st->lpib)
425 copy = st->bsize - st->lpib;
426 if (copy > st->bpl[st->be].len - st->bp)
427 copy = st->bpl[st->be].len - st->bp;
428
429 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
430 st->be, st->bp, st->bpl[st->be].len, copy);
431
fa0ce55c 432 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
d61a4ce8
GH		 433 st->lpib += copy;
434 st->bp += copy;
435 buf += copy;
436 left -= copy;
437
438 if (st->bpl[st->be].len == st->bp) {
439 /* bpl entry filled */
440 if (st->bpl[st->be].flags & 0x01) {
441 irq = true;
442 }
443 st->bp = 0;
444 st->be++;
445 if (st->be == st->bentries) {
446 /* bpl wrap around */
447 st->be = 0;
448 st->lpib = 0;
449 }
450 }
451 }
452 if (d->dp_lbase & 0x01) {
d58ce68a 453 s = st - d->st;
d61a4ce8 454 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
fa0ce55c 455 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
d61a4ce8
GH		 456 }
457 dprint(d, 3, "dma: --\n");
458
459 if (irq) {
460 st->ctl |= (1 << 26); /* buffer completion interrupt */
461 intel_hda_update_irq(d);
462 }
463 return true;
464}
465
466static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
467{
a8170e5e 468 hwaddr addr;
d61a4ce8
GH		 469 uint8_t buf[16];
470 uint32_t i;
471
472 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
473 st->bentries = st->lvi +1;
7267c094
AL		 474 g_free(st->bpl);
475 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
d61a4ce8 476 for (i = 0; i < st->bentries; i++, addr += 16) {
fa0ce55c 477 pci_dma_read(&d->pci, addr, buf, 16);
d61a4ce8
GH		 478 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
479 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
480 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
481 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
482 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
483 }
484
485 st->bsize = st->cbl;
486 st->lpib = 0;
487 st->be = 0;
488 st->bp = 0;
489}
490
ba43d289 491static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
d61a4ce8 492{
0866aca1 493 BusChild *kid;
d61a4ce8
GH		 494 HDACodecDevice *cdev;
495
0866aca1
AL		 496 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
497 DeviceState *qdev = kid->child;
dbaa7904
AL		 498 HDACodecDeviceClass *cdc;
499
e19202af 500 cdev = HDA_CODEC_DEVICE(qdev);
dbaa7904
AL		 501 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
502 if (cdc->stream) {
503 cdc->stream(cdev, stream, running, output);
d61a4ce8
GH		 504 }
505 }
506}
507
508/* --------------------------------------------------------------------- */
509
510static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
511{
512 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
52bb7c6a 513 intel_hda_reset(DEVICE(d));
d61a4ce8
GH		 514 }
515}
516
6a0d02f5
GH		 517static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
518{
519 intel_hda_update_irq(d);
520}
521
d61a4ce8
GH		 522static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
523{
524 intel_hda_update_irq(d);
525}
526
527static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
528{
529 intel_hda_update_irq(d);
530}
531
532static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
533{
534 int64_t ns;
535
bc72ad67 536 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
d61a4ce8
GH		 537 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
538}
539
540static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
541{
542 intel_hda_corb_run(d);
543}
544
545static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
546{
547 intel_hda_corb_run(d);
548}
549
550static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
551{
552 if (d->rirb_wp & ICH6_RIRBWP_RST) {
553 d->rirb_wp = 0;
554 }
555}
556
557static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
558{
559 intel_hda_update_irq(d);
560
561 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
562 /* cleared ICH6_RBSTS_IRQ */
563 d->rirb_count = 0;
564 intel_hda_corb_run(d);
565 }
566}
567
568static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
569{
570 if (d->ics & ICH6_IRS_BUSY) {
571 intel_hda_corb_run(d);
572 }
573}
574
575static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
576{
ba43d289 577 bool output = reg->stream >= 4;
d61a4ce8
GH		 578 IntelHDAStream *st = d->st + reg->stream;
579
580 if (st->ctl & 0x01) {
581 /* reset */
582 dprint(d, 1, "st #%d: reset\n", reg->stream);
a2554a33 583 st->ctl = SD_STS_FIFO_READY << 24;
d61a4ce8
GH		 584 }
585 if ((st->ctl & 0x02) != (old & 0x02)) {
586 uint32_t stnr = (st->ctl >> 20) & 0x0f;
587 /* run bit flipped */
588 if (st->ctl & 0x02) {
589 /* start */
590 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
591 reg->stream, stnr, st->cbl);
592 intel_hda_parse_bdl(d, st);
ba43d289 593 intel_hda_notify_codecs(d, stnr, true, output);
d61a4ce8
GH		 594 } else {
595 /* stop */
596 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
ba43d289 597 intel_hda_notify_codecs(d, stnr, false, output);
d61a4ce8
GH		 598 }
599 }
600 intel_hda_update_irq(d);
601}
602
603/* --------------------------------------------------------------------- */
604
605#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
606
607static const struct IntelHDAReg regtab[] = {
608 /* global */
609 [ ICH6_REG_GCAP ] = {
610 .name = "GCAP",
611 .size = 2,
612 .reset = 0x4401,
613 },
614 [ ICH6_REG_VMIN ] = {
615 .name = "VMIN",
616 .size = 1,
617 },
618 [ ICH6_REG_VMAJ ] = {
619 .name = "VMAJ",
620 .size = 1,
621 .reset = 1,
622 },
623 [ ICH6_REG_OUTPAY ] = {
624 .name = "OUTPAY",
625 .size = 2,
626 .reset = 0x3c,
627 },
628 [ ICH6_REG_INPAY ] = {
629 .name = "INPAY",
630 .size = 2,
631 .reset = 0x1d,
632 },
633 [ ICH6_REG_GCTL ] = {
634 .name = "GCTL",
635 .size = 4,
636 .wmask = 0x0103,
637 .offset = offsetof(IntelHDAState, g_ctl),
638 .whandler = intel_hda_set_g_ctl,
639 },
640 [ ICH6_REG_WAKEEN ] = {
641 .name = "WAKEEN",
642 .size = 2,
df0db221 643 .wmask = 0x7fff,
d61a4ce8 644 .offset = offsetof(IntelHDAState, wake_en),
6a0d02f5 645 .whandler = intel_hda_set_wake_en,
d61a4ce8
GH		 646 },
647 [ ICH6_REG_STATESTS ] = {
648 .name = "STATESTS",
649 .size = 2,
df0db221
GH		 650 .wmask = 0x7fff,
651 .wclear = 0x7fff,
d61a4ce8
GH		 652 .offset = offsetof(IntelHDAState, state_sts),
653 .whandler = intel_hda_set_state_sts,
654 },
655
656 /* interrupts */
657 [ ICH6_REG_INTCTL ] = {
658 .name = "INTCTL",
659 .size = 4,
660 .wmask = 0xc00000ff,
661 .offset = offsetof(IntelHDAState, int_ctl),
662 .whandler = intel_hda_set_int_ctl,
663 },
664 [ ICH6_REG_INTSTS ] = {
665 .name = "INTSTS",
666 .size = 4,
667 .wmask = 0xc00000ff,
668 .wclear = 0xc00000ff,
669 .offset = offsetof(IntelHDAState, int_sts),
670 },
671
672 /* misc */
673 [ ICH6_REG_WALLCLK ] = {
674 .name = "WALLCLK",
675 .size = 4,
676 .offset = offsetof(IntelHDAState, wall_clk),
677 .rhandler = intel_hda_get_wall_clk,
678 },
679 [ ICH6_REG_WALLCLK + 0x2000 ] = {
680 .name = "WALLCLK(alias)",
681 .size = 4,
682 .offset = offsetof(IntelHDAState, wall_clk),
683 .rhandler = intel_hda_get_wall_clk,
684 },
685
686 /* dma engine */
687 [ ICH6_REG_CORBLBASE ] = {
688 .name = "CORBLBASE",
689 .size = 4,
690 .wmask = 0xffffff80,
691 .offset = offsetof(IntelHDAState, corb_lbase),
692 },
693 [ ICH6_REG_CORBUBASE ] = {
694 .name = "CORBUBASE",
695 .size = 4,
696 .wmask = 0xffffffff,
697 .offset = offsetof(IntelHDAState, corb_ubase),
698 },
699 [ ICH6_REG_CORBWP ] = {
700 .name = "CORBWP",
701 .size = 2,
702 .wmask = 0xff,
703 .offset = offsetof(IntelHDAState, corb_wp),
704 .whandler = intel_hda_set_corb_wp,
705 },
706 [ ICH6_REG_CORBRP ] = {
707 .name = "CORBRP",
708 .size = 2,
709 .wmask = 0x80ff,
710 .offset = offsetof(IntelHDAState, corb_rp),
711 },
712 [ ICH6_REG_CORBCTL ] = {
713 .name = "CORBCTL",
714 .size = 1,
715 .wmask = 0x03,
716 .offset = offsetof(IntelHDAState, corb_ctl),
717 .whandler = intel_hda_set_corb_ctl,
718 },
719 [ ICH6_REG_CORBSTS ] = {
720 .name = "CORBSTS",
721 .size = 1,
722 .wmask = 0x01,
723 .wclear = 0x01,
724 .offset = offsetof(IntelHDAState, corb_sts),
725 },
726 [ ICH6_REG_CORBSIZE ] = {
727 .name = "CORBSIZE",
728 .size = 1,
729 .reset = 0x42,
730 .offset = offsetof(IntelHDAState, corb_size),
731 },
732 [ ICH6_REG_RIRBLBASE ] = {
733 .name = "RIRBLBASE",
734 .size = 4,
735 .wmask = 0xffffff80,
736 .offset = offsetof(IntelHDAState, rirb_lbase),
737 },
738 [ ICH6_REG_RIRBUBASE ] = {
739 .name = "RIRBUBASE",
740 .size = 4,
741 .wmask = 0xffffffff,
742 .offset = offsetof(IntelHDAState, rirb_ubase),
743 },
744 [ ICH6_REG_RIRBWP ] = {
745 .name = "RIRBWP",
746 .size = 2,
747 .wmask = 0x8000,
748 .offset = offsetof(IntelHDAState, rirb_wp),
749 .whandler = intel_hda_set_rirb_wp,
750 },
751 [ ICH6_REG_RINTCNT ] = {
752 .name = "RINTCNT",
753 .size = 2,
754 .wmask = 0xff,
755 .offset = offsetof(IntelHDAState, rirb_cnt),
756 },
757 [ ICH6_REG_RIRBCTL ] = {
758 .name = "RIRBCTL",
759 .size = 1,
760 .wmask = 0x07,
761 .offset = offsetof(IntelHDAState, rirb_ctl),
762 },
763 [ ICH6_REG_RIRBSTS ] = {
764 .name = "RIRBSTS",
765 .size = 1,
766 .wmask = 0x05,
767 .wclear = 0x05,
768 .offset = offsetof(IntelHDAState, rirb_sts),
769 .whandler = intel_hda_set_rirb_sts,
770 },
771 [ ICH6_REG_RIRBSIZE ] = {
772 .name = "RIRBSIZE",
773 .size = 1,
774 .reset = 0x42,
775 .offset = offsetof(IntelHDAState, rirb_size),
776 },
777
778 [ ICH6_REG_DPLBASE ] = {
779 .name = "DPLBASE",
780 .size = 4,
781 .wmask = 0xffffff81,
782 .offset = offsetof(IntelHDAState, dp_lbase),
783 },
784 [ ICH6_REG_DPUBASE ] = {
785 .name = "DPUBASE",
786 .size = 4,
787 .wmask = 0xffffffff,
788 .offset = offsetof(IntelHDAState, dp_ubase),
789 },
790
791 [ ICH6_REG_IC ] = {
792 .name = "ICW",
793 .size = 4,
794 .wmask = 0xffffffff,
795 .offset = offsetof(IntelHDAState, icw),
796 },
797 [ ICH6_REG_IR ] = {
798 .name = "IRR",
799 .size = 4,
800 .offset = offsetof(IntelHDAState, irr),
801 },
802 [ ICH6_REG_IRS ] = {
803 .name = "ICS",
804 .size = 2,
805 .wmask = 0x0003,
806 .wclear = 0x0002,
807 .offset = offsetof(IntelHDAState, ics),
808 .whandler = intel_hda_set_ics,
809 },
810
811#define HDA_STREAM(_t, _i) \
812 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
813 .stream = _i, \
814 .name = _t stringify(_i) " CTL", \
815 .size = 4, \
816 .wmask = 0x1cff001f, \
817 .offset = offsetof(IntelHDAState, st[_i].ctl), \
818 .whandler = intel_hda_set_st_ctl, \
819 }, \
820 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
821 .stream = _i, \
822 .name = _t stringify(_i) " CTL(stnr)", \
823 .size = 1, \
824 .shift = 16, \
825 .wmask = 0x00ff0000, \
826 .offset = offsetof(IntelHDAState, st[_i].ctl), \
827 .whandler = intel_hda_set_st_ctl, \
828 }, \
829 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
830 .stream = _i, \
831 .name = _t stringify(_i) " CTL(sts)", \
832 .size = 1, \
833 .shift = 24, \
834 .wmask = 0x1c000000, \
835 .wclear = 0x1c000000, \
836 .offset = offsetof(IntelHDAState, st[_i].ctl), \
837 .whandler = intel_hda_set_st_ctl, \
a2554a33 838 .reset = SD_STS_FIFO_READY << 24 \
d61a4ce8
GH		 839 }, \
840 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
841 .stream = _i, \
842 .name = _t stringify(_i) " LPIB", \
843 .size = 4, \
844 .offset = offsetof(IntelHDAState, st[_i].lpib), \
845 }, \
846 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
847 .stream = _i, \
848 .name = _t stringify(_i) " LPIB(alias)", \
849 .size = 4, \
850 .offset = offsetof(IntelHDAState, st[_i].lpib), \
851 }, \
852 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
853 .stream = _i, \
854 .name = _t stringify(_i) " CBL", \
855 .size = 4, \
856 .wmask = 0xffffffff, \
857 .offset = offsetof(IntelHDAState, st[_i].cbl), \
858 }, \
859 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
860 .stream = _i, \
861 .name = _t stringify(_i) " LVI", \
862 .size = 2, \
863 .wmask = 0x00ff, \
864 .offset = offsetof(IntelHDAState, st[_i].lvi), \
865 }, \
866 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
867 .stream = _i, \
868 .name = _t stringify(_i) " FIFOS", \
869 .size = 2, \
870 .reset = HDA_BUFFER_SIZE, \
871 }, \
872 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
873 .stream = _i, \
874 .name = _t stringify(_i) " FMT", \
875 .size = 2, \
876 .wmask = 0x7f7f, \
877 .offset = offsetof(IntelHDAState, st[_i].fmt), \
878 }, \
879 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
880 .stream = _i, \
881 .name = _t stringify(_i) " BDLPL", \
882 .size = 4, \
883 .wmask = 0xffffff80, \
884 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
885 }, \
886 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
887 .stream = _i, \
888 .name = _t stringify(_i) " BDLPU", \
889 .size = 4, \
890 .wmask = 0xffffffff, \
891 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
892 }, \
893
894 HDA_STREAM("IN", 0)
895 HDA_STREAM("IN", 1)
896 HDA_STREAM("IN", 2)
897 HDA_STREAM("IN", 3)
898
899 HDA_STREAM("OUT", 4)
900 HDA_STREAM("OUT", 5)
901 HDA_STREAM("OUT", 6)
902 HDA_STREAM("OUT", 7)
903
904};
905
a8170e5e 906static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
d61a4ce8
GH		 907{
908 const IntelHDAReg *reg;
909
dff7424d 910 if (addr >= ARRAY_SIZE(regtab)) {
d61a4ce8
GH		 911 goto noreg;
912 }
913 reg = regtab+addr;
914 if (reg->name == NULL) {
915 goto noreg;
916 }
917 return reg;
918
919noreg:
920 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
921 return NULL;
922}
923
924static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
925{
926 uint8_t *addr = (void*)d;
927
928 addr += reg->offset;
929 return (uint32_t*)addr;
930}
931
932static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
933 uint32_t wmask)
934{
935 uint32_t *addr;
936 uint32_t old;
937
938 if (!reg) {
939 return;
940 }
941
942 if (d->debug) {
943 time_t now = time(NULL);
944 if (d->last_write && d->last_reg == reg && d->last_val == val) {
945 d->repeat_count++;
946 if (d->last_sec != now) {
947 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
948 d->last_sec = now;
949 d->repeat_count = 0;
950 }
951 } else {
952 if (d->repeat_count) {
953 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
954 }
955 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
956 d->last_write = 1;
957 d->last_reg = reg;
958 d->last_val = val;
959 d->last_sec = now;
960 d->repeat_count = 0;
961 }
962 }
963 assert(reg->offset != 0);
964
965 addr = intel_hda_reg_addr(d, reg);
966 old = *addr;
967
968 if (reg->shift) {
969 val <<= reg->shift;
970 wmask <<= reg->shift;
971 }
972 wmask &= reg->wmask;
973 *addr &= ~wmask;
974 *addr |= wmask & val;
975 *addr &= ~(val & reg->wclear);
976
977 if (reg->whandler) {
978 reg->whandler(d, reg, old);
979 }
980}
981
982static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
983 uint32_t rmask)
984{
985 uint32_t *addr, ret;
986
987 if (!reg) {
988 return 0;
989 }
990
991 if (reg->rhandler) {
992 reg->rhandler(d, reg);
993 }
994
995 if (reg->offset == 0) {
996 /* constant read-only register */
997 ret = reg->reset;
998 } else {
999 addr = intel_hda_reg_addr(d, reg);
1000 ret = *addr;
1001 if (reg->shift) {
1002 ret >>= reg->shift;
1003 }
1004 ret &= rmask;
1005 }
1006 if (d->debug) {
1007 time_t now = time(NULL);
1008 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1009 d->repeat_count++;
1010 if (d->last_sec != now) {
1011 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1012 d->last_sec = now;
1013 d->repeat_count = 0;
1014 }
1015 } else {
1016 if (d->repeat_count) {
1017 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1018 }
1019 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1020 d->last_write = 0;
1021 d->last_reg = reg;
1022 d->last_val = ret;
1023 d->last_sec = now;
1024 d->repeat_count = 0;
1025 }
1026 }
1027 return ret;
1028}
1029
1030static void intel_hda_regs_reset(IntelHDAState *d)
1031{
1032 uint32_t *addr;
1033 int i;
1034
dff7424d 1035 for (i = 0; i < ARRAY_SIZE(regtab); i++) {
d61a4ce8
GH		 1036 if (regtab[i].name == NULL) {
1037 continue;
1038 }
1039 if (regtab[i].offset == 0) {
1040 continue;
1041 }
1042 addr = intel_hda_reg_addr(d, regtab + i);
1043 *addr = regtab[i].reset;
1044 }
1045}
1046
1047/* --------------------------------------------------------------------- */
1048
a8170e5e 1049static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1050{
1051 IntelHDAState *d = opaque;
1052 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1053
1054 intel_hda_reg_write(d, reg, val, 0xff);
1055}
1056
a8170e5e 1057static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1058{
1059 IntelHDAState *d = opaque;
1060 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1061
1062 intel_hda_reg_write(d, reg, val, 0xffff);
1063}
1064
a8170e5e 1065static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1066{
1067 IntelHDAState *d = opaque;
1068 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1069
1070 intel_hda_reg_write(d, reg, val, 0xffffffff);
1071}
1072
a8170e5e 1073static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
d61a4ce8
GH		 1074{
1075 IntelHDAState *d = opaque;
1076 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1077
1078 return intel_hda_reg_read(d, reg, 0xff);
1079}
1080
a8170e5e 1081static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
d61a4ce8
GH		 1082{
1083 IntelHDAState *d = opaque;
1084 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1085
1086 return intel_hda_reg_read(d, reg, 0xffff);
1087}
1088
a8170e5e 1089static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
d61a4ce8
GH		 1090{
1091 IntelHDAState *d = opaque;
1092 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1093
1094 return intel_hda_reg_read(d, reg, 0xffffffff);
1095}
1096
234bbdf1
AK		 1097static const MemoryRegionOps intel_hda_mmio_ops = {
1098 .old_mmio = {
1099 .read = {
1100 intel_hda_mmio_readb,
1101 intel_hda_mmio_readw,
1102 intel_hda_mmio_readl,
1103 },
1104 .write = {
1105 intel_hda_mmio_writeb,
1106 intel_hda_mmio_writew,
1107 intel_hda_mmio_writel,
1108 },
1109 },
1110 .endianness = DEVICE_NATIVE_ENDIAN,
d61a4ce8
GH		 1111};
1112
d61a4ce8
GH		 1113/* --------------------------------------------------------------------- */
1114
1115static void intel_hda_reset(DeviceState *dev)
1116{
0866aca1 1117 BusChild *kid;
52bb7c6a 1118 IntelHDAState *d = INTEL_HDA(dev);
d61a4ce8
GH		 1119 HDACodecDevice *cdev;
1120
1121 intel_hda_regs_reset(d);
bc72ad67 1122 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
d61a4ce8
GH		 1123
1124 /* reset codecs */
0866aca1
AL		 1125 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1126 DeviceState *qdev = kid->child;
e19202af 1127 cdev = HDA_CODEC_DEVICE(qdev);
94afdadc 1128 device_reset(DEVICE(cdev));
d61a4ce8
GH		 1129 d->state_sts |= (1 << cdev->cad);
1130 }
1131 intel_hda_update_irq(d);
1132}
1133
9af21dbe 1134static void intel_hda_realize(PCIDevice *pci, Error **errp)
d61a4ce8 1135{
52bb7c6a 1136 IntelHDAState *d = INTEL_HDA(pci);
d61a4ce8
GH		 1137 uint8_t *conf = d->pci.config;
1138
f79f2bfc 1139 d->name = object_get_typename(OBJECT(d));
d61a4ce8 1140
d61a4ce8
GH		 1141 pci_config_set_interrupt_pin(conf, 1);
1142
1143 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1144 conf[0x40] = 0x01;
1145
64bde0f3 1146 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
234bbdf1 1147 "intel-hda", 0x4000);
e824b2cc 1148 pci_register_bar(&d->pci, 0, 0, &d->mmio);
17786d52 1149 if (d->msi) {
d209c744 1150 msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60, 1, true, false);
17786d52 1151 }
d61a4ce8 1152
ab809e84 1153 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
d61a4ce8 1154 intel_hda_response, intel_hda_xfer);
d61a4ce8
GH		 1155}
1156
f90c2bcd 1157static void intel_hda_exit(PCIDevice *pci)
dc4b9240 1158{
52bb7c6a 1159 IntelHDAState *d = INTEL_HDA(pci);
dc4b9240 1160
45fe15c2 1161 msi_uninit(&d->pci);
dc4b9240
GH		 1162}
1163
d61a4ce8
GH		 1164static int intel_hda_post_load(void *opaque, int version)
1165{
1166 IntelHDAState* d = opaque;
1167 int i;
1168
1169 dprint(d, 1, "%s\n", __FUNCTION__);
1170 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1171 if (d->st[i].ctl & 0x02) {
1172 intel_hda_parse_bdl(d, &d->st[i]);
1173 }
1174 }
1175 intel_hda_update_irq(d);
1176 return 0;
1177}
1178
1179static const VMStateDescription vmstate_intel_hda_stream = {
1180 .name = "intel-hda-stream",
1181 .version_id = 1,
d49805ae 1182 .fields = (VMStateField[]) {
d61a4ce8
GH		 1183 VMSTATE_UINT32(ctl, IntelHDAStream),
1184 VMSTATE_UINT32(lpib, IntelHDAStream),
1185 VMSTATE_UINT32(cbl, IntelHDAStream),
1186 VMSTATE_UINT32(lvi, IntelHDAStream),
1187 VMSTATE_UINT32(fmt, IntelHDAStream),
1188 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1189 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1190 VMSTATE_END_OF_LIST()
1191 }
1192};
1193
1194static const VMStateDescription vmstate_intel_hda = {
1195 .name = "intel-hda",
1196 .version_id = 1,
1197 .post_load = intel_hda_post_load,
d49805ae 1198 .fields = (VMStateField[]) {
d61a4ce8
GH		 1199 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1200
1201 /* registers */
1202 VMSTATE_UINT32(g_ctl, IntelHDAState),
1203 VMSTATE_UINT32(wake_en, IntelHDAState),
1204 VMSTATE_UINT32(state_sts, IntelHDAState),
1205 VMSTATE_UINT32(int_ctl, IntelHDAState),
1206 VMSTATE_UINT32(int_sts, IntelHDAState),
1207 VMSTATE_UINT32(wall_clk, IntelHDAState),
1208 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1209 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1210 VMSTATE_UINT32(corb_rp, IntelHDAState),
1211 VMSTATE_UINT32(corb_wp, IntelHDAState),
1212 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1213 VMSTATE_UINT32(corb_sts, IntelHDAState),
1214 VMSTATE_UINT32(corb_size, IntelHDAState),
1215 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1216 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1217 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1218 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1219 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1220 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1221 VMSTATE_UINT32(rirb_size, IntelHDAState),
1222 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1223 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1224 VMSTATE_UINT32(icw, IntelHDAState),
1225 VMSTATE_UINT32(irr, IntelHDAState),
1226 VMSTATE_UINT32(ics, IntelHDAState),
1227 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1228 vmstate_intel_hda_stream,
1229 IntelHDAStream),
1230
1231 /* additional state info */
1232 VMSTATE_UINT32(rirb_count, IntelHDAState),
1233 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1234
1235 VMSTATE_END_OF_LIST()
1236 }
1237};
1238
40021f08
AL		 1239static Property intel_hda_properties[] = {
1240 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1241 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
d209c744 1242 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
40021f08
AL		 1243 DEFINE_PROP_END_OF_LIST(),
1244};
1245
062db740 1246static void intel_hda_class_init(ObjectClass *klass, void *data)
40021f08 1247{
39bffca2 1248 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1249 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1250
9af21dbe 1251 k->realize = intel_hda_realize;
40021f08 1252 k->exit = intel_hda_exit;
40021f08 1253 k->vendor_id = PCI_VENDOR_ID_INTEL;
40021f08 1254 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
39bffca2
AL		 1255 dc->reset = intel_hda_reset;
1256 dc->vmsd = &vmstate_intel_hda;
1257 dc->props = intel_hda_properties;
40021f08
AL		 1258}
1259
8b07eaa1
GH		 1260static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1261{
1262 DeviceClass *dc = DEVICE_CLASS(klass);
1263 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1264
8b07eaa1
GH		 1265 k->device_id = 0x2668;
1266 k->revision = 1;
125ee0ed 1267 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
8b07eaa1
GH		 1268 dc->desc = "Intel HD Audio Controller (ich6)";
1269}
1270
1271static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1272{
1273 DeviceClass *dc = DEVICE_CLASS(klass);
1274 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1275
8b07eaa1
GH		 1276 k->device_id = 0x293e;
1277 k->revision = 3;
125ee0ed 1278 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
8b07eaa1
GH		 1279 dc->desc = "Intel HD Audio Controller (ich9)";
1280}
1281
062db740
PC		 1282static const TypeInfo intel_hda_info = {
1283 .name = TYPE_INTEL_HDA_GENERIC,
39bffca2
AL		 1284 .parent = TYPE_PCI_DEVICE,
1285 .instance_size = sizeof(IntelHDAState),
062db740
PC		 1286 .class_init = intel_hda_class_init,
1287 .abstract = true,
1288};
1289
1290static const TypeInfo intel_hda_info_ich6 = {
1291 .name = "intel-hda",
1292 .parent = TYPE_INTEL_HDA_GENERIC,
8b07eaa1
GH		 1293 .class_init = intel_hda_class_init_ich6,
1294};
1295
e2848a78 1296static const TypeInfo intel_hda_info_ich9 = {
8b07eaa1 1297 .name = "ich9-intel-hda",
062db740 1298 .parent = TYPE_INTEL_HDA_GENERIC,
8b07eaa1 1299 .class_init = intel_hda_class_init_ich9,
40021f08
AL		 1300};
1301
39bffca2
AL		 1302static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1303{
1304 DeviceClass *k = DEVICE_CLASS(klass);
bda8d9b8 1305 k->realize = hda_codec_dev_realize;
39bffca2 1306 k->exit = hda_codec_dev_exit;
125ee0ed 1307 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
0d936928 1308 k->bus_type = TYPE_HDA_BUS;
bce54474 1309 k->props = hda_props;
39bffca2
AL		 1310}
1311
8c43a6f0 1312static const TypeInfo hda_codec_device_type_info = {
40021f08
AL		 1313 .name = TYPE_HDA_CODEC_DEVICE,
1314 .parent = TYPE_DEVICE,
1315 .instance_size = sizeof(HDACodecDevice),
1316 .abstract = true,
1317 .class_size = sizeof(HDACodecDeviceClass),
39bffca2 1318 .class_init = hda_codec_device_class_init,
d61a4ce8
GH		 1319};
1320
d61a4ce8
GH		 1321/*
1322 * create intel hda controller with codec attached to it,
1323 * so '-soundhw hda' works.
1324 */
36cd6f6f 1325static int intel_hda_and_codec_init(PCIBus *bus)
d61a4ce8 1326{
52bb7c6a 1327 DeviceState *controller;
d61a4ce8
GH		 1328 BusState *hdabus;
1329 DeviceState *codec;
1330
52bb7c6a
PC		 1331 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1332 hdabus = QLIST_FIRST(&controller->child_bus);
d61a4ce8
GH		 1333 codec = qdev_create(hdabus, "hda-duplex");
1334 qdev_init_nofail(codec);
1335 return 0;
1336}
1337
36cd6f6f
PB		 1338static void intel_hda_register_types(void)
1339{
1340 type_register_static(&hda_codec_bus_info);
062db740 1341 type_register_static(&intel_hda_info);
36cd6f6f
PB		 1342 type_register_static(&intel_hda_info_ich6);
1343 type_register_static(&intel_hda_info_ich9);
1344 type_register_static(&hda_codec_device_type_info);
1345 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1346}
1347
1348type_init(intel_hda_register_types)
Empty description
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