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adlib: fix patching of port I/O addresses
[qemu.git] / hw / audio / intel-hda.c
CommitLineData
d61a4ce8
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
83c9f4ca
PB		 20#include "hw/hw.h"
21#include "hw/pci/pci.h"
22#include "hw/pci/msi.h"
1de7afc9 23#include "qemu/timer.h"
0d09e41a 24#include "hw/audio/audio.h"
47b43a1f
PB		 25#include "intel-hda.h"
26#include "intel-hda-defs.h"
9c17d615 27#include "sysemu/dma.h"
d61a4ce8
GH		 28
29/* --------------------------------------------------------------------- */
30/* hda bus */
31
3cb75a7c
PB		 32static Property hda_props[] = {
33 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
34 DEFINE_PROP_END_OF_LIST()
35};
36
0d936928
AL		 37static const TypeInfo hda_codec_bus_info = {
38 .name = TYPE_HDA_BUS,
39 .parent = TYPE_BUS,
40 .instance_size = sizeof(HDACodecBus),
d61a4ce8
GH		 41};
42
ab809e84 43void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
d61a4ce8
GH		 44 hda_codec_response_func response,
45 hda_codec_xfer_func xfer)
46{
fb17dfe0 47 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
d61a4ce8
GH		 48 bus->response = response;
49 bus->xfer = xfer;
50}
51
d307af79 52static int hda_codec_dev_init(DeviceState *qdev)
d61a4ce8
GH		 53{
54 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
55 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904 56 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
d61a4ce8 57
d61a4ce8
GH		 58 if (dev->cad == -1) {
59 dev->cad = bus->next_cad;
60 }
df0db221 61 if (dev->cad >= 15) {
d61a4ce8 62 return -1;
df0db221 63 }
d61a4ce8 64 bus->next_cad = dev->cad + 1;
dbaa7904 65 return cdc->init(dev);
d61a4ce8
GH		 66}
67
dc4b9240
GH		 68static int hda_codec_dev_exit(DeviceState *qdev)
69{
70 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904 71 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
dc4b9240 72
dbaa7904
AL		 73 if (cdc->exit) {
74 cdc->exit(dev);
dc4b9240
GH		 75 }
76 return 0;
77}
78
d61a4ce8
GH		 79HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
80{
0866aca1 81 BusChild *kid;
d61a4ce8
GH		 82 HDACodecDevice *cdev;
83
0866aca1
AL		 84 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
85 DeviceState *qdev = kid->child;
d61a4ce8
GH		 86 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
87 if (cdev->cad == cad) {
88 return cdev;
89 }
90 }
91 return NULL;
92}
93
94void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
95{
96 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
97 bus->response(dev, solicited, response);
98}
99
100bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
101 uint8_t *buf, uint32_t len)
102{
103 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
104 return bus->xfer(dev, stnr, output, buf, len);
105}
106
107/* --------------------------------------------------------------------- */
108/* intel hda emulation */
109
110typedef struct IntelHDAStream IntelHDAStream;
111typedef struct IntelHDAState IntelHDAState;
112typedef struct IntelHDAReg IntelHDAReg;
113
114typedef struct bpl {
115 uint64_t addr;
116 uint32_t len;
117 uint32_t flags;
118} bpl;
119
120struct IntelHDAStream {
121 /* registers */
122 uint32_t ctl;
123 uint32_t lpib;
124 uint32_t cbl;
125 uint32_t lvi;
126 uint32_t fmt;
127 uint32_t bdlp_lbase;
128 uint32_t bdlp_ubase;
129
130 /* state */
131 bpl *bpl;
132 uint32_t bentries;
133 uint32_t bsize, be, bp;
134};
135
136struct IntelHDAState {
137 PCIDevice pci;
138 const char *name;
139 HDACodecBus codecs;
140
141 /* registers */
142 uint32_t g_ctl;
143 uint32_t wake_en;
144 uint32_t state_sts;
145 uint32_t int_ctl;
146 uint32_t int_sts;
147 uint32_t wall_clk;
148
149 uint32_t corb_lbase;
150 uint32_t corb_ubase;
151 uint32_t corb_rp;
152 uint32_t corb_wp;
153 uint32_t corb_ctl;
154 uint32_t corb_sts;
155 uint32_t corb_size;
156
157 uint32_t rirb_lbase;
158 uint32_t rirb_ubase;
159 uint32_t rirb_wp;
160 uint32_t rirb_cnt;
161 uint32_t rirb_ctl;
162 uint32_t rirb_sts;
163 uint32_t rirb_size;
164
165 uint32_t dp_lbase;
166 uint32_t dp_ubase;
167
168 uint32_t icw;
169 uint32_t irr;
170 uint32_t ics;
171
172 /* streams */
173 IntelHDAStream st[8];
174
175 /* state */
234bbdf1 176 MemoryRegion mmio;
d61a4ce8
GH		 177 uint32_t rirb_count;
178 int64_t wall_base_ns;
179
180 /* debug logging */
181 const IntelHDAReg *last_reg;
182 uint32_t last_val;
183 uint32_t last_write;
184 uint32_t last_sec;
185 uint32_t repeat_count;
186
187 /* properties */
188 uint32_t debug;
17786d52 189 uint32_t msi;
d61a4ce8
GH		 190};
191
062db740
PC		 192#define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
193
52bb7c6a
PC		 194#define INTEL_HDA(obj) \
195 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
196
d61a4ce8
GH		 197struct IntelHDAReg {
198 const char *name; /* register name */
199 uint32_t size; /* size in bytes */
200 uint32_t reset; /* reset value */
201 uint32_t wmask; /* write mask */
202 uint32_t wclear; /* write 1 to clear bits */
203 uint32_t offset; /* location in IntelHDAState */
204 uint32_t shift; /* byte access entries for dwords */
205 uint32_t stream;
206 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
207 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
208};
209
210static void intel_hda_reset(DeviceState *dev);
211
212/* --------------------------------------------------------------------- */
213
a8170e5e 214static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
d61a4ce8 215{
a8170e5e 216 hwaddr addr;
d61a4ce8 217
4be403c8 218 addr = ((uint64_t)ubase << 32) | lbase;
d61a4ce8
GH		 219 return addr;
220}
221
d61a4ce8
GH		 222static void intel_hda_update_int_sts(IntelHDAState *d)
223{
224 uint32_t sts = 0;
225 uint32_t i;
226
227 /* update controller status */
228 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
229 sts |= (1 << 30);
230 }
231 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
232 sts |= (1 << 30);
233 }
af93485c 234 if (d->state_sts & d->wake_en) {
d61a4ce8
GH		 235 sts |= (1 << 30);
236 }
237
238 /* update stream status */
239 for (i = 0; i < 8; i++) {
240 /* buffer completion interrupt */
241 if (d->st[i].ctl & (1 << 26)) {
242 sts |= (1 << i);
243 }
244 }
245
246 /* update global status */
247 if (sts & d->int_ctl) {
248 sts |= (1 << 31);
249 }
250
251 d->int_sts = sts;
252}
253
254static void intel_hda_update_irq(IntelHDAState *d)
255{
17786d52 256 int msi = d->msi && msi_enabled(&d->pci);
d61a4ce8
GH		 257 int level;
258
259 intel_hda_update_int_sts(d);
260 if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
261 level = 1;
262 } else {
263 level = 0;
264 }
17786d52
GH		 265 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
266 level, msi ? "msi" : "intx");
267 if (msi) {
268 if (level) {
269 msi_notify(&d->pci, 0);
270 }
271 } else {
9e64f8a3 272 pci_set_irq(&d->pci, level);
17786d52 273 }
d61a4ce8
GH		 274}
275
276static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
277{
278 uint32_t cad, nid, data;
279 HDACodecDevice *codec;
dbaa7904 280 HDACodecDeviceClass *cdc;
d61a4ce8
GH		 281
282 cad = (verb >> 28) & 0x0f;
283 if (verb & (1 << 27)) {
284 /* indirect node addressing, not specified in HDA 1.0 */
285 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
286 return -1;
287 }
288 nid = (verb >> 20) & 0x7f;
289 data = verb & 0xfffff;
290
291 codec = hda_codec_find(&d->codecs, cad);
292 if (codec == NULL) {
293 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
294 return -1;
295 }
dbaa7904
AL		 296 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
297 cdc->command(codec, nid, data);
d61a4ce8
GH		 298 return 0;
299}
300
301static void intel_hda_corb_run(IntelHDAState *d)
302{
a8170e5e 303 hwaddr addr;
d61a4ce8
GH		 304 uint32_t rp, verb;
305
306 if (d->ics & ICH6_IRS_BUSY) {
307 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
308 intel_hda_send_command(d, d->icw);
309 return;
310 }
311
312 for (;;) {
313 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
314 dprint(d, 2, "%s: !run\n", __FUNCTION__);
315 return;
316 }
317 if ((d->corb_rp & 0xff) == d->corb_wp) {
318 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
319 return;
320 }
321 if (d->rirb_count == d->rirb_cnt) {
322 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
323 return;
324 }
325
326 rp = (d->corb_rp + 1) & 0xff;
327 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
fa0ce55c 328 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
d61a4ce8
GH		 329 d->corb_rp = rp;
330
331 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
332 intel_hda_send_command(d, verb);
333 }
334}
335
336static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
337{
338 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
339 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
a8170e5e 340 hwaddr addr;
d61a4ce8
GH		 341 uint32_t wp, ex;
342
343 if (d->ics & ICH6_IRS_BUSY) {
344 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
345 __FUNCTION__, response, dev->cad);
346 d->irr = response;
347 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
348 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
349 return;
350 }
351
352 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
353 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
354 return;
355 }
356
357 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
358 wp = (d->rirb_wp + 1) & 0xff;
359 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
fa0ce55c
DG		 360 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
361 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
d61a4ce8
GH		 362 d->rirb_wp = wp;
363
364 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
365 __FUNCTION__, wp, response, ex);
366
367 d->rirb_count++;
368 if (d->rirb_count == d->rirb_cnt) {
369 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
370 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
371 d->rirb_sts |= ICH6_RBSTS_IRQ;
372 intel_hda_update_irq(d);
373 }
374 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
375 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
376 d->rirb_count, d->rirb_cnt);
377 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
378 d->rirb_sts |= ICH6_RBSTS_IRQ;
379 intel_hda_update_irq(d);
380 }
381 }
382}
383
384static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
385 uint8_t *buf, uint32_t len)
386{
387 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
388 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
a8170e5e 389 hwaddr addr;
d61a4ce8 390 uint32_t s, copy, left;
36ac4ad3 391 IntelHDAStream *st;
d61a4ce8
GH		 392 bool irq = false;
393
36ac4ad3
MAL		 394 st = output ? d->st + 4 : d->st;
395 for (s = 0; s < 4; s++) {
396 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
397 st = st + s;
d61a4ce8
GH		 398 break;
399 }
400 }
18ebcc86 401 if (s == 4) {
d61a4ce8
GH		 402 return false;
403 }
404 if (st->bpl == NULL) {
405 return false;
406 }
407 if (st->ctl & (1 << 26)) {
408 /*
409 * Wait with the next DMA xfer until the guest
410 * has acked the buffer completion interrupt
411 */
412 return false;
413 }
414
415 left = len;
416 while (left > 0) {
417 copy = left;
418 if (copy > st->bsize - st->lpib)
419 copy = st->bsize - st->lpib;
420 if (copy > st->bpl[st->be].len - st->bp)
421 copy = st->bpl[st->be].len - st->bp;
422
423 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
424 st->be, st->bp, st->bpl[st->be].len, copy);
425
fa0ce55c 426 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
d61a4ce8
GH		 427 st->lpib += copy;
428 st->bp += copy;
429 buf += copy;
430 left -= copy;
431
432 if (st->bpl[st->be].len == st->bp) {
433 /* bpl entry filled */
434 if (st->bpl[st->be].flags & 0x01) {
435 irq = true;
436 }
437 st->bp = 0;
438 st->be++;
439 if (st->be == st->bentries) {
440 /* bpl wrap around */
441 st->be = 0;
442 st->lpib = 0;
443 }
444 }
445 }
446 if (d->dp_lbase & 0x01) {
447 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
fa0ce55c 448 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
d61a4ce8
GH		 449 }
450 dprint(d, 3, "dma: --\n");
451
452 if (irq) {
453 st->ctl |= (1 << 26); /* buffer completion interrupt */
454 intel_hda_update_irq(d);
455 }
456 return true;
457}
458
459static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
460{
a8170e5e 461 hwaddr addr;
d61a4ce8
GH		 462 uint8_t buf[16];
463 uint32_t i;
464
465 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
466 st->bentries = st->lvi +1;
7267c094
AL		 467 g_free(st->bpl);
468 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
d61a4ce8 469 for (i = 0; i < st->bentries; i++, addr += 16) {
fa0ce55c 470 pci_dma_read(&d->pci, addr, buf, 16);
d61a4ce8
GH		 471 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
472 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
473 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
474 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
475 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
476 }
477
478 st->bsize = st->cbl;
479 st->lpib = 0;
480 st->be = 0;
481 st->bp = 0;
482}
483
ba43d289 484static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
d61a4ce8 485{
0866aca1 486 BusChild *kid;
d61a4ce8
GH		 487 HDACodecDevice *cdev;
488
0866aca1
AL		 489 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
490 DeviceState *qdev = kid->child;
dbaa7904
AL		 491 HDACodecDeviceClass *cdc;
492
d61a4ce8 493 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904
AL		 494 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
495 if (cdc->stream) {
496 cdc->stream(cdev, stream, running, output);
d61a4ce8
GH		 497 }
498 }
499}
500
501/* --------------------------------------------------------------------- */
502
503static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
504{
505 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
52bb7c6a 506 intel_hda_reset(DEVICE(d));
d61a4ce8
GH		 507 }
508}
509
6a0d02f5
GH		 510static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
511{
512 intel_hda_update_irq(d);
513}
514
d61a4ce8
GH		 515static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
516{
517 intel_hda_update_irq(d);
518}
519
520static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
521{
522 intel_hda_update_irq(d);
523}
524
525static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
526{
527 int64_t ns;
528
bc72ad67 529 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
d61a4ce8
GH		 530 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
531}
532
533static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
534{
535 intel_hda_corb_run(d);
536}
537
538static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
539{
540 intel_hda_corb_run(d);
541}
542
543static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
544{
545 if (d->rirb_wp & ICH6_RIRBWP_RST) {
546 d->rirb_wp = 0;
547 }
548}
549
550static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
551{
552 intel_hda_update_irq(d);
553
554 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
555 /* cleared ICH6_RBSTS_IRQ */
556 d->rirb_count = 0;
557 intel_hda_corb_run(d);
558 }
559}
560
561static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
562{
563 if (d->ics & ICH6_IRS_BUSY) {
564 intel_hda_corb_run(d);
565 }
566}
567
568static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
569{
ba43d289 570 bool output = reg->stream >= 4;
d61a4ce8
GH		 571 IntelHDAStream *st = d->st + reg->stream;
572
573 if (st->ctl & 0x01) {
574 /* reset */
575 dprint(d, 1, "st #%d: reset\n", reg->stream);
576 st->ctl = 0;
577 }
578 if ((st->ctl & 0x02) != (old & 0x02)) {
579 uint32_t stnr = (st->ctl >> 20) & 0x0f;
580 /* run bit flipped */
581 if (st->ctl & 0x02) {
582 /* start */
583 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
584 reg->stream, stnr, st->cbl);
585 intel_hda_parse_bdl(d, st);
ba43d289 586 intel_hda_notify_codecs(d, stnr, true, output);
d61a4ce8
GH		 587 } else {
588 /* stop */
589 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
ba43d289 590 intel_hda_notify_codecs(d, stnr, false, output);
d61a4ce8
GH		 591 }
592 }
593 intel_hda_update_irq(d);
594}
595
596/* --------------------------------------------------------------------- */
597
598#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
599
600static const struct IntelHDAReg regtab[] = {
601 /* global */
602 [ ICH6_REG_GCAP ] = {
603 .name = "GCAP",
604 .size = 2,
605 .reset = 0x4401,
606 },
607 [ ICH6_REG_VMIN ] = {
608 .name = "VMIN",
609 .size = 1,
610 },
611 [ ICH6_REG_VMAJ ] = {
612 .name = "VMAJ",
613 .size = 1,
614 .reset = 1,
615 },
616 [ ICH6_REG_OUTPAY ] = {
617 .name = "OUTPAY",
618 .size = 2,
619 .reset = 0x3c,
620 },
621 [ ICH6_REG_INPAY ] = {
622 .name = "INPAY",
623 .size = 2,
624 .reset = 0x1d,
625 },
626 [ ICH6_REG_GCTL ] = {
627 .name = "GCTL",
628 .size = 4,
629 .wmask = 0x0103,
630 .offset = offsetof(IntelHDAState, g_ctl),
631 .whandler = intel_hda_set_g_ctl,
632 },
633 [ ICH6_REG_WAKEEN ] = {
634 .name = "WAKEEN",
635 .size = 2,
df0db221 636 .wmask = 0x7fff,
d61a4ce8 637 .offset = offsetof(IntelHDAState, wake_en),
6a0d02f5 638 .whandler = intel_hda_set_wake_en,
d61a4ce8
GH		 639 },
640 [ ICH6_REG_STATESTS ] = {
641 .name = "STATESTS",
642 .size = 2,
df0db221
GH		 643 .wmask = 0x7fff,
644 .wclear = 0x7fff,
d61a4ce8
GH		 645 .offset = offsetof(IntelHDAState, state_sts),
646 .whandler = intel_hda_set_state_sts,
647 },
648
649 /* interrupts */
650 [ ICH6_REG_INTCTL ] = {
651 .name = "INTCTL",
652 .size = 4,
653 .wmask = 0xc00000ff,
654 .offset = offsetof(IntelHDAState, int_ctl),
655 .whandler = intel_hda_set_int_ctl,
656 },
657 [ ICH6_REG_INTSTS ] = {
658 .name = "INTSTS",
659 .size = 4,
660 .wmask = 0xc00000ff,
661 .wclear = 0xc00000ff,
662 .offset = offsetof(IntelHDAState, int_sts),
663 },
664
665 /* misc */
666 [ ICH6_REG_WALLCLK ] = {
667 .name = "WALLCLK",
668 .size = 4,
669 .offset = offsetof(IntelHDAState, wall_clk),
670 .rhandler = intel_hda_get_wall_clk,
671 },
672 [ ICH6_REG_WALLCLK + 0x2000 ] = {
673 .name = "WALLCLK(alias)",
674 .size = 4,
675 .offset = offsetof(IntelHDAState, wall_clk),
676 .rhandler = intel_hda_get_wall_clk,
677 },
678
679 /* dma engine */
680 [ ICH6_REG_CORBLBASE ] = {
681 .name = "CORBLBASE",
682 .size = 4,
683 .wmask = 0xffffff80,
684 .offset = offsetof(IntelHDAState, corb_lbase),
685 },
686 [ ICH6_REG_CORBUBASE ] = {
687 .name = "CORBUBASE",
688 .size = 4,
689 .wmask = 0xffffffff,
690 .offset = offsetof(IntelHDAState, corb_ubase),
691 },
692 [ ICH6_REG_CORBWP ] = {
693 .name = "CORBWP",
694 .size = 2,
695 .wmask = 0xff,
696 .offset = offsetof(IntelHDAState, corb_wp),
697 .whandler = intel_hda_set_corb_wp,
698 },
699 [ ICH6_REG_CORBRP ] = {
700 .name = "CORBRP",
701 .size = 2,
702 .wmask = 0x80ff,
703 .offset = offsetof(IntelHDAState, corb_rp),
704 },
705 [ ICH6_REG_CORBCTL ] = {
706 .name = "CORBCTL",
707 .size = 1,
708 .wmask = 0x03,
709 .offset = offsetof(IntelHDAState, corb_ctl),
710 .whandler = intel_hda_set_corb_ctl,
711 },
712 [ ICH6_REG_CORBSTS ] = {
713 .name = "CORBSTS",
714 .size = 1,
715 .wmask = 0x01,
716 .wclear = 0x01,
717 .offset = offsetof(IntelHDAState, corb_sts),
718 },
719 [ ICH6_REG_CORBSIZE ] = {
720 .name = "CORBSIZE",
721 .size = 1,
722 .reset = 0x42,
723 .offset = offsetof(IntelHDAState, corb_size),
724 },
725 [ ICH6_REG_RIRBLBASE ] = {
726 .name = "RIRBLBASE",
727 .size = 4,
728 .wmask = 0xffffff80,
729 .offset = offsetof(IntelHDAState, rirb_lbase),
730 },
731 [ ICH6_REG_RIRBUBASE ] = {
732 .name = "RIRBUBASE",
733 .size = 4,
734 .wmask = 0xffffffff,
735 .offset = offsetof(IntelHDAState, rirb_ubase),
736 },
737 [ ICH6_REG_RIRBWP ] = {
738 .name = "RIRBWP",
739 .size = 2,
740 .wmask = 0x8000,
741 .offset = offsetof(IntelHDAState, rirb_wp),
742 .whandler = intel_hda_set_rirb_wp,
743 },
744 [ ICH6_REG_RINTCNT ] = {
745 .name = "RINTCNT",
746 .size = 2,
747 .wmask = 0xff,
748 .offset = offsetof(IntelHDAState, rirb_cnt),
749 },
750 [ ICH6_REG_RIRBCTL ] = {
751 .name = "RIRBCTL",
752 .size = 1,
753 .wmask = 0x07,
754 .offset = offsetof(IntelHDAState, rirb_ctl),
755 },
756 [ ICH6_REG_RIRBSTS ] = {
757 .name = "RIRBSTS",
758 .size = 1,
759 .wmask = 0x05,
760 .wclear = 0x05,
761 .offset = offsetof(IntelHDAState, rirb_sts),
762 .whandler = intel_hda_set_rirb_sts,
763 },
764 [ ICH6_REG_RIRBSIZE ] = {
765 .name = "RIRBSIZE",
766 .size = 1,
767 .reset = 0x42,
768 .offset = offsetof(IntelHDAState, rirb_size),
769 },
770
771 [ ICH6_REG_DPLBASE ] = {
772 .name = "DPLBASE",
773 .size = 4,
774 .wmask = 0xffffff81,
775 .offset = offsetof(IntelHDAState, dp_lbase),
776 },
777 [ ICH6_REG_DPUBASE ] = {
778 .name = "DPUBASE",
779 .size = 4,
780 .wmask = 0xffffffff,
781 .offset = offsetof(IntelHDAState, dp_ubase),
782 },
783
784 [ ICH6_REG_IC ] = {
785 .name = "ICW",
786 .size = 4,
787 .wmask = 0xffffffff,
788 .offset = offsetof(IntelHDAState, icw),
789 },
790 [ ICH6_REG_IR ] = {
791 .name = "IRR",
792 .size = 4,
793 .offset = offsetof(IntelHDAState, irr),
794 },
795 [ ICH6_REG_IRS ] = {
796 .name = "ICS",
797 .size = 2,
798 .wmask = 0x0003,
799 .wclear = 0x0002,
800 .offset = offsetof(IntelHDAState, ics),
801 .whandler = intel_hda_set_ics,
802 },
803
804#define HDA_STREAM(_t, _i) \
805 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
806 .stream = _i, \
807 .name = _t stringify(_i) " CTL", \
808 .size = 4, \
809 .wmask = 0x1cff001f, \
810 .offset = offsetof(IntelHDAState, st[_i].ctl), \
811 .whandler = intel_hda_set_st_ctl, \
812 }, \
813 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
814 .stream = _i, \
815 .name = _t stringify(_i) " CTL(stnr)", \
816 .size = 1, \
817 .shift = 16, \
818 .wmask = 0x00ff0000, \
819 .offset = offsetof(IntelHDAState, st[_i].ctl), \
820 .whandler = intel_hda_set_st_ctl, \
821 }, \
822 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
823 .stream = _i, \
824 .name = _t stringify(_i) " CTL(sts)", \
825 .size = 1, \
826 .shift = 24, \
827 .wmask = 0x1c000000, \
828 .wclear = 0x1c000000, \
829 .offset = offsetof(IntelHDAState, st[_i].ctl), \
830 .whandler = intel_hda_set_st_ctl, \
831 }, \
832 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
833 .stream = _i, \
834 .name = _t stringify(_i) " LPIB", \
835 .size = 4, \
836 .offset = offsetof(IntelHDAState, st[_i].lpib), \
837 }, \
838 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
839 .stream = _i, \
840 .name = _t stringify(_i) " LPIB(alias)", \
841 .size = 4, \
842 .offset = offsetof(IntelHDAState, st[_i].lpib), \
843 }, \
844 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
845 .stream = _i, \
846 .name = _t stringify(_i) " CBL", \
847 .size = 4, \
848 .wmask = 0xffffffff, \
849 .offset = offsetof(IntelHDAState, st[_i].cbl), \
850 }, \
851 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
852 .stream = _i, \
853 .name = _t stringify(_i) " LVI", \
854 .size = 2, \
855 .wmask = 0x00ff, \
856 .offset = offsetof(IntelHDAState, st[_i].lvi), \
857 }, \
858 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
859 .stream = _i, \
860 .name = _t stringify(_i) " FIFOS", \
861 .size = 2, \
862 .reset = HDA_BUFFER_SIZE, \
863 }, \
864 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
865 .stream = _i, \
866 .name = _t stringify(_i) " FMT", \
867 .size = 2, \
868 .wmask = 0x7f7f, \
869 .offset = offsetof(IntelHDAState, st[_i].fmt), \
870 }, \
871 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
872 .stream = _i, \
873 .name = _t stringify(_i) " BDLPL", \
874 .size = 4, \
875 .wmask = 0xffffff80, \
876 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
877 }, \
878 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
879 .stream = _i, \
880 .name = _t stringify(_i) " BDLPU", \
881 .size = 4, \
882 .wmask = 0xffffffff, \
883 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
884 }, \
885
886 HDA_STREAM("IN", 0)
887 HDA_STREAM("IN", 1)
888 HDA_STREAM("IN", 2)
889 HDA_STREAM("IN", 3)
890
891 HDA_STREAM("OUT", 4)
892 HDA_STREAM("OUT", 5)
893 HDA_STREAM("OUT", 6)
894 HDA_STREAM("OUT", 7)
895
896};
897
a8170e5e 898static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
d61a4ce8
GH		 899{
900 const IntelHDAReg *reg;
901
902 if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
903 goto noreg;
904 }
905 reg = regtab+addr;
906 if (reg->name == NULL) {
907 goto noreg;
908 }
909 return reg;
910
911noreg:
912 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
913 return NULL;
914}
915
916static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
917{
918 uint8_t *addr = (void*)d;
919
920 addr += reg->offset;
921 return (uint32_t*)addr;
922}
923
924static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
925 uint32_t wmask)
926{
927 uint32_t *addr;
928 uint32_t old;
929
930 if (!reg) {
931 return;
932 }
933
934 if (d->debug) {
935 time_t now = time(NULL);
936 if (d->last_write && d->last_reg == reg && d->last_val == val) {
937 d->repeat_count++;
938 if (d->last_sec != now) {
939 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
940 d->last_sec = now;
941 d->repeat_count = 0;
942 }
943 } else {
944 if (d->repeat_count) {
945 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
946 }
947 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
948 d->last_write = 1;
949 d->last_reg = reg;
950 d->last_val = val;
951 d->last_sec = now;
952 d->repeat_count = 0;
953 }
954 }
955 assert(reg->offset != 0);
956
957 addr = intel_hda_reg_addr(d, reg);
958 old = *addr;
959
960 if (reg->shift) {
961 val <<= reg->shift;
962 wmask <<= reg->shift;
963 }
964 wmask &= reg->wmask;
965 *addr &= ~wmask;
966 *addr |= wmask & val;
967 *addr &= ~(val & reg->wclear);
968
969 if (reg->whandler) {
970 reg->whandler(d, reg, old);
971 }
972}
973
974static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
975 uint32_t rmask)
976{
977 uint32_t *addr, ret;
978
979 if (!reg) {
980 return 0;
981 }
982
983 if (reg->rhandler) {
984 reg->rhandler(d, reg);
985 }
986
987 if (reg->offset == 0) {
988 /* constant read-only register */
989 ret = reg->reset;
990 } else {
991 addr = intel_hda_reg_addr(d, reg);
992 ret = *addr;
993 if (reg->shift) {
994 ret >>= reg->shift;
995 }
996 ret &= rmask;
997 }
998 if (d->debug) {
999 time_t now = time(NULL);
1000 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1001 d->repeat_count++;
1002 if (d->last_sec != now) {
1003 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1004 d->last_sec = now;
1005 d->repeat_count = 0;
1006 }
1007 } else {
1008 if (d->repeat_count) {
1009 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1010 }
1011 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1012 d->last_write = 0;
1013 d->last_reg = reg;
1014 d->last_val = ret;
1015 d->last_sec = now;
1016 d->repeat_count = 0;
1017 }
1018 }
1019 return ret;
1020}
1021
1022static void intel_hda_regs_reset(IntelHDAState *d)
1023{
1024 uint32_t *addr;
1025 int i;
1026
1027 for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1028 if (regtab[i].name == NULL) {
1029 continue;
1030 }
1031 if (regtab[i].offset == 0) {
1032 continue;
1033 }
1034 addr = intel_hda_reg_addr(d, regtab + i);
1035 *addr = regtab[i].reset;
1036 }
1037}
1038
1039/* --------------------------------------------------------------------- */
1040
a8170e5e 1041static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1042{
1043 IntelHDAState *d = opaque;
1044 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1045
1046 intel_hda_reg_write(d, reg, val, 0xff);
1047}
1048
a8170e5e 1049static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1050{
1051 IntelHDAState *d = opaque;
1052 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1053
1054 intel_hda_reg_write(d, reg, val, 0xffff);
1055}
1056
a8170e5e 1057static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1058{
1059 IntelHDAState *d = opaque;
1060 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1061
1062 intel_hda_reg_write(d, reg, val, 0xffffffff);
1063}
1064
a8170e5e 1065static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
d61a4ce8
GH		 1066{
1067 IntelHDAState *d = opaque;
1068 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1069
1070 return intel_hda_reg_read(d, reg, 0xff);
1071}
1072
a8170e5e 1073static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
d61a4ce8
GH		 1074{
1075 IntelHDAState *d = opaque;
1076 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1077
1078 return intel_hda_reg_read(d, reg, 0xffff);
1079}
1080
a8170e5e 1081static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
d61a4ce8
GH		 1082{
1083 IntelHDAState *d = opaque;
1084 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1085
1086 return intel_hda_reg_read(d, reg, 0xffffffff);
1087}
1088
234bbdf1
AK		 1089static const MemoryRegionOps intel_hda_mmio_ops = {
1090 .old_mmio = {
1091 .read = {
1092 intel_hda_mmio_readb,
1093 intel_hda_mmio_readw,
1094 intel_hda_mmio_readl,
1095 },
1096 .write = {
1097 intel_hda_mmio_writeb,
1098 intel_hda_mmio_writew,
1099 intel_hda_mmio_writel,
1100 },
1101 },
1102 .endianness = DEVICE_NATIVE_ENDIAN,
d61a4ce8
GH		 1103};
1104
d61a4ce8
GH		 1105/* --------------------------------------------------------------------- */
1106
1107static void intel_hda_reset(DeviceState *dev)
1108{
0866aca1 1109 BusChild *kid;
52bb7c6a 1110 IntelHDAState *d = INTEL_HDA(dev);
d61a4ce8
GH		 1111 HDACodecDevice *cdev;
1112
1113 intel_hda_regs_reset(d);
bc72ad67 1114 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
d61a4ce8
GH		 1115
1116 /* reset codecs */
0866aca1
AL		 1117 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1118 DeviceState *qdev = kid->child;
d61a4ce8 1119 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
94afdadc 1120 device_reset(DEVICE(cdev));
d61a4ce8
GH		 1121 d->state_sts |= (1 << cdev->cad);
1122 }
1123 intel_hda_update_irq(d);
1124}
1125
1126static int intel_hda_init(PCIDevice *pci)
1127{
52bb7c6a 1128 IntelHDAState *d = INTEL_HDA(pci);
d61a4ce8
GH		 1129 uint8_t *conf = d->pci.config;
1130
f79f2bfc 1131 d->name = object_get_typename(OBJECT(d));
d61a4ce8 1132
d61a4ce8
GH		 1133 pci_config_set_interrupt_pin(conf, 1);
1134
1135 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1136 conf[0x40] = 0x01;
1137
64bde0f3 1138 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
234bbdf1 1139 "intel-hda", 0x4000);
e824b2cc 1140 pci_register_bar(&d->pci, 0, 0, &d->mmio);
17786d52
GH		 1141 if (d->msi) {
1142 msi_init(&d->pci, 0x50, 1, true, false);
1143 }
d61a4ce8 1144
ab809e84 1145 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
d61a4ce8
GH		 1146 intel_hda_response, intel_hda_xfer);
1147
1148 return 0;
1149}
1150
f90c2bcd 1151static void intel_hda_exit(PCIDevice *pci)
dc4b9240 1152{
52bb7c6a 1153 IntelHDAState *d = INTEL_HDA(pci);
dc4b9240 1154
45fe15c2 1155 msi_uninit(&d->pci);
234bbdf1 1156 memory_region_destroy(&d->mmio);
dc4b9240
GH		 1157}
1158
d61a4ce8
GH		 1159static int intel_hda_post_load(void *opaque, int version)
1160{
1161 IntelHDAState* d = opaque;
1162 int i;
1163
1164 dprint(d, 1, "%s\n", __FUNCTION__);
1165 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1166 if (d->st[i].ctl & 0x02) {
1167 intel_hda_parse_bdl(d, &d->st[i]);
1168 }
1169 }
1170 intel_hda_update_irq(d);
1171 return 0;
1172}
1173
1174static const VMStateDescription vmstate_intel_hda_stream = {
1175 .name = "intel-hda-stream",
1176 .version_id = 1,
1177 .fields = (VMStateField []) {
1178 VMSTATE_UINT32(ctl, IntelHDAStream),
1179 VMSTATE_UINT32(lpib, IntelHDAStream),
1180 VMSTATE_UINT32(cbl, IntelHDAStream),
1181 VMSTATE_UINT32(lvi, IntelHDAStream),
1182 VMSTATE_UINT32(fmt, IntelHDAStream),
1183 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1184 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1185 VMSTATE_END_OF_LIST()
1186 }
1187};
1188
1189static const VMStateDescription vmstate_intel_hda = {
1190 .name = "intel-hda",
1191 .version_id = 1,
1192 .post_load = intel_hda_post_load,
1193 .fields = (VMStateField []) {
1194 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1195
1196 /* registers */
1197 VMSTATE_UINT32(g_ctl, IntelHDAState),
1198 VMSTATE_UINT32(wake_en, IntelHDAState),
1199 VMSTATE_UINT32(state_sts, IntelHDAState),
1200 VMSTATE_UINT32(int_ctl, IntelHDAState),
1201 VMSTATE_UINT32(int_sts, IntelHDAState),
1202 VMSTATE_UINT32(wall_clk, IntelHDAState),
1203 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1204 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1205 VMSTATE_UINT32(corb_rp, IntelHDAState),
1206 VMSTATE_UINT32(corb_wp, IntelHDAState),
1207 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1208 VMSTATE_UINT32(corb_sts, IntelHDAState),
1209 VMSTATE_UINT32(corb_size, IntelHDAState),
1210 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1211 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1212 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1213 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1214 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1215 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1216 VMSTATE_UINT32(rirb_size, IntelHDAState),
1217 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1218 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1219 VMSTATE_UINT32(icw, IntelHDAState),
1220 VMSTATE_UINT32(irr, IntelHDAState),
1221 VMSTATE_UINT32(ics, IntelHDAState),
1222 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1223 vmstate_intel_hda_stream,
1224 IntelHDAStream),
1225
1226 /* additional state info */
1227 VMSTATE_UINT32(rirb_count, IntelHDAState),
1228 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1229
1230 VMSTATE_END_OF_LIST()
1231 }
1232};
1233
40021f08
AL		 1234static Property intel_hda_properties[] = {
1235 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1236 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1237 DEFINE_PROP_END_OF_LIST(),
1238};
1239
062db740 1240static void intel_hda_class_init(ObjectClass *klass, void *data)
40021f08 1241{
39bffca2 1242 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1243 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1244
1245 k->init = intel_hda_init;
1246 k->exit = intel_hda_exit;
40021f08 1247 k->vendor_id = PCI_VENDOR_ID_INTEL;
40021f08 1248 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
39bffca2
AL		 1249 dc->reset = intel_hda_reset;
1250 dc->vmsd = &vmstate_intel_hda;
1251 dc->props = intel_hda_properties;
40021f08
AL		 1252}
1253
8b07eaa1
GH		 1254static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1255{
1256 DeviceClass *dc = DEVICE_CLASS(klass);
1257 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1258
8b07eaa1
GH		 1259 k->device_id = 0x2668;
1260 k->revision = 1;
125ee0ed 1261 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
8b07eaa1
GH		 1262 dc->desc = "Intel HD Audio Controller (ich6)";
1263}
1264
1265static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1266{
1267 DeviceClass *dc = DEVICE_CLASS(klass);
1268 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1269
8b07eaa1
GH		 1270 k->device_id = 0x293e;
1271 k->revision = 3;
125ee0ed 1272 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
8b07eaa1
GH		 1273 dc->desc = "Intel HD Audio Controller (ich9)";
1274}
1275
062db740
PC		 1276static const TypeInfo intel_hda_info = {
1277 .name = TYPE_INTEL_HDA_GENERIC,
39bffca2
AL		 1278 .parent = TYPE_PCI_DEVICE,
1279 .instance_size = sizeof(IntelHDAState),
062db740
PC		 1280 .class_init = intel_hda_class_init,
1281 .abstract = true,
1282};
1283
1284static const TypeInfo intel_hda_info_ich6 = {
1285 .name = "intel-hda",
1286 .parent = TYPE_INTEL_HDA_GENERIC,
8b07eaa1
GH		 1287 .class_init = intel_hda_class_init_ich6,
1288};
1289
e2848a78 1290static const TypeInfo intel_hda_info_ich9 = {
8b07eaa1 1291 .name = "ich9-intel-hda",
062db740 1292 .parent = TYPE_INTEL_HDA_GENERIC,
8b07eaa1 1293 .class_init = intel_hda_class_init_ich9,
40021f08
AL		 1294};
1295
39bffca2
AL		 1296static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1297{
1298 DeviceClass *k = DEVICE_CLASS(klass);
1299 k->init = hda_codec_dev_init;
1300 k->exit = hda_codec_dev_exit;
125ee0ed 1301 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
0d936928 1302 k->bus_type = TYPE_HDA_BUS;
bce54474 1303 k->props = hda_props;
39bffca2
AL		 1304}
1305
8c43a6f0 1306static const TypeInfo hda_codec_device_type_info = {
40021f08
AL		 1307 .name = TYPE_HDA_CODEC_DEVICE,
1308 .parent = TYPE_DEVICE,
1309 .instance_size = sizeof(HDACodecDevice),
1310 .abstract = true,
1311 .class_size = sizeof(HDACodecDeviceClass),
39bffca2 1312 .class_init = hda_codec_device_class_init,
d61a4ce8
GH		 1313};
1314
d61a4ce8
GH		 1315/*
1316 * create intel hda controller with codec attached to it,
1317 * so '-soundhw hda' works.
1318 */
36cd6f6f 1319static int intel_hda_and_codec_init(PCIBus *bus)
d61a4ce8 1320{
52bb7c6a 1321 DeviceState *controller;
d61a4ce8
GH		 1322 BusState *hdabus;
1323 DeviceState *codec;
1324
52bb7c6a
PC		 1325 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1326 hdabus = QLIST_FIRST(&controller->child_bus);
d61a4ce8
GH		 1327 codec = qdev_create(hdabus, "hda-duplex");
1328 qdev_init_nofail(codec);
1329 return 0;
1330}
1331
36cd6f6f
PB		 1332static void intel_hda_register_types(void)
1333{
1334 type_register_static(&hda_codec_bus_info);
062db740 1335 type_register_static(&intel_hda_info);
36cd6f6f
PB		 1336 type_register_static(&intel_hda_info_ich6);
1337 type_register_static(&intel_hda_info_ich9);
1338 type_register_static(&hda_codec_device_type_info);
1339 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1340}
1341
1342type_init(intel_hda_register_types)
Empty description
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