[qemu.git] / hw / char / ipoctal232.c

/*
 * QEMU GE IP-Octal 232 IndustryPack emulation
 *
 * Copyright (C) 2012 Igalia, S.L.
 * Author: Alberto Garcia <[email protected]>
 *
 * This code is licensed under the GNU GPL v2 or (at your option) any
 * later version.
 */

#include "qemu/osdep.h"
#include "hw/ipack/ipack.h"
#include "qemu/bitops.h"
#include "qemu/module.h"
#include "chardev/char-fe.h"

/* #define DEBUG_IPOCTAL */

#ifdef DEBUG_IPOCTAL
#define DPRINTF2(fmt, ...) \
    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF2(fmt, ...) do { } while (0)
#endif

#define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)

#define RX_FIFO_SIZE 3

/* The IP-Octal has 8 channels (a-h)
   divided into 4 blocks (A-D) */
#define N_CHANNELS 8
#define N_BLOCKS   4

#define REG_MRa  0x01
#define REG_MRb  0x11
#define REG_SRa  0x03
#define REG_SRb  0x13
#define REG_CSRa 0x03
#define REG_CSRb 0x13
#define REG_CRa  0x05
#define REG_CRb  0x15
#define REG_RHRa 0x07
#define REG_RHRb 0x17
#define REG_THRa 0x07
#define REG_THRb 0x17
#define REG_ACR  0x09
#define REG_ISR  0x0B
#define REG_IMR  0x0B
#define REG_OPCR 0x1B

#define CR_ENABLE_RX    BIT(0)
#define CR_DISABLE_RX   BIT(1)
#define CR_ENABLE_TX    BIT(2)
#define CR_DISABLE_TX   BIT(3)
#define CR_CMD(cr)      ((cr) >> 4)
#define CR_NO_OP        0
#define CR_RESET_MR     1
#define CR_RESET_RX     2
#define CR_RESET_TX     3
#define CR_RESET_ERR    4
#define CR_RESET_BRKINT 5
#define CR_START_BRK    6
#define CR_STOP_BRK     7
#define CR_ASSERT_RTSN  8
#define CR_NEGATE_RTSN  9
#define CR_TIMEOUT_ON   10
#define CR_TIMEOUT_OFF  12

#define SR_RXRDY   BIT(0)
#define SR_FFULL   BIT(1)
#define SR_TXRDY   BIT(2)
#define SR_TXEMT   BIT(3)
#define SR_OVERRUN BIT(4)
#define SR_PARITY  BIT(5)
#define SR_FRAMING BIT(6)
#define SR_BREAK   BIT(7)

#define ISR_TXRDYA BIT(0)
#define ISR_RXRDYA BIT(1)
#define ISR_BREAKA BIT(2)
#define ISR_CNTRDY BIT(3)
#define ISR_TXRDYB BIT(4)
#define ISR_RXRDYB BIT(5)
#define ISR_BREAKB BIT(6)
#define ISR_MPICHG BIT(7)
#define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
#define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
#define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))

typedef struct IPOctalState IPOctalState;
typedef struct SCC2698Channel SCC2698Channel;
typedef struct SCC2698Block SCC2698Block;

struct SCC2698Channel {
    IPOctalState *ipoctal;
    CharBackend dev;
    bool rx_enabled;
    uint8_t mr[2];
    uint8_t mr_idx;
    uint8_t sr;
    uint8_t rhr[RX_FIFO_SIZE];
    uint8_t rhr_idx;
    uint8_t rx_pending;
};

struct SCC2698Block {
    uint8_t imr;
    uint8_t isr;
};

struct IPOctalState {
    IPackDevice parent_obj;

    SCC2698Channel ch[N_CHANNELS];
    SCC2698Block blk[N_BLOCKS];
    uint8_t irq_vector;
};

#define TYPE_IPOCTAL "ipoctal232"

#define IPOCTAL(obj) \
    OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)

static const VMStateDescription vmstate_scc2698_channel = {
    .name = "scc2698_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_BOOL(rx_enabled, SCC2698Channel),
        VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
        VMSTATE_UINT8(mr_idx, SCC2698Channel),
        VMSTATE_UINT8(sr, SCC2698Channel),
        VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
        VMSTATE_UINT8(rhr_idx, SCC2698Channel),
        VMSTATE_UINT8(rx_pending, SCC2698Channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_scc2698_block = {
    .name = "scc2698_block",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(imr, SCC2698Block),
        VMSTATE_UINT8(isr, SCC2698Block),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ipoctal = {
    .name = "ipoctal232",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
        VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
                             vmstate_scc2698_channel, SCC2698Channel),
        VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
                             vmstate_scc2698_block, SCC2698Block),
        VMSTATE_UINT8(irq_vector, IPOctalState),
        VMSTATE_END_OF_LIST()
    }
};

/* data[10] is 0x0C, not 0x0B as the doc says */
static const uint8_t id_prom_data[] = {
    0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
    0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
};

static void update_irq(IPOctalState *dev, unsigned block)
{
    IPackDevice *idev = IPACK_DEVICE(dev);
    /* Blocks A and B interrupt on INT0#, C and D on INT1#.
       Thus, to get the status we have to check two blocks. */
    SCC2698Block *blk0 = &dev->blk[block];
    SCC2698Block *blk1 = &dev->blk[block^1];
    unsigned intno = block / 2;

    if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
        qemu_irq_raise(idev->irq[intno]);
    } else {
        qemu_irq_lower(idev->irq[intno]);
    }
}

static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
{
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[channel / 2];

    DPRINTF("Write CR%c %u: ", channel + 'a', val);

    /* The lower 4 bits are used to enable and disable Tx and Rx */
    if (val & CR_ENABLE_RX) {
        DPRINTF2("Rx on, ");
        ch->rx_enabled = true;
    }
    if (val & CR_DISABLE_RX) {
        DPRINTF2("Rx off, ");
        ch->rx_enabled = false;
    }
    if (val & CR_ENABLE_TX) {
        DPRINTF2("Tx on, ");
        ch->sr |= SR_TXRDY | SR_TXEMT;
        blk->isr |= ISR_TXRDY(channel);
    }
    if (val & CR_DISABLE_TX) {
        DPRINTF2("Tx off, ");
        ch->sr &= ~(SR_TXRDY | SR_TXEMT);
        blk->isr &= ~ISR_TXRDY(channel);
    }

    DPRINTF2("cmd: ");

    /* The rest of the bits implement different commands */
    switch (CR_CMD(val)) {
    case CR_NO_OP:
        DPRINTF2("none");
        break;
    case CR_RESET_MR:
        DPRINTF2("reset MR");
        ch->mr_idx = 0;
        break;
    case CR_RESET_RX:
        DPRINTF2("reset Rx");
        ch->rx_enabled = false;
        ch->rx_pending = 0;
        ch->sr &= ~SR_RXRDY;
        blk->isr &= ~ISR_RXRDY(channel);
        break;
    case CR_RESET_TX:
        DPRINTF2("reset Tx");
        ch->sr &= ~(SR_TXRDY | SR_TXEMT);
        blk->isr &= ~ISR_TXRDY(channel);
        break;
    case CR_RESET_ERR:
        DPRINTF2("reset err");
        ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK);
        break;
    case CR_RESET_BRKINT:
        DPRINTF2("reset brk ch int");
        blk->isr &= ~(ISR_BREAKA | ISR_BREAKB);
        break;
    default:
        DPRINTF2("unsupported 0x%x", CR_CMD(val));
    }

    DPRINTF2("\n");
}

static uint16_t io_read(IPackDevice *ip, uint8_t addr)
{
    IPOctalState *dev = IPOCTAL(ip);
    uint16_t ret = 0;
    /* addr[7:6]: block   (A-D)
       addr[7:5]: channel (a-h)
       addr[5:0]: register */
    unsigned block = addr >> 5;
    unsigned channel = addr >> 4;
    /* Big endian, accessed using 8-bit bytes at odd locations */
    unsigned offset = (addr & 0x1F) ^ 1;
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[block];
    uint8_t old_isr = blk->isr;

    switch (offset) {

    case REG_MRa:
    case REG_MRb:
        ret = ch->mr[ch->mr_idx];
        DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
        ch->mr_idx = 1;
        break;

    case REG_SRa:
    case REG_SRb:
        ret = ch->sr;
        DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
        break;

    case REG_RHRa:
    case REG_RHRb:
        ret = ch->rhr[ch->rhr_idx];
        if (ch->rx_pending > 0) {
            ch->rx_pending--;
            if (ch->rx_pending == 0) {
                ch->sr &= ~SR_RXRDY;
                blk->isr &= ~ISR_RXRDY(channel);
                qemu_chr_fe_accept_input(&ch->dev);
            } else {
                ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
            }
            if (ch->sr & SR_BREAK) {
                ch->sr &= ~SR_BREAK;
                blk->isr |= ISR_BREAK(channel);
            }
        }
        DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
        break;

    case REG_ISR:
        ret = blk->isr;
        DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
        break;

    default:
        DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
    }

    if (old_isr != blk->isr) {
        update_irq(dev, block);
    }

    return ret;
}

static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    unsigned reg = val & 0xFF;
    /* addr[7:6]: block   (A-D)
       addr[7:5]: channel (a-h)
       addr[5:0]: register */
    unsigned block = addr >> 5;
    unsigned channel = addr >> 4;
    /* Big endian, accessed using 8-bit bytes at odd locations */
    unsigned offset = (addr & 0x1F) ^ 1;
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[block];
    uint8_t old_isr = blk->isr;
    uint8_t old_imr = blk->imr;

    switch (offset) {

    case REG_MRa:
    case REG_MRb:
        ch->mr[ch->mr_idx] = reg;
        DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
        ch->mr_idx = 1;
        break;

    /* Not implemented */
    case REG_CSRa:
    case REG_CSRb:
        DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
        break;

    case REG_CRa:
    case REG_CRb:
        write_cr(dev, channel, reg);
        break;

    case REG_THRa:
    case REG_THRb:
        if (ch->sr & SR_TXRDY) {
            uint8_t thr = reg;
            DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&ch->dev, &thr, 1);
        } else {
            DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
        }
        break;

    /* Not implemented */
    case REG_ACR:
        DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
        break;

    case REG_IMR:
        DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
        blk->imr = reg;
        break;

    /* Not implemented */
    case REG_OPCR:
        DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
        break;

    default:
        DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
    }

    if (old_isr != blk->isr || old_imr != blk->imr) {
        update_irq(dev, block);
    }
}

static uint16_t id_read(IPackDevice *ip, uint8_t addr)
{
    uint16_t ret = 0;
    unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */

    if (pos < ARRAY_SIZE(id_prom_data)) {
        ret = id_prom_data[pos];
    } else {
        DPRINTF("Attempt to read unavailable PROM data at 0x%x\n",  addr);
    }

    return ret;
}

static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    if (addr == 1) {
        DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
        dev->irq_vector = val; /* Undocumented, but the hw works like that */
    } else {
        DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
    }
}

static uint16_t int_read(IPackDevice *ip, uint8_t addr)
{
    IPOctalState *dev = IPOCTAL(ip);
    /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
    if (addr != 0 && addr != 2) {
        DPRINTF("Attempt to read from 0x%x\n", addr);
        return 0;
    } else {
        /* Update interrupts if necessary */
        update_irq(dev, addr);
        return dev->irq_vector;
    }
}

static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
}

static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
{
    DPRINTF("Attempt to read from 0x%x\n", addr);
    return 0;
}

static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
{
    DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
}

static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
{
    DPRINTF("Attempt to read from 0x%x\n", addr);
    return 0;
}

static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    if (addr == 1) {
        DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
        dev->irq_vector = val;
    } else {
        DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
    }
}

static int hostdev_can_receive(void *opaque)
{
    SCC2698Channel *ch = opaque;
    int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
    return ch->rx_enabled ? available_bytes : 0;
}

static void hostdev_receive(void *opaque, const uint8_t *buf, int size)
{
    SCC2698Channel *ch = opaque;
    IPOctalState *dev = ch->ipoctal;
    unsigned pos = ch->rhr_idx + ch->rx_pending;
    int i;

    assert(size + ch->rx_pending <= RX_FIFO_SIZE);

    /* Copy data to the RxFIFO */
    for (i = 0; i < size; i++) {
        pos %= RX_FIFO_SIZE;
        ch->rhr[pos++] = buf[i];
    }

    ch->rx_pending += size;

    /* If the RxFIFO was empty raise an interrupt */
    if (!(ch->sr & SR_RXRDY)) {
        unsigned block, channel = 0;
        /* Find channel number to update the ISR register */
        while (&dev->ch[channel] != ch) {
            channel++;
        }
        block = channel / 2;
        dev->blk[block].isr |= ISR_RXRDY(channel);
        ch->sr |= SR_RXRDY;
        update_irq(dev, block);
    }
}

static void hostdev_event(void *opaque, int event)
{
    SCC2698Channel *ch = opaque;
    switch (event) {
    case CHR_EVENT_OPENED:
        DPRINTF("Device %s opened\n", ch->dev->label);
        break;
    case CHR_EVENT_BREAK: {
        uint8_t zero = 0;
        DPRINTF("Device %s received break\n", ch->dev->label);

        if (!(ch->sr & SR_BREAK)) {
            IPOctalState *dev = ch->ipoctal;
            unsigned block, channel = 0;

            while (&dev->ch[channel] != ch) {
                channel++;
            }
            block = channel / 2;

            ch->sr |= SR_BREAK;
            dev->blk[block].isr |= ISR_BREAK(channel);
        }

        /* Put a zero character in the buffer */
        hostdev_receive(ch, &zero, 1);
    }
        break;
    default:
        DPRINTF("Device %s received event %d\n", ch->dev->label, event);
    }
}

static void ipoctal_realize(DeviceState *dev, Error **errp)
{
    IPOctalState *s = IPOCTAL(dev);
    unsigned i;

    for (i = 0; i < N_CHANNELS; i++) {
        SCC2698Channel *ch = &s->ch[i];
        ch->ipoctal = s;

        /* Redirect IP-Octal channels to host character devices */
        if (qemu_chr_fe_backend_connected(&ch->dev)) {
            qemu_chr_fe_set_handlers(&ch->dev, hostdev_can_receive,
                                     hostdev_receive, hostdev_event,
                                     NULL, ch, NULL, true);
            DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
        } else {
            DPRINTF("Could not redirect channel %u, no chardev set\n", i);
        }
    }
}

static Property ipoctal_properties[] = {
    DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
    DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
    DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
    DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
    DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
    DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
    DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
    DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
    DEFINE_PROP_END_OF_LIST(),
};

static void ipoctal_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);

    ic->realize     = ipoctal_realize;
    ic->io_read     = io_read;
    ic->io_write    = io_write;
    ic->id_read     = id_read;
    ic->id_write    = id_write;
    ic->int_read    = int_read;
    ic->int_write   = int_write;
    ic->mem_read16  = mem_read16;
    ic->mem_write16 = mem_write16;
    ic->mem_read8   = mem_read8;
    ic->mem_write8  = mem_write8;

    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
    dc->desc    = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
    dc->props   = ipoctal_properties;
    dc->vmsd    = &vmstate_ipoctal;
}

static const TypeInfo ipoctal_info = {
    .name          = TYPE_IPOCTAL,
    .parent        = TYPE_IPACK_DEVICE,
    .instance_size = sizeof(IPOctalState),
    .class_init    = ipoctal_class_init,
};

static void ipoctal_register_types(void)
{
    type_register_static(&ipoctal_info);
}

type_init(ipoctal_register_types)
Commit	Line	Data
be657dea AG	1	/*
	2	* QEMU GE IP-Octal 232 IndustryPack emulation
	3	*
	4	* Copyright (C) 2012 Igalia, S.L.
b996aed5	5	* Author: Alberto Garcia <[email protected]>
be657dea AG	6	*
	7	* This code is licensed under the GNU GPL v2 or (at your option) any
	8	* later version.
	9	*/
	10
0430891c	11	#include "qemu/osdep.h"
1f9c4cfd	12	#include "hw/ipack/ipack.h"
be657dea	13	#include "qemu/bitops.h"
0b8fa32f	14	#include "qemu/module.h"
4d43a603	15	#include "chardev/char-fe.h"
be657dea AG	16
	17	/* #define DEBUG_IPOCTAL */
	18
	19	#ifdef DEBUG_IPOCTAL
	20	#define DPRINTF2(fmt, ...) \
	21	do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
	22	#else
	23	#define DPRINTF2(fmt, ...) do { } while (0)
	24	#endif
	25
	26	#define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
	27
	28	#define RX_FIFO_SIZE 3
	29
	30	/* The IP-Octal has 8 channels (a-h)
	31	divided into 4 blocks (A-D) */
	32	#define N_CHANNELS 8
	33	#define N_BLOCKS 4
	34
	35	#define REG_MRa 0x01
	36	#define REG_MRb 0x11
	37	#define REG_SRa 0x03
	38	#define REG_SRb 0x13
	39	#define REG_CSRa 0x03
	40	#define REG_CSRb 0x13
	41	#define REG_CRa 0x05
	42	#define REG_CRb 0x15
	43	#define REG_RHRa 0x07
	44	#define REG_RHRb 0x17
	45	#define REG_THRa 0x07
	46	#define REG_THRb 0x17
	47	#define REG_ACR 0x09
	48	#define REG_ISR 0x0B
	49	#define REG_IMR 0x0B
	50	#define REG_OPCR 0x1B
	51
	52	#define CR_ENABLE_RX BIT(0)
	53	#define CR_DISABLE_RX BIT(1)
	54	#define CR_ENABLE_TX BIT(2)
	55	#define CR_DISABLE_TX BIT(3)
	56	#define CR_CMD(cr) ((cr) >> 4)
	57	#define CR_NO_OP 0
	58	#define CR_RESET_MR 1
	59	#define CR_RESET_RX 2
	60	#define CR_RESET_TX 3
	61	#define CR_RESET_ERR 4
	62	#define CR_RESET_BRKINT 5
	63	#define CR_START_BRK 6
	64	#define CR_STOP_BRK 7
	65	#define CR_ASSERT_RTSN 8
	66	#define CR_NEGATE_RTSN 9
	67	#define CR_TIMEOUT_ON 10
	68	#define CR_TIMEOUT_OFF 12
	69
	70	#define SR_RXRDY BIT(0)
	71	#define SR_FFULL BIT(1)
	72	#define SR_TXRDY BIT(2)
	73	#define SR_TXEMT BIT(3)
	74	#define SR_OVERRUN BIT(4)
	75	#define SR_PARITY BIT(5)
	76	#define SR_FRAMING BIT(6)
	77	#define SR_BREAK BIT(7)
	78
	79	#define ISR_TXRDYA BIT(0)
80	#define ISR_RXRDYA BIT(1)
81	#define ISR_BREAKA BIT(2)
82	#define ISR_CNTRDY BIT(3)
83	#define ISR_TXRDYB BIT(4)
84	#define ISR_RXRDYB BIT(5)
85	#define ISR_BREAKB BIT(6)
86	#define ISR_MPICHG BIT(7)
87	#define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
88	#define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
89	#define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))
90
91	typedef struct IPOctalState IPOctalState;
92	typedef struct SCC2698Channel SCC2698Channel;
93	typedef struct SCC2698Block SCC2698Block;
94
95	struct SCC2698Channel {
96	IPOctalState *ipoctal;
becdfa00	97	CharBackend dev;
be657dea AG	98	bool rx_enabled;
	99	uint8_t mr[2];
	100	uint8_t mr_idx;
	101	uint8_t sr;
	102	uint8_t rhr[RX_FIFO_SIZE];
	103	uint8_t rhr_idx;
	104	uint8_t rx_pending;
	105	};
	106
	107	struct SCC2698Block {
	108	uint8_t imr;
	109	uint8_t isr;
	110	};
	111
	112	struct IPOctalState {
08c9cacf AF	113	IPackDevice parent_obj;
08c9cacf AF	114
be657dea AG	115	SCC2698Channel ch[N_CHANNELS];
	116	SCC2698Block blk[N_BLOCKS];
	117	uint8_t irq_vector;
	118	};
	119
	120	#define TYPE_IPOCTAL "ipoctal232"
	121
	122	#define IPOCTAL(obj) \
	123	OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)
	124
	125	static const VMStateDescription vmstate_scc2698_channel = {
	126	.name = "scc2698_channel",
	127	.version_id = 1,
	128	.minimum_version_id = 1,
35d08458	129	.fields = (VMStateField[]) {
be657dea AG	130	VMSTATE_BOOL(rx_enabled, SCC2698Channel),
	131	VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
	132	VMSTATE_UINT8(mr_idx, SCC2698Channel),
	133	VMSTATE_UINT8(sr, SCC2698Channel),
	134	VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
	135	VMSTATE_UINT8(rhr_idx, SCC2698Channel),
	136	VMSTATE_UINT8(rx_pending, SCC2698Channel),
	137	VMSTATE_END_OF_LIST()
	138	}
	139	};
	140
	141	static const VMStateDescription vmstate_scc2698_block = {
	142	.name = "scc2698_block",
	143	.version_id = 1,
	144	.minimum_version_id = 1,
35d08458	145	.fields = (VMStateField[]) {
be657dea AG	146	VMSTATE_UINT8(imr, SCC2698Block),
	147	VMSTATE_UINT8(isr, SCC2698Block),
	148	VMSTATE_END_OF_LIST()
	149	}
	150	};
	151
	152	static const VMStateDescription vmstate_ipoctal = {
	153	.name = "ipoctal232",
	154	.version_id = 1,
	155	.minimum_version_id = 1,
35d08458	156	.fields = (VMStateField[]) {
08c9cacf	157	VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
be657dea AG	158	VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
	159	vmstate_scc2698_channel, SCC2698Channel),
	160	VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
	161	vmstate_scc2698_block, SCC2698Block),
	162	VMSTATE_UINT8(irq_vector, IPOctalState),
	163	VMSTATE_END_OF_LIST()
	164	}
	165	};
	166
	167	/* data[10] is 0x0C, not 0x0B as the doc says */
	168	static const uint8_t id_prom_data[] = {
	169	0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
	170	0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
	171	};
	172
	173	static void update_irq(IPOctalState *dev, unsigned block)
	174	{
08c9cacf	175	IPackDevice *idev = IPACK_DEVICE(dev);
be657dea AG	176	/* Blocks A and B interrupt on INT0#, C and D on INT1#.
	177	Thus, to get the status we have to check two blocks. */
	178	SCC2698Block *blk0 = &dev->blk[block];
	179	SCC2698Block *blk1 = &dev->blk[block^1];
	180	unsigned intno = block / 2;
	181
	182	if ((blk0->isr & blk0->imr) \|\| (blk1->isr & blk1->imr)) {
08c9cacf	183	qemu_irq_raise(idev->irq[intno]);
be657dea	184	} else {
08c9cacf	185	qemu_irq_lower(idev->irq[intno]);
be657dea AG	186	}
	187	}
	188
	189	static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
	190	{
	191	SCC2698Channel *ch = &dev->ch[channel];
	192	SCC2698Block *blk = &dev->blk[channel / 2];
	193
	194	DPRINTF("Write CR%c %u: ", channel + 'a', val);
	195
	196	/* The lower 4 bits are used to enable and disable Tx and Rx */
	197	if (val & CR_ENABLE_RX) {
	198	DPRINTF2("Rx on, ");
	199	ch->rx_enabled = true;
	200	}
	201	if (val & CR_DISABLE_RX) {
	202	DPRINTF2("Rx off, ");
	203	ch->rx_enabled = false;
	204	}
	205	if (val & CR_ENABLE_TX) {
	206	DPRINTF2("Tx on, ");
	207	ch->sr \|= SR_TXRDY \| SR_TXEMT;
	208	blk->isr \|= ISR_TXRDY(channel);
	209	}
	210	if (val & CR_DISABLE_TX) {
	211	DPRINTF2("Tx off, ");
	212	ch->sr &= ~(SR_TXRDY \| SR_TXEMT);
	213	blk->isr &= ~ISR_TXRDY(channel);
	214	}
	215
	216	DPRINTF2("cmd: ");
	217
	218	/* The rest of the bits implement different commands */
	219	switch (CR_CMD(val)) {
	220	case CR_NO_OP:
	221	DPRINTF2("none");
	222	break;
	223	case CR_RESET_MR:
	224	DPRINTF2("reset MR");
	225	ch->mr_idx = 0;
	226	break;
	227	case CR_RESET_RX:
	228	DPRINTF2("reset Rx");
	229	ch->rx_enabled = false;
	230	ch->rx_pending = 0;
	231	ch->sr &= ~SR_RXRDY;
	232	blk->isr &= ~ISR_RXRDY(channel);
	233	break;
	234	case CR_RESET_TX:
	235	DPRINTF2("reset Tx");
	236	ch->sr &= ~(SR_TXRDY \| SR_TXEMT);
	237	blk->isr &= ~ISR_TXRDY(channel);
	238	break;
	239	case CR_RESET_ERR:
	240	DPRINTF2("reset err");
	241	ch->sr &= ~(SR_OVERRUN \| SR_PARITY \| SR_FRAMING \| SR_BREAK);
	242	break;
	243	case CR_RESET_BRKINT:
	244	DPRINTF2("reset brk ch int");
	245	blk->isr &= ~(ISR_BREAKA \| ISR_BREAKB);
	246	break;
	247	default:
	248	DPRINTF2("unsupported 0x%x", CR_CMD(val));
	249	}
250
251	DPRINTF2("\n");
252	}
253
254	static uint16_t io_read(IPackDevice *ip, uint8_t addr)
255	{
256	IPOctalState *dev = IPOCTAL(ip);
257	uint16_t ret = 0;
258	/* addr[7:6]: block (A-D)
259	addr[7:5]: channel (a-h)
260	addr[5:0]: register */
261	unsigned block = addr >> 5;
262	unsigned channel = addr >> 4;
263	/* Big endian, accessed using 8-bit bytes at odd locations */
264	unsigned offset = (addr & 0x1F) ^ 1;
265	SCC2698Channel *ch = &dev->ch[channel];
266	SCC2698Block *blk = &dev->blk[block];
267	uint8_t old_isr = blk->isr;
268
269	switch (offset) {
270
271	case REG_MRa:
272	case REG_MRb:
273	ret = ch->mr[ch->mr_idx];
274	DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
275	ch->mr_idx = 1;
276	break;
277
278	case REG_SRa:
279	case REG_SRb:
280	ret = ch->sr;
281	DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
282	break;
283
284	case REG_RHRa:
285	case REG_RHRb:
286	ret = ch->rhr[ch->rhr_idx];
287	if (ch->rx_pending > 0) {
288	ch->rx_pending--;
289	if (ch->rx_pending == 0) {
290	ch->sr &= ~SR_RXRDY;
291	blk->isr &= ~ISR_RXRDY(channel);
fa394ed6	292	qemu_chr_fe_accept_input(&ch->dev);
be657dea AG	293	} else {
	294	ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
	295	}
	296	if (ch->sr & SR_BREAK) {
	297	ch->sr &= ~SR_BREAK;
	298	blk->isr \|= ISR_BREAK(channel);
	299	}
	300	}
	301	DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
	302	break;
	303
	304	case REG_ISR:
	305	ret = blk->isr;
	306	DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
	307	break;
	308
	309	default:
	310	DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
	311	}
	312
	313	if (old_isr != blk->isr) {
	314	update_irq(dev, block);
	315	}
	316
	317	return ret;
	318	}
	319
	320	static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
	321	{
	322	IPOctalState *dev = IPOCTAL(ip);
	323	unsigned reg = val & 0xFF;
	324	/* addr[7:6]: block (A-D)
	325	addr[7:5]: channel (a-h)
	326	addr[5:0]: register */
	327	unsigned block = addr >> 5;
	328	unsigned channel = addr >> 4;
	329	/* Big endian, accessed using 8-bit bytes at odd locations */
	330	unsigned offset = (addr & 0x1F) ^ 1;
	331	SCC2698Channel *ch = &dev->ch[channel];
	332	SCC2698Block *blk = &dev->blk[block];
	333	uint8_t old_isr = blk->isr;
	334	uint8_t old_imr = blk->imr;
	335
	336	switch (offset) {
	337
	338	case REG_MRa:
	339	case REG_MRb:
	340	ch->mr[ch->mr_idx] = reg;
	341	DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
	342	ch->mr_idx = 1;
	343	break;
	344
	345	/* Not implemented */
	346	case REG_CSRa:
	347	case REG_CSRb:
	348	DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
	349	break;
	350
	351	case REG_CRa:
	352	case REG_CRb:
	353	write_cr(dev, channel, reg);
	354	break;
	355
	356	case REG_THRa:
357	case REG_THRb:
358	if (ch->sr & SR_TXRDY) {
fa394ed6	359	uint8_t thr = reg;
be657dea	360	DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
fa394ed6 MAL	361	/* XXX this blocks entire thread. Rewrite to use
	362	* qemu_chr_fe_write and background I/O callbacks */
	363	qemu_chr_fe_write_all(&ch->dev, &thr, 1);
be657dea AG	364	} else {
	365	DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
	366	}
	367	break;
	368
	369	/* Not implemented */
	370	case REG_ACR:
	371	DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
	372	break;
	373
	374	case REG_IMR:
	375	DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
	376	blk->imr = reg;
	377	break;
	378
	379	/* Not implemented */
	380	case REG_OPCR:
	381	DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
	382	break;
	383
	384	default:
	385	DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
	386	}
	387
	388	if (old_isr != blk->isr \|\| old_imr != blk->imr) {
	389	update_irq(dev, block);
	390	}
	391	}
	392
	393	static uint16_t id_read(IPackDevice *ip, uint8_t addr)
	394	{
	395	uint16_t ret = 0;
	396	unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */
	397
	398	if (pos < ARRAY_SIZE(id_prom_data)) {
	399	ret = id_prom_data[pos];
	400	} else {
	401	DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr);
	402	}
	403
	404	return ret;
	405	}
	406
	407	static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
	408	{
	409	IPOctalState *dev = IPOCTAL(ip);
	410	if (addr == 1) {
	411	DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
	412	dev->irq_vector = val; /* Undocumented, but the hw works like that */
	413	} else {
	414	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
	415	}
	416	}
	417
	418	static uint16_t int_read(IPackDevice *ip, uint8_t addr)
	419	{
	420	IPOctalState *dev = IPOCTAL(ip);
	421	/* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
	422	if (addr != 0 && addr != 2) {
	423	DPRINTF("Attempt to read from 0x%x\n", addr);
	424	return 0;
	425	} else {
	426	/* Update interrupts if necessary */
	427	update_irq(dev, addr);
428	return dev->irq_vector;
429	}
430	}
431
432	static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
433	{
434	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
435	}
436
437	static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
438	{
439	DPRINTF("Attempt to read from 0x%x\n", addr);
440	return 0;
441	}
442
443	static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
444	{
445	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
446	}
447
448	static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
449	{
450	DPRINTF("Attempt to read from 0x%x\n", addr);
451	return 0;
452	}
453
454	static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
455	{
456	IPOctalState *dev = IPOCTAL(ip);
457	if (addr == 1) {
458	DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
459	dev->irq_vector = val;
460	} else {
461	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
462	}
463	}
464
465	static int hostdev_can_receive(void *opaque)
466	{
467	SCC2698Channel *ch = opaque;
468	int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
469	return ch->rx_enabled ? available_bytes : 0;
470	}
471
472	static void hostdev_receive(void opaque, const uint8_t buf, int size)
473	{
474	SCC2698Channel *ch = opaque;
475	IPOctalState *dev = ch->ipoctal;
476	unsigned pos = ch->rhr_idx + ch->rx_pending;
477	int i;
478
479	assert(size + ch->rx_pending <= RX_FIFO_SIZE);
480
481	/* Copy data to the RxFIFO */
482	for (i = 0; i < size; i++) {
483	pos %= RX_FIFO_SIZE;
484	ch->rhr[pos++] = buf[i];
485	}
486
487	ch->rx_pending += size;
488
489	/* If the RxFIFO was empty raise an interrupt */
490	if (!(ch->sr & SR_RXRDY)) {
491	unsigned block, channel = 0;
492	/* Find channel number to update the ISR register */
493	while (&dev->ch[channel] != ch) {
494	channel++;
495	}
496	block = channel / 2;
497	dev->blk[block].isr \|= ISR_RXRDY(channel);
498	ch->sr \|= SR_RXRDY;
499	update_irq(dev, block);
500	}
501	}
502
503	static void hostdev_event(void *opaque, int event)
504	{
505	SCC2698Channel *ch = opaque;
506	switch (event) {
507	case CHR_EVENT_OPENED:
508	DPRINTF("Device %s opened\n", ch->dev->label);
509	break;
510	case CHR_EVENT_BREAK: {
511	uint8_t zero = 0;
512	DPRINTF("Device %s received break\n", ch->dev->label);
513
514	if (!(ch->sr & SR_BREAK)) {
515	IPOctalState *dev = ch->ipoctal;
516	unsigned block, channel = 0;
517
518	while (&dev->ch[channel] != ch) {
519	channel++;
520	}
521	block = channel / 2;
522
523	ch->sr \|= SR_BREAK;
524	dev->blk[block].isr \|= ISR_BREAK(channel);
525	}
526
527	/* Put a zero character in the buffer */
528	hostdev_receive(ch, &zero, 1);
529	}
530	break;
531	default:
532	DPRINTF("Device %s received event %d\n", ch->dev->label, event);
533	}
534	}
535
5c570902	536	static void ipoctal_realize(DeviceState dev, Error *errp)
be657dea	537	{
5c570902	538	IPOctalState *s = IPOCTAL(dev);
be657dea AG	539	unsigned i;
	540
	541	for (i = 0; i < N_CHANNELS; i++) {
	542	SCC2698Channel *ch = &s->ch[i];
	543	ch->ipoctal = s;
	544
	545	/* Redirect IP-Octal channels to host character devices */
30650701	546	if (qemu_chr_fe_backend_connected(&ch->dev)) {
5345fdb4	547	qemu_chr_fe_set_handlers(&ch->dev, hostdev_can_receive,
39ab61c6	548	hostdev_receive, hostdev_event,
81517ba3	549	NULL, ch, NULL, true);
b9936159 HG	550	DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
	551	} else {
	552	DPRINTF("Could not redirect channel %u, no chardev set\n", i);
be657dea AG	553	}
be657dea AG	554	}
be657dea AG	555	}
	556
	557	static Property ipoctal_properties[] = {
b9936159 HG	558	DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
	559	DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
	560	DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
	561	DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
	562	DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
	563	DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
	564	DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
	565	DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
be657dea AG	566	DEFINE_PROP_END_OF_LIST(),
	567	};
	568
	569	static void ipoctal_class_init(ObjectClass klass, void data)
	570	{
	571	DeviceClass *dc = DEVICE_CLASS(klass);
	572	IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);
	573
5c570902	574	ic->realize = ipoctal_realize;
be657dea AG	575	ic->io_read = io_read;
	576	ic->io_write = io_write;
	577	ic->id_read = id_read;
	578	ic->id_write = id_write;
	579	ic->int_read = int_read;
	580	ic->int_write = int_write;
	581	ic->mem_read16 = mem_read16;
	582	ic->mem_write16 = mem_write16;
	583	ic->mem_read8 = mem_read8;
	584	ic->mem_write8 = mem_write8;
	585
125ee0ed	586	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
be657dea AG	587	dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
	588	dc->props = ipoctal_properties;
	589	dc->vmsd = &vmstate_ipoctal;
	590	}
	591
	592	static const TypeInfo ipoctal_info = {
	593	.name = TYPE_IPOCTAL,
	594	.parent = TYPE_IPACK_DEVICE,
	595	.instance_size = sizeof(IPOctalState),
	596	.class_init = ipoctal_class_init,
	597	};
	598
	599	static void ipoctal_register_types(void)
	600	{
	601	type_register_static(&ipoctal_info);
	602	}
	603
	604	type_init(ipoctal_register_types)