[qemu.git] / hw / char / ipoctal232.c

/*
 * QEMU GE IP-Octal 232 IndustryPack emulation
 *
 * Copyright (C) 2012 Igalia, S.L.
 * Author: Alberto Garcia <[email protected]>
 *
 * This code is licensed under the GNU GPL v2 or (at your option) any
 * later version.
 */

#include "qemu/osdep.h"
#include "hw/ipack/ipack.h"
#include "qemu/bitops.h"
#include "sysemu/char.h"

/* #define DEBUG_IPOCTAL */

#ifdef DEBUG_IPOCTAL
#define DPRINTF2(fmt, ...) \
    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF2(fmt, ...) do { } while (0)
#endif

#define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)

#define RX_FIFO_SIZE 3

/* The IP-Octal has 8 channels (a-h)
   divided into 4 blocks (A-D) */
#define N_CHANNELS 8
#define N_BLOCKS   4

#define REG_MRa  0x01
#define REG_MRb  0x11
#define REG_SRa  0x03
#define REG_SRb  0x13
#define REG_CSRa 0x03
#define REG_CSRb 0x13
#define REG_CRa  0x05
#define REG_CRb  0x15
#define REG_RHRa 0x07
#define REG_RHRb 0x17
#define REG_THRa 0x07
#define REG_THRb 0x17
#define REG_ACR  0x09
#define REG_ISR  0x0B
#define REG_IMR  0x0B
#define REG_OPCR 0x1B

#define CR_ENABLE_RX    BIT(0)
#define CR_DISABLE_RX   BIT(1)
#define CR_ENABLE_TX    BIT(2)
#define CR_DISABLE_TX   BIT(3)
#define CR_CMD(cr)      ((cr) >> 4)
#define CR_NO_OP        0
#define CR_RESET_MR     1
#define CR_RESET_RX     2
#define CR_RESET_TX     3
#define CR_RESET_ERR    4
#define CR_RESET_BRKINT 5
#define CR_START_BRK    6
#define CR_STOP_BRK     7
#define CR_ASSERT_RTSN  8
#define CR_NEGATE_RTSN  9
#define CR_TIMEOUT_ON   10
#define CR_TIMEOUT_OFF  12

#define SR_RXRDY   BIT(0)
#define SR_FFULL   BIT(1)
#define SR_TXRDY   BIT(2)
#define SR_TXEMT   BIT(3)
#define SR_OVERRUN BIT(4)
#define SR_PARITY  BIT(5)
#define SR_FRAMING BIT(6)
#define SR_BREAK   BIT(7)

#define ISR_TXRDYA BIT(0)
#define ISR_RXRDYA BIT(1)
#define ISR_BREAKA BIT(2)
#define ISR_CNTRDY BIT(3)
#define ISR_TXRDYB BIT(4)
#define ISR_RXRDYB BIT(5)
#define ISR_BREAKB BIT(6)
#define ISR_MPICHG BIT(7)
#define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
#define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
#define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))

typedef struct IPOctalState IPOctalState;
typedef struct SCC2698Channel SCC2698Channel;
typedef struct SCC2698Block SCC2698Block;

struct SCC2698Channel {
    IPOctalState *ipoctal;
    CharBackend dev;
    bool rx_enabled;
    uint8_t mr[2];
    uint8_t mr_idx;
    uint8_t sr;
    uint8_t rhr[RX_FIFO_SIZE];
    uint8_t rhr_idx;
    uint8_t rx_pending;
};

struct SCC2698Block {
    uint8_t imr;
    uint8_t isr;
};

struct IPOctalState {
    IPackDevice parent_obj;

    SCC2698Channel ch[N_CHANNELS];
    SCC2698Block blk[N_BLOCKS];
    uint8_t irq_vector;
};

#define TYPE_IPOCTAL "ipoctal232"

#define IPOCTAL(obj) \
    OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)

static const VMStateDescription vmstate_scc2698_channel = {
    .name = "scc2698_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_BOOL(rx_enabled, SCC2698Channel),
        VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
        VMSTATE_UINT8(mr_idx, SCC2698Channel),
        VMSTATE_UINT8(sr, SCC2698Channel),
        VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
        VMSTATE_UINT8(rhr_idx, SCC2698Channel),
        VMSTATE_UINT8(rx_pending, SCC2698Channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_scc2698_block = {
    .name = "scc2698_block",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(imr, SCC2698Block),
        VMSTATE_UINT8(isr, SCC2698Block),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ipoctal = {
    .name = "ipoctal232",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
        VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
                             vmstate_scc2698_channel, SCC2698Channel),
        VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
                             vmstate_scc2698_block, SCC2698Block),
        VMSTATE_UINT8(irq_vector, IPOctalState),
        VMSTATE_END_OF_LIST()
    }
};

/* data[10] is 0x0C, not 0x0B as the doc says */
static const uint8_t id_prom_data[] = {
    0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
    0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
};

static void update_irq(IPOctalState *dev, unsigned block)
{
    IPackDevice *idev = IPACK_DEVICE(dev);
    /* Blocks A and B interrupt on INT0#, C and D on INT1#.
       Thus, to get the status we have to check two blocks. */
    SCC2698Block *blk0 = &dev->blk[block];
    SCC2698Block *blk1 = &dev->blk[block^1];
    unsigned intno = block / 2;

    if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
        qemu_irq_raise(idev->irq[intno]);
    } else {
        qemu_irq_lower(idev->irq[intno]);
    }
}

static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
{
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[channel / 2];

    DPRINTF("Write CR%c %u: ", channel + 'a', val);

    /* The lower 4 bits are used to enable and disable Tx and Rx */
    if (val & CR_ENABLE_RX) {
        DPRINTF2("Rx on, ");
        ch->rx_enabled = true;
    }
    if (val & CR_DISABLE_RX) {
        DPRINTF2("Rx off, ");
        ch->rx_enabled = false;
    }
    if (val & CR_ENABLE_TX) {
        DPRINTF2("Tx on, ");
        ch->sr |= SR_TXRDY | SR_TXEMT;
        blk->isr |= ISR_TXRDY(channel);
    }
    if (val & CR_DISABLE_TX) {
        DPRINTF2("Tx off, ");
        ch->sr &= ~(SR_TXRDY | SR_TXEMT);
        blk->isr &= ~ISR_TXRDY(channel);
    }

    DPRINTF2("cmd: ");

    /* The rest of the bits implement different commands */
    switch (CR_CMD(val)) {
    case CR_NO_OP:
        DPRINTF2("none");
        break;
    case CR_RESET_MR:
        DPRINTF2("reset MR");
        ch->mr_idx = 0;
        break;
    case CR_RESET_RX:
        DPRINTF2("reset Rx");
        ch->rx_enabled = false;
        ch->rx_pending = 0;
        ch->sr &= ~SR_RXRDY;
        blk->isr &= ~ISR_RXRDY(channel);
        break;
    case CR_RESET_TX:
        DPRINTF2("reset Tx");
        ch->sr &= ~(SR_TXRDY | SR_TXEMT);
        blk->isr &= ~ISR_TXRDY(channel);
        break;
    case CR_RESET_ERR:
        DPRINTF2("reset err");
        ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK);
        break;
    case CR_RESET_BRKINT:
        DPRINTF2("reset brk ch int");
        blk->isr &= ~(ISR_BREAKA | ISR_BREAKB);
        break;
    default:
        DPRINTF2("unsupported 0x%x", CR_CMD(val));
    }

    DPRINTF2("\n");
}

static uint16_t io_read(IPackDevice *ip, uint8_t addr)
{
    IPOctalState *dev = IPOCTAL(ip);
    uint16_t ret = 0;
    /* addr[7:6]: block   (A-D)
       addr[7:5]: channel (a-h)
       addr[5:0]: register */
    unsigned block = addr >> 5;
    unsigned channel = addr >> 4;
    /* Big endian, accessed using 8-bit bytes at odd locations */
    unsigned offset = (addr & 0x1F) ^ 1;
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[block];
    uint8_t old_isr = blk->isr;

    switch (offset) {

    case REG_MRa:
    case REG_MRb:
        ret = ch->mr[ch->mr_idx];
        DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
        ch->mr_idx = 1;
        break;

    case REG_SRa:
    case REG_SRb:
        ret = ch->sr;
        DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
        break;

    case REG_RHRa:
    case REG_RHRb:
        ret = ch->rhr[ch->rhr_idx];
        if (ch->rx_pending > 0) {
            ch->rx_pending--;
            if (ch->rx_pending == 0) {
                ch->sr &= ~SR_RXRDY;
                blk->isr &= ~ISR_RXRDY(channel);
                if (ch->dev.chr) {
                    qemu_chr_fe_accept_input(ch->dev.chr);
                }
            } else {
                ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
            }
            if (ch->sr & SR_BREAK) {
                ch->sr &= ~SR_BREAK;
                blk->isr |= ISR_BREAK(channel);
            }
        }
        DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
        break;

    case REG_ISR:
        ret = blk->isr;
        DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
        break;

    default:
        DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
    }

    if (old_isr != blk->isr) {
        update_irq(dev, block);
    }

    return ret;
}

static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    unsigned reg = val & 0xFF;
    /* addr[7:6]: block   (A-D)
       addr[7:5]: channel (a-h)
       addr[5:0]: register */
    unsigned block = addr >> 5;
    unsigned channel = addr >> 4;
    /* Big endian, accessed using 8-bit bytes at odd locations */
    unsigned offset = (addr & 0x1F) ^ 1;
    SCC2698Channel *ch = &dev->ch[channel];
    SCC2698Block *blk = &dev->blk[block];
    uint8_t old_isr = blk->isr;
    uint8_t old_imr = blk->imr;

    switch (offset) {

    case REG_MRa:
    case REG_MRb:
        ch->mr[ch->mr_idx] = reg;
        DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
        ch->mr_idx = 1;
        break;

    /* Not implemented */
    case REG_CSRa:
    case REG_CSRb:
        DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
        break;

    case REG_CRa:
    case REG_CRb:
        write_cr(dev, channel, reg);
        break;

    case REG_THRa:
    case REG_THRb:
        if (ch->sr & SR_TXRDY) {
            DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
            if (ch->dev.chr) {
                uint8_t thr = reg;
                /* XXX this blocks entire thread. Rewrite to use
                 * qemu_chr_fe_write and background I/O callbacks */
                qemu_chr_fe_write_all(ch->dev.chr, &thr, 1);
            }
        } else {
            DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
        }
        break;

    /* Not implemented */
    case REG_ACR:
        DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
        break;

    case REG_IMR:
        DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
        blk->imr = reg;
        break;

    /* Not implemented */
    case REG_OPCR:
        DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
        break;

    default:
        DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
    }

    if (old_isr != blk->isr || old_imr != blk->imr) {
        update_irq(dev, block);
    }
}

static uint16_t id_read(IPackDevice *ip, uint8_t addr)
{
    uint16_t ret = 0;
    unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */

    if (pos < ARRAY_SIZE(id_prom_data)) {
        ret = id_prom_data[pos];
    } else {
        DPRINTF("Attempt to read unavailable PROM data at 0x%x\n",  addr);
    }

    return ret;
}

static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    if (addr == 1) {
        DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
        dev->irq_vector = val; /* Undocumented, but the hw works like that */
    } else {
        DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
    }
}

static uint16_t int_read(IPackDevice *ip, uint8_t addr)
{
    IPOctalState *dev = IPOCTAL(ip);
    /* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
    if (addr != 0 && addr != 2) {
        DPRINTF("Attempt to read from 0x%x\n", addr);
        return 0;
    } else {
        /* Update interrupts if necessary */
        update_irq(dev, addr);
        return dev->irq_vector;
    }
}

static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
{
    DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
}

static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
{
    DPRINTF("Attempt to read from 0x%x\n", addr);
    return 0;
}

static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
{
    DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
}

static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
{
    DPRINTF("Attempt to read from 0x%x\n", addr);
    return 0;
}

static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
{
    IPOctalState *dev = IPOCTAL(ip);
    if (addr == 1) {
        DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
        dev->irq_vector = val;
    } else {
        DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
    }
}

static int hostdev_can_receive(void *opaque)
{
    SCC2698Channel *ch = opaque;
    int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
    return ch->rx_enabled ? available_bytes : 0;
}

static void hostdev_receive(void *opaque, const uint8_t *buf, int size)
{
    SCC2698Channel *ch = opaque;
    IPOctalState *dev = ch->ipoctal;
    unsigned pos = ch->rhr_idx + ch->rx_pending;
    int i;

    assert(size + ch->rx_pending <= RX_FIFO_SIZE);

    /* Copy data to the RxFIFO */
    for (i = 0; i < size; i++) {
        pos %= RX_FIFO_SIZE;
        ch->rhr[pos++] = buf[i];
    }

    ch->rx_pending += size;

    /* If the RxFIFO was empty raise an interrupt */
    if (!(ch->sr & SR_RXRDY)) {
        unsigned block, channel = 0;
        /* Find channel number to update the ISR register */
        while (&dev->ch[channel] != ch) {
            channel++;
        }
        block = channel / 2;
        dev->blk[block].isr |= ISR_RXRDY(channel);
        ch->sr |= SR_RXRDY;
        update_irq(dev, block);
    }
}

static void hostdev_event(void *opaque, int event)
{
    SCC2698Channel *ch = opaque;
    switch (event) {
    case CHR_EVENT_OPENED:
        DPRINTF("Device %s opened\n", ch->dev->label);
        break;
    case CHR_EVENT_BREAK: {
        uint8_t zero = 0;
        DPRINTF("Device %s received break\n", ch->dev->label);

        if (!(ch->sr & SR_BREAK)) {
            IPOctalState *dev = ch->ipoctal;
            unsigned block, channel = 0;

            while (&dev->ch[channel] != ch) {
                channel++;
            }
            block = channel / 2;

            ch->sr |= SR_BREAK;
            dev->blk[block].isr |= ISR_BREAK(channel);
        }

        /* Put a zero character in the buffer */
        hostdev_receive(ch, &zero, 1);
    }
        break;
    default:
        DPRINTF("Device %s received event %d\n", ch->dev->label, event);
    }
}

static void ipoctal_realize(DeviceState *dev, Error **errp)
{
    IPOctalState *s = IPOCTAL(dev);
    unsigned i;

    for (i = 0; i < N_CHANNELS; i++) {
        SCC2698Channel *ch = &s->ch[i];
        ch->ipoctal = s;

        /* Redirect IP-Octal channels to host character devices */
        if (ch->dev.chr) {
            qemu_chr_add_handlers(ch->dev.chr, hostdev_can_receive,
                                  hostdev_receive, hostdev_event, ch);
            DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
        } else {
            DPRINTF("Could not redirect channel %u, no chardev set\n", i);
        }
    }
}

static Property ipoctal_properties[] = {
    DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
    DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
    DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
    DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
    DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
    DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
    DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
    DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
    DEFINE_PROP_END_OF_LIST(),
};

static void ipoctal_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);

    ic->realize     = ipoctal_realize;
    ic->io_read     = io_read;
    ic->io_write    = io_write;
    ic->id_read     = id_read;
    ic->id_write    = id_write;
    ic->int_read    = int_read;
    ic->int_write   = int_write;
    ic->mem_read16  = mem_read16;
    ic->mem_write16 = mem_write16;
    ic->mem_read8   = mem_read8;
    ic->mem_write8  = mem_write8;

    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
    dc->desc    = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
    dc->props   = ipoctal_properties;
    dc->vmsd    = &vmstate_ipoctal;
}

static const TypeInfo ipoctal_info = {
    .name          = TYPE_IPOCTAL,
    .parent        = TYPE_IPACK_DEVICE,
    .instance_size = sizeof(IPOctalState),
    .class_init    = ipoctal_class_init,
};

static void ipoctal_register_types(void)
{
    type_register_static(&ipoctal_info);
}

type_init(ipoctal_register_types)
Commit	Line	Data
be657dea AG	1	/*
	2	* QEMU GE IP-Octal 232 IndustryPack emulation
	3	*
	4	* Copyright (C) 2012 Igalia, S.L.
b996aed5	5	* Author: Alberto Garcia <[email protected]>
be657dea AG	6	*
	7	* This code is licensed under the GNU GPL v2 or (at your option) any
	8	* later version.
	9	*/
	10
0430891c	11	#include "qemu/osdep.h"
1f9c4cfd	12	#include "hw/ipack/ipack.h"
be657dea	13	#include "qemu/bitops.h"
dccfcd0e	14	#include "sysemu/char.h"
be657dea AG	15
	16	/* #define DEBUG_IPOCTAL */
	17
	18	#ifdef DEBUG_IPOCTAL
	19	#define DPRINTF2(fmt, ...) \
	20	do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
	21	#else
	22	#define DPRINTF2(fmt, ...) do { } while (0)
	23	#endif
	24
	25	#define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
	26
	27	#define RX_FIFO_SIZE 3
	28
	29	/* The IP-Octal has 8 channels (a-h)
	30	divided into 4 blocks (A-D) */
	31	#define N_CHANNELS 8
	32	#define N_BLOCKS 4
	33
	34	#define REG_MRa 0x01
	35	#define REG_MRb 0x11
	36	#define REG_SRa 0x03
	37	#define REG_SRb 0x13
	38	#define REG_CSRa 0x03
	39	#define REG_CSRb 0x13
	40	#define REG_CRa 0x05
	41	#define REG_CRb 0x15
	42	#define REG_RHRa 0x07
	43	#define REG_RHRb 0x17
	44	#define REG_THRa 0x07
	45	#define REG_THRb 0x17
	46	#define REG_ACR 0x09
	47	#define REG_ISR 0x0B
	48	#define REG_IMR 0x0B
	49	#define REG_OPCR 0x1B
	50
	51	#define CR_ENABLE_RX BIT(0)
	52	#define CR_DISABLE_RX BIT(1)
	53	#define CR_ENABLE_TX BIT(2)
	54	#define CR_DISABLE_TX BIT(3)
	55	#define CR_CMD(cr) ((cr) >> 4)
	56	#define CR_NO_OP 0
	57	#define CR_RESET_MR 1
	58	#define CR_RESET_RX 2
	59	#define CR_RESET_TX 3
	60	#define CR_RESET_ERR 4
	61	#define CR_RESET_BRKINT 5
	62	#define CR_START_BRK 6
	63	#define CR_STOP_BRK 7
	64	#define CR_ASSERT_RTSN 8
	65	#define CR_NEGATE_RTSN 9
	66	#define CR_TIMEOUT_ON 10
	67	#define CR_TIMEOUT_OFF 12
	68
	69	#define SR_RXRDY BIT(0)
	70	#define SR_FFULL BIT(1)
	71	#define SR_TXRDY BIT(2)
	72	#define SR_TXEMT BIT(3)
	73	#define SR_OVERRUN BIT(4)
	74	#define SR_PARITY BIT(5)
	75	#define SR_FRAMING BIT(6)
	76	#define SR_BREAK BIT(7)
	77
	78	#define ISR_TXRDYA BIT(0)
79	#define ISR_RXRDYA BIT(1)
80	#define ISR_BREAKA BIT(2)
81	#define ISR_CNTRDY BIT(3)
82	#define ISR_TXRDYB BIT(4)
83	#define ISR_RXRDYB BIT(5)
84	#define ISR_BREAKB BIT(6)
85	#define ISR_MPICHG BIT(7)
86	#define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
87	#define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
88	#define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))
89
90	typedef struct IPOctalState IPOctalState;
91	typedef struct SCC2698Channel SCC2698Channel;
92	typedef struct SCC2698Block SCC2698Block;
93
94	struct SCC2698Channel {
95	IPOctalState *ipoctal;
becdfa00	96	CharBackend dev;
be657dea AG	97	bool rx_enabled;
	98	uint8_t mr[2];
	99	uint8_t mr_idx;
	100	uint8_t sr;
	101	uint8_t rhr[RX_FIFO_SIZE];
	102	uint8_t rhr_idx;
	103	uint8_t rx_pending;
	104	};
	105
	106	struct SCC2698Block {
	107	uint8_t imr;
	108	uint8_t isr;
	109	};
	110
	111	struct IPOctalState {
08c9cacf AF	112	IPackDevice parent_obj;
08c9cacf AF	113
be657dea AG	114	SCC2698Channel ch[N_CHANNELS];
	115	SCC2698Block blk[N_BLOCKS];
	116	uint8_t irq_vector;
	117	};
	118
	119	#define TYPE_IPOCTAL "ipoctal232"
	120
	121	#define IPOCTAL(obj) \
	122	OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)
	123
	124	static const VMStateDescription vmstate_scc2698_channel = {
	125	.name = "scc2698_channel",
	126	.version_id = 1,
	127	.minimum_version_id = 1,
35d08458	128	.fields = (VMStateField[]) {
be657dea AG	129	VMSTATE_BOOL(rx_enabled, SCC2698Channel),
	130	VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
	131	VMSTATE_UINT8(mr_idx, SCC2698Channel),
	132	VMSTATE_UINT8(sr, SCC2698Channel),
	133	VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
	134	VMSTATE_UINT8(rhr_idx, SCC2698Channel),
	135	VMSTATE_UINT8(rx_pending, SCC2698Channel),
	136	VMSTATE_END_OF_LIST()
	137	}
	138	};
	139
	140	static const VMStateDescription vmstate_scc2698_block = {
	141	.name = "scc2698_block",
	142	.version_id = 1,
	143	.minimum_version_id = 1,
35d08458	144	.fields = (VMStateField[]) {
be657dea AG	145	VMSTATE_UINT8(imr, SCC2698Block),
	146	VMSTATE_UINT8(isr, SCC2698Block),
	147	VMSTATE_END_OF_LIST()
	148	}
	149	};
	150
	151	static const VMStateDescription vmstate_ipoctal = {
	152	.name = "ipoctal232",
	153	.version_id = 1,
	154	.minimum_version_id = 1,
35d08458	155	.fields = (VMStateField[]) {
08c9cacf	156	VMSTATE_IPACK_DEVICE(parent_obj, IPOctalState),
be657dea AG	157	VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
	158	vmstate_scc2698_channel, SCC2698Channel),
	159	VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
	160	vmstate_scc2698_block, SCC2698Block),
	161	VMSTATE_UINT8(irq_vector, IPOctalState),
	162	VMSTATE_END_OF_LIST()
	163	}
	164	};
	165
	166	/* data[10] is 0x0C, not 0x0B as the doc says */
	167	static const uint8_t id_prom_data[] = {
	168	0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
	169	0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
	170	};
	171
	172	static void update_irq(IPOctalState *dev, unsigned block)
	173	{
08c9cacf	174	IPackDevice *idev = IPACK_DEVICE(dev);
be657dea AG	175	/* Blocks A and B interrupt on INT0#, C and D on INT1#.
	176	Thus, to get the status we have to check two blocks. */
	177	SCC2698Block *blk0 = &dev->blk[block];
	178	SCC2698Block *blk1 = &dev->blk[block^1];
	179	unsigned intno = block / 2;
	180
	181	if ((blk0->isr & blk0->imr) \|\| (blk1->isr & blk1->imr)) {
08c9cacf	182	qemu_irq_raise(idev->irq[intno]);
be657dea	183	} else {
08c9cacf	184	qemu_irq_lower(idev->irq[intno]);
be657dea AG	185	}
	186	}
	187
	188	static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
	189	{
	190	SCC2698Channel *ch = &dev->ch[channel];
	191	SCC2698Block *blk = &dev->blk[channel / 2];
	192
	193	DPRINTF("Write CR%c %u: ", channel + 'a', val);
	194
	195	/* The lower 4 bits are used to enable and disable Tx and Rx */
	196	if (val & CR_ENABLE_RX) {
	197	DPRINTF2("Rx on, ");
	198	ch->rx_enabled = true;
	199	}
	200	if (val & CR_DISABLE_RX) {
	201	DPRINTF2("Rx off, ");
	202	ch->rx_enabled = false;
	203	}
	204	if (val & CR_ENABLE_TX) {
	205	DPRINTF2("Tx on, ");
	206	ch->sr \|= SR_TXRDY \| SR_TXEMT;
	207	blk->isr \|= ISR_TXRDY(channel);
	208	}
	209	if (val & CR_DISABLE_TX) {
	210	DPRINTF2("Tx off, ");
	211	ch->sr &= ~(SR_TXRDY \| SR_TXEMT);
	212	blk->isr &= ~ISR_TXRDY(channel);
	213	}
	214
	215	DPRINTF2("cmd: ");
	216
	217	/* The rest of the bits implement different commands */
	218	switch (CR_CMD(val)) {
	219	case CR_NO_OP:
	220	DPRINTF2("none");
	221	break;
	222	case CR_RESET_MR:
	223	DPRINTF2("reset MR");
	224	ch->mr_idx = 0;
	225	break;
	226	case CR_RESET_RX:
	227	DPRINTF2("reset Rx");
	228	ch->rx_enabled = false;
	229	ch->rx_pending = 0;
	230	ch->sr &= ~SR_RXRDY;
	231	blk->isr &= ~ISR_RXRDY(channel);
	232	break;
	233	case CR_RESET_TX:
	234	DPRINTF2("reset Tx");
	235	ch->sr &= ~(SR_TXRDY \| SR_TXEMT);
	236	blk->isr &= ~ISR_TXRDY(channel);
	237	break;
	238	case CR_RESET_ERR:
	239	DPRINTF2("reset err");
	240	ch->sr &= ~(SR_OVERRUN \| SR_PARITY \| SR_FRAMING \| SR_BREAK);
	241	break;
	242	case CR_RESET_BRKINT:
	243	DPRINTF2("reset brk ch int");
	244	blk->isr &= ~(ISR_BREAKA \| ISR_BREAKB);
	245	break;
	246	default:
	247	DPRINTF2("unsupported 0x%x", CR_CMD(val));
	248	}
249
250	DPRINTF2("\n");
251	}
252
253	static uint16_t io_read(IPackDevice *ip, uint8_t addr)
254	{
255	IPOctalState *dev = IPOCTAL(ip);
256	uint16_t ret = 0;
257	/* addr[7:6]: block (A-D)
258	addr[7:5]: channel (a-h)
259	addr[5:0]: register */
260	unsigned block = addr >> 5;
261	unsigned channel = addr >> 4;
262	/* Big endian, accessed using 8-bit bytes at odd locations */
263	unsigned offset = (addr & 0x1F) ^ 1;
264	SCC2698Channel *ch = &dev->ch[channel];
265	SCC2698Block *blk = &dev->blk[block];
266	uint8_t old_isr = blk->isr;
267
268	switch (offset) {
269
270	case REG_MRa:
271	case REG_MRb:
272	ret = ch->mr[ch->mr_idx];
273	DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
274	ch->mr_idx = 1;
275	break;
276
277	case REG_SRa:
278	case REG_SRb:
279	ret = ch->sr;
280	DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
281	break;
282
283	case REG_RHRa:
284	case REG_RHRb:
285	ret = ch->rhr[ch->rhr_idx];
286	if (ch->rx_pending > 0) {
287	ch->rx_pending--;
288	if (ch->rx_pending == 0) {
289	ch->sr &= ~SR_RXRDY;
290	blk->isr &= ~ISR_RXRDY(channel);
becdfa00	291	if (ch->dev.chr) {
7fa47e2a	292	qemu_chr_fe_accept_input(ch->dev.chr);
be657dea AG	293	}
	294	} else {
	295	ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
	296	}
	297	if (ch->sr & SR_BREAK) {
	298	ch->sr &= ~SR_BREAK;
	299	blk->isr \|= ISR_BREAK(channel);
	300	}
	301	}
	302	DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
	303	break;
	304
	305	case REG_ISR:
	306	ret = blk->isr;
	307	DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
	308	break;
	309
	310	default:
	311	DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
	312	}
	313
	314	if (old_isr != blk->isr) {
	315	update_irq(dev, block);
	316	}
	317
	318	return ret;
	319	}
	320
	321	static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
	322	{
	323	IPOctalState *dev = IPOCTAL(ip);
	324	unsigned reg = val & 0xFF;
	325	/* addr[7:6]: block (A-D)
	326	addr[7:5]: channel (a-h)
	327	addr[5:0]: register */
	328	unsigned block = addr >> 5;
	329	unsigned channel = addr >> 4;
	330	/* Big endian, accessed using 8-bit bytes at odd locations */
	331	unsigned offset = (addr & 0x1F) ^ 1;
	332	SCC2698Channel *ch = &dev->ch[channel];
	333	SCC2698Block *blk = &dev->blk[block];
	334	uint8_t old_isr = blk->isr;
	335	uint8_t old_imr = blk->imr;
	336
	337	switch (offset) {
	338
	339	case REG_MRa:
	340	case REG_MRb:
	341	ch->mr[ch->mr_idx] = reg;
	342	DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
	343	ch->mr_idx = 1;
	344	break;
	345
	346	/* Not implemented */
	347	case REG_CSRa:
	348	case REG_CSRb:
	349	DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
	350	break;
	351
	352	case REG_CRa:
	353	case REG_CRb:
	354	write_cr(dev, channel, reg);
	355	break;
	356
357	case REG_THRa:
358	case REG_THRb:
359	if (ch->sr & SR_TXRDY) {
360	DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
becdfa00	361	if (ch->dev.chr) {
be657dea	362	uint8_t thr = reg;
6ab3fc32 DB	363	/* XXX this blocks entire thread. Rewrite to use
6ab3fc32 DB	364	* qemu_chr_fe_write and background I/O callbacks */
becdfa00	365	qemu_chr_fe_write_all(ch->dev.chr, &thr, 1);
be657dea AG	366	}
	367	} else {
	368	DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
	369	}
	370	break;
	371
	372	/* Not implemented */
	373	case REG_ACR:
	374	DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
	375	break;
	376
	377	case REG_IMR:
	378	DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
	379	blk->imr = reg;
	380	break;
	381
	382	/* Not implemented */
	383	case REG_OPCR:
	384	DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
	385	break;
	386
	387	default:
	388	DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
	389	}
	390
	391	if (old_isr != blk->isr \|\| old_imr != blk->imr) {
	392	update_irq(dev, block);
	393	}
	394	}
	395
	396	static uint16_t id_read(IPackDevice *ip, uint8_t addr)
	397	{
	398	uint16_t ret = 0;
	399	unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */
	400
	401	if (pos < ARRAY_SIZE(id_prom_data)) {
	402	ret = id_prom_data[pos];
	403	} else {
	404	DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr);
	405	}
	406
	407	return ret;
	408	}
	409
	410	static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
	411	{
	412	IPOctalState *dev = IPOCTAL(ip);
	413	if (addr == 1) {
	414	DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
	415	dev->irq_vector = val; /* Undocumented, but the hw works like that */
	416	} else {
	417	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
	418	}
	419	}
	420
	421	static uint16_t int_read(IPackDevice *ip, uint8_t addr)
	422	{
	423	IPOctalState *dev = IPOCTAL(ip);
	424	/* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
	425	if (addr != 0 && addr != 2) {
	426	DPRINTF("Attempt to read from 0x%x\n", addr);
	427	return 0;
	428	} else {
	429	/* Update interrupts if necessary */
430	update_irq(dev, addr);
431	return dev->irq_vector;
432	}
433	}
434
435	static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
436	{
437	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
438	}
439
440	static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
441	{
442	DPRINTF("Attempt to read from 0x%x\n", addr);
443	return 0;
444	}
445
446	static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
447	{
448	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
449	}
450
451	static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
452	{
453	DPRINTF("Attempt to read from 0x%x\n", addr);
454	return 0;
455	}
456
457	static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
458	{
459	IPOctalState *dev = IPOCTAL(ip);
460	if (addr == 1) {
461	DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
462	dev->irq_vector = val;
463	} else {
464	DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
465	}
466	}
467
468	static int hostdev_can_receive(void *opaque)
469	{
470	SCC2698Channel *ch = opaque;
471	int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
472	return ch->rx_enabled ? available_bytes : 0;
473	}
474
475	static void hostdev_receive(void opaque, const uint8_t buf, int size)
476	{
477	SCC2698Channel *ch = opaque;
478	IPOctalState *dev = ch->ipoctal;
479	unsigned pos = ch->rhr_idx + ch->rx_pending;
480	int i;
481
482	assert(size + ch->rx_pending <= RX_FIFO_SIZE);
483
484	/* Copy data to the RxFIFO */
485	for (i = 0; i < size; i++) {
486	pos %= RX_FIFO_SIZE;
487	ch->rhr[pos++] = buf[i];
488	}
489
490	ch->rx_pending += size;
491
492	/* If the RxFIFO was empty raise an interrupt */
493	if (!(ch->sr & SR_RXRDY)) {
494	unsigned block, channel = 0;
495	/* Find channel number to update the ISR register */
496	while (&dev->ch[channel] != ch) {
497	channel++;
498	}
499	block = channel / 2;
500	dev->blk[block].isr \|= ISR_RXRDY(channel);
501	ch->sr \|= SR_RXRDY;
502	update_irq(dev, block);
503	}
504	}
505
506	static void hostdev_event(void *opaque, int event)
507	{
508	SCC2698Channel *ch = opaque;
509	switch (event) {
510	case CHR_EVENT_OPENED:
511	DPRINTF("Device %s opened\n", ch->dev->label);
512	break;
513	case CHR_EVENT_BREAK: {
514	uint8_t zero = 0;
515	DPRINTF("Device %s received break\n", ch->dev->label);
516
517	if (!(ch->sr & SR_BREAK)) {
518	IPOctalState *dev = ch->ipoctal;
519	unsigned block, channel = 0;
520
521	while (&dev->ch[channel] != ch) {
522	channel++;
523	}
524	block = channel / 2;
525
526	ch->sr \|= SR_BREAK;
527	dev->blk[block].isr \|= ISR_BREAK(channel);
528	}
529
530	/* Put a zero character in the buffer */
531	hostdev_receive(ch, &zero, 1);
532	}
533	break;
534	default:
535	DPRINTF("Device %s received event %d\n", ch->dev->label, event);
536	}
537	}
538
5c570902	539	static void ipoctal_realize(DeviceState dev, Error *errp)
be657dea	540	{
5c570902	541	IPOctalState *s = IPOCTAL(dev);
be657dea AG	542	unsigned i;
	543
	544	for (i = 0; i < N_CHANNELS; i++) {
	545	SCC2698Channel *ch = &s->ch[i];
	546	ch->ipoctal = s;
	547
	548	/* Redirect IP-Octal channels to host character devices */
becdfa00 MAL	549	if (ch->dev.chr) {
becdfa00 MAL	550	qemu_chr_add_handlers(ch->dev.chr, hostdev_can_receive,
b9936159 HG	551	hostdev_receive, hostdev_event, ch);
	552	DPRINTF("Redirecting channel %u to %s\n", i, ch->dev->label);
	553	} else {
	554	DPRINTF("Could not redirect channel %u, no chardev set\n", i);
be657dea AG	555	}
be657dea AG	556	}
be657dea AG	557	}
	558
	559	static Property ipoctal_properties[] = {
b9936159 HG	560	DEFINE_PROP_CHR("chardev0", IPOctalState, ch[0].dev),
	561	DEFINE_PROP_CHR("chardev1", IPOctalState, ch[1].dev),
	562	DEFINE_PROP_CHR("chardev2", IPOctalState, ch[2].dev),
	563	DEFINE_PROP_CHR("chardev3", IPOctalState, ch[3].dev),
	564	DEFINE_PROP_CHR("chardev4", IPOctalState, ch[4].dev),
	565	DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev),
	566	DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev),
	567	DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev),
be657dea AG	568	DEFINE_PROP_END_OF_LIST(),
	569	};
	570
	571	static void ipoctal_class_init(ObjectClass klass, void data)
	572	{
	573	DeviceClass *dc = DEVICE_CLASS(klass);
	574	IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);
	575
5c570902	576	ic->realize = ipoctal_realize;
be657dea AG	577	ic->io_read = io_read;
	578	ic->io_write = io_write;
	579	ic->id_read = id_read;
	580	ic->id_write = id_write;
	581	ic->int_read = int_read;
	582	ic->int_write = int_write;
	583	ic->mem_read16 = mem_read16;
	584	ic->mem_write16 = mem_write16;
	585	ic->mem_read8 = mem_read8;
	586	ic->mem_write8 = mem_write8;
	587
125ee0ed	588	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
be657dea AG	589	dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
	590	dc->props = ipoctal_properties;
	591	dc->vmsd = &vmstate_ipoctal;
	592	}
	593
	594	static const TypeInfo ipoctal_info = {
	595	.name = TYPE_IPOCTAL,
	596	.parent = TYPE_IPACK_DEVICE,
	597	.instance_size = sizeof(IPOctalState),
	598	.class_init = ipoctal_class_init,
	599	};
	600
	601	static void ipoctal_register_types(void)
	602	{
	603	type_register_static(&ipoctal_info);
	604	}
	605
	606	type_init(ipoctal_register_types)