[qemu.git] / target-arm / cpu.h

/*
 * ARM virtual CPU header
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_ARM_H
#define CPU_ARM_H

#define TARGET_LONG_BITS 32

#define ELF_MACHINE	EM_ARM

#define CPUState struct CPUARMState

#include "config.h"
#include "qemu-common.h"
#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#define EXCP_UDEF            1   /* undefined instruction */
#define EXCP_SWI             2   /* software interrupt */
#define EXCP_PREFETCH_ABORT  3
#define EXCP_DATA_ABORT      4
#define EXCP_IRQ             5
#define EXCP_FIQ             6
#define EXCP_BKPT            7
#define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
#define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
#define EXCP_STREX          10

#define ARMV7M_EXCP_RESET   1
#define ARMV7M_EXCP_NMI     2
#define ARMV7M_EXCP_HARD    3
#define ARMV7M_EXCP_MEM     4
#define ARMV7M_EXCP_BUS     5
#define ARMV7M_EXCP_USAGE   6
#define ARMV7M_EXCP_SVC     11
#define ARMV7M_EXCP_DEBUG   12
#define ARMV7M_EXCP_PENDSV  14
#define ARMV7M_EXCP_SYSTICK 15

/* ARM-specific interrupt pending bits.  */
#define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1


typedef void ARMWriteCPFunc(void *opaque, int cp_info,
                            int srcreg, int operand, uint32_t value);
typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
                               int dstreg, int operand);

struct arm_boot_info;

#define NB_MMU_MODES 2

/* We currently assume float and double are IEEE single and double
   precision respectively.
   Doing runtime conversions is tricky because VFP registers may contain
   integer values (eg. as the result of a FTOSI instruction).
   s<2n> maps to the least significant half of d<n>
   s<2n+1> maps to the most significant half of d<n>
 */

typedef struct CPUARMState {
    /* Regs for current mode.  */
    uint32_t regs[16];
    /* Frequently accessed CPSR bits are stored separately for efficiently.
       This contains all the other bits.  Use cpsr_{read,write} to access
       the whole CPSR.  */
    uint32_t uncached_cpsr;
    uint32_t spsr;

    /* Banked registers.  */
    uint32_t banked_spsr[6];
    uint32_t banked_r13[6];
    uint32_t banked_r14[6];

    /* These hold r8-r12.  */
    uint32_t usr_regs[5];
    uint32_t fiq_regs[5];

    /* cpsr flag cache for faster execution */
    uint32_t CF; /* 0 or 1 */
    uint32_t VF; /* V is the bit 31. All other bits are undefined */
    uint32_t NF; /* N is bit 31. All other bits are undefined.  */
    uint32_t ZF; /* Z set if zero.  */
    uint32_t QF; /* 0 or 1 */
    uint32_t GE; /* cpsr[19:16] */
    uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
    uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */

    /* System control coprocessor (cp15) */
    struct {
        uint32_t c0_cpuid;
        uint32_t c0_cachetype;
        uint32_t c0_ccsid[16]; /* Cache size.  */
        uint32_t c0_clid; /* Cache level.  */
        uint32_t c0_cssel; /* Cache size selection.  */
        uint32_t c0_c1[8]; /* Feature registers.  */
        uint32_t c0_c2[8]; /* Instruction set registers.  */
        uint32_t c1_sys; /* System control register.  */
        uint32_t c1_coproc; /* Coprocessor access register.  */
        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
        uint32_t c2_base0; /* MMU translation table base 0.  */
        uint32_t c2_base1; /* MMU translation table base 1.  */
        uint32_t c2_control; /* MMU translation table base control.  */
        uint32_t c2_mask; /* MMU translation table base selection mask.  */
        uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
        uint32_t c2_data; /* MPU data cachable bits.  */
        uint32_t c2_insn; /* MPU instruction cachable bits.  */
        uint32_t c3; /* MMU domain access control register
                        MPU write buffer control.  */
        uint32_t c5_insn; /* Fault status registers.  */
        uint32_t c5_data;
        uint32_t c6_region[8]; /* MPU base/size registers.  */
        uint32_t c6_insn; /* Fault address registers.  */
        uint32_t c6_data;
        uint32_t c7_par;  /* Translation result. */
        uint32_t c9_insn; /* Cache lockdown registers.  */
        uint32_t c9_data;
        uint32_t c9_pmcr; /* performance monitor control register */
        uint32_t c9_pmcnten; /* perf monitor counter enables */
        uint32_t c9_pmovsr; /* perf monitor overflow status */
        uint32_t c9_pmxevtyper; /* perf monitor event type */
        uint32_t c9_pmuserenr; /* perf monitor user enable */
        uint32_t c9_pminten; /* perf monitor interrupt enables */
        uint32_t c13_fcse; /* FCSE PID.  */
        uint32_t c13_context; /* Context ID.  */
        uint32_t c13_tls1; /* User RW Thread register.  */
        uint32_t c13_tls2; /* User RO Thread register.  */
        uint32_t c13_tls3; /* Privileged Thread register.  */
        uint32_t c15_cpar; /* XScale Coprocessor Access Register */
        uint32_t c15_ticonfig; /* TI925T configuration byte.  */
        uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
        uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
        uint32_t c15_threadid; /* TI debugger thread-ID.  */
    } cp15;

    struct {
        uint32_t other_sp;
        uint32_t vecbase;
        uint32_t basepri;
        uint32_t control;
        int current_sp;
        int exception;
        int pending_exception;
    } v7m;

    /* Thumb-2 EE state.  */
    uint32_t teecr;
    uint32_t teehbr;

    /* Internal CPU feature flags.  */
    uint32_t features;

    /* VFP coprocessor state.  */
    struct {
        float64 regs[32];

        uint32_t xregs[16];
        /* We store these fpcsr fields separately for convenience.  */
        int vec_len;
        int vec_stride;

        /* scratch space when Tn are not sufficient.  */
        uint32_t scratch[8];

        /* fp_status is the "normal" fp status. standard_fp_status retains
         * values corresponding to the ARM "Standard FPSCR Value", ie
         * default-NaN, flush-to-zero, round-to-nearest and is used by
         * any operations (generally Neon) which the architecture defines
         * as controlled by the standard FPSCR value rather than the FPSCR.
         *
         * To avoid having to transfer exception bits around, we simply
         * say that the FPSCR cumulative exception flags are the logical
         * OR of the flags in the two fp statuses. This relies on the
         * only thing which needs to read the exception flags being
         * an explicit FPSCR read.
         */
        float_status fp_status;
        float_status standard_fp_status;
    } vfp;
    uint32_t exclusive_addr;
    uint32_t exclusive_val;
    uint32_t exclusive_high;
#if defined(CONFIG_USER_ONLY)
    uint32_t exclusive_test;
    uint32_t exclusive_info;
#endif

    /* iwMMXt coprocessor state.  */
    struct {
        uint64_t regs[16];
        uint64_t val;

        uint32_t cregs[16];
    } iwmmxt;

#if defined(CONFIG_USER_ONLY)
    /* For usermode syscall translation.  */
    int eabi;
#endif

    CPU_COMMON

    /* These fields after the common ones so they are preserved on reset.  */

    /* Coprocessor IO used by peripherals */
    struct {
        ARMReadCPFunc *cp_read;
        ARMWriteCPFunc *cp_write;
        void *opaque;
    } cp[15];
    void *nvic;
    const struct arm_boot_info *boot_info;
} CPUARMState;

CPUARMState *cpu_arm_init(const char *cpu_model);
void arm_translate_init(void);
int cpu_arm_exec(CPUARMState *s);
void cpu_arm_close(CPUARMState *s);
void do_interrupt(CPUARMState *);
void switch_mode(CPUARMState *, int);
uint32_t do_arm_semihosting(CPUARMState *env);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_arm_signal_handler(int host_signum, void *pinfo,
                           void *puc);
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
                              int mmu_idx, int is_softmuu);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault

static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
{
  env->cp15.c13_tls2 = newtls;
}

#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)
#define CPSR_F (1 << 6)
#define CPSR_I (1 << 7)
#define CPSR_A (1 << 8)
#define CPSR_E (1 << 9)
#define CPSR_IT_2_7 (0xfc00)
#define CPSR_GE (0xf << 16)
#define CPSR_RESERVED (0xf << 20)
#define CPSR_J (1 << 24)
#define CPSR_IT_0_1 (3 << 25)
#define CPSR_Q (1 << 27)
#define CPSR_V (1 << 28)
#define CPSR_C (1 << 29)
#define CPSR_Z (1 << 30)
#define CPSR_N (1 << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)

#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
/* Bits writable in user mode.  */
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/* Execution state bits.  MRS read as zero, MSR writes ignored.  */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)

/* Return the current CPSR value.  */
uint32_t cpsr_read(CPUARMState *env);
/* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);

/* Return the current xPSR value.  */
static inline uint32_t xpsr_read(CPUARMState *env)
{
    int ZF;
    ZF = (env->ZF == 0);
    return (env->NF & 0x80000000) | (ZF << 30)
        | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
        | ((env->condexec_bits & 0xfc) << 8)
        | env->v7m.exception;
}

/* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    if (mask & CPSR_NZCV) {
        env->ZF = (~val) & CPSR_Z;
        env->NF = val;
        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & (1 << 24))
        env->thumb = ((val & (1 << 24)) != 0);
    if (mask & CPSR_IT_0_1) {
        env->condexec_bits &= ~3;
        env->condexec_bits |= (val >> 25) & 3;
    }
    if (mask & CPSR_IT_2_7) {
        env->condexec_bits &= 3;
        env->condexec_bits |= (val >> 8) & 0xfc;
    }
    if (mask & 0x1ff) {
        env->v7m.exception = val & 0x1ff;
    }
}

/* Return the current FPSCR value.  */
uint32_t vfp_get_fpscr(CPUARMState *env);
void vfp_set_fpscr(CPUARMState *env, uint32_t val);

enum arm_cpu_mode {
  ARM_CPU_MODE_USR = 0x10,
  ARM_CPU_MODE_FIQ = 0x11,
  ARM_CPU_MODE_IRQ = 0x12,
  ARM_CPU_MODE_SVC = 0x13,
  ARM_CPU_MODE_ABT = 0x17,
  ARM_CPU_MODE_UND = 0x1b,
  ARM_CPU_MODE_SYS = 0x1f
};

/* VFP system registers.  */
#define ARM_VFP_FPSID   0
#define ARM_VFP_FPSCR   1
#define ARM_VFP_MVFR1   6
#define ARM_VFP_MVFR0   7
#define ARM_VFP_FPEXC   8
#define ARM_VFP_FPINST  9
#define ARM_VFP_FPINST2 10

/* iwMMXt coprocessor control registers.  */
#define ARM_IWMMXT_wCID		0
#define ARM_IWMMXT_wCon		1
#define ARM_IWMMXT_wCSSF	2
#define ARM_IWMMXT_wCASF	3
#define ARM_IWMMXT_wCGR0	8
#define ARM_IWMMXT_wCGR1	9
#define ARM_IWMMXT_wCGR2	10
#define ARM_IWMMXT_wCGR3	11

enum arm_features {
    ARM_FEATURE_VFP,
    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
    ARM_FEATURE_V6,
    ARM_FEATURE_V6K,
    ARM_FEATURE_V7,
    ARM_FEATURE_THUMB2,
    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
    ARM_FEATURE_VFP3,
    ARM_FEATURE_VFP_FP16,
    ARM_FEATURE_NEON,
    ARM_FEATURE_DIV,
    ARM_FEATURE_M, /* Microcontroller profile.  */
    ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
    ARM_FEATURE_THUMB2EE,
    ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
    ARM_FEATURE_V4T,
    ARM_FEATURE_V5,
    ARM_FEATURE_STRONGARM,
};

static inline int arm_feature(CPUARMState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);

/* Interface between CPU and Interrupt controller.  */
void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);

void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
                       ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
                       void *opaque);

/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
   Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
   conventional cores (ie. Application or Realtime profile).  */

#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
#define ARM_CPUID(env) (env->cp15.c0_cpuid)

#define ARM_CPUID_ARM1026     0x4106a262
#define ARM_CPUID_ARM926      0x41069265
#define ARM_CPUID_ARM946      0x41059461
#define ARM_CPUID_TI915T      0x54029152
#define ARM_CPUID_TI925T      0x54029252
#define ARM_CPUID_SA1100      0x4401A11B
#define ARM_CPUID_SA1110      0x6901B119
#define ARM_CPUID_PXA250      0x69052100
#define ARM_CPUID_PXA255      0x69052d00
#define ARM_CPUID_PXA260      0x69052903
#define ARM_CPUID_PXA261      0x69052d05
#define ARM_CPUID_PXA262      0x69052d06
#define ARM_CPUID_PXA270      0x69054110
#define ARM_CPUID_PXA270_A0   0x69054110
#define ARM_CPUID_PXA270_A1   0x69054111
#define ARM_CPUID_PXA270_B0   0x69054112
#define ARM_CPUID_PXA270_B1   0x69054113
#define ARM_CPUID_PXA270_C0   0x69054114
#define ARM_CPUID_PXA270_C5   0x69054117
#define ARM_CPUID_ARM1136     0x4117b363
#define ARM_CPUID_ARM1136_R2  0x4107b362
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8    0x410fc080
#define ARM_CPUID_CORTEXA9    0x410fc090
#define ARM_CPUID_CORTEXM3    0x410fc231
#define ARM_CPUID_ANY         0xffffffff

#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
#else
/* The ARM MMU allows 1k pages.  */
/* ??? Linux doesn't actually use these, and they're deprecated in recent
   architecture revisions.  Maybe a configure option to disable them.  */
#define TARGET_PAGE_BITS 10
#endif

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define cpu_init cpu_arm_init
#define cpu_exec cpu_arm_exec
#define cpu_gen_code cpu_arm_gen_code
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list

#define CPU_SAVE_VERSION 4

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
    return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->regs[13] = newsp;
    env->regs[0] = 0;
}
#endif

#include "cpu-all.h"

/* Bit usage in the TB flags field: */
#define ARM_TBFLAG_THUMB_SHIFT      0
#define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
#define ARM_TBFLAG_VECLEN_SHIFT     1
#define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
#define ARM_TBFLAG_VECSTRIDE_SHIFT  4
#define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
#define ARM_TBFLAG_PRIV_SHIFT       6
#define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
#define ARM_TBFLAG_VFPEN_SHIFT      7
#define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
#define ARM_TBFLAG_CONDEXEC_SHIFT   8
#define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
/* Bits 31..16 are currently unused. */

/* some convenience accessor macros */
#define ARM_TBFLAG_THUMB(F) \
    (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
#define ARM_TBFLAG_VECLEN(F) \
    (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
#define ARM_TBFLAG_VECSTRIDE(F) \
    (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
#define ARM_TBFLAG_PRIV(F) \
    (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
#define ARM_TBFLAG_VFPEN(F) \
    (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
#define ARM_TBFLAG_CONDEXEC(F) \
    (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)

static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    int privmode;
    *pc = env->regs[15];
    *cs_base = 0;
    *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
        | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
        | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
        | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
    if (arm_feature(env, ARM_FEATURE_M)) {
        privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
    } else {
        privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
    }
    if (privmode) {
        *flags |= ARM_TBFLAG_PRIV_MASK;
    }
    if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
        *flags |= ARM_TBFLAG_VFPEN_MASK;
    }
}

static inline bool cpu_has_work(CPUState *env)
{
    return env->interrupt_request &
        (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}

#include "exec-all.h"

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
    env->regs[15] = tb->pc;
}

#endif
Commit	Line	Data
2c0262af FB	1	/*
2c0262af FB	2	* ARM virtual CPU header
5fafdf24	3	*
2c0262af FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af FB	18	*/
	19	#ifndef CPU_ARM_H
	20	#define CPU_ARM_H
	21
3cf1e035 FB	22	#define TARGET_LONG_BITS 32
3cf1e035 FB	23
9042c0e2 TS	24	#define ELF_MACHINE EM_ARM
9042c0e2 TS	25
c2764719 PB	26	#define CPUState struct CPUARMState
c2764719 PB	27
9a78eead SW	28	#include "config.h"
9a78eead SW	29	#include "qemu-common.h"
2c0262af FB	30	#include "cpu-defs.h"
2c0262af FB	31
53cd6637 FB	32	#include "softfloat.h"
53cd6637 FB	33
1fddef4b FB	34	#define TARGET_HAS_ICE 1
1fddef4b FB	35
b8a9e8f1 FB	36	#define EXCP_UDEF 1 /* undefined instruction */
	37	#define EXCP_SWI 2 /* software interrupt */
	38	#define EXCP_PREFETCH_ABORT 3
	39	#define EXCP_DATA_ABORT 4
b5ff1b31 FB	40	#define EXCP_IRQ 5
b5ff1b31 FB	41	#define EXCP_FIQ 6
06c949e6	42	#define EXCP_BKPT 7
9ee6e8bb	43	#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
fbb4a2e3	44	#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
426f5abc	45	#define EXCP_STREX 10
9ee6e8bb PB	46
	47	#define ARMV7M_EXCP_RESET 1
	48	#define ARMV7M_EXCP_NMI 2
	49	#define ARMV7M_EXCP_HARD 3
	50	#define ARMV7M_EXCP_MEM 4
	51	#define ARMV7M_EXCP_BUS 5
	52	#define ARMV7M_EXCP_USAGE 6
	53	#define ARMV7M_EXCP_SVC 11
	54	#define ARMV7M_EXCP_DEBUG 12
	55	#define ARMV7M_EXCP_PENDSV 14
	56	#define ARMV7M_EXCP_SYSTICK 15
2c0262af	57
403946c0 RH	58	/* ARM-specific interrupt pending bits. */
	59	#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
	60
	61
c1713132 AZ	62	typedef void ARMWriteCPFunc(void *opaque, int cp_info,
	63	int srcreg, int operand, uint32_t value);
	64	typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
	65	int dstreg, int operand);
	66
f93eb9ff AZ	67	struct arm_boot_info;
f93eb9ff AZ	68
6ebbf390 JM	69	#define NB_MMU_MODES 2
6ebbf390 JM	70
b7bcbe95 FB	71	/* We currently assume float and double are IEEE single and double
	72	precision respectively.
	73	Doing runtime conversions is tricky because VFP registers may contain
	74	integer values (eg. as the result of a FTOSI instruction).
8e96005d FB	75	s<2n> maps to the least significant half of d<n>
	76	s<2n+1> maps to the most significant half of d<n>
	77	*/
b7bcbe95	78
2c0262af	79	typedef struct CPUARMState {
b5ff1b31	80	/* Regs for current mode. */
2c0262af	81	uint32_t regs[16];
b5ff1b31	82	/* Frequently accessed CPSR bits are stored separately for efficiently.
d37aca66	83	This contains all the other bits. Use cpsr_{read,write} to access
b5ff1b31 FB	84	the whole CPSR. */
	85	uint32_t uncached_cpsr;
	86	uint32_t spsr;
	87
	88	/* Banked registers. */
	89	uint32_t banked_spsr[6];
	90	uint32_t banked_r13[6];
	91	uint32_t banked_r14[6];
3b46e624	92
b5ff1b31 FB	93	/* These hold r8-r12. */
	94	uint32_t usr_regs[5];
	95	uint32_t fiq_regs[5];
3b46e624	96
2c0262af FB	97	/* cpsr flag cache for faster execution */
	98	uint32_t CF; /* 0 or 1 */
	99	uint32_t VF; /* V is the bit 31. All other bits are undefined */
6fbe23d5 PB	100	uint32_t NF; /* N is bit 31. All other bits are undefined. */
6fbe23d5 PB	101	uint32_t ZF; /* Z set if zero. */
99c475ab	102	uint32_t QF; /* 0 or 1 */
9ee6e8bb	103	uint32_t GE; /* cpsr[19:16] */
b26eefb6	104	uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
9ee6e8bb	105	uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
2c0262af	106
b5ff1b31 FB	107	/* System control coprocessor (cp15) */
b5ff1b31 FB	108	struct {
40f137e1	109	uint32_t c0_cpuid;
c1713132	110	uint32_t c0_cachetype;
a49ea279 PB	111	uint32_t c0_ccsid[16]; /* Cache size. */
	112	uint32_t c0_clid; /* Cache level. */
	113	uint32_t c0_cssel; /* Cache size selection. */
9ee6e8bb PB	114	uint32_t c0_c1[8]; /* Feature registers. */
9ee6e8bb PB	115	uint32_t c0_c2[8]; /* Instruction set registers. */
b5ff1b31 FB	116	uint32_t c1_sys; /* System control register. */
b5ff1b31 FB	117	uint32_t c1_coproc; /* Coprocessor access register. */
610c3c8a	118	uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
9ee6e8bb PB	119	uint32_t c2_base0; /* MMU translation table base 0. */
9ee6e8bb PB	120	uint32_t c2_base1; /* MMU translation table base 1. */
b2fa1797 PB	121	uint32_t c2_control; /* MMU translation table base control. */
	122	uint32_t c2_mask; /* MMU translation table base selection mask. */
	123	uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
ce819861 PB	124	uint32_t c2_data; /* MPU data cachable bits. */
	125	uint32_t c2_insn; /* MPU instruction cachable bits. */
	126	uint32_t c3; /* MMU domain access control register
	127	MPU write buffer control. */
b5ff1b31 FB	128	uint32_t c5_insn; /* Fault status registers. */
b5ff1b31 FB	129	uint32_t c5_data;
ce819861	130	uint32_t c6_region[8]; /* MPU base/size registers. */
b5ff1b31 FB	131	uint32_t c6_insn; /* Fault address registers. */
b5ff1b31 FB	132	uint32_t c6_data;
f8bf8606	133	uint32_t c7_par; /* Translation result. */
b5ff1b31 FB	134	uint32_t c9_insn; /* Cache lockdown registers. */
b5ff1b31 FB	135	uint32_t c9_data;
74594c9d PM	136	uint32_t c9_pmcr; /* performance monitor control register */
	137	uint32_t c9_pmcnten; /* perf monitor counter enables */
	138	uint32_t c9_pmovsr; /* perf monitor overflow status */
	139	uint32_t c9_pmxevtyper; /* perf monitor event type */
	140	uint32_t c9_pmuserenr; /* perf monitor user enable */
	141	uint32_t c9_pminten; /* perf monitor interrupt enables */
b5ff1b31 FB	142	uint32_t c13_fcse; /* FCSE PID. */
b5ff1b31 FB	143	uint32_t c13_context; /* Context ID. */
9ee6e8bb PB	144	uint32_t c13_tls1; /* User RW Thread register. */
	145	uint32_t c13_tls2; /* User RO Thread register. */
	146	uint32_t c13_tls3; /* Privileged Thread register. */
c1713132	147	uint32_t c15_cpar; /* XScale Coprocessor Access Register */
c3d2689d AZ	148	uint32_t c15_ticonfig; /* TI925T configuration byte. */
	149	uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
	150	uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
	151	uint32_t c15_threadid; /* TI debugger thread-ID. */
b5ff1b31	152	} cp15;
40f137e1	153
9ee6e8bb PB	154	struct {
	155	uint32_t other_sp;
	156	uint32_t vecbase;
	157	uint32_t basepri;
	158	uint32_t control;
	159	int current_sp;
	160	int exception;
	161	int pending_exception;
9ee6e8bb PB	162	} v7m;
9ee6e8bb PB	163
fe1479c3 PB	164	/* Thumb-2 EE state. */
	165	uint32_t teecr;
	166	uint32_t teehbr;
	167
40f137e1 PB	168	/* Internal CPU feature flags. */
	169	uint32_t features;
	170
b7bcbe95 FB	171	/* VFP coprocessor state. */
b7bcbe95 FB	172	struct {
9ee6e8bb	173	float64 regs[32];
b7bcbe95	174
40f137e1	175	uint32_t xregs[16];
b7bcbe95 FB	176	/* We store these fpcsr fields separately for convenience. */
	177	int vec_len;
	178	int vec_stride;
	179
9ee6e8bb PB	180	/* scratch space when Tn are not sufficient. */
9ee6e8bb PB	181	uint32_t scratch[8];
3b46e624	182
3a492f3a PM	183	/* fp_status is the "normal" fp status. standard_fp_status retains
	184	* values corresponding to the ARM "Standard FPSCR Value", ie
	185	* default-NaN, flush-to-zero, round-to-nearest and is used by
	186	* any operations (generally Neon) which the architecture defines
	187	* as controlled by the standard FPSCR value rather than the FPSCR.
	188	*
	189	* To avoid having to transfer exception bits around, we simply
	190	* say that the FPSCR cumulative exception flags are the logical
	191	* OR of the flags in the two fp statuses. This relies on the
	192	* only thing which needs to read the exception flags being
	193	* an explicit FPSCR read.
	194	*/
53cd6637	195	float_status fp_status;
3a492f3a	196	float_status standard_fp_status;
b7bcbe95	197	} vfp;
426f5abc PB	198	uint32_t exclusive_addr;
	199	uint32_t exclusive_val;
	200	uint32_t exclusive_high;
9ee6e8bb	201	#if defined(CONFIG_USER_ONLY)
426f5abc PB	202	uint32_t exclusive_test;
426f5abc PB	203	uint32_t exclusive_info;
9ee6e8bb	204	#endif
b7bcbe95	205
18c9b560 AZ	206	/* iwMMXt coprocessor state. */
	207	struct {
	208	uint64_t regs[16];
	209	uint64_t val;
	210
	211	uint32_t cregs[16];
	212	} iwmmxt;
	213
ce4defa0 PB	214	#if defined(CONFIG_USER_ONLY)
	215	/* For usermode syscall translation. */
	216	int eabi;
	217	#endif
	218
a316d335 FB	219	CPU_COMMON
a316d335 FB	220
9d551997	221	/* These fields after the common ones so they are preserved on reset. */
9ba8c3f4 LM	222
	223	/* Coprocessor IO used by peripherals */
	224	struct {
	225	ARMReadCPFunc *cp_read;
	226	ARMWriteCPFunc *cp_write;
	227	void *opaque;
	228	} cp[15];
983fe826	229	void *nvic;
462a8bc6	230	const struct arm_boot_info *boot_info;
2c0262af FB	231	} CPUARMState;
2c0262af FB	232
aaed909a	233	CPUARMState cpu_arm_init(const char cpu_model);
b26eefb6	234	void arm_translate_init(void);
2c0262af FB	235	int cpu_arm_exec(CPUARMState *s);
2c0262af FB	236	void cpu_arm_close(CPUARMState *s);
b5ff1b31 FB	237	void do_interrupt(CPUARMState *);
b5ff1b31 FB	238	void switch_mode(CPUARMState *, int);
9ee6e8bb	239	uint32_t do_arm_semihosting(CPUARMState *env);
b5ff1b31	240
2c0262af FB	241	/* you can call this signal handler from your SIGBUS and SIGSEGV
	242	signal handlers to inform the virtual CPU of exceptions. non zero
	243	is returned if the signal was handled by the virtual CPU. */
5fafdf24	244	int cpu_arm_signal_handler(int host_signum, void *pinfo,
2c0262af	245	void *puc);
84a031c6 AJ	246	int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
84a031c6 AJ	247	int mmu_idx, int is_softmuu);
0b5c1ce8	248	#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
2c0262af	249
fbb4a2e3 PB	250	static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
	251	{
	252	env->cp15.c13_tls2 = newtls;
	253	}
9ee6e8bb	254
b5ff1b31 FB	255	#define CPSR_M (0x1f)
	256	#define CPSR_T (1 << 5)
	257	#define CPSR_F (1 << 6)
	258	#define CPSR_I (1 << 7)
	259	#define CPSR_A (1 << 8)
	260	#define CPSR_E (1 << 9)
	261	#define CPSR_IT_2_7 (0xfc00)
9ee6e8bb PB	262	#define CPSR_GE (0xf << 16)
9ee6e8bb PB	263	#define CPSR_RESERVED (0xf << 20)
b5ff1b31 FB	264	#define CPSR_J (1 << 24)
	265	#define CPSR_IT_0_1 (3 << 25)
	266	#define CPSR_Q (1 << 27)
9ee6e8bb PB	267	#define CPSR_V (1 << 28)
	268	#define CPSR_C (1 << 29)
	269	#define CPSR_Z (1 << 30)
	270	#define CPSR_N (1 << 31)
	271	#define CPSR_NZCV (CPSR_N \| CPSR_Z \| CPSR_C \| CPSR_V)
	272
	273	#define CPSR_IT (CPSR_IT_0_1 \| CPSR_IT_2_7)
	274	#define CACHED_CPSR_BITS (CPSR_T \| CPSR_GE \| CPSR_IT \| CPSR_Q \| CPSR_NZCV)
	275	/* Bits writable in user mode. */
	276	#define CPSR_USER (CPSR_NZCV \| CPSR_Q \| CPSR_GE)
	277	/* Execution state bits. MRS read as zero, MSR writes ignored. */
	278	#define CPSR_EXEC (CPSR_T \| CPSR_IT \| CPSR_J)
b5ff1b31	279
b5ff1b31	280	/* Return the current CPSR value. */
2f4a40e5 AZ	281	uint32_t cpsr_read(CPUARMState *env);
	282	/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
	283	void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
9ee6e8bb PB	284
	285	/* Return the current xPSR value. */
	286	static inline uint32_t xpsr_read(CPUARMState *env)
	287	{
	288	int ZF;
6fbe23d5 PB	289	ZF = (env->ZF == 0);
6fbe23d5 PB	290	return (env->NF & 0x80000000) \| (ZF << 30)
9ee6e8bb PB	291	\| (env->CF << 29) \| ((env->VF & 0x80000000) >> 3) \| (env->QF << 27)
	292	\| (env->thumb << 24) \| ((env->condexec_bits & 3) << 25)
	293	\| ((env->condexec_bits & 0xfc) << 8)
	294	\| env->v7m.exception;
b5ff1b31 FB	295	}
b5ff1b31 FB	296
9ee6e8bb PB	297	/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
	298	static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
	299	{
9ee6e8bb	300	if (mask & CPSR_NZCV) {
6fbe23d5 PB	301	env->ZF = (~val) & CPSR_Z;
6fbe23d5 PB	302	env->NF = val;
9ee6e8bb PB	303	env->CF = (val >> 29) & 1;
	304	env->VF = (val << 3) & 0x80000000;
	305	}
	306	if (mask & CPSR_Q)
	307	env->QF = ((val & CPSR_Q) != 0);
	308	if (mask & (1 << 24))
	309	env->thumb = ((val & (1 << 24)) != 0);
	310	if (mask & CPSR_IT_0_1) {
	311	env->condexec_bits &= ~3;
	312	env->condexec_bits \|= (val >> 25) & 3;
	313	}
	314	if (mask & CPSR_IT_2_7) {
	315	env->condexec_bits &= 3;
	316	env->condexec_bits \|= (val >> 8) & 0xfc;
	317	}
	318	if (mask & 0x1ff) {
	319	env->v7m.exception = val & 0x1ff;
	320	}
	321	}
	322
01653295 PM	323	/* Return the current FPSCR value. */
	324	uint32_t vfp_get_fpscr(CPUARMState *env);
	325	void vfp_set_fpscr(CPUARMState *env, uint32_t val);
	326
b5ff1b31 FB	327	enum arm_cpu_mode {
	328	ARM_CPU_MODE_USR = 0x10,
	329	ARM_CPU_MODE_FIQ = 0x11,
	330	ARM_CPU_MODE_IRQ = 0x12,
	331	ARM_CPU_MODE_SVC = 0x13,
	332	ARM_CPU_MODE_ABT = 0x17,
	333	ARM_CPU_MODE_UND = 0x1b,
	334	ARM_CPU_MODE_SYS = 0x1f
	335	};
	336
40f137e1 PB	337	/* VFP system registers. */
	338	#define ARM_VFP_FPSID 0
	339	#define ARM_VFP_FPSCR 1
9ee6e8bb PB	340	#define ARM_VFP_MVFR1 6
9ee6e8bb PB	341	#define ARM_VFP_MVFR0 7
40f137e1 PB	342	#define ARM_VFP_FPEXC 8
	343	#define ARM_VFP_FPINST 9
	344	#define ARM_VFP_FPINST2 10
	345
18c9b560 AZ	346	/* iwMMXt coprocessor control registers. */
	347	#define ARM_IWMMXT_wCID 0
	348	#define ARM_IWMMXT_wCon 1
	349	#define ARM_IWMMXT_wCSSF 2
	350	#define ARM_IWMMXT_wCASF 3
	351	#define ARM_IWMMXT_wCGR0 8
	352	#define ARM_IWMMXT_wCGR1 9
	353	#define ARM_IWMMXT_wCGR2 10
	354	#define ARM_IWMMXT_wCGR3 11
	355
40f137e1 PB	356	enum arm_features {
40f137e1 PB	357	ARM_FEATURE_VFP,
c1713132 AZ	358	ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
c1713132 AZ	359	ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ce819861	360	ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
9ee6e8bb PB	361	ARM_FEATURE_V6,
	362	ARM_FEATURE_V6K,
	363	ARM_FEATURE_V7,
	364	ARM_FEATURE_THUMB2,
c3d2689d	365	ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
9ee6e8bb	366	ARM_FEATURE_VFP3,
60011498	367	ARM_FEATURE_VFP_FP16,
9ee6e8bb PB	368	ARM_FEATURE_NEON,
	369	ARM_FEATURE_DIV,
	370	ARM_FEATURE_M, /* Microcontroller profile. */
fe1479c3	371	ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
e1bbf446	372	ARM_FEATURE_THUMB2EE,
be5e7a76 DES	373	ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
	374	ARM_FEATURE_V4T,
	375	ARM_FEATURE_V5,
5bc95aa2	376	ARM_FEATURE_STRONGARM,
40f137e1 PB	377	};
	378
	379	static inline int arm_feature(CPUARMState *env, int feature)
	380	{
	381	return (env->features & (1u << feature)) != 0;
	382	}
	383
9a78eead	384	void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
40f137e1	385
9ee6e8bb PB	386	/* Interface between CPU and Interrupt controller. */
	387	void armv7m_nvic_set_pending(void *opaque, int irq);
	388	int armv7m_nvic_acknowledge_irq(void *opaque);
	389	void armv7m_nvic_complete_irq(void *opaque, int irq);
	390
c1713132 AZ	391	void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
	392	ARMReadCPFunc cp_read, ARMWriteCPFunc cp_write,
	393	void *opaque);
	394
9ee6e8bb PB	395	/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
	396	Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
	397	conventional cores (ie. Application or Realtime profile). */
	398
	399	#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
	400	#define ARM_CPUID(env) (env->cp15.c0_cpuid)
	401
	402	#define ARM_CPUID_ARM1026 0x4106a262
	403	#define ARM_CPUID_ARM926 0x41069265
	404	#define ARM_CPUID_ARM946 0x41059461
	405	#define ARM_CPUID_TI915T 0x54029152
	406	#define ARM_CPUID_TI925T 0x54029252
5bc95aa2 DES	407	#define ARM_CPUID_SA1100 0x4401A11B
5bc95aa2 DES	408	#define ARM_CPUID_SA1110 0x6901B119
9ee6e8bb PB	409	#define ARM_CPUID_PXA250 0x69052100
	410	#define ARM_CPUID_PXA255 0x69052d00
	411	#define ARM_CPUID_PXA260 0x69052903
	412	#define ARM_CPUID_PXA261 0x69052d05
	413	#define ARM_CPUID_PXA262 0x69052d06
	414	#define ARM_CPUID_PXA270 0x69054110
	415	#define ARM_CPUID_PXA270_A0 0x69054110
	416	#define ARM_CPUID_PXA270_A1 0x69054111
	417	#define ARM_CPUID_PXA270_B0 0x69054112
	418	#define ARM_CPUID_PXA270_B1 0x69054113
	419	#define ARM_CPUID_PXA270_C0 0x69054114
	420	#define ARM_CPUID_PXA270_C5 0x69054117
	421	#define ARM_CPUID_ARM1136 0x4117b363
827df9f3	422	#define ARM_CPUID_ARM1136_R2 0x4107b362
9ee6e8bb PB	423	#define ARM_CPUID_ARM11MPCORE 0x410fb022
9ee6e8bb PB	424	#define ARM_CPUID_CORTEXA8 0x410fc080
10055562	425	#define ARM_CPUID_CORTEXA9 0x410fc090
9ee6e8bb PB	426	#define ARM_CPUID_CORTEXM3 0x410fc231
9ee6e8bb PB	427	#define ARM_CPUID_ANY 0xffffffff
40f137e1	428
b5ff1b31	429	#if defined(CONFIG_USER_ONLY)
2c0262af	430	#define TARGET_PAGE_BITS 12
b5ff1b31 FB	431	#else
	432	/* The ARM MMU allows 1k pages. */
	433	/* ??? Linux doesn't actually use these, and they're deprecated in recent
82d17978	434	architecture revisions. Maybe a configure option to disable them. */
b5ff1b31 FB	435	#define TARGET_PAGE_BITS 10
b5ff1b31 FB	436	#endif
9467d44c	437
52705890 RH	438	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	439	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	440
9467d44c TS	441	#define cpu_init cpu_arm_init
	442	#define cpu_exec cpu_arm_exec
	443	#define cpu_gen_code cpu_arm_gen_code
	444	#define cpu_signal_handler cpu_arm_signal_handler
c732abe2	445	#define cpu_list arm_cpu_list
9467d44c	446
74594c9d	447	#define CPU_SAVE_VERSION 4
9ee6e8bb	448
6ebbf390 JM	449	/* MMU modes definitions */
	450	#define MMU_MODE0_SUFFIX _kernel
	451	#define MMU_MODE1_SUFFIX _user
	452	#define MMU_USER_IDX 1
	453	static inline int cpu_mmu_index (CPUState *env)
	454	{
	455	return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
	456	}
	457
6e68e076 PB	458	#if defined(CONFIG_USER_ONLY)
	459	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
	460	{
f8ed7070	461	if (newsp)
6e68e076 PB	462	env->regs[13] = newsp;
	463	env->regs[0] = 0;
	464	}
	465	#endif
	466
2c0262af	467	#include "cpu-all.h"
622ed360	468
a1705768 PM	469	/* Bit usage in the TB flags field: */
	470	#define ARM_TBFLAG_THUMB_SHIFT 0
	471	#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
	472	#define ARM_TBFLAG_VECLEN_SHIFT 1
	473	#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
	474	#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
	475	#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
	476	#define ARM_TBFLAG_PRIV_SHIFT 6
	477	#define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
	478	#define ARM_TBFLAG_VFPEN_SHIFT 7
	479	#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
	480	#define ARM_TBFLAG_CONDEXEC_SHIFT 8
	481	#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
	482	/* Bits 31..16 are currently unused. */
	483
	484	/* some convenience accessor macros */
	485	#define ARM_TBFLAG_THUMB(F) \
	486	(((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
	487	#define ARM_TBFLAG_VECLEN(F) \
	488	(((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
	489	#define ARM_TBFLAG_VECSTRIDE(F) \
	490	(((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
	491	#define ARM_TBFLAG_PRIV(F) \
	492	(((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
	493	#define ARM_TBFLAG_VFPEN(F) \
	494	(((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
	495	#define ARM_TBFLAG_CONDEXEC(F) \
	496	(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
	497
6b917547 AL	498	static inline void cpu_get_tb_cpu_state(CPUState env, target_ulong pc,
	499	target_ulong cs_base, int flags)
	500	{
05ed9a99	501	int privmode;
6b917547 AL	502	*pc = env->regs[15];
6b917547 AL	503	*cs_base = 0;
a1705768 PM	504	*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
	505	\| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
	506	\| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
	507	\| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
05ed9a99 PM	508	if (arm_feature(env, ARM_FEATURE_M)) {
	509	privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
	510	} else {
	511	privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
	512	}
	513	if (privmode) {
a1705768 PM	514	*flags \|= ARM_TBFLAG_PRIV_MASK;
	515	}
	516	if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
	517	*flags \|= ARM_TBFLAG_VFPEN_MASK;
	518	}
6b917547 AL	519	}
6b917547 AL	520
f081c76c BS	521	static inline bool cpu_has_work(CPUState *env)
	522	{
	523	return env->interrupt_request &
	524	(CPU_INTERRUPT_FIQ \| CPU_INTERRUPT_HARD \| CPU_INTERRUPT_EXITTB);
	525	}
	526
	527	#include "exec-all.h"
	528
	529	static inline void cpu_pc_from_tb(CPUState env, TranslationBlock tb)
	530	{
	531	env->regs[15] = tb->pc;
	532	}
	533
2c0262af	534	#endif