[qemu.git] / target-arm / cpu.h

/*
 * ARM virtual CPU header
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef CPU_ARM_H
#define CPU_ARM_H

#define TARGET_LONG_BITS 32

#define ELF_MACHINE	EM_ARM

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#define EXCP_UDEF            1   /* undefined instruction */
#define EXCP_SWI             2   /* software interrupt */
#define EXCP_PREFETCH_ABORT  3
#define EXCP_DATA_ABORT      4
#define EXCP_IRQ             5
#define EXCP_FIQ             6
#define EXCP_BKPT            7

typedef void ARMWriteCPFunc(void *opaque, int cp_info,
                            int srcreg, int operand, uint32_t value);
typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
                               int dstreg, int operand);

/* We currently assume float and double are IEEE single and double
   precision respectively.
   Doing runtime conversions is tricky because VFP registers may contain
   integer values (eg. as the result of a FTOSI instruction).
   s<2n> maps to the least significant half of d<n>
   s<2n+1> maps to the most significant half of d<n>
 */

typedef struct CPUARMState {
    /* Regs for current mode.  */
    uint32_t regs[16];
    /* Frequently accessed CPSR bits are stored separately for efficiently.
       This contains all the other bits.  Use cpsr_{read,write} to access
       the whole CPSR.  */
    uint32_t uncached_cpsr;
    uint32_t spsr;

    /* Banked registers.  */
    uint32_t banked_spsr[6];
    uint32_t banked_r13[6];
    uint32_t banked_r14[6];
   
    /* These hold r8-r12.  */
    uint32_t usr_regs[5];
    uint32_t fiq_regs[5];
   
    /* cpsr flag cache for faster execution */
    uint32_t CF; /* 0 or 1 */
    uint32_t VF; /* V is the bit 31. All other bits are undefined */
    uint32_t NZF; /* N is bit 31. Z is computed from NZF */
    uint32_t QF; /* 0 or 1 */

    int thumb; /* 0 = arm mode, 1 = thumb mode */

    /* System control coprocessor (cp15) */
    struct {
        uint32_t c0_cpuid;
        uint32_t c0_cachetype;
        uint32_t c1_sys; /* System control register.  */
        uint32_t c1_coproc; /* Coprocessor access register.  */
        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
        uint32_t c2_base; /* MMU translation table base.  */
        uint32_t c2_data; /* MPU data cachable bits.  */
        uint32_t c2_insn; /* MPU instruction cachable bits.  */
        uint32_t c3; /* MMU domain access control register
                        MPU write buffer control.  */
        uint32_t c5_insn; /* Fault status registers.  */
        uint32_t c5_data;
        uint32_t c6_region[8]; /* MPU base/size registers.  */
        uint32_t c6_insn; /* Fault address registers.  */
        uint32_t c6_data;
        uint32_t c9_insn; /* Cache lockdown registers.  */
        uint32_t c9_data;
        uint32_t c13_fcse; /* FCSE PID.  */
        uint32_t c13_context; /* Context ID.  */
        uint32_t c15_cpar; /* XScale Coprocessor Access Register */
        uint32_t c15_ticonfig; /* TI925T configuration byte.  */
        uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
        uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
        uint32_t c15_threadid; /* TI debugger thread-ID.  */
    } cp15;

    /* Coprocessor IO used by peripherals */
    struct {
        ARMReadCPFunc *cp_read;
        ARMWriteCPFunc *cp_write;
        void *opaque;
    } cp[15];

    /* Internal CPU feature flags.  */
    uint32_t features;

    /* exception/interrupt handling */
    jmp_buf jmp_env;
    int exception_index;
    int interrupt_request;
    int user_mode_only;
    int halted;

    /* VFP coprocessor state.  */
    struct {
        float64 regs[16];

        uint32_t xregs[16];
        /* We store these fpcsr fields separately for convenience.  */
        int vec_len;
        int vec_stride;

        /* Temporary variables if we don't have spare fp regs.  */
        float32 tmp0s, tmp1s;
        float64 tmp0d, tmp1d;
       
        float_status fp_status;
    } vfp;

    /* iwMMXt coprocessor state.  */
    struct {
        uint64_t regs[16];
        uint64_t val;

        uint32_t cregs[16];
    } iwmmxt;

#if defined(CONFIG_USER_ONLY)
    /* For usermode syscall translation.  */
    int eabi;
#endif

    CPU_COMMON

    /* These fields after the common ones so they are preserved on reset.  */
    int ram_size;
    const char *kernel_filename;
    const char *kernel_cmdline;
    const char *initrd_filename;
    int board_id;
    target_phys_addr_t loader_start;
} CPUARMState;

CPUARMState *cpu_arm_init(void);
int cpu_arm_exec(CPUARMState *s);
void cpu_arm_close(CPUARMState *s);
void do_interrupt(CPUARMState *);
void switch_mode(CPUARMState *, int);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_arm_signal_handler(int host_signum, void *pinfo,
                           void *puc);

#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)
#define CPSR_F (1 << 6)
#define CPSR_I (1 << 7)
#define CPSR_A (1 << 8)
#define CPSR_E (1 << 9)
#define CPSR_IT_2_7 (0xfc00)
/* Bits 20-23 reserved.  */
#define CPSR_J (1 << 24)
#define CPSR_IT_0_1 (3 << 25)
#define CPSR_Q (1 << 27)
#define CPSR_NZCV (0xf << 28)

#define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
/* Return the current CPSR value.  */
static inline uint32_t cpsr_read(CPUARMState *env)
{
    int ZF;
    ZF = (env->NZF == 0);
    return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
        (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 5);
}

/* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    /* NOTE: N = 1 and Z = 1 cannot be stored currently */
    if (mask & CPSR_NZCV) {
        env->NZF = (val & 0xc0000000) ^ 0x40000000;
        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & CPSR_T)
        env->thumb = ((val & CPSR_T) != 0);

    if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
        switch_mode(env, val & CPSR_M);
    }
    mask &= ~CACHED_CPSR_BITS;
    env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}

enum arm_cpu_mode {
  ARM_CPU_MODE_USR = 0x10,
  ARM_CPU_MODE_FIQ = 0x11,
  ARM_CPU_MODE_IRQ = 0x12,
  ARM_CPU_MODE_SVC = 0x13,
  ARM_CPU_MODE_ABT = 0x17,
  ARM_CPU_MODE_UND = 0x1b,
  ARM_CPU_MODE_SYS = 0x1f
};

/* VFP system registers.  */
#define ARM_VFP_FPSID   0
#define ARM_VFP_FPSCR   1
#define ARM_VFP_FPEXC   8
#define ARM_VFP_FPINST  9
#define ARM_VFP_FPINST2 10

/* iwMMXt coprocessor control registers.  */
#define ARM_IWMMXT_wCID		0
#define ARM_IWMMXT_wCon		1
#define ARM_IWMMXT_wCSSF	2
#define ARM_IWMMXT_wCASF	3
#define ARM_IWMMXT_wCGR0	8
#define ARM_IWMMXT_wCGR1	9
#define ARM_IWMMXT_wCGR2	10
#define ARM_IWMMXT_wCGR3	11

enum arm_features {
    ARM_FEATURE_VFP,
    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
    ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
};

static inline int arm_feature(CPUARMState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void arm_cpu_list(void);
void cpu_arm_set_model(CPUARMState *env, const char *name);

void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
                       ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
                       void *opaque);

#define ARM_CPUID_ARM1026   0x4106a262
#define ARM_CPUID_ARM926    0x41069265
#define ARM_CPUID_ARM946    0x41059461
#define ARM_CPUID_TI915T    0x54029152
#define ARM_CPUID_TI925T    0x54029252
#define ARM_CPUID_PXA250    0x69052100
#define ARM_CPUID_PXA255    0x69052d00
#define ARM_CPUID_PXA260    0x69052903
#define ARM_CPUID_PXA261    0x69052d05
#define ARM_CPUID_PXA262    0x69052d06
#define ARM_CPUID_PXA270    0x69054110
#define ARM_CPUID_PXA270_A0 0x69054110
#define ARM_CPUID_PXA270_A1 0x69054111
#define ARM_CPUID_PXA270_B0 0x69054112
#define ARM_CPUID_PXA270_B1 0x69054113
#define ARM_CPUID_PXA270_C0 0x69054114
#define ARM_CPUID_PXA270_C5 0x69054117

#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
#else
/* The ARM MMU allows 1k pages.  */
/* ??? Linux doesn't actually use these, and they're deprecated in recent
   architecture revisions.  Maybe a configure option to disable them.  */
#define TARGET_PAGE_BITS 10
#endif

#define CPUState CPUARMState
#define cpu_init cpu_arm_init
#define cpu_exec cpu_arm_exec
#define cpu_gen_code cpu_arm_gen_code
#define cpu_signal_handler cpu_arm_signal_handler

#include "cpu-all.h"

#endif
Commit	Line	Data
2c0262af FB	1	/*
2c0262af FB	2	* ARM virtual CPU header
5fafdf24	3	*
2c0262af FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef CPU_ARM_H
	21	#define CPU_ARM_H
	22
3cf1e035 FB	23	#define TARGET_LONG_BITS 32
3cf1e035 FB	24
9042c0e2 TS	25	#define ELF_MACHINE EM_ARM
9042c0e2 TS	26
2c0262af FB	27	#include "cpu-defs.h"
2c0262af FB	28
53cd6637 FB	29	#include "softfloat.h"
53cd6637 FB	30
1fddef4b FB	31	#define TARGET_HAS_ICE 1
1fddef4b FB	32
b8a9e8f1 FB	33	#define EXCP_UDEF 1 /* undefined instruction */
	34	#define EXCP_SWI 2 /* software interrupt */
	35	#define EXCP_PREFETCH_ABORT 3
	36	#define EXCP_DATA_ABORT 4
b5ff1b31 FB	37	#define EXCP_IRQ 5
b5ff1b31 FB	38	#define EXCP_FIQ 6
06c949e6	39	#define EXCP_BKPT 7
2c0262af	40
c1713132 AZ	41	typedef void ARMWriteCPFunc(void *opaque, int cp_info,
	42	int srcreg, int operand, uint32_t value);
	43	typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
	44	int dstreg, int operand);
	45
b7bcbe95 FB	46	/* We currently assume float and double are IEEE single and double
	47	precision respectively.
	48	Doing runtime conversions is tricky because VFP registers may contain
	49	integer values (eg. as the result of a FTOSI instruction).
8e96005d FB	50	s<2n> maps to the least significant half of d<n>
	51	s<2n+1> maps to the most significant half of d<n>
	52	*/
b7bcbe95	53
2c0262af	54	typedef struct CPUARMState {
b5ff1b31	55	/* Regs for current mode. */
2c0262af	56	uint32_t regs[16];
b5ff1b31	57	/* Frequently accessed CPSR bits are stored separately for efficiently.
d37aca66	58	This contains all the other bits. Use cpsr_{read,write} to access
b5ff1b31 FB	59	the whole CPSR. */
	60	uint32_t uncached_cpsr;
	61	uint32_t spsr;
	62
	63	/* Banked registers. */
	64	uint32_t banked_spsr[6];
	65	uint32_t banked_r13[6];
	66	uint32_t banked_r14[6];
5fafdf24	67
b5ff1b31 FB	68	/* These hold r8-r12. */
	69	uint32_t usr_regs[5];
	70	uint32_t fiq_regs[5];
5fafdf24	71
2c0262af FB	72	/* cpsr flag cache for faster execution */
	73	uint32_t CF; /* 0 or 1 */
	74	uint32_t VF; /* V is the bit 31. All other bits are undefined */
	75	uint32_t NZF; /* N is bit 31. Z is computed from NZF */
99c475ab FB	76	uint32_t QF; /* 0 or 1 */
	77
	78	int thumb; /* 0 = arm mode, 1 = thumb mode */
2c0262af	79
b5ff1b31 FB	80	/* System control coprocessor (cp15) */
b5ff1b31 FB	81	struct {
40f137e1	82	uint32_t c0_cpuid;
c1713132	83	uint32_t c0_cachetype;
b5ff1b31 FB	84	uint32_t c1_sys; /* System control register. */
b5ff1b31 FB	85	uint32_t c1_coproc; /* Coprocessor access register. */
610c3c8a	86	uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
ce819861 PB	87	uint32_t c2_base; /* MMU translation table base. */
	88	uint32_t c2_data; /* MPU data cachable bits. */
	89	uint32_t c2_insn; /* MPU instruction cachable bits. */
	90	uint32_t c3; /* MMU domain access control register
	91	MPU write buffer control. */
b5ff1b31 FB	92	uint32_t c5_insn; /* Fault status registers. */
b5ff1b31 FB	93	uint32_t c5_data;
ce819861	94	uint32_t c6_region[8]; /* MPU base/size registers. */
b5ff1b31 FB	95	uint32_t c6_insn; /* Fault address registers. */
	96	uint32_t c6_data;
	97	uint32_t c9_insn; /* Cache lockdown registers. */
	98	uint32_t c9_data;
	99	uint32_t c13_fcse; /* FCSE PID. */
	100	uint32_t c13_context; /* Context ID. */
c1713132	101	uint32_t c15_cpar; /* XScale Coprocessor Access Register */
c3d2689d AZ	102	uint32_t c15_ticonfig; /* TI925T configuration byte. */
	103	uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
	104	uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
	105	uint32_t c15_threadid; /* TI debugger thread-ID. */
b5ff1b31	106	} cp15;
40f137e1	107
c1713132 AZ	108	/* Coprocessor IO used by peripherals */
	109	struct {
	110	ARMReadCPFunc *cp_read;
	111	ARMWriteCPFunc *cp_write;
	112	void *opaque;
	113	} cp[15];
	114
40f137e1 PB	115	/* Internal CPU feature flags. */
	116	uint32_t features;
	117
2c0262af FB	118	/* exception/interrupt handling */
	119	jmp_buf jmp_env;
	120	int exception_index;
	121	int interrupt_request;
2c0262af	122	int user_mode_only;
9332f9da	123	int halted;
2c0262af	124
b7bcbe95 FB	125	/* VFP coprocessor state. */
b7bcbe95 FB	126	struct {
8e96005d	127	float64 regs[16];
b7bcbe95	128
40f137e1	129	uint32_t xregs[16];
b7bcbe95 FB	130	/* We store these fpcsr fields separately for convenience. */
	131	int vec_len;
	132	int vec_stride;
	133
b7bcbe95	134	/* Temporary variables if we don't have spare fp regs. */
53cd6637 FB	135	float32 tmp0s, tmp1s;
53cd6637 FB	136	float64 tmp0d, tmp1d;
5fafdf24	137
53cd6637	138	float_status fp_status;
b7bcbe95 FB	139	} vfp;
b7bcbe95 FB	140
18c9b560 AZ	141	/* iwMMXt coprocessor state. */
	142	struct {
	143	uint64_t regs[16];
	144	uint64_t val;
	145
	146	uint32_t cregs[16];
	147	} iwmmxt;
	148
ce4defa0 PB	149	#if defined(CONFIG_USER_ONLY)
	150	/* For usermode syscall translation. */
	151	int eabi;
	152	#endif
	153
a316d335 FB	154	CPU_COMMON
a316d335 FB	155
9d551997	156	/* These fields after the common ones so they are preserved on reset. */
f3d6b95e PB	157	int ram_size;
	158	const char *kernel_filename;
	159	const char *kernel_cmdline;
	160	const char *initrd_filename;
	161	int board_id;
9d551997	162	target_phys_addr_t loader_start;
2c0262af FB	163	} CPUARMState;
	164
	165	CPUARMState *cpu_arm_init(void);
	166	int cpu_arm_exec(CPUARMState *s);
	167	void cpu_arm_close(CPUARMState *s);
b5ff1b31 FB	168	void do_interrupt(CPUARMState *);
	169	void switch_mode(CPUARMState *, int);
	170
2c0262af FB	171	/* you can call this signal handler from your SIGBUS and SIGSEGV
	172	signal handlers to inform the virtual CPU of exceptions. non zero
	173	is returned if the signal was handled by the virtual CPU. */
5fafdf24	174	int cpu_arm_signal_handler(int host_signum, void *pinfo,
2c0262af FB	175	void *puc);
2c0262af FB	176
b5ff1b31 FB	177	#define CPSR_M (0x1f)
	178	#define CPSR_T (1 << 5)
	179	#define CPSR_F (1 << 6)
	180	#define CPSR_I (1 << 7)
	181	#define CPSR_A (1 << 8)
	182	#define CPSR_E (1 << 9)
	183	#define CPSR_IT_2_7 (0xfc00)
	184	/* Bits 20-23 reserved. */
	185	#define CPSR_J (1 << 24)
	186	#define CPSR_IT_0_1 (3 << 25)
	187	#define CPSR_Q (1 << 27)
	188	#define CPSR_NZCV (0xf << 28)
	189
	190	#define CACHED_CPSR_BITS (CPSR_T \| CPSR_Q \| CPSR_NZCV)
	191	/* Return the current CPSR value. */
	192	static inline uint32_t cpsr_read(CPUARMState *env)
	193	{
	194	int ZF;
	195	ZF = (env->NZF == 0);
5fafdf24	196	return env->uncached_cpsr \| (env->NZF & 0x80000000) \| (ZF << 30) \|
b5ff1b31 FB	197	(env->CF << 29) \| ((env->VF & 0x80000000) >> 3) \| (env->QF << 27)
	198	\| (env->thumb << 5);
	199	}
	200
	201	/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
	202	static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
	203	{
	204	/* NOTE: N = 1 and Z = 1 cannot be stored currently */
	205	if (mask & CPSR_NZCV) {
	206	env->NZF = (val & 0xc0000000) ^ 0x40000000;
	207	env->CF = (val >> 29) & 1;
	208	env->VF = (val << 3) & 0x80000000;
	209	}
	210	if (mask & CPSR_Q)
	211	env->QF = ((val & CPSR_Q) != 0);
	212	if (mask & CPSR_T)
	213	env->thumb = ((val & CPSR_T) != 0);
	214
	215	if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
	216	switch_mode(env, val & CPSR_M);
	217	}
	218	mask &= ~CACHED_CPSR_BITS;
	219	env->uncached_cpsr = (env->uncached_cpsr & ~mask) \| (val & mask);
	220	}
	221
	222	enum arm_cpu_mode {
	223	ARM_CPU_MODE_USR = 0x10,
	224	ARM_CPU_MODE_FIQ = 0x11,
	225	ARM_CPU_MODE_IRQ = 0x12,
	226	ARM_CPU_MODE_SVC = 0x13,
	227	ARM_CPU_MODE_ABT = 0x17,
	228	ARM_CPU_MODE_UND = 0x1b,
	229	ARM_CPU_MODE_SYS = 0x1f
	230	};
	231
40f137e1 PB	232	/* VFP system registers. */
	233	#define ARM_VFP_FPSID 0
	234	#define ARM_VFP_FPSCR 1
	235	#define ARM_VFP_FPEXC 8
	236	#define ARM_VFP_FPINST 9
	237	#define ARM_VFP_FPINST2 10
	238
18c9b560 AZ	239	/* iwMMXt coprocessor control registers. */
	240	#define ARM_IWMMXT_wCID 0
	241	#define ARM_IWMMXT_wCon 1
	242	#define ARM_IWMMXT_wCSSF 2
	243	#define ARM_IWMMXT_wCASF 3
	244	#define ARM_IWMMXT_wCGR0 8
	245	#define ARM_IWMMXT_wCGR1 9
	246	#define ARM_IWMMXT_wCGR2 10
	247	#define ARM_IWMMXT_wCGR3 11
	248
40f137e1 PB	249	enum arm_features {
40f137e1 PB	250	ARM_FEATURE_VFP,
c1713132 AZ	251	ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
c1713132 AZ	252	ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ce819861	253	ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
c3d2689d AZ	254	ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
c3d2689d AZ	255	ARM_FEATURE_OMAPCP /* OMAP specific CP15 ops handling. */
40f137e1 PB	256	};
	257
	258	static inline int arm_feature(CPUARMState *env, int feature)
	259	{
	260	return (env->features & (1u << feature)) != 0;
	261	}
	262
5adb4839	263	void arm_cpu_list(void);
3371d272	264	void cpu_arm_set_model(CPUARMState env, const char name);
40f137e1	265
c1713132 AZ	266	void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
	267	ARMReadCPFunc cp_read, ARMWriteCPFunc cp_write,
	268	void *opaque);
	269
	270	#define ARM_CPUID_ARM1026 0x4106a262
	271	#define ARM_CPUID_ARM926 0x41069265
ce819861	272	#define ARM_CPUID_ARM946 0x41059461
c3d2689d AZ	273	#define ARM_CPUID_TI915T 0x54029152
c3d2689d AZ	274	#define ARM_CPUID_TI925T 0x54029252
c1713132 AZ	275	#define ARM_CPUID_PXA250 0x69052100
	276	#define ARM_CPUID_PXA255 0x69052d00
	277	#define ARM_CPUID_PXA260 0x69052903
	278	#define ARM_CPUID_PXA261 0x69052d05
	279	#define ARM_CPUID_PXA262 0x69052d06
	280	#define ARM_CPUID_PXA270 0x69054110
	281	#define ARM_CPUID_PXA270_A0 0x69054110
	282	#define ARM_CPUID_PXA270_A1 0x69054111
	283	#define ARM_CPUID_PXA270_B0 0x69054112
	284	#define ARM_CPUID_PXA270_B1 0x69054113
	285	#define ARM_CPUID_PXA270_C0 0x69054114
	286	#define ARM_CPUID_PXA270_C5 0x69054117
40f137e1	287
b5ff1b31	288	#if defined(CONFIG_USER_ONLY)
2c0262af	289	#define TARGET_PAGE_BITS 12
b5ff1b31 FB	290	#else
	291	/* The ARM MMU allows 1k pages. */
	292	/* ??? Linux doesn't actually use these, and they're deprecated in recent
82d17978	293	architecture revisions. Maybe a configure option to disable them. */
b5ff1b31 FB	294	#define TARGET_PAGE_BITS 10
b5ff1b31 FB	295	#endif
9467d44c TS	296
	297	#define CPUState CPUARMState
	298	#define cpu_init cpu_arm_init
	299	#define cpu_exec cpu_arm_exec
	300	#define cpu_gen_code cpu_arm_gen_code
	301	#define cpu_signal_handler cpu_arm_signal_handler
	302
2c0262af FB	303	#include "cpu-all.h"
	304
	305	#endif