[qemu.git] / target-arm / cpu.h

/*
 * ARM virtual CPU header
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_ARM_H
#define CPU_ARM_H

#define TARGET_LONG_BITS 32

#define ELF_MACHINE	EM_ARM

#define CPUState struct CPUARMState

#include "config.h"
#include "qemu-common.h"
#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#define EXCP_UDEF            1   /* undefined instruction */
#define EXCP_SWI             2   /* software interrupt */
#define EXCP_PREFETCH_ABORT  3
#define EXCP_DATA_ABORT      4
#define EXCP_IRQ             5
#define EXCP_FIQ             6
#define EXCP_BKPT            7
#define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
#define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
#define EXCP_STREX          10

#define ARMV7M_EXCP_RESET   1
#define ARMV7M_EXCP_NMI     2
#define ARMV7M_EXCP_HARD    3
#define ARMV7M_EXCP_MEM     4
#define ARMV7M_EXCP_BUS     5
#define ARMV7M_EXCP_USAGE   6
#define ARMV7M_EXCP_SVC     11
#define ARMV7M_EXCP_DEBUG   12
#define ARMV7M_EXCP_PENDSV  14
#define ARMV7M_EXCP_SYSTICK 15

typedef void ARMWriteCPFunc(void *opaque, int cp_info,
                            int srcreg, int operand, uint32_t value);
typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
                               int dstreg, int operand);

struct arm_boot_info;

#define NB_MMU_MODES 2

/* We currently assume float and double are IEEE single and double
   precision respectively.
   Doing runtime conversions is tricky because VFP registers may contain
   integer values (eg. as the result of a FTOSI instruction).
   s<2n> maps to the least significant half of d<n>
   s<2n+1> maps to the most significant half of d<n>
 */

typedef struct CPUARMState {
    /* Regs for current mode.  */
    uint32_t regs[16];
    /* Frequently accessed CPSR bits are stored separately for efficiently.
       This contains all the other bits.  Use cpsr_{read,write} to access
       the whole CPSR.  */
    uint32_t uncached_cpsr;
    uint32_t spsr;

    /* Banked registers.  */
    uint32_t banked_spsr[6];
    uint32_t banked_r13[6];
    uint32_t banked_r14[6];

    /* These hold r8-r12.  */
    uint32_t usr_regs[5];
    uint32_t fiq_regs[5];

    /* cpsr flag cache for faster execution */
    uint32_t CF; /* 0 or 1 */
    uint32_t VF; /* V is the bit 31. All other bits are undefined */
    uint32_t NF; /* N is bit 31. All other bits are undefined.  */
    uint32_t ZF; /* Z set if zero.  */
    uint32_t QF; /* 0 or 1 */
    uint32_t GE; /* cpsr[19:16] */
    uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
    uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */

    /* System control coprocessor (cp15) */
    struct {
        uint32_t c0_cpuid;
        uint32_t c0_cachetype;
        uint32_t c0_ccsid[16]; /* Cache size.  */
        uint32_t c0_clid; /* Cache level.  */
        uint32_t c0_cssel; /* Cache size selection.  */
        uint32_t c0_c1[8]; /* Feature registers.  */
        uint32_t c0_c2[8]; /* Instruction set registers.  */
        uint32_t c1_sys; /* System control register.  */
        uint32_t c1_coproc; /* Coprocessor access register.  */
        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
        uint32_t c2_base0; /* MMU translation table base 0.  */
        uint32_t c2_base1; /* MMU translation table base 1.  */
        uint32_t c2_control; /* MMU translation table base control.  */
        uint32_t c2_mask; /* MMU translation table base selection mask.  */
        uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
        uint32_t c2_data; /* MPU data cachable bits.  */
        uint32_t c2_insn; /* MPU instruction cachable bits.  */
        uint32_t c3; /* MMU domain access control register
                        MPU write buffer control.  */
        uint32_t c5_insn; /* Fault status registers.  */
        uint32_t c5_data;
        uint32_t c6_region[8]; /* MPU base/size registers.  */
        uint32_t c6_insn; /* Fault address registers.  */
        uint32_t c6_data;
        uint32_t c7_par;  /* Translation result. */
        uint32_t c9_insn; /* Cache lockdown registers.  */
        uint32_t c9_data;
        uint32_t c13_fcse; /* FCSE PID.  */
        uint32_t c13_context; /* Context ID.  */
        uint32_t c13_tls1; /* User RW Thread register.  */
        uint32_t c13_tls2; /* User RO Thread register.  */
        uint32_t c13_tls3; /* Privileged Thread register.  */
        uint32_t c15_cpar; /* XScale Coprocessor Access Register */
        uint32_t c15_ticonfig; /* TI925T configuration byte.  */
        uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
        uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
        uint32_t c15_threadid; /* TI debugger thread-ID.  */
    } cp15;

    struct {
        uint32_t other_sp;
        uint32_t vecbase;
        uint32_t basepri;
        uint32_t control;
        int current_sp;
        int exception;
        int pending_exception;
    } v7m;

    /* Thumb-2 EE state.  */
    uint32_t teecr;
    uint32_t teehbr;

    /* Internal CPU feature flags.  */
    uint32_t features;

    /* VFP coprocessor state.  */
    struct {
        float64 regs[32];

        uint32_t xregs[16];
        /* We store these fpcsr fields separately for convenience.  */
        int vec_len;
        int vec_stride;

        /* scratch space when Tn are not sufficient.  */
        uint32_t scratch[8];

        /* fp_status is the "normal" fp status. standard_fp_status retains
         * values corresponding to the ARM "Standard FPSCR Value", ie
         * default-NaN, flush-to-zero, round-to-nearest and is used by
         * any operations (generally Neon) which the architecture defines
         * as controlled by the standard FPSCR value rather than the FPSCR.
         *
         * To avoid having to transfer exception bits around, we simply
         * say that the FPSCR cumulative exception flags are the logical
         * OR of the flags in the two fp statuses. This relies on the
         * only thing which needs to read the exception flags being
         * an explicit FPSCR read.
         */
        float_status fp_status;
        float_status standard_fp_status;
    } vfp;
    uint32_t exclusive_addr;
    uint32_t exclusive_val;
    uint32_t exclusive_high;
#if defined(CONFIG_USER_ONLY)
    uint32_t exclusive_test;
    uint32_t exclusive_info;
#endif

    /* iwMMXt coprocessor state.  */
    struct {
        uint64_t regs[16];
        uint64_t val;

        uint32_t cregs[16];
    } iwmmxt;

#if defined(CONFIG_USER_ONLY)
    /* For usermode syscall translation.  */
    int eabi;
#endif

    CPU_COMMON

    /* These fields after the common ones so they are preserved on reset.  */

    /* Coprocessor IO used by peripherals */
    struct {
        ARMReadCPFunc *cp_read;
        ARMWriteCPFunc *cp_write;
        void *opaque;
    } cp[15];
    void *nvic;
    struct arm_boot_info *boot_info;
} CPUARMState;

CPUARMState *cpu_arm_init(const char *cpu_model);
void arm_translate_init(void);
int cpu_arm_exec(CPUARMState *s);
void cpu_arm_close(CPUARMState *s);
void do_interrupt(CPUARMState *);
void switch_mode(CPUARMState *, int);
uint32_t do_arm_semihosting(CPUARMState *env);

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_arm_signal_handler(int host_signum, void *pinfo,
                           void *puc);
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
                              int mmu_idx, int is_softmuu);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault

static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
{
  env->cp15.c13_tls2 = newtls;
}

#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)
#define CPSR_F (1 << 6)
#define CPSR_I (1 << 7)
#define CPSR_A (1 << 8)
#define CPSR_E (1 << 9)
#define CPSR_IT_2_7 (0xfc00)
#define CPSR_GE (0xf << 16)
#define CPSR_RESERVED (0xf << 20)
#define CPSR_J (1 << 24)
#define CPSR_IT_0_1 (3 << 25)
#define CPSR_Q (1 << 27)
#define CPSR_V (1 << 28)
#define CPSR_C (1 << 29)
#define CPSR_Z (1 << 30)
#define CPSR_N (1 << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)

#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
#define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
/* Bits writable in user mode.  */
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/* Execution state bits.  MRS read as zero, MSR writes ignored.  */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)

/* Return the current CPSR value.  */
uint32_t cpsr_read(CPUARMState *env);
/* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);

/* Return the current xPSR value.  */
static inline uint32_t xpsr_read(CPUARMState *env)
{
    int ZF;
    ZF = (env->ZF == 0);
    return (env->NF & 0x80000000) | (ZF << 30)
        | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
        | ((env->condexec_bits & 0xfc) << 8)
        | env->v7m.exception;
}

/* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    if (mask & CPSR_NZCV) {
        env->ZF = (~val) & CPSR_Z;
        env->NF = val;
        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & (1 << 24))
        env->thumb = ((val & (1 << 24)) != 0);
    if (mask & CPSR_IT_0_1) {
        env->condexec_bits &= ~3;
        env->condexec_bits |= (val >> 25) & 3;
    }
    if (mask & CPSR_IT_2_7) {
        env->condexec_bits &= 3;
        env->condexec_bits |= (val >> 8) & 0xfc;
    }
    if (mask & 0x1ff) {
        env->v7m.exception = val & 0x1ff;
    }
}

/* Return the current FPSCR value.  */
uint32_t vfp_get_fpscr(CPUARMState *env);
void vfp_set_fpscr(CPUARMState *env, uint32_t val);

enum arm_cpu_mode {
  ARM_CPU_MODE_USR = 0x10,
  ARM_CPU_MODE_FIQ = 0x11,
  ARM_CPU_MODE_IRQ = 0x12,
  ARM_CPU_MODE_SVC = 0x13,
  ARM_CPU_MODE_ABT = 0x17,
  ARM_CPU_MODE_UND = 0x1b,
  ARM_CPU_MODE_SYS = 0x1f
};

/* VFP system registers.  */
#define ARM_VFP_FPSID   0
#define ARM_VFP_FPSCR   1
#define ARM_VFP_MVFR1   6
#define ARM_VFP_MVFR0   7
#define ARM_VFP_FPEXC   8
#define ARM_VFP_FPINST  9
#define ARM_VFP_FPINST2 10

/* iwMMXt coprocessor control registers.  */
#define ARM_IWMMXT_wCID		0
#define ARM_IWMMXT_wCon		1
#define ARM_IWMMXT_wCSSF	2
#define ARM_IWMMXT_wCASF	3
#define ARM_IWMMXT_wCGR0	8
#define ARM_IWMMXT_wCGR1	9
#define ARM_IWMMXT_wCGR2	10
#define ARM_IWMMXT_wCGR3	11

enum arm_features {
    ARM_FEATURE_VFP,
    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
    ARM_FEATURE_V6,
    ARM_FEATURE_V6K,
    ARM_FEATURE_V7,
    ARM_FEATURE_THUMB2,
    ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
    ARM_FEATURE_VFP3,
    ARM_FEATURE_VFP_FP16,
    ARM_FEATURE_NEON,
    ARM_FEATURE_DIV,
    ARM_FEATURE_M, /* Microcontroller profile.  */
    ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
    ARM_FEATURE_THUMB2EE,
    ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
    ARM_FEATURE_V4T,
    ARM_FEATURE_V5,
};

static inline int arm_feature(CPUARMState *env, int feature)
{
    return (env->features & (1u << feature)) != 0;
}

void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);

/* Interface between CPU and Interrupt controller.  */
void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);

void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
                       ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
                       void *opaque);

/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
   Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
   conventional cores (ie. Application or Realtime profile).  */

#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
#define ARM_CPUID(env) (env->cp15.c0_cpuid)

#define ARM_CPUID_ARM1026     0x4106a262
#define ARM_CPUID_ARM926      0x41069265
#define ARM_CPUID_ARM946      0x41059461
#define ARM_CPUID_TI915T      0x54029152
#define ARM_CPUID_TI925T      0x54029252
#define ARM_CPUID_PXA250      0x69052100
#define ARM_CPUID_PXA255      0x69052d00
#define ARM_CPUID_PXA260      0x69052903
#define ARM_CPUID_PXA261      0x69052d05
#define ARM_CPUID_PXA262      0x69052d06
#define ARM_CPUID_PXA270      0x69054110
#define ARM_CPUID_PXA270_A0   0x69054110
#define ARM_CPUID_PXA270_A1   0x69054111
#define ARM_CPUID_PXA270_B0   0x69054112
#define ARM_CPUID_PXA270_B1   0x69054113
#define ARM_CPUID_PXA270_C0   0x69054114
#define ARM_CPUID_PXA270_C5   0x69054117
#define ARM_CPUID_ARM1136     0x4117b363
#define ARM_CPUID_ARM1136_R2  0x4107b362
#define ARM_CPUID_ARM11MPCORE 0x410fb022
#define ARM_CPUID_CORTEXA8    0x410fc080
#define ARM_CPUID_CORTEXA9    0x410fc090
#define ARM_CPUID_CORTEXM3    0x410fc231
#define ARM_CPUID_ANY         0xffffffff

#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
#else
/* The ARM MMU allows 1k pages.  */
/* ??? Linux doesn't actually use these, and they're deprecated in recent
   architecture revisions.  Maybe a configure option to disable them.  */
#define TARGET_PAGE_BITS 10
#endif

#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define cpu_init cpu_arm_init
#define cpu_exec cpu_arm_exec
#define cpu_gen_code cpu_arm_gen_code
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list

#define CPU_SAVE_VERSION 3

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUState *env)
{
    return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->regs[13] = newsp;
    env->regs[0] = 0;
}
#endif

#include "cpu-all.h"

/* Bit usage in the TB flags field: */
#define ARM_TBFLAG_THUMB_SHIFT      0
#define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
#define ARM_TBFLAG_VECLEN_SHIFT     1
#define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
#define ARM_TBFLAG_VECSTRIDE_SHIFT  4
#define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
#define ARM_TBFLAG_PRIV_SHIFT       6
#define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
#define ARM_TBFLAG_VFPEN_SHIFT      7
#define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
#define ARM_TBFLAG_CONDEXEC_SHIFT   8
#define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
/* Bits 31..16 are currently unused. */

/* some convenience accessor macros */
#define ARM_TBFLAG_THUMB(F) \
    (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
#define ARM_TBFLAG_VECLEN(F) \
    (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
#define ARM_TBFLAG_VECSTRIDE(F) \
    (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
#define ARM_TBFLAG_PRIV(F) \
    (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
#define ARM_TBFLAG_VFPEN(F) \
    (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
#define ARM_TBFLAG_CONDEXEC(F) \
    (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)

static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    int privmode;
    *pc = env->regs[15];
    *cs_base = 0;
    *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
        | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
        | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
        | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
    if (arm_feature(env, ARM_FEATURE_M)) {
        privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
    } else {
        privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
    }
    if (privmode) {
        *flags |= ARM_TBFLAG_PRIV_MASK;
    }
    if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
        *flags |= ARM_TBFLAG_VFPEN_MASK;
    }
}

#endif
Commit	Line	Data
2c0262af FB	1	/*
2c0262af FB	2	* ARM virtual CPU header
5fafdf24	3	*
2c0262af FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
2c0262af FB	18	*/
	19	#ifndef CPU_ARM_H
	20	#define CPU_ARM_H
	21
3cf1e035 FB	22	#define TARGET_LONG_BITS 32
3cf1e035 FB	23
9042c0e2 TS	24	#define ELF_MACHINE EM_ARM
9042c0e2 TS	25
c2764719 PB	26	#define CPUState struct CPUARMState
c2764719 PB	27
9a78eead SW	28	#include "config.h"
9a78eead SW	29	#include "qemu-common.h"
2c0262af FB	30	#include "cpu-defs.h"
2c0262af FB	31
53cd6637 FB	32	#include "softfloat.h"
53cd6637 FB	33
1fddef4b FB	34	#define TARGET_HAS_ICE 1
1fddef4b FB	35
b8a9e8f1 FB	36	#define EXCP_UDEF 1 /* undefined instruction */
	37	#define EXCP_SWI 2 /* software interrupt */
	38	#define EXCP_PREFETCH_ABORT 3
	39	#define EXCP_DATA_ABORT 4
b5ff1b31 FB	40	#define EXCP_IRQ 5
b5ff1b31 FB	41	#define EXCP_FIQ 6
06c949e6	42	#define EXCP_BKPT 7
9ee6e8bb	43	#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
fbb4a2e3	44	#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
426f5abc	45	#define EXCP_STREX 10
9ee6e8bb PB	46
	47	#define ARMV7M_EXCP_RESET 1
	48	#define ARMV7M_EXCP_NMI 2
	49	#define ARMV7M_EXCP_HARD 3
	50	#define ARMV7M_EXCP_MEM 4
	51	#define ARMV7M_EXCP_BUS 5
	52	#define ARMV7M_EXCP_USAGE 6
	53	#define ARMV7M_EXCP_SVC 11
	54	#define ARMV7M_EXCP_DEBUG 12
	55	#define ARMV7M_EXCP_PENDSV 14
	56	#define ARMV7M_EXCP_SYSTICK 15
2c0262af	57
c1713132 AZ	58	typedef void ARMWriteCPFunc(void *opaque, int cp_info,
	59	int srcreg, int operand, uint32_t value);
	60	typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
	61	int dstreg, int operand);
	62
f93eb9ff AZ	63	struct arm_boot_info;
f93eb9ff AZ	64
6ebbf390 JM	65	#define NB_MMU_MODES 2
6ebbf390 JM	66
b7bcbe95 FB	67	/* We currently assume float and double are IEEE single and double
	68	precision respectively.
	69	Doing runtime conversions is tricky because VFP registers may contain
	70	integer values (eg. as the result of a FTOSI instruction).
8e96005d FB	71	s<2n> maps to the least significant half of d<n>
	72	s<2n+1> maps to the most significant half of d<n>
	73	*/
b7bcbe95	74
2c0262af	75	typedef struct CPUARMState {
b5ff1b31	76	/* Regs for current mode. */
2c0262af	77	uint32_t regs[16];
b5ff1b31	78	/* Frequently accessed CPSR bits are stored separately for efficiently.
d37aca66	79	This contains all the other bits. Use cpsr_{read,write} to access
b5ff1b31 FB	80	the whole CPSR. */
	81	uint32_t uncached_cpsr;
	82	uint32_t spsr;
	83
	84	/* Banked registers. */
	85	uint32_t banked_spsr[6];
	86	uint32_t banked_r13[6];
	87	uint32_t banked_r14[6];
3b46e624	88
b5ff1b31 FB	89	/* These hold r8-r12. */
	90	uint32_t usr_regs[5];
	91	uint32_t fiq_regs[5];
3b46e624	92
2c0262af FB	93	/* cpsr flag cache for faster execution */
	94	uint32_t CF; /* 0 or 1 */
	95	uint32_t VF; /* V is the bit 31. All other bits are undefined */
6fbe23d5 PB	96	uint32_t NF; /* N is bit 31. All other bits are undefined. */
6fbe23d5 PB	97	uint32_t ZF; /* Z set if zero. */
99c475ab	98	uint32_t QF; /* 0 or 1 */
9ee6e8bb	99	uint32_t GE; /* cpsr[19:16] */
b26eefb6	100	uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
9ee6e8bb	101	uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
2c0262af	102
b5ff1b31 FB	103	/* System control coprocessor (cp15) */
b5ff1b31 FB	104	struct {
40f137e1	105	uint32_t c0_cpuid;
c1713132	106	uint32_t c0_cachetype;
a49ea279 PB	107	uint32_t c0_ccsid[16]; /* Cache size. */
	108	uint32_t c0_clid; /* Cache level. */
	109	uint32_t c0_cssel; /* Cache size selection. */
9ee6e8bb PB	110	uint32_t c0_c1[8]; /* Feature registers. */
9ee6e8bb PB	111	uint32_t c0_c2[8]; /* Instruction set registers. */
b5ff1b31 FB	112	uint32_t c1_sys; /* System control register. */
b5ff1b31 FB	113	uint32_t c1_coproc; /* Coprocessor access register. */
610c3c8a	114	uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
9ee6e8bb PB	115	uint32_t c2_base0; /* MMU translation table base 0. */
9ee6e8bb PB	116	uint32_t c2_base1; /* MMU translation table base 1. */
b2fa1797 PB	117	uint32_t c2_control; /* MMU translation table base control. */
	118	uint32_t c2_mask; /* MMU translation table base selection mask. */
	119	uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
ce819861 PB	120	uint32_t c2_data; /* MPU data cachable bits. */
	121	uint32_t c2_insn; /* MPU instruction cachable bits. */
	122	uint32_t c3; /* MMU domain access control register
	123	MPU write buffer control. */
b5ff1b31 FB	124	uint32_t c5_insn; /* Fault status registers. */
b5ff1b31 FB	125	uint32_t c5_data;
ce819861	126	uint32_t c6_region[8]; /* MPU base/size registers. */
b5ff1b31 FB	127	uint32_t c6_insn; /* Fault address registers. */
b5ff1b31 FB	128	uint32_t c6_data;
f8bf8606	129	uint32_t c7_par; /* Translation result. */
b5ff1b31 FB	130	uint32_t c9_insn; /* Cache lockdown registers. */
	131	uint32_t c9_data;
	132	uint32_t c13_fcse; /* FCSE PID. */
	133	uint32_t c13_context; /* Context ID. */
9ee6e8bb PB	134	uint32_t c13_tls1; /* User RW Thread register. */
	135	uint32_t c13_tls2; /* User RO Thread register. */
	136	uint32_t c13_tls3; /* Privileged Thread register. */
c1713132	137	uint32_t c15_cpar; /* XScale Coprocessor Access Register */
c3d2689d AZ	138	uint32_t c15_ticonfig; /* TI925T configuration byte. */
	139	uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
	140	uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
	141	uint32_t c15_threadid; /* TI debugger thread-ID. */
b5ff1b31	142	} cp15;
40f137e1	143
9ee6e8bb PB	144	struct {
	145	uint32_t other_sp;
	146	uint32_t vecbase;
	147	uint32_t basepri;
	148	uint32_t control;
	149	int current_sp;
	150	int exception;
	151	int pending_exception;
9ee6e8bb PB	152	} v7m;
9ee6e8bb PB	153
fe1479c3 PB	154	/* Thumb-2 EE state. */
	155	uint32_t teecr;
	156	uint32_t teehbr;
	157
40f137e1 PB	158	/* Internal CPU feature flags. */
	159	uint32_t features;
	160
b7bcbe95 FB	161	/* VFP coprocessor state. */
b7bcbe95 FB	162	struct {
9ee6e8bb	163	float64 regs[32];
b7bcbe95	164
40f137e1	165	uint32_t xregs[16];
b7bcbe95 FB	166	/* We store these fpcsr fields separately for convenience. */
	167	int vec_len;
	168	int vec_stride;
	169
9ee6e8bb PB	170	/* scratch space when Tn are not sufficient. */
9ee6e8bb PB	171	uint32_t scratch[8];
3b46e624	172
3a492f3a PM	173	/* fp_status is the "normal" fp status. standard_fp_status retains
	174	* values corresponding to the ARM "Standard FPSCR Value", ie
	175	* default-NaN, flush-to-zero, round-to-nearest and is used by
	176	* any operations (generally Neon) which the architecture defines
	177	* as controlled by the standard FPSCR value rather than the FPSCR.
	178	*
	179	* To avoid having to transfer exception bits around, we simply
	180	* say that the FPSCR cumulative exception flags are the logical
	181	* OR of the flags in the two fp statuses. This relies on the
	182	* only thing which needs to read the exception flags being
	183	* an explicit FPSCR read.
	184	*/
53cd6637	185	float_status fp_status;
3a492f3a	186	float_status standard_fp_status;
b7bcbe95	187	} vfp;
426f5abc PB	188	uint32_t exclusive_addr;
	189	uint32_t exclusive_val;
	190	uint32_t exclusive_high;
9ee6e8bb	191	#if defined(CONFIG_USER_ONLY)
426f5abc PB	192	uint32_t exclusive_test;
426f5abc PB	193	uint32_t exclusive_info;
9ee6e8bb	194	#endif
b7bcbe95	195
18c9b560 AZ	196	/* iwMMXt coprocessor state. */
	197	struct {
	198	uint64_t regs[16];
	199	uint64_t val;
	200
	201	uint32_t cregs[16];
	202	} iwmmxt;
	203
ce4defa0 PB	204	#if defined(CONFIG_USER_ONLY)
	205	/* For usermode syscall translation. */
	206	int eabi;
	207	#endif
	208
a316d335 FB	209	CPU_COMMON
a316d335 FB	210
9d551997	211	/* These fields after the common ones so they are preserved on reset. */
9ba8c3f4 LM	212
	213	/* Coprocessor IO used by peripherals */
	214	struct {
	215	ARMReadCPFunc *cp_read;
	216	ARMWriteCPFunc *cp_write;
	217	void *opaque;
	218	} cp[15];
983fe826	219	void *nvic;
f93eb9ff	220	struct arm_boot_info *boot_info;
2c0262af FB	221	} CPUARMState;
2c0262af FB	222
aaed909a	223	CPUARMState cpu_arm_init(const char cpu_model);
b26eefb6	224	void arm_translate_init(void);
2c0262af FB	225	int cpu_arm_exec(CPUARMState *s);
2c0262af FB	226	void cpu_arm_close(CPUARMState *s);
b5ff1b31 FB	227	void do_interrupt(CPUARMState *);
b5ff1b31 FB	228	void switch_mode(CPUARMState *, int);
9ee6e8bb	229	uint32_t do_arm_semihosting(CPUARMState *env);
b5ff1b31	230
2c0262af FB	231	/* you can call this signal handler from your SIGBUS and SIGSEGV
	232	signal handlers to inform the virtual CPU of exceptions. non zero
	233	is returned if the signal was handled by the virtual CPU. */
5fafdf24	234	int cpu_arm_signal_handler(int host_signum, void *pinfo,
2c0262af	235	void *puc);
84a031c6 AJ	236	int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
84a031c6 AJ	237	int mmu_idx, int is_softmuu);
0b5c1ce8	238	#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
2c0262af	239
fbb4a2e3 PB	240	static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
	241	{
	242	env->cp15.c13_tls2 = newtls;
	243	}
9ee6e8bb	244
b5ff1b31 FB	245	#define CPSR_M (0x1f)
	246	#define CPSR_T (1 << 5)
	247	#define CPSR_F (1 << 6)
	248	#define CPSR_I (1 << 7)
	249	#define CPSR_A (1 << 8)
	250	#define CPSR_E (1 << 9)
	251	#define CPSR_IT_2_7 (0xfc00)
9ee6e8bb PB	252	#define CPSR_GE (0xf << 16)
9ee6e8bb PB	253	#define CPSR_RESERVED (0xf << 20)
b5ff1b31 FB	254	#define CPSR_J (1 << 24)
	255	#define CPSR_IT_0_1 (3 << 25)
	256	#define CPSR_Q (1 << 27)
9ee6e8bb PB	257	#define CPSR_V (1 << 28)
	258	#define CPSR_C (1 << 29)
	259	#define CPSR_Z (1 << 30)
	260	#define CPSR_N (1 << 31)
	261	#define CPSR_NZCV (CPSR_N \| CPSR_Z \| CPSR_C \| CPSR_V)
	262
	263	#define CPSR_IT (CPSR_IT_0_1 \| CPSR_IT_2_7)
	264	#define CACHED_CPSR_BITS (CPSR_T \| CPSR_GE \| CPSR_IT \| CPSR_Q \| CPSR_NZCV)
	265	/* Bits writable in user mode. */
	266	#define CPSR_USER (CPSR_NZCV \| CPSR_Q \| CPSR_GE)
	267	/* Execution state bits. MRS read as zero, MSR writes ignored. */
	268	#define CPSR_EXEC (CPSR_T \| CPSR_IT \| CPSR_J)
b5ff1b31	269
b5ff1b31	270	/* Return the current CPSR value. */
2f4a40e5 AZ	271	uint32_t cpsr_read(CPUARMState *env);
	272	/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
	273	void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
9ee6e8bb PB	274
	275	/* Return the current xPSR value. */
	276	static inline uint32_t xpsr_read(CPUARMState *env)
	277	{
	278	int ZF;
6fbe23d5 PB	279	ZF = (env->ZF == 0);
6fbe23d5 PB	280	return (env->NF & 0x80000000) \| (ZF << 30)
9ee6e8bb PB	281	\| (env->CF << 29) \| ((env->VF & 0x80000000) >> 3) \| (env->QF << 27)
	282	\| (env->thumb << 24) \| ((env->condexec_bits & 3) << 25)
	283	\| ((env->condexec_bits & 0xfc) << 8)
	284	\| env->v7m.exception;
b5ff1b31 FB	285	}
b5ff1b31 FB	286
9ee6e8bb PB	287	/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
	288	static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
	289	{
9ee6e8bb	290	if (mask & CPSR_NZCV) {
6fbe23d5 PB	291	env->ZF = (~val) & CPSR_Z;
6fbe23d5 PB	292	env->NF = val;
9ee6e8bb PB	293	env->CF = (val >> 29) & 1;
	294	env->VF = (val << 3) & 0x80000000;
	295	}
	296	if (mask & CPSR_Q)
	297	env->QF = ((val & CPSR_Q) != 0);
	298	if (mask & (1 << 24))
	299	env->thumb = ((val & (1 << 24)) != 0);
	300	if (mask & CPSR_IT_0_1) {
	301	env->condexec_bits &= ~3;
	302	env->condexec_bits \|= (val >> 25) & 3;
	303	}
	304	if (mask & CPSR_IT_2_7) {
	305	env->condexec_bits &= 3;
	306	env->condexec_bits \|= (val >> 8) & 0xfc;
	307	}
	308	if (mask & 0x1ff) {
	309	env->v7m.exception = val & 0x1ff;
	310	}
	311	}
	312
01653295 PM	313	/* Return the current FPSCR value. */
	314	uint32_t vfp_get_fpscr(CPUARMState *env);
	315	void vfp_set_fpscr(CPUARMState *env, uint32_t val);
	316
b5ff1b31 FB	317	enum arm_cpu_mode {
	318	ARM_CPU_MODE_USR = 0x10,
	319	ARM_CPU_MODE_FIQ = 0x11,
	320	ARM_CPU_MODE_IRQ = 0x12,
	321	ARM_CPU_MODE_SVC = 0x13,
	322	ARM_CPU_MODE_ABT = 0x17,
	323	ARM_CPU_MODE_UND = 0x1b,
	324	ARM_CPU_MODE_SYS = 0x1f
	325	};
	326
40f137e1 PB	327	/* VFP system registers. */
	328	#define ARM_VFP_FPSID 0
	329	#define ARM_VFP_FPSCR 1
9ee6e8bb PB	330	#define ARM_VFP_MVFR1 6
9ee6e8bb PB	331	#define ARM_VFP_MVFR0 7
40f137e1 PB	332	#define ARM_VFP_FPEXC 8
	333	#define ARM_VFP_FPINST 9
	334	#define ARM_VFP_FPINST2 10
	335
18c9b560 AZ	336	/* iwMMXt coprocessor control registers. */
	337	#define ARM_IWMMXT_wCID 0
	338	#define ARM_IWMMXT_wCon 1
	339	#define ARM_IWMMXT_wCSSF 2
	340	#define ARM_IWMMXT_wCASF 3
	341	#define ARM_IWMMXT_wCGR0 8
	342	#define ARM_IWMMXT_wCGR1 9
	343	#define ARM_IWMMXT_wCGR2 10
	344	#define ARM_IWMMXT_wCGR3 11
	345
40f137e1 PB	346	enum arm_features {
40f137e1 PB	347	ARM_FEATURE_VFP,
c1713132 AZ	348	ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
c1713132 AZ	349	ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ce819861	350	ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
9ee6e8bb PB	351	ARM_FEATURE_V6,
	352	ARM_FEATURE_V6K,
	353	ARM_FEATURE_V7,
	354	ARM_FEATURE_THUMB2,
c3d2689d	355	ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
9ee6e8bb	356	ARM_FEATURE_VFP3,
60011498	357	ARM_FEATURE_VFP_FP16,
9ee6e8bb PB	358	ARM_FEATURE_NEON,
	359	ARM_FEATURE_DIV,
	360	ARM_FEATURE_M, /* Microcontroller profile. */
fe1479c3	361	ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
e1bbf446	362	ARM_FEATURE_THUMB2EE,
be5e7a76 DES	363	ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
	364	ARM_FEATURE_V4T,
	365	ARM_FEATURE_V5,
40f137e1 PB	366	};
	367
	368	static inline int arm_feature(CPUARMState *env, int feature)
	369	{
	370	return (env->features & (1u << feature)) != 0;
	371	}
	372
9a78eead	373	void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
40f137e1	374
9ee6e8bb PB	375	/* Interface between CPU and Interrupt controller. */
	376	void armv7m_nvic_set_pending(void *opaque, int irq);
	377	int armv7m_nvic_acknowledge_irq(void *opaque);
	378	void armv7m_nvic_complete_irq(void *opaque, int irq);
	379
c1713132 AZ	380	void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
	381	ARMReadCPFunc cp_read, ARMWriteCPFunc cp_write,
	382	void *opaque);
	383
9ee6e8bb PB	384	/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
	385	Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
	386	conventional cores (ie. Application or Realtime profile). */
	387
	388	#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
	389	#define ARM_CPUID(env) (env->cp15.c0_cpuid)
	390
	391	#define ARM_CPUID_ARM1026 0x4106a262
	392	#define ARM_CPUID_ARM926 0x41069265
	393	#define ARM_CPUID_ARM946 0x41059461
	394	#define ARM_CPUID_TI915T 0x54029152
	395	#define ARM_CPUID_TI925T 0x54029252
	396	#define ARM_CPUID_PXA250 0x69052100
	397	#define ARM_CPUID_PXA255 0x69052d00
	398	#define ARM_CPUID_PXA260 0x69052903
	399	#define ARM_CPUID_PXA261 0x69052d05
	400	#define ARM_CPUID_PXA262 0x69052d06
	401	#define ARM_CPUID_PXA270 0x69054110
	402	#define ARM_CPUID_PXA270_A0 0x69054110
	403	#define ARM_CPUID_PXA270_A1 0x69054111
	404	#define ARM_CPUID_PXA270_B0 0x69054112
	405	#define ARM_CPUID_PXA270_B1 0x69054113
	406	#define ARM_CPUID_PXA270_C0 0x69054114
	407	#define ARM_CPUID_PXA270_C5 0x69054117
	408	#define ARM_CPUID_ARM1136 0x4117b363
827df9f3	409	#define ARM_CPUID_ARM1136_R2 0x4107b362
9ee6e8bb PB	410	#define ARM_CPUID_ARM11MPCORE 0x410fb022
9ee6e8bb PB	411	#define ARM_CPUID_CORTEXA8 0x410fc080
10055562	412	#define ARM_CPUID_CORTEXA9 0x410fc090
9ee6e8bb PB	413	#define ARM_CPUID_CORTEXM3 0x410fc231
9ee6e8bb PB	414	#define ARM_CPUID_ANY 0xffffffff
40f137e1	415
b5ff1b31	416	#if defined(CONFIG_USER_ONLY)
2c0262af	417	#define TARGET_PAGE_BITS 12
b5ff1b31 FB	418	#else
	419	/* The ARM MMU allows 1k pages. */
	420	/* ??? Linux doesn't actually use these, and they're deprecated in recent
82d17978	421	architecture revisions. Maybe a configure option to disable them. */
b5ff1b31 FB	422	#define TARGET_PAGE_BITS 10
b5ff1b31 FB	423	#endif
9467d44c	424
52705890 RH	425	#define TARGET_PHYS_ADDR_SPACE_BITS 32
	426	#define TARGET_VIRT_ADDR_SPACE_BITS 32
	427
9467d44c TS	428	#define cpu_init cpu_arm_init
	429	#define cpu_exec cpu_arm_exec
	430	#define cpu_gen_code cpu_arm_gen_code
	431	#define cpu_signal_handler cpu_arm_signal_handler
c732abe2	432	#define cpu_list arm_cpu_list
9467d44c	433
f8bf8606	434	#define CPU_SAVE_VERSION 3
9ee6e8bb	435
6ebbf390 JM	436	/* MMU modes definitions */
	437	#define MMU_MODE0_SUFFIX _kernel
	438	#define MMU_MODE1_SUFFIX _user
	439	#define MMU_USER_IDX 1
	440	static inline int cpu_mmu_index (CPUState *env)
	441	{
	442	return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
	443	}
	444
6e68e076 PB	445	#if defined(CONFIG_USER_ONLY)
	446	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
	447	{
f8ed7070	448	if (newsp)
6e68e076 PB	449	env->regs[13] = newsp;
	450	env->regs[0] = 0;
	451	}
	452	#endif
	453
2c0262af	454	#include "cpu-all.h"
622ed360	455
a1705768 PM	456	/* Bit usage in the TB flags field: */
	457	#define ARM_TBFLAG_THUMB_SHIFT 0
	458	#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
	459	#define ARM_TBFLAG_VECLEN_SHIFT 1
	460	#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
	461	#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
	462	#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
	463	#define ARM_TBFLAG_PRIV_SHIFT 6
	464	#define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
	465	#define ARM_TBFLAG_VFPEN_SHIFT 7
	466	#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
	467	#define ARM_TBFLAG_CONDEXEC_SHIFT 8
	468	#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
	469	/* Bits 31..16 are currently unused. */
	470
	471	/* some convenience accessor macros */
	472	#define ARM_TBFLAG_THUMB(F) \
	473	(((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
	474	#define ARM_TBFLAG_VECLEN(F) \
	475	(((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
	476	#define ARM_TBFLAG_VECSTRIDE(F) \
	477	(((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
	478	#define ARM_TBFLAG_PRIV(F) \
	479	(((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
	480	#define ARM_TBFLAG_VFPEN(F) \
	481	(((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
	482	#define ARM_TBFLAG_CONDEXEC(F) \
	483	(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
	484
6b917547 AL	485	static inline void cpu_get_tb_cpu_state(CPUState env, target_ulong pc,
	486	target_ulong cs_base, int flags)
	487	{
05ed9a99	488	int privmode;
6b917547 AL	489	*pc = env->regs[15];
6b917547 AL	490	*cs_base = 0;
a1705768 PM	491	*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
	492	\| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
	493	\| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
	494	\| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
05ed9a99 PM	495	if (arm_feature(env, ARM_FEATURE_M)) {
	496	privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
	497	} else {
	498	privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
	499	}
	500	if (privmode) {
a1705768 PM	501	*flags \|= ARM_TBFLAG_PRIV_MASK;
	502	}
	503	if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
	504	*flags \|= ARM_TBFLAG_VFPEN_MASK;
	505	}
6b917547 AL	506	}
6b917547 AL	507
2c0262af	508	#endif