[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern long gen_labels[OPC_BUF_SIZE];
extern int nb_gen_labels;
extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern target_ulong gen_opc_jump_pc[2];
extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);

#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb,
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
                      target_phys_addr_t paddr, int prot,
                      int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
                               target_phys_addr_t paddr, int prot,
                               int mmu_idx, int is_softmmu)
{
    if (prot & PAGE_READ)
        prot |= PAGE_EXEC;
    return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
}

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__ia64)
#define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)	/* range of addl */
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
#define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__)
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    uint64_t flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next;
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2];
    target_ulong page_addr[2];

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2];
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
}

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
	    (tmp & TB_JMP_ADDR_MASK));
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_flush(CPUState *env);
void tb_link_phys(TranslationBlock *tb,
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n,
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);

        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

#define ASM_OP_LABEL_NAME(n, opname) \
    ASM_NAME(__op_label) #n "." ASM_NAME(opname)

#if defined(__powerpc__)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, tbparam, n)\
do {\
    asm volatile (ASM_DATA_SECTION\
		  ASM_OP_LABEL_NAME(n, opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "b " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#elif defined(__i386__) && defined(USE_DIRECT_JUMP)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, tbparam, n)\
do {\
    asm volatile (".section .data\n"\
		  ASM_OP_LABEL_NAME(n, opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "jmp " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define GOTO_TB(opname, tbparam, n)\
do {\
    static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\
    static void __attribute__((used)) *__op_label ## n \
        __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n: ;\
dummy_label ## n: ;\
} while (0)

#endif

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#if defined(__powerpc__)
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#elif defined(__i386__)
static inline int testandset (int *p)
{
    long int readval = 0;

    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#elif defined(__x86_64__)
static inline int testandset (int *p)
{
    long int readval = 0;

    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#elif defined(__s390__)
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p)
			  : "cc", "memory" );
    return ret;
}
#elif defined(__alpha__)
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#elif defined(__sparc__)
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#elif defined(__arm__)
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));

    return ret;
}
#elif defined(__mc68000)
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret;
}
#elif defined(__ia64)

#include <ia64intrin.h>

static inline int testandset (int *p)
{
    return __sync_lock_test_and_set (p, 1);
}
#elif defined(__mips__)
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ (
	"	.set push		\n"
	"	.set noat		\n"
	"	.set mips2		\n"
	"1:	li	$1, 1		\n"
	"	ll	%0, %1		\n"
	"	sc	$1, %1		\n"
	"	beqz	$1, 1b		\n"
	"	.set pop		"
	: "=r" (ret), "+R" (*p)
	:
	: "memory");

    return ret;
}
#else
#error unimplemented CPU support
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
              void *retaddr);

#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int mmu_idx, index, pd;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = cpu_mmu_index(env);
    if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code(addr);
    }
    pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
        do_unassigned_access(addr, 0, 1, 0);
#else
        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
#endif
    }
    return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
}
#endif

#ifdef USE_KQEMU
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))

int kqemu_init(CPUState *env);
int kqemu_cpu_exec(CPUState *env);
void kqemu_flush_page(CPUState *env, target_ulong addr);
void kqemu_flush(CPUState *env, int global);
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
void kqemu_cpu_interrupt(CPUState *env);
void kqemu_record_dump(void);

static inline int kqemu_is_ok(CPUState *env)
{
    return(env->kqemu_enabled &&
           (env->cr[0] & CR0_PE_MASK) &&
           !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
           (env->eflags & IF_MASK) &&
           !(env->eflags & VM_MASK) &&
           (env->kqemu_enabled == 2 ||
            ((env->hflags & HF_CPL_MASK) == 3 &&
             (env->eflags & IOPL_MASK) != IOPL_MASK)));
}

#endif
Commit	Line	Data
d4e8164f FB	1	/*
d4e8164f FB	2	* internal execution defines for qemu
5fafdf24	3	*
d4e8164f FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
	24	/* is_jmp field values */
	25	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	26	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	27	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	28	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	29
	30	struct TranslationBlock;
	31
	32	/* XXX: make safe guess about sizes */
	33	#define MAX_OP_PER_INSTR 32
	34	#define OPC_BUF_SIZE 512
	35	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	36
	37	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	38
	39	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	40	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
c27004ec FB	41	extern long gen_labels[OPC_BUF_SIZE];
	42	extern int nb_gen_labels;
	43	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
	44	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	45	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46	46	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
c3278b7b	47	extern target_ulong gen_opc_jump_pc[2];
30d6cb84	48	extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
b346ff46	49
9886cc16 FB	50	typedef void (GenOpFunc)(void);
	51	typedef void (GenOpFunc1)(long);
	52	typedef void (GenOpFunc2)(long, long);
	53	typedef void (GenOpFunc3)(long, long, long);
3b46e624	54
b346ff46 FB	55	#if defined(TARGET_I386)
b346ff46 FB	56
33417e70	57	void optimize_flags_init(void);
d4e8164f	58
b346ff46 FB	59	#endif
	60
	61	extern FILE *logfile;
	62	extern int loglevel;
	63
4c3a88a2 FB	64	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	65	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	66	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	67	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	68	int max_code_size, int *gen_code_size_ptr);
5fafdf24	69	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	70	CPUState *env, unsigned long searched_pc,
	71	void *puc);
	72	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	73	int max_code_size, int *gen_code_size_ptr);
5fafdf24	74	int cpu_restore_state_copy(struct TranslationBlock *tb,
58fe2f10 FB	75	CPUState *env, unsigned long searched_pc,
58fe2f10 FB	76	void *puc);
2e12669a	77	void cpu_resume_from_signal(CPUState env1, void puc);
6a00d601	78	void cpu_exec_init(CPUState *env);
53a5960a	79	int page_unprotect(target_ulong address, unsigned long pc, void *puc);
5fafdf24	80	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
2e12669a	81	int is_cpu_write_access);
4390df51	82	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	83	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	84	void tlb_flush(CPUState *env, int flush_global);
5fafdf24 TS	85	int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
5fafdf24 TS	86	target_phys_addr_t paddr, int prot,
6ebbf390	87	int mmu_idx, int is_softmmu);
5fafdf24 TS	88	static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
5fafdf24 TS	89	target_phys_addr_t paddr, int prot,
6ebbf390	90	int mmu_idx, int is_softmmu)
84b7b8e7 FB	91	{
	92	if (prot & PAGE_READ)
	93	prot \|= PAGE_EXEC;
6ebbf390	94	return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
84b7b8e7	95	}
d4e8164f FB	96
	97	#define CODE_GEN_MAX_SIZE 65536
	98	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	99
4390df51 FB	100	#define CODE_GEN_PHYS_HASH_BITS 15
	101	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	102
d4e8164f	103	/* maximum total translate dcode allocated */
4390df51 FB	104
4390df51 FB	105	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	106	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	107	summary of the ranges:
	108
	109	i386 : signed 32 bits
	110	arm : signed 26 bits
	111	ppc : signed 24 bits
	112	sparc : signed 32 bits
	113	alpha : signed 23 bits
	114	*/
	115
	116	#if defined(__alpha__)
	117	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
b8076a74 FB	118	#elif defined(__ia64)
b8076a74 FB	119	#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
4390df51	120	#elif defined(__powerpc__)
c4c7e3e6	121	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51	122	#else
c98baaac	123	#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
4390df51 FB	124	#endif
4390df51 FB	125
d4e8164f FB	126	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	127
4390df51 FB	128	/* estimated block size for TB allocation */
	129	/* XXX: use a per code average code fragment size and modulate it
	130	according to the host CPU */
	131	#if defined(CONFIG_SOFTMMU)
	132	#define CODE_GEN_AVG_BLOCK_SIZE 128
	133	#else
	134	#define CODE_GEN_AVG_BLOCK_SIZE 64
	135	#endif
	136
	137	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	138
5fafdf24	139	#if defined(__powerpc__)
4390df51 FB	140	#define USE_DIRECT_JUMP
4390df51 FB	141	#endif
67b915a5	142	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	143	#define USE_DIRECT_JUMP
	144	#endif
	145
	146	typedef struct TranslationBlock {
2e12669a FB	147	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	148	target_ulong cs_base; /* CS base for this block */
c068688b	149	uint64_t flags; /* flags defining in which context the code was generated */
d4e8164f FB	150	uint16_t size; /* size of target code for this block (1 <=
d4e8164f FB	151	size <= TARGET_PAGE_SIZE) */
58fe2f10	152	uint16_t cflags; /* compile flags */
bf088061 FB	153	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	154	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	155	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	156	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	157
d4e8164f	158	uint8_t tc_ptr; / pointer to the translated code */
4390df51	159	/* next matching tb for physical address. */
5fafdf24	160	struct TranslationBlock *phys_hash_next;
4390df51 FB	161	/* first and second physical page containing code. The lower bit
4390df51 FB	162	of the pointer tells the index in page_next[] */
5fafdf24 TS	163	struct TranslationBlock *page_next[2];
5fafdf24 TS	164	target_ulong page_addr[2];
4390df51	165
d4e8164f FB	166	/* the following data are used to directly call another TB from
	167	the code of this one. */
	168	uint16_t tb_next_offset[2]; /* offset of original jump target */
	169	#ifdef USE_DIRECT_JUMP
4cbb86e1	170	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	171	#else
95f7652d	172	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	173	#endif
	174	/* list of TBs jumping to this one. This is a circular list using
	175	the two least significant bits of the pointers to tell what is
	176	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	177	jmp_first */
5fafdf24	178	struct TranslationBlock *jmp_next[2];
d4e8164f FB	179	struct TranslationBlock *jmp_first;
	180	} TranslationBlock;
	181
b362e5e0 PB	182	static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
	183	{
	184	target_ulong tmp;
	185	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	186	return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
	187	}
	188
8a40a180	189	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
d4e8164f	190	{
b362e5e0 PB	191	target_ulong tmp;
	192	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	193	return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) \|
	194	(tmp & TB_JMP_ADDR_MASK));
d4e8164f FB	195	}
d4e8164f FB	196
4390df51 FB	197	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	198	{
	199	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	200	}
	201
c27004ec	202	TranslationBlock *tb_alloc(target_ulong pc);
0124311e	203	void tb_flush(CPUState *env);
5fafdf24	204	void tb_link_phys(TranslationBlock *tb,
4390df51	205	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f	206
4390df51	207	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	208
	209	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	210	extern uint8_t *code_gen_ptr;
	211
4390df51 FB	212	#if defined(USE_DIRECT_JUMP)
	213
	214	#if defined(__powerpc__)
4cbb86e1	215	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	216	{
d4e8164f FB	217	uint32_t val, *ptr;
d4e8164f FB	218
d4e8164f FB	219	/* patch the branch destination */
4cbb86e1	220	ptr = (uint32_t *)jmp_addr;
d4e8164f	221	val = *ptr;
4cbb86e1	222	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	223	*ptr = val;
	224	/* flush icache */
	225	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	226	asm volatile ("sync" : : : "memory");
	227	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	228	asm volatile ("sync" : : : "memory");
	229	asm volatile ("isync" : : : "memory");
	230	}
4390df51 FB	231	#elif defined(__i386__)
	232	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	233	{
	234	/* patch the branch destination */
	235	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	236	/* no need to flush icache explicitely */
	237	}
	238	#endif
d4e8164f	239
5fafdf24	240	static inline void tb_set_jmp_target(TranslationBlock *tb,
4cbb86e1 FB	241	int n, unsigned long addr)
	242	{
	243	unsigned long offset;
	244
	245	offset = tb->tb_jmp_offset[n];
	246	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	247	offset = tb->tb_jmp_offset[n + 2];
	248	if (offset != 0xffff)
	249	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	250	}
	251
d4e8164f FB	252	#else
	253
	254	/* set the jump target */
5fafdf24	255	static inline void tb_set_jmp_target(TranslationBlock *tb,
d4e8164f FB	256	int n, unsigned long addr)
d4e8164f FB	257	{
95f7652d	258	tb->tb_next[n] = addr;
d4e8164f FB	259	}
	260
	261	#endif
	262
5fafdf24	263	static inline void tb_add_jump(TranslationBlock *tb, int n,
d4e8164f FB	264	TranslationBlock *tb_next)
d4e8164f FB	265	{
cf25629d FB	266	/* NOTE: this test is only needed for thread safety */
	267	if (!tb->jmp_next[n]) {
	268	/* patch the native jump address */
	269	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
3b46e624	270
cf25629d FB	271	/* add in TB jmp circular list */
	272	tb->jmp_next[n] = tb_next->jmp_first;
	273	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	274	}
d4e8164f FB	275	}
d4e8164f FB	276
a513fe19 FB	277	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	278
d4e8164f FB	279	#ifndef offsetof
	280	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	281	#endif
	282
d549f7d9 FB	283	#if defined(_WIN32)
	284	#define ASM_DATA_SECTION ".section \".data\"\n"
	285	#define ASM_PREVIOUS_SECTION ".section .text\n"
	286	#elif defined(__APPLE__)
	287	#define ASM_DATA_SECTION ".data\n"
	288	#define ASM_PREVIOUS_SECTION ".text\n"
d549f7d9 FB	289	#else
	290	#define ASM_DATA_SECTION ".section \".data\"\n"
	291	#define ASM_PREVIOUS_SECTION ".previous\n"
d549f7d9 FB	292	#endif
d549f7d9 FB	293
75913b72 FB	294	#define ASM_OP_LABEL_NAME(n, opname) \
	295	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
	296
b346ff46 FB	297	#if defined(__powerpc__)
b346ff46 FB	298
4390df51	299	/* we patch the jump instruction directly */
ae063a68	300	#define GOTO_TB(opname, tbparam, n)\
b346ff46	301	do {\
d549f7d9	302	asm volatile (ASM_DATA_SECTION\
75913b72	303	ASM_OP_LABEL_NAME(n, opname) ":\n"\
9257a9e4	304	".long 1f\n"\
d549f7d9 FB	305	ASM_PREVIOUS_SECTION \
d549f7d9 FB	306	"b " ASM_NAME(__op_jmp) #n "\n"\
9257a9e4	307	"1:\n");\
4390df51 FB	308	} while (0)
	309
	310	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
	311
	312	/* we patch the jump instruction directly */
ae063a68	313	#define GOTO_TB(opname, tbparam, n)\
c27004ec FB	314	do {\
c27004ec FB	315	asm volatile (".section .data\n"\
75913b72	316	ASM_OP_LABEL_NAME(n, opname) ":\n"\
c27004ec FB	317	".long 1f\n"\
	318	ASM_PREVIOUS_SECTION \
	319	"jmp " ASM_NAME(__op_jmp) #n "\n"\
	320	"1:\n");\
	321	} while (0)
	322
b346ff46 FB	323	#else
	324
	325	/* jump to next block operations (more portable code, does not need
	326	cache flushing, but slower because of indirect jump) */
ae063a68	327	#define GOTO_TB(opname, tbparam, n)\
b346ff46	328	do {\
6d8aa3bf AZ	329	static void __attribute__((used)) *dummy ## n = &&dummy_label ## n;\
6d8aa3bf AZ	330	static void __attribute__((used)) *__op_label ## n \
75913b72	331	__asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
b346ff46	332	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
ae063a68 FB	333	label ## n: ;\
ae063a68 FB	334	dummy_label ## n: ;\
b346ff46 FB	335	} while (0)
b346ff46 FB	336
ae063a68 FB	337	#endif
ae063a68 FB	338
33417e70 FB	339	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	340	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	341	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	342
204a1b8d	343	#if defined(__powerpc__)
d4e8164f FB	344	static inline int testandset (int *p)
	345	{
	346	int ret;
	347	__asm__ __volatile__ (
02e1ec9b FB	348	"0: lwarx %0,0,%1\n"
	349	" xor. %0,%3,%0\n"
	350	" bne 1f\n"
	351	" stwcx. %2,0,%1\n"
	352	" bne- 0b\n"
d4e8164f FB	353	"1: "
	354	: "=&r" (ret)
	355	: "r" (p), "r" (1), "r" (0)
	356	: "cr0", "memory");
	357	return ret;
	358	}
204a1b8d	359	#elif defined(__i386__)
d4e8164f FB	360	static inline int testandset (int *p)
d4e8164f FB	361	{
4955a2cd	362	long int readval = 0;
3b46e624	363
4955a2cd FB	364	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	365	: "+m" (*p), "+a" (readval)
	366	: "r" (1)
	367	: "cc");
	368	return readval;
d4e8164f	369	}
204a1b8d	370	#elif defined(__x86_64__)
bc51c5c9 FB	371	static inline int testandset (int *p)
bc51c5c9 FB	372	{
4955a2cd	373	long int readval = 0;
3b46e624	374
4955a2cd FB	375	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	376	: "+m" (*p), "+a" (readval)
	377	: "r" (1)
	378	: "cc");
	379	return readval;
bc51c5c9	380	}
204a1b8d	381	#elif defined(__s390__)
d4e8164f FB	382	static inline int testandset (int *p)
	383	{
	384	int ret;
	385
	386	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	387	" jl 0b"
	388	: "=&d" (ret)
5fafdf24	389	: "r" (1), "a" (p), "0" (*p)
d4e8164f FB	390	: "cc", "memory" );
	391	return ret;
	392	}
204a1b8d	393	#elif defined(__alpha__)
2f87c607	394	static inline int testandset (int *p)
d4e8164f FB	395	{
	396	int ret;
	397	unsigned long one;
	398
	399	__asm__ __volatile__ ("0: mov 1,%2\n"
	400	" ldl_l %0,%1\n"
	401	" stl_c %2,%1\n"
	402	" beq %2,1f\n"
	403	".subsection 2\n"
	404	"1: br 0b\n"
	405	".previous"
	406	: "=r" (ret), "=m" (*p), "=r" (one)
	407	: "m" (*p));
	408	return ret;
	409	}
204a1b8d	410	#elif defined(__sparc__)
d4e8164f FB	411	static inline int testandset (int *p)
	412	{
	413	int ret;
	414
	415	__asm__ __volatile__("ldstub [%1], %0"
	416	: "=r" (ret)
	417	: "r" (p)
	418	: "memory");
	419
	420	return (ret ? 1 : 0);
	421	}
204a1b8d	422	#elif defined(__arm__)
a95c6790 FB	423	static inline int testandset (int *spinlock)
	424	{
	425	register unsigned int ret;
	426	__asm__ __volatile__("swp %0, %1, [%2]"
	427	: "=r"(ret)
	428	: "0"(1), "r"(spinlock));
3b46e624	429
a95c6790 FB	430	return ret;
a95c6790 FB	431	}
204a1b8d	432	#elif defined(__mc68000)
38e584a0 FB	433	static inline int testandset (int *p)
	434	{
	435	char ret;
	436	__asm__ __volatile__("tas %1; sne %0"
	437	: "=r" (ret)
	438	: "m" (p)
	439	: "cc","memory");
4955a2cd	440	return ret;
38e584a0	441	}
204a1b8d	442	#elif defined(__ia64)
38e584a0	443
b8076a74 FB	444	#include <ia64intrin.h>
	445
	446	static inline int testandset (int *p)
	447	{
	448	return __sync_lock_test_and_set (p, 1);
	449	}
204a1b8d	450	#elif defined(__mips__)
c4b89d18 TS	451	static inline int testandset (int *p)
	452	{
	453	int ret;
	454
	455	__asm__ __volatile__ (
	456	" .set push \n"
	457	" .set noat \n"
	458	" .set mips2 \n"
	459	"1: li $1, 1 \n"
	460	" ll %0, %1 \n"
	461	" sc $1, %1 \n"
976a0d0d	462	" beqz $1, 1b \n"
c4b89d18 TS	463	" .set pop "
	464	: "=r" (ret), "+R" (*p)
	465	:
	466	: "memory");
	467
	468	return ret;
	469	}
204a1b8d TS	470	#else
204a1b8d TS	471	#error unimplemented CPU support
c4b89d18 TS	472	#endif
c4b89d18 TS	473
d4e8164f FB	474	typedef int spinlock_t;
	475
	476	#define SPIN_LOCK_UNLOCKED 0
	477
aebcb60e	478	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	479	static inline void spin_lock(spinlock_t *lock)
	480	{
	481	while (testandset(lock));
	482	}
	483
	484	static inline void spin_unlock(spinlock_t *lock)
	485	{
	486	*lock = 0;
	487	}
	488
	489	static inline int spin_trylock(spinlock_t *lock)
	490	{
	491	return !testandset(lock);
	492	}
3c1cf9fa FB	493	#else
	494	static inline void spin_lock(spinlock_t *lock)
	495	{
	496	}
	497
	498	static inline void spin_unlock(spinlock_t *lock)
	499	{
	500	}
	501
	502	static inline int spin_trylock(spinlock_t *lock)
	503	{
	504	return 1;
	505	}
	506	#endif
d4e8164f FB	507
	508	extern spinlock_t tb_lock;
	509
36bdbe54	510	extern int tb_invalidated_flag;
6e59c1db	511
e95c8d51	512	#if !defined(CONFIG_USER_ONLY)
6e59c1db	513
6ebbf390	514	void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
6e59c1db FB	515	void *retaddr);
6e59c1db FB	516
6ebbf390	517	#define ACCESS_TYPE (NB_MMU_MODES + 1)
6e59c1db FB	518	#define MEMSUFFIX _code
	519	#define env cpu_single_env
	520
	521	#define DATA_SIZE 1
	522	#include "softmmu_header.h"
	523
	524	#define DATA_SIZE 2
	525	#include "softmmu_header.h"
	526
	527	#define DATA_SIZE 4
	528	#include "softmmu_header.h"
	529
c27004ec FB	530	#define DATA_SIZE 8
	531	#include "softmmu_header.h"
	532
6e59c1db FB	533	#undef ACCESS_TYPE
	534	#undef MEMSUFFIX
	535	#undef env
	536
	537	#endif
4390df51 FB	538
	539	#if defined(CONFIG_USER_ONLY)
	540	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	541	{
	542	return addr;
	543	}
	544	#else
	545	/* NOTE: this function can trigger an exception */
1ccde1cb FB	546	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	547	is the offset relative to phys_ram_base */
4390df51 FB	548	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
4390df51 FB	549	{
6ebbf390	550	int mmu_idx, index, pd;
4390df51 FB	551
4390df51 FB	552	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390 JM	553	mmu_idx = cpu_mmu_index(env);
6ebbf390 JM	554	if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
4390df51	555	(addr & TARGET_PAGE_MASK), 0)) {
c27004ec FB	556	ldub_code(addr);
c27004ec FB	557	}
6ebbf390	558	pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
2a4188a3	559	if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
647de6ca	560	#if defined(TARGET_SPARC) \|\| defined(TARGET_MIPS)
6c36d3fa BS	561	do_unassigned_access(addr, 0, 1, 0);
6c36d3fa BS	562	#else
36d23958	563	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
6c36d3fa	564	#endif
4390df51	565	}
6ebbf390	566	return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
4390df51 FB	567	}
4390df51 FB	568	#endif
9df217a3	569
9df217a3	570	#ifdef USE_KQEMU
f32fc648 FB	571	#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG \| CODE_DIRTY_FLAG))
f32fc648 FB	572
9df217a3 FB	573	int kqemu_init(CPUState *env);
	574	int kqemu_cpu_exec(CPUState *env);
	575	void kqemu_flush_page(CPUState *env, target_ulong addr);
	576	void kqemu_flush(CPUState *env, int global);
4b7df22f	577	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
f32fc648	578	void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
a332e112	579	void kqemu_cpu_interrupt(CPUState *env);
f32fc648	580	void kqemu_record_dump(void);
9df217a3 FB	581
	582	static inline int kqemu_is_ok(CPUState *env)
	583	{
	584	return(env->kqemu_enabled &&
5fafdf24	585	(env->cr[0] & CR0_PE_MASK) &&
f32fc648	586	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
9df217a3	587	(env->eflags & IF_MASK) &&
f32fc648	588	!(env->eflags & VM_MASK) &&
5fafdf24	589	(env->kqemu_enabled == 2 \|\|
f32fc648 FB	590	((env->hflags & HF_CPL_MASK) == 3 &&
f32fc648 FB	591	(env->eflags & IOPL_MASK) != IOPL_MASK)));
9df217a3 FB	592	}
	593
	594	#endif