[qemu.git] / hw / pci-host / uninorth.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/ppc/mac.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"

#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
#define U3_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)

typedef struct UNINState {
    PCIHostState parent_obj;

    MemoryRegion pci_mmio;
    MemoryRegion pci_hole;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    return (((devfn >> 11) & 0x1F) + irq_num) & 3;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ctz32(reg & 0xfffff800);
        if (slot == 32) {
            slot = -1; /* XXX: should this be 0? */
        }
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    UNIN_DPRINTF("write addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
                 addr, len, val);
    pci_data_write(phb->bus,
                   unin_get_config_reg(phb->config_reg, addr),
                   val, len);
}

static uint64_t unin_data_read(void *opaque, hwaddr addr,
                               unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    uint32_t val;

    val = pci_data_read(phb->bus,
                        unin_get_config_reg(phb->config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
                 addr, len, val);
    return val;
}

static const MemoryRegionOps unin_data_ops = {
    .read = unin_data_read,
    .write = unin_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}


static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth U3 AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth internal bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic,
                      MemoryRegion *address_space_mem,
                      MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(s);
    d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
    memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x10000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, NULL,
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

#if 0
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(h->bus, PCI_DEVFN(14, 0),
                      "uni-north-internal-pci");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return h->bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(dev);
    d = U3_AGP_HOST_BRIDGE(dev);

    memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, NULL,
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(h->bus, 11 << 3, "u3-agp");

    return h->bus;
}

static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
}

static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
    /*
     * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
     * memory space with base 0x80000000, size 0x10000000 for Apple's
     * AppleMacRiscPCI driver
     */
    d->config[0x48] = 0x0;
    d->config[0x49] = 0x0;
    d->config[0x4a] = 0x0;
    d->config[0x4b] = 0x1;
}

static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
}

static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
}

static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_main_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_main_pci_host_info = {
    .name = "uni-north-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_main_pci_host_class_init,
};

static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = u3_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo u3_agp_pci_host_info = {
    .name = "u3-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = u3_agp_pci_host_class_init,
};

static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_agp_pci_host_info = {
    .name = "uni-north-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_agp_pci_host_class_init,
};

static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_internal_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_internal_pci_host_info = {
    .name = "uni-north-internal-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_internal_pci_host_class_init,
};

static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_main_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_main_info = {
    .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_main_class_init,
};

static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_u3_agp_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_u3_agp_info = {
    .name          = TYPE_U3_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_u3_agp_class_init,
};

static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_agp_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_agp_info = {
    .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_agp_class_init,
};

static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_internal_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_internal_info = {
    .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_internal_class_init,
};

static void unin_register_types(void)
{
    type_register_static(&unin_main_pci_host_info);
    type_register_static(&u3_agp_pci_host_info);
    type_register_static(&unin_agp_pci_host_info);
    type_register_static(&unin_internal_pci_host_info);

    type_register_static(&pci_unin_main_info);
    type_register_static(&pci_u3_agp_info);
    type_register_static(&pci_unin_agp_info);
    type_register_static(&pci_unin_internal_info);
}

type_init(unin_register_types)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
0d75590d	24	#include "qemu/osdep.h"
83c9f4ca PB	25	#include "hw/hw.h"
	26	#include "hw/ppc/mac.h"
	27	#include "hw/pci/pci.h"
	28	#include "hw/pci/pci_host.h"
87ecb68b	29
f3902383 BS	30	/* debug UniNorth */
	31	//#define DEBUG_UNIN
	32
	33	#ifdef DEBUG_UNIN
001faf32 BS	34	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	35	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	36	#else
001faf32	37	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	38	#endif
f3902383 BS	39
fa0be69a AG	40	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	41
57fd7b7f AF	42	#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
	43	#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
	44	#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
	45	#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
	46
	47	#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
	48	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
	49	#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
	50	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
	51	#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
	52	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
	53	#define U3_AGP_HOST_BRIDGE(obj) \
	54	OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
	55
2e29bd04	56	typedef struct UNINState {
67c332fd	57	PCIHostState parent_obj;
57fd7b7f	58
46f3069c BS	59	MemoryRegion pci_mmio;
46f3069c BS	60	MemoryRegion pci_hole;
2e29bd04	61	} UNINState;
502a5395	62
d2b59317	63	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	64	{
fa0be69a AG	65	int devfn = pci_dev->devfn & 0x00FFFFFF;
fa0be69a AG	66
9be38598	67	return (((devfn >> 11) & 0x1F) + irq_num) & 3;
d2b59317 PB	68	}
d2b59317 PB	69
5d4e84c8	70	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	71	{
5d4e84c8 JQ	72	qemu_irq *pic = opaque;
5d4e84c8 JQ	73
fa0be69a AG	74	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	75	unin_irq_line[irq_num], level);
	76	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	77	}
502a5395 PB	78
d86f0e32 AG	79	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	80	{
	81	uint32_t retval;
	82
	83	if (reg & (1u << 31)) {
	84	/* XXX OpenBIOS compatibility hack */
	85	retval = reg \| (addr & 3);
	86	} else if (reg & 1) {
	87	/* CFA1 style */
	88	retval = (reg & ~7u) \| (addr & 7);
	89	} else {
	90	uint32_t slot, func;
	91
	92	/* Grab CFA0 style values */
5863d374 SH	93	slot = ctz32(reg & 0xfffff800);
	94	if (slot == 32) {
	95	slot = -1; /* XXX: should this be 0? */
	96	}
d86f0e32 AG	97	func = (reg >> 8) & 7;
	98
	99	/* ... and then convert them to x86 format */
	100	/* config pointer */
	101	retval = (reg & (0xff - 7)) \| (addr & 7);
	102	/* slot */
	103	retval \|= slot << 11;
	104	/* fn */
	105	retval \|= func << 8;
	106	}
	107
	108
	109	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	110	reg, addr, retval);
	111
	112	return retval;
	113	}
	114
a8170e5e	115	static void unin_data_write(void *opaque, hwaddr addr,
d0ed8076	116	uint64_t val, unsigned len)
d86f0e32	117	{
d0ed8076	118	UNINState *s = opaque;
67c332fd	119	PCIHostState *phb = PCI_HOST_BRIDGE(s);
2f448e41	120	UNIN_DPRINTF("write addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
d0ed8076	121	addr, len, val);
67c332fd AF	122	pci_data_write(phb->bus,
67c332fd AF	123	unin_get_config_reg(phb->config_reg, addr),
d86f0e32 AG	124	val, len);
	125	}
	126
a8170e5e	127	static uint64_t unin_data_read(void *opaque, hwaddr addr,
d0ed8076	128	unsigned len)
d86f0e32	129	{
d0ed8076	130	UNINState *s = opaque;
67c332fd	131	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d86f0e32 AG	132	uint32_t val;
d86f0e32 AG	133
67c332fd AF	134	val = pci_data_read(phb->bus,
67c332fd AF	135	unin_get_config_reg(phb->config_reg, addr),
d86f0e32	136	len);
2f448e41	137	UNIN_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
d0ed8076	138	addr, len, val);
d86f0e32 AG	139	return val;
	140	}
	141
d0ed8076 AK	142	static const MemoryRegionOps unin_data_ops = {
	143	.read = unin_data_read,
	144	.write = unin_data_write,
	145	.endianness = DEVICE_LITTLE_ENDIAN,
	146	};
	147
81a322d4	148	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395	149	{
ff452ace	150	PCIHostState *h;
502a5395 PB	151
	152	/* Use values found on a real PowerMac */
	153	/* Uninorth main bus */
8558d942	154	h = PCI_HOST_BRIDGE(dev);
502a5395	155
40c5dce9	156	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	157	dev, "pci-conf-idx", 0x1000);
40c5dce9	158	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
d0ed8076	159	"pci-conf-data", 0x1000);
57fd7b7f AF	160	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	161	sysbus_init_mmio(dev, &h->data_mem);
2e29bd04	162
81a322d4	163	return 0;
2e29bd04 BS	164	}
2e29bd04 BS	165
d0ed8076	166
0f921197 AG	167	static int pci_u3_agp_init_device(SysBusDevice *dev)
0f921197 AG	168	{
ff452ace	169	PCIHostState *h;
0f921197 AG	170
0f921197 AG	171	/* Uninorth U3 AGP bus */
8558d942	172	h = PCI_HOST_BRIDGE(dev);
0f921197	173
40c5dce9	174	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	175	dev, "pci-conf-idx", 0x1000);
40c5dce9	176	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
d0ed8076	177	"pci-conf-data", 0x1000);
57fd7b7f AF	178	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	179	sysbus_init_mmio(dev, &h->data_mem);
0f921197	180
0f921197 AG	181	return 0;
	182	}
	183
81a322d4	184	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04	185	{
ff452ace	186	PCIHostState *h;
2e29bd04 BS	187
2e29bd04 BS	188	/* Uninorth AGP bus */
8558d942	189	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	190
40c5dce9	191	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	192	dev, "pci-conf-idx", 0x1000);
40c5dce9	193	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
57fd7b7f AF	194	dev, "pci-conf-data", 0x1000);
	195	sysbus_init_mmio(dev, &h->conf_mem);
	196	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	197	return 0;
2e29bd04 BS	198	}
2e29bd04 BS	199
81a322d4	200	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04	201	{
ff452ace	202	PCIHostState *h;
2e29bd04 BS	203
2e29bd04 BS	204	/* Uninorth internal bus */
8558d942	205	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	206
40c5dce9	207	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	208	dev, "pci-conf-idx", 0x1000);
40c5dce9	209	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
57fd7b7f AF	210	dev, "pci-conf-data", 0x1000);
	211	sysbus_init_mmio(dev, &h->conf_mem);
	212	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	213	return 0;
2e29bd04 BS	214	}
2e29bd04 BS	215
aee97b84 AK	216	PCIBus pci_pmac_init(qemu_irq pic,
	217	MemoryRegion *address_space_mem,
	218	MemoryRegion *address_space_io)
2e29bd04 BS	219	{
	220	DeviceState *dev;
	221	SysBusDevice *s;
ff452ace	222	PCIHostState *h;
2e29bd04 BS	223	UNINState *d;
	224
	225	/* Use values found on a real PowerMac */
	226	/* Uninorth main bus */
57fd7b7f	227	dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
e23a1b33	228	qdev_init_nofail(dev);
57fd7b7f	229	s = SYS_BUS_DEVICE(dev);
8558d942	230	h = PCI_HOST_BRIDGE(s);
57fd7b7f	231	d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
40c5dce9 PB	232	memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
40c5dce9 PB	233	memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
1be88255	234	0x80000000ULL, 0x10000000ULL);
46f3069c BS	235	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	236	&d->pci_hole);
	237
8a0e1104	238	h->bus = pci_register_bus(dev, NULL,
57fd7b7f AF	239	pci_unin_set_irq, pci_unin_map_irq,
	240	pic,
	241	&d->pci_mmio,
	242	address_space_io,
60a0e443	243	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
2e29bd04	244
60398748	245	#if 0
57fd7b7f	246	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
60398748	247	#endif
2e29bd04 BS	248
	249	sysbus_mmio_map(s, 0, 0xf2800000);
	250	sysbus_mmio_map(s, 1, 0xf2c00000);
	251
	252	/* DEC 21154 bridge */
	253	#if 0
	254	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
57fd7b7f	255	pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	256	#endif
	257
	258	/* Uninorth AGP bus */
57fd7b7f AF	259	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
57fd7b7f AF	260	dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
d27d06f2	261	qdev_init_nofail(dev);
57fd7b7f	262	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	263	sysbus_mmio_map(s, 0, 0xf0800000);
d27d06f2 BS	264	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	265
	266	/* Uninorth internal bus */
	267	#if 0
	268	/* XXX: not needed for now */
57fd7b7f	269	pci_create_simple(h->bus, PCI_DEVFN(14, 0),
70f9c987	270	"uni-north-internal-pci");
57fd7b7f	271	dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
d27d06f2	272	qdev_init_nofail(dev);
57fd7b7f	273	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	274	sysbus_mmio_map(s, 0, 0xf4800000);
d27d06f2 BS	275	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	276	#endif
2e29bd04 BS	277
57fd7b7f	278	return h->bus;
2e29bd04 BS	279	}
2e29bd04 BS	280
aee97b84 AK	281	PCIBus pci_pmac_u3_init(qemu_irq pic,
	282	MemoryRegion *address_space_mem,
	283	MemoryRegion *address_space_io)
0f921197 AG	284	{
	285	DeviceState *dev;
	286	SysBusDevice *s;
ff452ace	287	PCIHostState *h;
0f921197 AG	288	UNINState *d;
	289
	290	/* Uninorth AGP bus */
	291
57fd7b7f	292	dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
0f921197	293	qdev_init_nofail(dev);
57fd7b7f	294	s = SYS_BUS_DEVICE(dev);
8558d942	295	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	296	d = U3_AGP_HOST_BRIDGE(dev);
0f921197	297
40c5dce9 PB	298	memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
40c5dce9 PB	299	memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
46f3069c BS	300	0x80000000ULL, 0x70000000ULL);
	301	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	302	&d->pci_hole);
	303
8a0e1104	304	h->bus = pci_register_bus(dev, NULL,
57fd7b7f AF	305	pci_unin_set_irq, pci_unin_map_irq,
	306	pic,
	307	&d->pci_mmio,
	308	address_space_io,
60a0e443	309	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
0f921197 AG	310
	311	sysbus_mmio_map(s, 0, 0xf0800000);
	312	sysbus_mmio_map(s, 1, 0xf0c00000);
	313
57fd7b7f	314	pci_create_simple(h->bus, 11 << 3, "u3-agp");
0f921197	315
57fd7b7f	316	return h->bus;
0f921197 AG	317	}
0f921197 AG	318
9af21dbe	319	static void unin_main_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	320	{
502a5395 PB	321	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	322	d->config[0x0D] = 0x10; // latency_timer
502a5395	323	d->config[0x34] = 0x00; // capabilities_pointer
2e29bd04	324	}
502a5395	325
9af21dbe	326	static void unin_agp_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	327	{
502a5395 PB	328	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	329	d->config[0x0D] = 0x10; // latency_timer
502a5395	330	// d->config[0x34] = 0x80; // capabilities_pointer
98ae3b27 JA	331	/*
	332	* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
	333	* memory space with base 0x80000000, size 0x10000000 for Apple's
	334	* AppleMacRiscPCI driver
	335	*/
	336	d->config[0x48] = 0x0;
	337	d->config[0x49] = 0x0;
	338	d->config[0x4a] = 0x0;
	339	d->config[0x4b] = 0x1;
2e29bd04	340	}
502a5395	341
9af21dbe	342	static void u3_agp_pci_host_realize(PCIDevice d, Error *errp)
0f921197	343	{
0f921197 AG	344	/* cache line size */
	345	d->config[0x0C] = 0x08;
	346	/* latency timer */
	347	d->config[0x0D] = 0x10;
0f921197 AG	348	}
0f921197 AG	349
9af21dbe	350	static void unin_internal_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	351	{
502a5395 PB	352	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	353	d->config[0x0D] = 0x10; // latency_timer
502a5395	354	d->config[0x34] = 0x00; // capabilities_pointer
2e29bd04 BS	355	}
2e29bd04 BS	356
40021f08 AL	357	static void unin_main_pci_host_class_init(ObjectClass klass, void data)
	358	{
	359	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	360	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	361
9af21dbe	362	k->realize = unin_main_pci_host_realize;
40021f08 AL	363	k->vendor_id = PCI_VENDOR_ID_APPLE;
	364	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
	365	k->revision = 0x00;
	366	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	367	/*
	368	* PCI-facing part of the host bridge, not usable without the
	369	* host-facing part, which can't be device_add'ed, yet.
	370	*/
	371	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	372	}
40021f08 AL	373
4240abff	374	static const TypeInfo unin_main_pci_host_info = {
40021f08	375	.name = "uni-north-pci",
39bffca2 AL	376	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	377	.instance_size = sizeof(PCIDevice),
40021f08	378	.class_init = unin_main_pci_host_class_init,
2e29bd04 BS	379	};
2e29bd04 BS	380
40021f08 AL	381	static void u3_agp_pci_host_class_init(ObjectClass klass, void data)
	382	{
	383	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	384	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	385
9af21dbe	386	k->realize = u3_agp_pci_host_realize;
40021f08 AL	387	k->vendor_id = PCI_VENDOR_ID_APPLE;
	388	k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
	389	k->revision = 0x00;
	390	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	391	/*
	392	* PCI-facing part of the host bridge, not usable without the
	393	* host-facing part, which can't be device_add'ed, yet.
	394	*/
	395	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	396	}
40021f08 AL	397
4240abff	398	static const TypeInfo u3_agp_pci_host_info = {
40021f08	399	.name = "u3-agp",
39bffca2 AL	400	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	401	.instance_size = sizeof(PCIDevice),
40021f08	402	.class_init = u3_agp_pci_host_class_init,
0f921197 AG	403	};
0f921197 AG	404
40021f08 AL	405	static void unin_agp_pci_host_class_init(ObjectClass klass, void data)
	406	{
	407	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	408	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	409
9af21dbe	410	k->realize = unin_agp_pci_host_realize;
40021f08 AL	411	k->vendor_id = PCI_VENDOR_ID_APPLE;
	412	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
	413	k->revision = 0x00;
	414	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	415	/*
	416	* PCI-facing part of the host bridge, not usable without the
	417	* host-facing part, which can't be device_add'ed, yet.
	418	*/
	419	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	420	}
40021f08 AL	421
4240abff	422	static const TypeInfo unin_agp_pci_host_info = {
40021f08	423	.name = "uni-north-agp",
39bffca2 AL	424	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	425	.instance_size = sizeof(PCIDevice),
40021f08	426	.class_init = unin_agp_pci_host_class_init,
2e29bd04 BS	427	};
2e29bd04 BS	428
40021f08 AL	429	static void unin_internal_pci_host_class_init(ObjectClass klass, void data)
	430	{
	431	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	432	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	433
9af21dbe	434	k->realize = unin_internal_pci_host_realize;
40021f08 AL	435	k->vendor_id = PCI_VENDOR_ID_APPLE;
	436	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
	437	k->revision = 0x00;
	438	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	439	/*
	440	* PCI-facing part of the host bridge, not usable without the
	441	* host-facing part, which can't be device_add'ed, yet.
	442	*/
	443	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	444	}
40021f08 AL	445
4240abff	446	static const TypeInfo unin_internal_pci_host_info = {
40021f08	447	.name = "uni-north-internal-pci",
39bffca2 AL	448	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	449	.instance_size = sizeof(PCIDevice),
40021f08	450	.class_init = unin_internal_pci_host_class_init,
2e29bd04 BS	451	};
2e29bd04 BS	452
999e12bb AL	453	static void pci_unin_main_class_init(ObjectClass klass, void data)
	454	{
	455	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	456	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	457
999e12bb AL	458	sbc->init = pci_unin_main_init_device;
1d16f86a	459	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	460	}
999e12bb AL	461
4240abff	462	static const TypeInfo pci_unin_main_info = {
57fd7b7f	463	.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
8558d942	464	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	465	.instance_size = sizeof(UNINState),
39bffca2 AL	466	.class_init = pci_unin_main_class_init,
70f9c987 AF	467	};
70f9c987 AF	468
999e12bb AL	469	static void pci_u3_agp_class_init(ObjectClass klass, void data)
	470	{
	471	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	472	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	473
999e12bb AL	474	sbc->init = pci_u3_agp_init_device;
1d16f86a	475	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	476	}
999e12bb AL	477
4240abff	478	static const TypeInfo pci_u3_agp_info = {
57fd7b7f	479	.name = TYPE_U3_AGP_HOST_BRIDGE,
8558d942	480	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	481	.instance_size = sizeof(UNINState),
39bffca2 AL	482	.class_init = pci_u3_agp_class_init,
70f9c987 AF	483	};
70f9c987 AF	484
999e12bb AL	485	static void pci_unin_agp_class_init(ObjectClass klass, void data)
	486	{
	487	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	488	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	489
999e12bb AL	490	sbc->init = pci_unin_agp_init_device;
1d16f86a	491	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	492	}
999e12bb AL	493
4240abff	494	static const TypeInfo pci_unin_agp_info = {
57fd7b7f	495	.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
8558d942	496	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	497	.instance_size = sizeof(UNINState),
39bffca2 AL	498	.class_init = pci_unin_agp_class_init,
70f9c987 AF	499	};
70f9c987 AF	500
999e12bb AL	501	static void pci_unin_internal_class_init(ObjectClass klass, void data)
	502	{
	503	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	504	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	505
999e12bb AL	506	sbc->init = pci_unin_internal_init_device;
1d16f86a	507	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	508	}
999e12bb AL	509
4240abff	510	static const TypeInfo pci_unin_internal_info = {
57fd7b7f	511	.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
8558d942	512	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	513	.instance_size = sizeof(UNINState),
39bffca2 AL	514	.class_init = pci_unin_internal_class_init,
70f9c987 AF	515	};
70f9c987 AF	516
83f7d43a	517	static void unin_register_types(void)
2e29bd04	518	{
39bffca2 AL	519	type_register_static(&unin_main_pci_host_info);
	520	type_register_static(&u3_agp_pci_host_info);
	521	type_register_static(&unin_agp_pci_host_info);
	522	type_register_static(&unin_internal_pci_host_info);
	523
	524	type_register_static(&pci_unin_main_info);
	525	type_register_static(&pci_u3_agp_info);
	526	type_register_static(&pci_unin_agp_info);
	527	type_register_static(&pci_unin_internal_info);
502a5395	528	}
2e29bd04	529
83f7d43a	530	type_init(unin_register_types)