[qemu.git] / hw / pc.h

#ifndef HW_PC_H
#define HW_PC_H

#include "qemu-common.h"
#include "memory.h"
#include "ioport.h"
#include "isa.h"
#include "fdc.h"
#include "net.h"
#include "memory.h"
#include "ioapic.h"

/* PC-style peripherals (also used by other machines).  */

/* serial.c */

SerialState *serial_init(int base, qemu_irq irq, int baudbase,
                         CharDriverState *chr);
SerialState *serial_mm_init(MemoryRegion *address_space,
                            target_phys_addr_t base, int it_shift,
                            qemu_irq irq, int baudbase,
                            CharDriverState *chr, enum device_endian);
static inline bool serial_isa_init(ISABus *bus, int index,
                                   CharDriverState *chr)
{
    ISADevice *dev;

    dev = isa_try_create(bus, "isa-serial");
    if (!dev) {
        return false;
    }
    qdev_prop_set_uint32(&dev->qdev, "index", index);
    qdev_prop_set_chr(&dev->qdev, "chardev", chr);
    if (qdev_init(&dev->qdev) < 0) {
        return false;
    }
    return true;
}

void serial_set_frequency(SerialState *s, uint32_t frequency);

/* parallel.c */
static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
{
    ISADevice *dev;

    dev = isa_try_create(bus, "isa-parallel");
    if (!dev) {
        return false;
    }
    qdev_prop_set_uint32(&dev->qdev, "index", index);
    qdev_prop_set_chr(&dev->qdev, "chardev", chr);
    if (qdev_init(&dev->qdev) < 0) {
        return false;
    }
    return true;
}

bool parallel_mm_init(MemoryRegion *address_space,
                      target_phys_addr_t base, int it_shift, qemu_irq irq,
                      CharDriverState *chr);

/* i8259.c */

extern DeviceState *isa_pic;
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
qemu_irq *kvm_i8259_init(ISABus *bus);
int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
void pic_info(Monitor *mon);
void irq_info(Monitor *mon);

/* Global System Interrupts */

#define GSI_NUM_PINS IOAPIC_NUM_PINS

typedef struct GSIState {
    qemu_irq i8259_irq[ISA_NUM_IRQS];
    qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
} GSIState;

void gsi_handler(void *opaque, int n, int level);

/* i8254.c */

#define PIT_FREQ 1193182

static inline ISADevice *pit_init(ISABus *bus, int base, int irq)
{
    ISADevice *dev;

    dev = isa_create(bus, "isa-pit");
    qdev_prop_set_uint32(&dev->qdev, "iobase", base);
    qdev_prop_set_uint32(&dev->qdev, "irq", irq);
    qdev_init_nofail(&dev->qdev);

    return dev;
}

void pit_set_gate(ISADevice *dev, int channel, int val);
int pit_get_gate(ISADevice *dev, int channel);
int pit_get_initial_count(ISADevice *dev, int channel);
int pit_get_mode(ISADevice *dev, int channel);
int pit_get_out(ISADevice *dev, int channel, int64_t current_time);

void hpet_pit_disable(void);
void hpet_pit_enable(void);

/* vmport.c */
static inline void vmport_init(ISABus *bus)
{
    isa_create_simple(bus, "vmport");
}
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
void vmmouse_get_data(uint32_t *data);
void vmmouse_set_data(const uint32_t *data);

/* pckbd.c */

void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   MemoryRegion *region, ram_addr_t size,
                   target_phys_addr_t mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);

/* pc.c */
extern int fd_bootchk;

void pc_register_ferr_irq(qemu_irq irq);
void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);

void pc_cpus_init(const char *cpu_model);
void pc_memory_init(MemoryRegion *system_memory,
                    const char *kernel_filename,
                    const char *kernel_cmdline,
                    const char *initrd_filename,
                    ram_addr_t below_4g_mem_size,
                    ram_addr_t above_4g_mem_size,
                    MemoryRegion *rom_memory,
                    MemoryRegion **ram_memory);
qemu_irq *pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
                          ISADevice **rtc_state,
                          ISADevice **floppy,
                          bool no_vmport);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
                  const char *boot_device,
                  ISADevice *floppy, BusState *ide0, BusState *ide1,
                  ISADevice *s);
void pc_pci_device_init(PCIBus *pci_bus);

typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);

/* acpi.c */
extern int acpi_enabled;
extern char *acpi_tables;
extern size_t acpi_tables_len;

void acpi_bios_init(void);
int acpi_table_add(const char *table_desc);

/* acpi_piix.c */

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
                       int kvm_enabled);
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);

/* hpet.c */
extern int no_hpet;

/* pcspk.c */
void pcspk_init(ISADevice *pit);
int pcspk_audio_init(ISABus *bus);

/* piix_pci.c */
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
                    ISABus **isa_bus, qemu_irq *pic,
                    MemoryRegion *address_space_mem,
                    MemoryRegion *address_space_io,
                    ram_addr_t ram_size,
                    target_phys_addr_t pci_hole_start,
                    target_phys_addr_t pci_hole_size,
                    target_phys_addr_t pci_hole64_start,
                    target_phys_addr_t pci_hole64_size,
                    MemoryRegion *pci_memory,
                    MemoryRegion *ram_memory);

/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);

/* vga.c */
enum vga_retrace_method {
    VGA_RETRACE_DUMB,
    VGA_RETRACE_PRECISE
};

extern enum vga_retrace_method vga_retrace_method;

static inline DeviceState *isa_vga_init(ISABus *bus)
{
    ISADevice *dev;

    dev = isa_try_create(bus, "isa-vga");
    if (!dev) {
        fprintf(stderr, "Warning: isa-vga not available\n");
        return NULL;
    }
    qdev_init_nofail(&dev->qdev);
    return &dev->qdev;
}

DeviceState *pci_vga_init(PCIBus *bus);
int isa_vga_mm_init(target_phys_addr_t vram_base,
                    target_phys_addr_t ctrl_base, int it_shift,
                    MemoryRegion *address_space);

/* cirrus_vga.c */
DeviceState *pci_cirrus_vga_init(PCIBus *bus);

/* ne2000.c */
static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
{
    ISADevice *dev;

    qemu_check_nic_model(nd, "ne2k_isa");

    dev = isa_try_create(bus, "ne2k_isa");
    if (!dev) {
        return false;
    }
    qdev_prop_set_uint32(&dev->qdev, "iobase", base);
    qdev_prop_set_uint32(&dev->qdev, "irq",    irq);
    qdev_set_nic_properties(&dev->qdev, nd);
    qdev_init_nofail(&dev->qdev);
    return true;
}

/* e820 types */
#define E820_RAM        1
#define E820_RESERVED   2
#define E820_ACPI       3
#define E820_NVS        4
#define E820_UNUSABLE   5

int e820_add_entry(uint64_t, uint64_t, uint32_t);

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef HW_PC_H
87ecb68b PB	2	#define HW_PC_H
376253ec AL	3
376253ec AL	4	#include "qemu-common.h"
00cb2a99	5	#include "memory.h"
35bed8ee	6	#include "ioport.h"
845773ab IY	7	#include "isa.h"
845773ab IY	8	#include "fdc.h"
cd1b8a8b	9	#include "net.h"
4aa63af1	10	#include "memory.h"
b881fbe9	11	#include "ioapic.h"
376253ec	12
87ecb68b PB	13	/* PC-style peripherals (also used by other machines). */
	14
	15	/* serial.c */
	16
b6cd0ea1 AJ	17	SerialState *serial_init(int base, qemu_irq irq, int baudbase,
b6cd0ea1 AJ	18	CharDriverState *chr);
39186d8a RH	19	SerialState serial_mm_init(MemoryRegion address_space,
	20	target_phys_addr_t base, int it_shift,
	21	qemu_irq irq, int baudbase,
	22	CharDriverState *chr, enum device_endian);
48a18b3c HP	23	static inline bool serial_isa_init(ISABus *bus, int index,
48a18b3c HP	24	CharDriverState *chr)
e22cf21e BS	25	{
	26	ISADevice *dev;
	27
48a18b3c	28	dev = isa_try_create(bus, "isa-serial");
9b13ef9f BS	29	if (!dev) {
	30	return false;
	31	}
e22cf21e BS	32	qdev_prop_set_uint32(&dev->qdev, "index", index);
	33	qdev_prop_set_chr(&dev->qdev, "chardev", chr);
	34	if (qdev_init(&dev->qdev) < 0) {
	35	return false;
	36	}
	37	return true;
	38	}
	39
038eaf82	40	void serial_set_frequency(SerialState *s, uint32_t frequency);
87ecb68b PB	41
87ecb68b PB	42	/* parallel.c */
48a18b3c	43	static inline bool parallel_init(ISABus bus, int index, CharDriverState chr)
defdb20e BS	44	{
	45	ISADevice *dev;
	46
48a18b3c	47	dev = isa_try_create(bus, "isa-parallel");
73531538 BS	48	if (!dev) {
	49	return false;
	50	}
defdb20e BS	51	qdev_prop_set_uint32(&dev->qdev, "index", index);
	52	qdev_prop_set_chr(&dev->qdev, "chardev", chr);
	53	if (qdev_init(&dev->qdev) < 0) {
	54	return false;
	55	}
	56	return true;
	57	}
	58
63858cd9 AK	59	bool parallel_mm_init(MemoryRegion *address_space,
63858cd9 AK	60	target_phys_addr_t base, int it_shift, qemu_irq irq,
defdb20e	61	CharDriverState *chr);
87ecb68b PB	62
	63	/* i8259.c */
	64
9aa78c42	65	extern DeviceState *isa_pic;
48a18b3c	66	qemu_irq i8259_init(ISABus bus, qemu_irq parent_irq);
10b61882	67	qemu_irq kvm_i8259_init(ISABus bus);
9aa78c42 JK	68	int pic_read_irq(DeviceState *d);
9aa78c42 JK	69	int pic_get_output(DeviceState *d);
376253ec AL	70	void pic_info(Monitor *mon);
376253ec AL	71	void irq_info(Monitor *mon);
87ecb68b	72
b881fbe9	73	/* Global System Interrupts */
96051119	74
b881fbe9	75	#define GSI_NUM_PINS IOAPIC_NUM_PINS
845773ab	76
b881fbe9	77	typedef struct GSIState {
43a0db35	78	qemu_irq i8259_irq[ISA_NUM_IRQS];
b881fbe9 JK	79	qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
	80	} GSIState;
	81
	82	void gsi_handler(void *opaque, int n, int level);
845773ab	83
87ecb68b PB	84	/* i8254.c */
	85
	86	#define PIT_FREQ 1193182
	87
48a18b3c	88	static inline ISADevice pit_init(ISABus bus, int base, int irq)
64d7e9a4 BS	89	{
	90	ISADevice *dev;
	91
48a18b3c	92	dev = isa_create(bus, "isa-pit");
64d7e9a4 BS	93	qdev_prop_set_uint32(&dev->qdev, "iobase", base);
	94	qdev_prop_set_uint32(&dev->qdev, "irq", irq);
	95	qdev_init_nofail(&dev->qdev);
	96
	97	return dev;
	98	}
87ecb68b	99
64d7e9a4 BS	100	void pit_set_gate(ISADevice *dev, int channel, int val);
	101	int pit_get_gate(ISADevice *dev, int channel);
	102	int pit_get_initial_count(ISADevice *dev, int channel);
	103	int pit_get_mode(ISADevice *dev, int channel);
	104	int pit_get_out(ISADevice *dev, int channel, int64_t current_time);
87ecb68b	105
bf4f74c0 AJ	106	void hpet_pit_disable(void);
	107	void hpet_pit_enable(void);
	108
87ecb68b	109	/* vmport.c */
48a18b3c	110	static inline void vmport_init(ISABus *bus)
6872ef61	111	{
48a18b3c	112	isa_create_simple(bus, "vmport");
6872ef61	113	}
87ecb68b	114	void vmport_register(unsigned char command, IOPortReadFunc func, void opaque);
86d86414 BS	115	void vmmouse_get_data(uint32_t *data);
86d86414 BS	116	void vmmouse_set_data(const uint32_t *data);
87ecb68b	117
87ecb68b PB	118	/* pckbd.c */
	119
	120	void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
	121	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
dbff76ac	122	MemoryRegion *region, ram_addr_t size,
c227f099	123	target_phys_addr_t mask);
956a3e6b BS	124	void i8042_isa_mouse_fake_event(void *opaque);
956a3e6b BS	125	void i8042_setup_a20_line(ISADevice dev, qemu_irq a20_out);
87ecb68b	126
87ecb68b PB	127	/* pc.c */
	128	extern int fd_bootchk;
	129
8e78eb28	130	void pc_register_ferr_irq(qemu_irq irq);
845773ab IY	131	void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
	132	void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
	133
	134	void pc_cpus_init(const char *cpu_model);
4aa63af1 AK	135	void pc_memory_init(MemoryRegion *system_memory,
4aa63af1 AK	136	const char *kernel_filename,
845773ab IY	137	const char *kernel_cmdline,
845773ab IY	138	const char *initrd_filename,
e0e7e67b	139	ram_addr_t below_4g_mem_size,
ae0a5466	140	ram_addr_t above_4g_mem_size,
4463aee6	141	MemoryRegion *rom_memory,
ae0a5466	142	MemoryRegion **ram_memory);
845773ab	143	qemu_irq *pc_allocate_cpu_irq(void);
48a18b3c HP	144	DeviceState pc_vga_init(ISABus isa_bus, PCIBus *pci_bus);
48a18b3c HP	145	void pc_basic_device_init(ISABus isa_bus, qemu_irq gsi,
1611977c	146	ISADevice **rtc_state,
34d4260e	147	ISADevice **floppy,
1611977c	148	bool no_vmport);
48a18b3c	149	void pc_init_ne2k_isa(ISABus bus, NICInfo nd);
845773ab	150	void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
c0897e0c	151	const char *boot_device,
34d4260e	152	ISADevice floppy, BusState ide0, BusState *ide1,
63ffb564	153	ISADevice *s);
845773ab	154	void pc_pci_device_init(PCIBus *pci_bus);
8e78eb28	155
f885f1ea IY	156	typedef void (cpu_set_smm_t)(int smm, void arg);
	157	void cpu_smm_register(cpu_set_smm_t callback, void *arg);
	158
87ecb68b PB	159	/* acpi.c */
87ecb68b PB	160	extern int acpi_enabled;
80deece2 BS	161	extern char *acpi_tables;
	162	extern size_t acpi_tables_len;
	163
9d5e77a2 IY	164	void acpi_bios_init(void);
	165	int acpi_table_add(const char *table_desc);
	166
	167	/* acpi_piix.c */
53b67b30	168
cf7a2fe2	169	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
53b67b30 BS	170	qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
53b67b30 BS	171	int kvm_enabled);
87ecb68b	172	void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
87ecb68b	173
16b29ae1 AL	174	/* hpet.c */
	175	extern int no_hpet;
	176
87ecb68b	177	/* pcspk.c */
64d7e9a4	178	void pcspk_init(ISADevice *pit);
4a0f031d	179	int pcspk_audio_init(ISABus *bus);
87ecb68b PB	180
87ecb68b PB	181	/* piix_pci.c */
0a3bacf3 JQ	182	struct PCII440FXState;
	183	typedef struct PCII440FXState PCII440FXState;
	184
1e39101c	185	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix_devfn,
60573079	186	ISABus *isa_bus, qemu_irq pic,
aee97b84 AK	187	MemoryRegion *address_space_mem,
aee97b84 AK	188	MemoryRegion *address_space_io,
ae0a5466 AK	189	ram_addr_t ram_size,
	190	target_phys_addr_t pci_hole_start,
	191	target_phys_addr_t pci_hole_size,
	192	target_phys_addr_t pci_hole64_start,
	193	target_phys_addr_t pci_hole64_size,
	194	MemoryRegion *pci_memory,
	195	MemoryRegion *ram_memory);
87ecb68b	196
823e675a	197	/* piix4.c */
b1d8e52e	198	extern PCIDevice *piix4_dev;
142e9787	199	int piix4_init(PCIBus bus, ISABus *isa_bus, int devfn);
87ecb68b PB	200
87ecb68b PB	201	/* vga.c */
cb5a7aa8	202	enum vga_retrace_method {
	203	VGA_RETRACE_DUMB,
	204	VGA_RETRACE_PRECISE
	205	};
	206
	207	extern enum vga_retrace_method vga_retrace_method;
87ecb68b	208
48a18b3c	209	static inline DeviceState isa_vga_init(ISABus bus)
7435b791	210	{
c74b88df	211	ISADevice *dev;
7435b791	212
48a18b3c	213	dev = isa_try_create(bus, "isa-vga");
c74b88df BS	214	if (!dev) {
c74b88df BS	215	fprintf(stderr, "Warning: isa-vga not available\n");
ad6d45fa	216	return NULL;
c74b88df BS	217	}
c74b88df BS	218	qdev_init_nofail(&dev->qdev);
ad6d45fa	219	return &dev->qdev;
7435b791 BS	220	}
7435b791 BS	221
ad6d45fa	222	DeviceState pci_vga_init(PCIBus bus);
c227f099	223	int isa_vga_mm_init(target_phys_addr_t vram_base,
be20f9e9 AK	224	target_phys_addr_t ctrl_base, int it_shift,
be20f9e9 AK	225	MemoryRegion *address_space);
87ecb68b PB	226
87ecb68b PB	227	/* cirrus_vga.c */
ad6d45fa	228	DeviceState pci_cirrus_vga_init(PCIBus bus);
87ecb68b	229
87ecb68b	230	/* ne2000.c */
48a18b3c	231	static inline bool isa_ne2000_init(ISABus bus, int base, int irq, NICInfo nd)
60a14ad3 BS	232	{
60a14ad3 BS	233	ISADevice *dev;
87ecb68b	234
60a14ad3 BS	235	qemu_check_nic_model(nd, "ne2k_isa");
60a14ad3 BS	236
48a18b3c	237	dev = isa_try_create(bus, "ne2k_isa");
cd1b8a8b BS	238	if (!dev) {
	239	return false;
	240	}
60a14ad3 BS	241	qdev_prop_set_uint32(&dev->qdev, "iobase", base);
	242	qdev_prop_set_uint32(&dev->qdev, "irq", irq);
	243	qdev_set_nic_properties(&dev->qdev, nd);
	244	qdev_init_nofail(&dev->qdev);
cd1b8a8b	245	return true;
60a14ad3	246	}
87ecb68b	247
4c5b10b7 JS	248	/* e820 types */
	249	#define E820_RAM 1
	250	#define E820_RESERVED 2
	251	#define E820_ACPI 3
	252	#define E820_NVS 4
	253	#define E820_UNUSABLE 5
	254
	255	int e820_add_entry(uint64_t, uint64_t, uint32_t);
	256
87ecb68b	257	#endif