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 103
 104 <div class="header">
 105   <div class="headertitle"><div class="title">sio.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00003" name="l00003"></a><span class="lineno">    3</span><span class="comment">/*</span></div>
 111 <div class="line"><a id="l00004" name="l00004"></a><span class="lineno">    4</span><span class="comment"> * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.</span></div>
 112 <div class="line"><a id="l00005" name="l00005"></a><span class="lineno">    5</span><span class="comment"> *</span></div>
 113 <div class="line"><a id="l00006" name="l00006"></a><span class="lineno">    6</span><span class="comment"> * SPDX-License-Identifier: BSD-3-Clause</span></div>
 114 <div class="line"><a id="l00007" name="l00007"></a><span class="lineno">    7</span><span class="comment"> */</span></div>
 115 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span> </div>
 116 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_SIO_H</span></div>
 117 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span><span class="preprocessor">#define _HARDWARE_STRUCTS_SIO_H</span></div>
 118 <div class="line"><a id="l00011" name="l00011"></a><span class="lineno">   11</span> </div>
 119 <div class="line"><a id="l00012" name="l00012"></a><span class="lineno">   12</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 120 <div class="line"><a id="l00013" name="l00013"></a><span class="lineno">   13</span><span class="preprocessor">#include &quot;hardware/regs/sio.h&quot;</span></div>
 121 <div class="line"><a id="l00014" name="l00014"></a><span class="lineno">   14</span><span class="preprocessor">#include &quot;hardware/structs/interp.h&quot;</span></div>
 122 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span> </div>
 123 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio</span></div>
 124 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span><span class="comment">//</span></div>
 125 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 126 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.</span></div>
 127 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">//</span></div>
 128 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 129 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION</span></div>
 130 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span> </div>
 131 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno"><a class="line" href="structsio__hw__t.html">   24</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 132 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span>    _REG_(SIO_CPUID_OFFSET) <span class="comment">// SIO_CPUID</span></div>
 133 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno">   26</span>    <span class="comment">// Processor core identifier</span></div>
 134 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    io_ro_32 cpuid;</div>
 135 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span> </div>
 136 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    _REG_(SIO_GPIO_IN_OFFSET) <span class="comment">// SIO_GPIO_IN</span></div>
 137 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// Input value for GPIO pins</span></div>
 138 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_IN (0): Input value for GPIO0</span></div>
 139 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    io_ro_32 gpio_in;</div>
 140 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span> </div>
 141 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    _REG_(SIO_GPIO_HI_IN_OFFSET) <span class="comment">// SIO_GPIO_HI_IN</span></div>
 142 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    <span class="comment">// Input value for QSPI pins</span></div>
 143 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_IN (0): Input value on QSPI IO in order 0</span></div>
 144 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    io_ro_32 gpio_hi_in;</div>
 145 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span> </div>
 146 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    uint32_t _pad0;</div>
 147 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span> </div>
 148 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    _REG_(SIO_GPIO_OUT_OFFSET) <span class="comment">// SIO_GPIO_OUT</span></div>
 149 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    <span class="comment">// GPIO output value</span></div>
 150 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_OUT (0): Set output level (1/0 -&gt; high/low) for GPIO0</span></div>
 151 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    io_rw_32 gpio_out;</div>
 152 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span> </div>
 153 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    _REG_(SIO_GPIO_OUT_SET_OFFSET) <span class="comment">// SIO_GPIO_OUT_SET</span></div>
 154 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    <span class="comment">// GPIO output value set</span></div>
 155 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_OUT_SET (0): Perform an atomic bit-set on GPIO_OUT, i</span></div>
 156 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    io_wo_32 gpio_set;</div>
 157 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span> </div>
 158 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    _REG_(SIO_GPIO_OUT_CLR_OFFSET) <span class="comment">// SIO_GPIO_OUT_CLR</span></div>
 159 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    <span class="comment">// GPIO output value clear</span></div>
 160 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_OUT_CLR (0): Perform an atomic bit-clear on GPIO_OUT, i</span></div>
 161 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    io_wo_32 gpio_clr;</div>
 162 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span> </div>
 163 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    _REG_(SIO_GPIO_OUT_XOR_OFFSET) <span class="comment">// SIO_GPIO_OUT_XOR</span></div>
 164 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// GPIO output value XOR</span></div>
 165 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_OUT, i</span></div>
 166 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    io_wo_32 gpio_togl;</div>
 167 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span> </div>
 168 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    _REG_(SIO_GPIO_OE_OFFSET) <span class="comment">// SIO_GPIO_OE</span></div>
 169 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    <span class="comment">// GPIO output enable</span></div>
 170 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_OE (0): Set output enable (1/0 -&gt; output/input) for GPIO0</span></div>
 171 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    io_rw_32 gpio_oe;</div>
 172 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span> </div>
 173 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    _REG_(SIO_GPIO_OE_SET_OFFSET) <span class="comment">// SIO_GPIO_OE_SET</span></div>
 174 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    <span class="comment">// GPIO output enable set</span></div>
 175 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_OE_SET (0): Perform an atomic bit-set on GPIO_OE, i</span></div>
 176 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    io_wo_32 gpio_oe_set;</div>
 177 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span> </div>
 178 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    _REG_(SIO_GPIO_OE_CLR_OFFSET) <span class="comment">// SIO_GPIO_OE_CLR</span></div>
 179 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    <span class="comment">// GPIO output enable clear</span></div>
 180 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_OE_CLR (0): Perform an atomic bit-clear on GPIO_OE, i</span></div>
 181 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>    io_wo_32 gpio_oe_clr;</div>
 182 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span> </div>
 183 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>    _REG_(SIO_GPIO_OE_XOR_OFFSET) <span class="comment">// SIO_GPIO_OE_XOR</span></div>
 184 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    <span class="comment">// GPIO output enable XOR</span></div>
 185 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// 0x3fffffff [29:0]  : GPIO_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_OE, i</span></div>
 186 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    io_wo_32 gpio_oe_togl;</div>
 187 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span> </div>
 188 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    _REG_(SIO_GPIO_HI_OUT_OFFSET) <span class="comment">// SIO_GPIO_HI_OUT</span></div>
 189 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>    <span class="comment">// QSPI output value</span></div>
 190 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_OUT (0): Set output level (1/0 -&gt; high/low) for QSPI IO0</span></div>
 191 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>    io_rw_32 gpio_hi_out;</div>
 192 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span> </div>
 193 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) <span class="comment">// SIO_GPIO_HI_OUT_SET</span></div>
 194 <div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>    <span class="comment">// QSPI output value set</span></div>
 195 <div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_OUT_SET (0): Perform an atomic bit-set on GPIO_HI_OUT, i</span></div>
 196 <div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    io_wo_32 gpio_hi_set;</div>
 197 <div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span> </div>
 198 <div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span>    _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) <span class="comment">// SIO_GPIO_HI_OUT_CLR</span></div>
 199 <div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>    <span class="comment">// QSPI output value clear</span></div>
 200 <div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_OUT_CLR (0): Perform an atomic bit-clear on GPIO_HI_OUT, i</span></div>
 201 <div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    io_wo_32 gpio_hi_clr;</div>
 202 <div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span> </div>
 203 <div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span>    _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) <span class="comment">// SIO_GPIO_HI_OUT_XOR</span></div>
 204 <div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span>    <span class="comment">// QSPI output value XOR</span></div>
 205 <div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OUT, i</span></div>
 206 <div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    io_wo_32 gpio_hi_togl;</div>
 207 <div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span> </div>
 208 <div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    _REG_(SIO_GPIO_HI_OE_OFFSET) <span class="comment">// SIO_GPIO_HI_OE</span></div>
 209 <div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span>    <span class="comment">// QSPI output enable</span></div>
 210 <div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_OE (0): Set output enable (1/0 -&gt; output/input) for QSPI IO0</span></div>
 211 <div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    io_rw_32 gpio_hi_oe;</div>
 212 <div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span> </div>
 213 <div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    _REG_(SIO_GPIO_HI_OE_SET_OFFSET) <span class="comment">// SIO_GPIO_HI_OE_SET</span></div>
 214 <div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    <span class="comment">// QSPI output enable set</span></div>
 215 <div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_OE_SET (0): Perform an atomic bit-set on GPIO_HI_OE, i</span></div>
 216 <div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    io_wo_32 gpio_hi_oe_set;</div>
 217 <div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span> </div>
 218 <div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>    _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) <span class="comment">// SIO_GPIO_HI_OE_CLR</span></div>
 219 <div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span>    <span class="comment">// QSPI output enable clear</span></div>
 220 <div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_OE_CLR (0): Perform an atomic bit-clear on GPIO_HI_OE, i</span></div>
 221 <div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span>    io_wo_32 gpio_hi_oe_clr;</div>
 222 <div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span> </div>
 223 <div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) <span class="comment">// SIO_GPIO_HI_OE_XOR</span></div>
 224 <div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    <span class="comment">// QSPI output enable XOR</span></div>
 225 <div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    <span class="comment">// 0x0000003f [5:0]   : GPIO_HI_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OE, i</span></div>
 226 <div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>    io_wo_32 gpio_hi_oe_togl;</div>
 227 <div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span> </div>
 228 <div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span>    _REG_(SIO_FIFO_ST_OFFSET) <span class="comment">// SIO_FIFO_ST</span></div>
 229 <div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>    <span class="comment">// Status register for inter-core FIFOs (mailboxes)</span></div>
 230 <div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span>    <span class="comment">// 0x00000008 [3]     : ROE (0): Sticky flag indicating the RX FIFO was read when empty</span></div>
 231 <div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span>    <span class="comment">// 0x00000004 [2]     : WOF (0): Sticky flag indicating the TX FIFO was written when full</span></div>
 232 <div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span>    <span class="comment">// 0x00000002 [1]     : RDY (1): Value is 1 if this core&#39;s TX FIFO is not full (i</span></div>
 233 <div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span>    <span class="comment">// 0x00000001 [0]     : VLD (0): Value is 1 if this core&#39;s RX FIFO is not empty (i</span></div>
 234 <div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    io_rw_32 fifo_st;</div>
 235 <div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span> </div>
 236 <div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span>    _REG_(SIO_FIFO_WR_OFFSET) <span class="comment">// SIO_FIFO_WR</span></div>
 237 <div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    <span class="comment">// Write access to this core&#39;s TX FIFO</span></div>
 238 <div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    io_wo_32 fifo_wr;</div>
 239 <div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span> </div>
 240 <div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    _REG_(SIO_FIFO_RD_OFFSET) <span class="comment">// SIO_FIFO_RD</span></div>
 241 <div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span>    <span class="comment">// Read access to this core&#39;s RX FIFO</span></div>
 242 <div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    io_ro_32 fifo_rd;</div>
 243 <div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span> </div>
 244 <div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    _REG_(SIO_SPINLOCK_ST_OFFSET) <span class="comment">// SIO_SPINLOCK_ST</span></div>
 245 <div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span>    <span class="comment">// Spinlock state</span></div>
 246 <div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span>    io_ro_32 spinlock_st;</div>
 247 <div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span> </div>
 248 <div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span>    _REG_(SIO_DIV_UDIVIDEND_OFFSET) <span class="comment">// SIO_DIV_UDIVIDEND</span></div>
 249 <div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>    <span class="comment">// Divider unsigned dividend</span></div>
 250 <div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    io_rw_32 div_udividend;</div>
 251 <div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span> </div>
 252 <div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span>    _REG_(SIO_DIV_UDIVISOR_OFFSET) <span class="comment">// SIO_DIV_UDIVISOR</span></div>
 253 <div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span>    <span class="comment">// Divider unsigned divisor</span></div>
 254 <div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span>    io_rw_32 div_udivisor;</div>
 255 <div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span> </div>
 256 <div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    _REG_(SIO_DIV_SDIVIDEND_OFFSET) <span class="comment">// SIO_DIV_SDIVIDEND</span></div>
 257 <div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span>    <span class="comment">// Divider signed dividend</span></div>
 258 <div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span>    io_rw_32 div_sdividend;</div>
 259 <div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span> </div>
 260 <div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span>    _REG_(SIO_DIV_SDIVISOR_OFFSET) <span class="comment">// SIO_DIV_SDIVISOR</span></div>
 261 <div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>    <span class="comment">// Divider signed divisor</span></div>
 262 <div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span>    io_rw_32 div_sdivisor;</div>
 263 <div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span> </div>
 264 <div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span>    _REG_(SIO_DIV_QUOTIENT_OFFSET) <span class="comment">// SIO_DIV_QUOTIENT</span></div>
 265 <div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>    <span class="comment">// Divider result quotient</span></div>
 266 <div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span>    io_rw_32 div_quotient;</div>
 267 <div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span> </div>
 268 <div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>    _REG_(SIO_DIV_REMAINDER_OFFSET) <span class="comment">// SIO_DIV_REMAINDER</span></div>
 269 <div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span>    <span class="comment">// Divider result remainder</span></div>
 270 <div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>    io_rw_32 div_remainder;</div>
 271 <div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span> </div>
 272 <div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>    _REG_(SIO_DIV_CSR_OFFSET) <span class="comment">// SIO_DIV_CSR</span></div>
 273 <div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span>    <span class="comment">// Control and status register for divider</span></div>
 274 <div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span>    <span class="comment">// 0x00000002 [1]     : DIRTY (0): Changes to 1 when any register is written, and back to 0 when QUOTIENT is read</span></div>
 275 <div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span>    <span class="comment">// 0x00000001 [0]     : READY (1): Reads as 0 when a calculation is in progress, 1 otherwise</span></div>
 276 <div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>    io_ro_32 div_csr;</div>
 277 <div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>    uint32_t _pad1;</div>
 278 <div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span>    <a class="code hl_struct" href="structinterp__hw__t.html">interp_hw_t</a> interp[2];</div>
 279 <div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span>} <a class="code hl_struct" href="structsio__hw__t.html">sio_hw_t</a>;</div>
 280 <div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span> </div>
 281 <div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span><span class="preprocessor">#define sio_hw ((sio_hw_t *)SIO_BASE)</span></div>
 282 <div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span> </div>
 283 <div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span><span class="preprocessor">#endif</span></div>
 284 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 285 <div class="ttc" id="astructinterp__hw__t_html"><div class="ttname"><a href="structinterp__hw__t.html">interp_hw_t</a></div><div class="ttdef"><b>Definition:</b> interp.h:23</div></div>
 286 <div class="ttc" id="astructsio__hw__t_html"><div class="ttname"><a href="structsio__hw__t.html">sio_hw_t</a></div><div class="ttdef"><b>Definition:</b> sio.h:24</div></div>
 287 </div><!-- fragment --></div><!-- contents -->
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 289
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