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 103
 104 <div class="header">
 105   <div class="headertitle"><div class="title">sio.h</div></div>
 106 </div><!--header-->
 107 <div class="contents">
 108 <div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
 109 <div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
 110 <div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_SIO_H</span></div>
 111 <div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_SIO_H</span></div>
 112 <div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
 113 <div class="line"><a id="l00011" name="l00011"></a><span class="lineno">   11</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
 114 <div class="line"><a id="l00012" name="l00012"></a><span class="lineno">   12</span><span class="preprocessor">#include &quot;hardware/regs/sio.h&quot;</span></div>
 115 <div class="line"><a id="l00013" name="l00013"></a><span class="lineno">   13</span><span class="preprocessor">#include &quot;hardware/structs/interp.h&quot;</span></div>
 116 <div class="line"><a id="l00014" name="l00014"></a><span class="lineno">   14</span> </div>
 117 <div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio</span></div>
 118 <div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="comment">//</span></div>
 119 <div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
 120 <div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.</span></div>
 121 <div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
 122 <div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
 123 <div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
 124 <div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span> </div>
 125 <div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span> </div>
 126 <div class="line"><a id="l00024" name="l00024"></a><span class="lineno"><a class="line" href="structsio__hw__t.html">   24</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
 127 <div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span>    _REG_(SIO_CPUID_OFFSET) <span class="comment">// SIO_CPUID</span></div>
 128 <div class="line"><a id="l00026" name="l00026"></a><span class="lineno">   26</span>    <span class="comment">// Processor core identifier</span></div>
 129 <div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    <span class="comment">// 0xffffffff [31:0]  CPUID        (-) Value is 0 when read from processor core 0, and 1 when...</span></div>
 130 <div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    io_ro_32 cpuid;</div>
 131 <div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span> </div>
 132 <div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    _REG_(SIO_GPIO_IN_OFFSET) <span class="comment">// SIO_GPIO_IN</span></div>
 133 <div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// Input value for GPIO0</span></div>
 134 <div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_IN      (0x00000000) </span></div>
 135 <div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    io_ro_32 gpio_in;</div>
 136 <div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span> </div>
 137 <div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    _REG_(SIO_GPIO_HI_IN_OFFSET) <span class="comment">// SIO_GPIO_HI_IN</span></div>
 138 <div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    <span class="comment">// Input value on GPIO32</span></div>
 139 <div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins</span></div>
 140 <div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) Input value on QSPI CSn pin</span></div>
 141 <div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) Input value on QSPI SCK pin</span></div>
 142 <div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) Input value on USB D- pin</span></div>
 143 <div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) Input value on USB D+ pin</span></div>
 144 <div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) Input value on GPIO32</span></div>
 145 <div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    io_ro_32 gpio_hi_in;</div>
 146 <div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span> </div>
 147 <div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    uint32_t _pad0;</div>
 148 <div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span> </div>
 149 <div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    _REG_(SIO_GPIO_OUT_OFFSET) <span class="comment">// SIO_GPIO_OUT</span></div>
 150 <div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// GPIO0</span></div>
 151 <div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_OUT     (0x00000000) Set output level (1/0 -&gt; high/low) for GPIO0</span></div>
 152 <div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>    io_rw_32 gpio_out;</div>
 153 <div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span> </div>
 154 <div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    _REG_(SIO_GPIO_HI_OUT_OFFSET) <span class="comment">// SIO_GPIO_HI_OUT</span></div>
 155 <div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// Output value for GPIO32</span></div>
 156 <div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins</span></div>
 157 <div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) Output value for QSPI CSn pin</span></div>
 158 <div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) Output value for QSPI SCK pin</span></div>
 159 <div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) Output value for USB D- pin</span></div>
 160 <div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) Output value for USB D+ pin</span></div>
 161 <div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) Output value for GPIO32</span></div>
 162 <div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    io_rw_32 gpio_hi_out;</div>
 163 <div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span> </div>
 164 <div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    _REG_(SIO_GPIO_OUT_SET_OFFSET) <span class="comment">// SIO_GPIO_OUT_SET</span></div>
 165 <div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    <span class="comment">// GPIO0</span></div>
 166 <div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i</span></div>
 167 <div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    io_wo_32 gpio_set;</div>
 168 <div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span> </div>
 169 <div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) <span class="comment">// SIO_GPIO_HI_OUT_SET</span></div>
 170 <div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    <span class="comment">// Output value set for GPIO32</span></div>
 171 <div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) </span></div>
 172 <div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) </span></div>
 173 <div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) </span></div>
 174 <div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) </span></div>
 175 <div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) </span></div>
 176 <div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) </span></div>
 177 <div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    io_wo_32 gpio_hi_set;</div>
 178 <div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span> </div>
 179 <div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    _REG_(SIO_GPIO_OUT_CLR_OFFSET) <span class="comment">// SIO_GPIO_OUT_CLR</span></div>
 180 <div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// GPIO0</span></div>
 181 <div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i</span></div>
 182 <div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    io_wo_32 gpio_clr;</div>
 183 <div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span> </div>
 184 <div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>    _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) <span class="comment">// SIO_GPIO_HI_OUT_CLR</span></div>
 185 <div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>    <span class="comment">// Output value clear for GPIO32</span></div>
 186 <div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) </span></div>
 187 <div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) </span></div>
 188 <div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) </span></div>
 189 <div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) </span></div>
 190 <div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) </span></div>
 191 <div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) </span></div>
 192 <div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    io_wo_32 gpio_hi_clr;</div>
 193 <div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span> </div>
 194 <div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>    _REG_(SIO_GPIO_OUT_XOR_OFFSET) <span class="comment">// SIO_GPIO_OUT_XOR</span></div>
 195 <div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    <span class="comment">// GPIO0</span></div>
 196 <div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i</span></div>
 197 <div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    io_wo_32 gpio_togl;</div>
 198 <div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span> </div>
 199 <div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span>    _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) <span class="comment">// SIO_GPIO_HI_OUT_XOR</span></div>
 200 <div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    <span class="comment">// Output value XOR for GPIO32</span></div>
 201 <div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) </span></div>
 202 <div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) </span></div>
 203 <div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) </span></div>
 204 <div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) </span></div>
 205 <div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) </span></div>
 206 <div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) </span></div>
 207 <div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span>    io_wo_32 gpio_hi_togl;</div>
 208 <div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span> </div>
 209 <div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    _REG_(SIO_GPIO_OE_OFFSET) <span class="comment">// SIO_GPIO_OE</span></div>
 210 <div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span>    <span class="comment">// GPIO0</span></div>
 211 <div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_OE      (0x00000000) Set output enable (1/0 -&gt; output/input) for GPIO0</span></div>
 212 <div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span>    io_rw_32 gpio_oe;</div>
 213 <div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span> </div>
 214 <div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span>    _REG_(SIO_GPIO_HI_OE_OFFSET) <span class="comment">// SIO_GPIO_HI_OE</span></div>
 215 <div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    <span class="comment">// Output enable value for GPIO32</span></div>
 216 <div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2...</span></div>
 217 <div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) Output enable value for QSPI CSn pin</span></div>
 218 <div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) Output enable value for QSPI SCK pin</span></div>
 219 <div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) Output enable value for USB D- pin</span></div>
 220 <div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) Output enable value for USB D+ pin</span></div>
 221 <div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) Output enable value for GPIO32</span></div>
 222 <div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span>    io_rw_32 gpio_hi_oe;</div>
 223 <div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span> </div>
 224 <div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>    _REG_(SIO_GPIO_OE_SET_OFFSET) <span class="comment">// SIO_GPIO_OE_SET</span></div>
 225 <div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span>    <span class="comment">// GPIO0</span></div>
 226 <div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_OE_SET  (0x00000000) Perform an atomic bit-set on GPIO_OE, i</span></div>
 227 <div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span>    io_wo_32 gpio_oe_set;</div>
 228 <div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span> </div>
 229 <div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    _REG_(SIO_GPIO_HI_OE_SET_OFFSET) <span class="comment">// SIO_GPIO_HI_OE_SET</span></div>
 230 <div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span>    <span class="comment">// Output enable set for GPIO32</span></div>
 231 <div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) </span></div>
 232 <div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) </span></div>
 233 <div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) </span></div>
 234 <div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) </span></div>
 235 <div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) </span></div>
 236 <div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) </span></div>
 237 <div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    io_wo_32 gpio_hi_oe_set;</div>
 238 <div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span> </div>
 239 <div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    _REG_(SIO_GPIO_OE_CLR_OFFSET) <span class="comment">// SIO_GPIO_OE_CLR</span></div>
 240 <div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span>    <span class="comment">// GPIO0</span></div>
 241 <div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_OE_CLR  (0x00000000) Perform an atomic bit-clear on GPIO_OE, i</span></div>
 242 <div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span>    io_wo_32 gpio_oe_clr;</div>
 243 <div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span> </div>
 244 <div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>    _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) <span class="comment">// SIO_GPIO_HI_OE_CLR</span></div>
 245 <div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    <span class="comment">// Output enable clear for GPIO32</span></div>
 246 <div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) </span></div>
 247 <div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) </span></div>
 248 <div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) </span></div>
 249 <div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) </span></div>
 250 <div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) </span></div>
 251 <div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) </span></div>
 252 <div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span>    io_wo_32 gpio_hi_oe_clr;</div>
 253 <div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span> </div>
 254 <div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>    _REG_(SIO_GPIO_OE_XOR_OFFSET) <span class="comment">// SIO_GPIO_OE_XOR</span></div>
 255 <div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span>    <span class="comment">// GPIO0</span></div>
 256 <div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>    <span class="comment">// 0xffffffff [31:0]  GPIO_OE_XOR  (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i</span></div>
 257 <div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span>    io_wo_32 gpio_oe_togl;</div>
 258 <div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span> </div>
 259 <div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span>    _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) <span class="comment">// SIO_GPIO_HI_OE_XOR</span></div>
 260 <div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>    <span class="comment">// Output enable XOR for GPIO32</span></div>
 261 <div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span>    <span class="comment">// 0xf0000000 [31:28] QSPI_SD      (0x0) </span></div>
 262 <div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span>    <span class="comment">// 0x08000000 [27]    QSPI_CSN     (0) </span></div>
 263 <div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>    <span class="comment">// 0x04000000 [26]    QSPI_SCK     (0) </span></div>
 264 <div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span>    <span class="comment">// 0x02000000 [25]    USB_DM       (0) </span></div>
 265 <div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>    <span class="comment">// 0x01000000 [24]    USB_DP       (0) </span></div>
 266 <div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span>    <span class="comment">// 0x0000ffff [15:0]  GPIO         (0x0000) </span></div>
 267 <div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>    io_wo_32 gpio_hi_oe_togl;</div>
 268 <div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span> </div>
 269 <div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span>    _REG_(SIO_FIFO_ST_OFFSET) <span class="comment">// SIO_FIFO_ST</span></div>
 270 <div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span>    <span class="comment">// Status register for inter-core FIFOs (mailboxes).</span></div>
 271 <div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>    <span class="comment">// 0x00000008 [3]     ROE          (0) Sticky flag indicating the RX FIFO was read when empty</span></div>
 272 <div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>    <span class="comment">// 0x00000004 [2]     WOF          (0) Sticky flag indicating the TX FIFO was written when full</span></div>
 273 <div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span>    <span class="comment">// 0x00000002 [1]     RDY          (1) Value is 1 if this core&#39;s TX FIFO is not full (i</span></div>
 274 <div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span>    <span class="comment">// 0x00000001 [0]     VLD          (0) Value is 1 if this core&#39;s RX FIFO is not empty (i</span></div>
 275 <div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span>    io_rw_32 fifo_st;</div>
 276 <div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span> </div>
 277 <div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span>    _REG_(SIO_FIFO_WR_OFFSET) <span class="comment">// SIO_FIFO_WR</span></div>
 278 <div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span>    <span class="comment">// Write access to this core&#39;s TX FIFO</span></div>
 279 <div class="line"><a id="l00177" name="l00177"></a><span class="lineno">  177</span>    <span class="comment">// 0xffffffff [31:0]  FIFO_WR      (0x00000000) </span></div>
 280 <div class="line"><a id="l00178" name="l00178"></a><span class="lineno">  178</span>    io_wo_32 fifo_wr;</div>
 281 <div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span> </div>
 282 <div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span>    _REG_(SIO_FIFO_RD_OFFSET) <span class="comment">// SIO_FIFO_RD</span></div>
 283 <div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span>    <span class="comment">// Read access to this core&#39;s RX FIFO</span></div>
 284 <div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span>    <span class="comment">// 0xffffffff [31:0]  FIFO_RD      (-) </span></div>
 285 <div class="line"><a id="l00183" name="l00183"></a><span class="lineno">  183</span>    io_ro_32 fifo_rd;</div>
 286 <div class="line"><a id="l00184" name="l00184"></a><span class="lineno">  184</span> </div>
 287 <div class="line"><a id="l00185" name="l00185"></a><span class="lineno">  185</span>    _REG_(SIO_SPINLOCK_ST_OFFSET) <span class="comment">// SIO_SPINLOCK_ST</span></div>
 288 <div class="line"><a id="l00186" name="l00186"></a><span class="lineno">  186</span>    <span class="comment">// Spinlock state</span></div>
 289 <div class="line"><a id="l00187" name="l00187"></a><span class="lineno">  187</span>    <span class="comment">// 0xffffffff [31:0]  SPINLOCK_ST  (0x00000000) </span></div>
 290 <div class="line"><a id="l00188" name="l00188"></a><span class="lineno">  188</span>    io_ro_32 spinlock_st;</div>
 291 <div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span> </div>
 292 <div class="line"><a id="l00190" name="l00190"></a><span class="lineno">  190</span>    uint32_t _pad1[8];</div>
 293 <div class="line"><a id="l00191" name="l00191"></a><span class="lineno">  191</span> </div>
 294 <div class="line"><a id="l00192" name="l00192"></a><span class="lineno">  192</span>    <a class="code hl_struct" href="structinterp__hw__t.html">interp_hw_t</a> interp[2];</div>
 295 <div class="line"><a id="l00193" name="l00193"></a><span class="lineno">  193</span> </div>
 296 <div class="line"><a id="l00194" name="l00194"></a><span class="lineno">  194</span>    <span class="comment">// (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes)</span></div>
 297 <div class="line"><a id="l00195" name="l00195"></a><span class="lineno">  195</span>    _REG_(SIO_SPINLOCK0_OFFSET) <span class="comment">// SIO_SPINLOCK0</span></div>
 298 <div class="line"><a id="l00196" name="l00196"></a><span class="lineno">  196</span>    <span class="comment">// Spinlock register 0</span></div>
 299 <div class="line"><a id="l00197" name="l00197"></a><span class="lineno">  197</span>    <span class="comment">// 0xffffffff [31:0]  SPINLOCK0    (0x00000000) </span></div>
 300 <div class="line"><a id="l00198" name="l00198"></a><span class="lineno">  198</span>    io_rw_32 spinlock[32];</div>
 301 <div class="line"><a id="l00199" name="l00199"></a><span class="lineno">  199</span> </div>
 302 <div class="line"><a id="l00200" name="l00200"></a><span class="lineno">  200</span>    _REG_(SIO_DOORBELL_OUT_SET_OFFSET) <span class="comment">// SIO_DOORBELL_OUT_SET</span></div>
 303 <div class="line"><a id="l00201" name="l00201"></a><span class="lineno">  201</span>    <span class="comment">// Trigger a doorbell interrupt on the opposite core</span></div>
 304 <div class="line"><a id="l00202" name="l00202"></a><span class="lineno">  202</span>    <span class="comment">// 0x000000ff [7:0]   DOORBELL_OUT_SET (0x00) </span></div>
 305 <div class="line"><a id="l00203" name="l00203"></a><span class="lineno">  203</span>    io_rw_32 doorbell_out_set;</div>
 306 <div class="line"><a id="l00204" name="l00204"></a><span class="lineno">  204</span> </div>
 307 <div class="line"><a id="l00205" name="l00205"></a><span class="lineno">  205</span>    _REG_(SIO_DOORBELL_OUT_CLR_OFFSET) <span class="comment">// SIO_DOORBELL_OUT_CLR</span></div>
 308 <div class="line"><a id="l00206" name="l00206"></a><span class="lineno">  206</span>    <span class="comment">// Clear doorbells which have been posted to the opposite core</span></div>
 309 <div class="line"><a id="l00207" name="l00207"></a><span class="lineno">  207</span>    <span class="comment">// 0x000000ff [7:0]   DOORBELL_OUT_CLR (0x00) </span></div>
 310 <div class="line"><a id="l00208" name="l00208"></a><span class="lineno">  208</span>    io_rw_32 doorbell_out_clr;</div>
 311 <div class="line"><a id="l00209" name="l00209"></a><span class="lineno">  209</span> </div>
 312 <div class="line"><a id="l00210" name="l00210"></a><span class="lineno">  210</span>    _REG_(SIO_DOORBELL_IN_SET_OFFSET) <span class="comment">// SIO_DOORBELL_IN_SET</span></div>
 313 <div class="line"><a id="l00211" name="l00211"></a><span class="lineno">  211</span>    <span class="comment">// Write 1s to trigger doorbell interrupts on this core</span></div>
 314 <div class="line"><a id="l00212" name="l00212"></a><span class="lineno">  212</span>    <span class="comment">// 0x000000ff [7:0]   DOORBELL_IN_SET (0x00) </span></div>
 315 <div class="line"><a id="l00213" name="l00213"></a><span class="lineno">  213</span>    io_rw_32 doorbell_in_set;</div>
 316 <div class="line"><a id="l00214" name="l00214"></a><span class="lineno">  214</span> </div>
 317 <div class="line"><a id="l00215" name="l00215"></a><span class="lineno">  215</span>    _REG_(SIO_DOORBELL_IN_CLR_OFFSET) <span class="comment">// SIO_DOORBELL_IN_CLR</span></div>
 318 <div class="line"><a id="l00216" name="l00216"></a><span class="lineno">  216</span>    <span class="comment">// Check and acknowledge doorbells posted to this core</span></div>
 319 <div class="line"><a id="l00217" name="l00217"></a><span class="lineno">  217</span>    <span class="comment">// 0x000000ff [7:0]   DOORBELL_IN_CLR (0x00) </span></div>
 320 <div class="line"><a id="l00218" name="l00218"></a><span class="lineno">  218</span>    io_rw_32 doorbell_in_clr;</div>
 321 <div class="line"><a id="l00219" name="l00219"></a><span class="lineno">  219</span> </div>
 322 <div class="line"><a id="l00220" name="l00220"></a><span class="lineno">  220</span>    _REG_(SIO_PERI_NONSEC_OFFSET) <span class="comment">// SIO_PERI_NONSEC</span></div>
 323 <div class="line"><a id="l00221" name="l00221"></a><span class="lineno">  221</span>    <span class="comment">// Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so...</span></div>
 324 <div class="line"><a id="l00222" name="l00222"></a><span class="lineno">  222</span>    <span class="comment">// 0x00000020 [5]     TMDS         (0) IF 1, detach TMDS encoder (of this core) from the Secure...</span></div>
 325 <div class="line"><a id="l00223" name="l00223"></a><span class="lineno">  223</span>    <span class="comment">// 0x00000002 [1]     INTERP1      (0) If 1, detach interpolator 1 (of this core) from the...</span></div>
 326 <div class="line"><a id="l00224" name="l00224"></a><span class="lineno">  224</span>    <span class="comment">// 0x00000001 [0]     INTERP0      (0) If 1, detach interpolator 0 (of this core) from the...</span></div>
 327 <div class="line"><a id="l00225" name="l00225"></a><span class="lineno">  225</span>    io_rw_32 peri_nonsec;</div>
 328 <div class="line"><a id="l00226" name="l00226"></a><span class="lineno">  226</span> </div>
 329 <div class="line"><a id="l00227" name="l00227"></a><span class="lineno">  227</span>    uint32_t _pad2[3];</div>
 330 <div class="line"><a id="l00228" name="l00228"></a><span class="lineno">  228</span> </div>
 331 <div class="line"><a id="l00229" name="l00229"></a><span class="lineno">  229</span>    _REG_(SIO_RISCV_SOFTIRQ_OFFSET) <span class="comment">// SIO_RISCV_SOFTIRQ</span></div>
 332 <div class="line"><a id="l00230" name="l00230"></a><span class="lineno">  230</span>    <span class="comment">// Control the assertion of the standard software interrupt (MIP</span></div>
 333 <div class="line"><a id="l00231" name="l00231"></a><span class="lineno">  231</span>    <span class="comment">// 0x00000200 [9]     CORE1_CLR    (0) Write 1 to atomically clear the core 1 software interrupt flag</span></div>
 334 <div class="line"><a id="l00232" name="l00232"></a><span class="lineno">  232</span>    <span class="comment">// 0x00000100 [8]     CORE0_CLR    (0) Write 1 to atomically clear the core 0 software interrupt flag</span></div>
 335 <div class="line"><a id="l00233" name="l00233"></a><span class="lineno">  233</span>    <span class="comment">// 0x00000002 [1]     CORE1_SET    (0) Write 1 to atomically set the core 1 software interrupt flag</span></div>
 336 <div class="line"><a id="l00234" name="l00234"></a><span class="lineno">  234</span>    <span class="comment">// 0x00000001 [0]     CORE0_SET    (0) Write 1 to atomically set the core 0 software interrupt flag</span></div>
 337 <div class="line"><a id="l00235" name="l00235"></a><span class="lineno">  235</span>    io_rw_32 riscv_softirq;</div>
 338 <div class="line"><a id="l00236" name="l00236"></a><span class="lineno">  236</span> </div>
 339 <div class="line"><a id="l00237" name="l00237"></a><span class="lineno">  237</span>    _REG_(SIO_MTIME_CTRL_OFFSET) <span class="comment">// SIO_MTIME_CTRL</span></div>
 340 <div class="line"><a id="l00238" name="l00238"></a><span class="lineno">  238</span>    <span class="comment">// Control register for the RISC-V 64-bit Machine-mode timer</span></div>
 341 <div class="line"><a id="l00239" name="l00239"></a><span class="lineno">  239</span>    <span class="comment">// 0x00000008 [3]     DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state</span></div>
 342 <div class="line"><a id="l00240" name="l00240"></a><span class="lineno">  240</span>    <span class="comment">// 0x00000004 [2]     DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state</span></div>
 343 <div class="line"><a id="l00241" name="l00241"></a><span class="lineno">  241</span>    <span class="comment">// 0x00000002 [1]     FULLSPEED    (0) If 1, increment the timer every cycle (i</span></div>
 344 <div class="line"><a id="l00242" name="l00242"></a><span class="lineno">  242</span>    <span class="comment">// 0x00000001 [0]     EN           (1) Timer enable bit</span></div>
 345 <div class="line"><a id="l00243" name="l00243"></a><span class="lineno">  243</span>    io_rw_32 mtime_ctrl;</div>
 346 <div class="line"><a id="l00244" name="l00244"></a><span class="lineno">  244</span> </div>
 347 <div class="line"><a id="l00245" name="l00245"></a><span class="lineno">  245</span>    uint32_t _pad3[2];</div>
 348 <div class="line"><a id="l00246" name="l00246"></a><span class="lineno">  246</span> </div>
 349 <div class="line"><a id="l00247" name="l00247"></a><span class="lineno">  247</span>    _REG_(SIO_MTIME_OFFSET) <span class="comment">// SIO_MTIME</span></div>
 350 <div class="line"><a id="l00248" name="l00248"></a><span class="lineno">  248</span>    <span class="comment">// Read/write access to the high half of RISC-V Machine-mode timer</span></div>
 351 <div class="line"><a id="l00249" name="l00249"></a><span class="lineno">  249</span>    <span class="comment">// 0xffffffff [31:0]  MTIME        (0x00000000) </span></div>
 352 <div class="line"><a id="l00250" name="l00250"></a><span class="lineno">  250</span>    io_rw_32 mtime;</div>
 353 <div class="line"><a id="l00251" name="l00251"></a><span class="lineno">  251</span> </div>
 354 <div class="line"><a id="l00252" name="l00252"></a><span class="lineno">  252</span>    _REG_(SIO_MTIMEH_OFFSET) <span class="comment">// SIO_MTIMEH</span></div>
 355 <div class="line"><a id="l00253" name="l00253"></a><span class="lineno">  253</span>    <span class="comment">// Read/write access to the high half of RISC-V Machine-mode timer</span></div>
 356 <div class="line"><a id="l00254" name="l00254"></a><span class="lineno">  254</span>    <span class="comment">// 0xffffffff [31:0]  MTIMEH       (0x00000000) </span></div>
 357 <div class="line"><a id="l00255" name="l00255"></a><span class="lineno">  255</span>    io_rw_32 mtimeh;</div>
 358 <div class="line"><a id="l00256" name="l00256"></a><span class="lineno">  256</span> </div>
 359 <div class="line"><a id="l00257" name="l00257"></a><span class="lineno">  257</span>    _REG_(SIO_MTIMECMP_OFFSET) <span class="comment">// SIO_MTIMECMP</span></div>
 360 <div class="line"><a id="l00258" name="l00258"></a><span class="lineno">  258</span>    <span class="comment">// Low half of RISC-V Machine-mode timer comparator</span></div>
 361 <div class="line"><a id="l00259" name="l00259"></a><span class="lineno">  259</span>    <span class="comment">// 0xffffffff [31:0]  MTIMECMP     (0xffffffff) </span></div>
 362 <div class="line"><a id="l00260" name="l00260"></a><span class="lineno">  260</span>    io_rw_32 mtimecmp;</div>
 363 <div class="line"><a id="l00261" name="l00261"></a><span class="lineno">  261</span> </div>
 364 <div class="line"><a id="l00262" name="l00262"></a><span class="lineno">  262</span>    _REG_(SIO_MTIMECMPH_OFFSET) <span class="comment">// SIO_MTIMECMPH</span></div>
 365 <div class="line"><a id="l00263" name="l00263"></a><span class="lineno">  263</span>    <span class="comment">// High half of RISC-V Machine-mode timer comparator</span></div>
 366 <div class="line"><a id="l00264" name="l00264"></a><span class="lineno">  264</span>    <span class="comment">// 0xffffffff [31:0]  MTIMECMPH    (0xffffffff) </span></div>
 367 <div class="line"><a id="l00265" name="l00265"></a><span class="lineno">  265</span>    io_rw_32 mtimecmph;</div>
 368 <div class="line"><a id="l00266" name="l00266"></a><span class="lineno">  266</span> </div>
 369 <div class="line"><a id="l00267" name="l00267"></a><span class="lineno">  267</span>    _REG_(SIO_TMDS_CTRL_OFFSET) <span class="comment">// SIO_TMDS_CTRL</span></div>
 370 <div class="line"><a id="l00268" name="l00268"></a><span class="lineno">  268</span>    <span class="comment">// Control register for TMDS encoder</span></div>
 371 <div class="line"><a id="l00269" name="l00269"></a><span class="lineno">  269</span>    <span class="comment">// 0x10000000 [28]    CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders</span></div>
 372 <div class="line"><a id="l00270" name="l00270"></a><span class="lineno">  270</span>    <span class="comment">// 0x08000000 [27]    PIX2_NOSHIFT (0) When encoding two pixels&#39;s worth of symbols in one cycle...</span></div>
 373 <div class="line"><a id="l00271" name="l00271"></a><span class="lineno">  271</span>    <span class="comment">// 0x07000000 [26:24] PIX_SHIFT    (0x0) Shift applied to the colour data register with each read...</span></div>
 374 <div class="line"><a id="l00272" name="l00272"></a><span class="lineno">  272</span>    <span class="comment">// 0x00800000 [23]    INTERLEAVE   (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE</span></div>
 375 <div class="line"><a id="l00273" name="l00273"></a><span class="lineno">  273</span>    <span class="comment">// 0x001c0000 [20:18] L2_NBITS     (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,...</span></div>
 376 <div class="line"><a id="l00274" name="l00274"></a><span class="lineno">  274</span>    <span class="comment">// 0x00038000 [17:15] L1_NBITS     (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,...</span></div>
 377 <div class="line"><a id="l00275" name="l00275"></a><span class="lineno">  275</span>    <span class="comment">// 0x00007000 [14:12] L0_NBITS     (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,...</span></div>
 378 <div class="line"><a id="l00276" name="l00276"></a><span class="lineno">  276</span>    <span class="comment">// 0x00000f00 [11:8]  L2_ROT       (0x0) Right-rotate the 16 LSBs of the colour accumulator by...</span></div>
 379 <div class="line"><a id="l00277" name="l00277"></a><span class="lineno">  277</span>    <span class="comment">// 0x000000f0 [7:4]   L1_ROT       (0x0) Right-rotate the 16 LSBs of the colour accumulator by...</span></div>
 380 <div class="line"><a id="l00278" name="l00278"></a><span class="lineno">  278</span>    <span class="comment">// 0x0000000f [3:0]   L0_ROT       (0x0) Right-rotate the 16 LSBs of the colour accumulator by...</span></div>
 381 <div class="line"><a id="l00279" name="l00279"></a><span class="lineno">  279</span>    io_rw_32 tmds_ctrl;</div>
 382 <div class="line"><a id="l00280" name="l00280"></a><span class="lineno">  280</span> </div>
 383 <div class="line"><a id="l00281" name="l00281"></a><span class="lineno">  281</span>    _REG_(SIO_TMDS_WDATA_OFFSET) <span class="comment">// SIO_TMDS_WDATA</span></div>
 384 <div class="line"><a id="l00282" name="l00282"></a><span class="lineno">  282</span>    <span class="comment">// Write-only access to the TMDS colour data register</span></div>
 385 <div class="line"><a id="l00283" name="l00283"></a><span class="lineno">  283</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_WDATA   (0x00000000) </span></div>
 386 <div class="line"><a id="l00284" name="l00284"></a><span class="lineno">  284</span>    io_wo_32 tmds_wdata;</div>
 387 <div class="line"><a id="l00285" name="l00285"></a><span class="lineno">  285</span> </div>
 388 <div class="line"><a id="l00286" name="l00286"></a><span class="lineno">  286</span>    _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) <span class="comment">// SIO_TMDS_PEEK_SINGLE</span></div>
 389 <div class="line"><a id="l00287" name="l00287"></a><span class="lineno">  287</span>    <span class="comment">// Get the encoding of one pixel&#39;s worth of colour data, packed into a 32-bit value (3x10-bit symbols)</span></div>
 390 <div class="line"><a id="l00288" name="l00288"></a><span class="lineno">  288</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_PEEK_SINGLE (0x00000000) </span></div>
 391 <div class="line"><a id="l00289" name="l00289"></a><span class="lineno">  289</span>    io_ro_32 tmds_peek_single;</div>
 392 <div class="line"><a id="l00290" name="l00290"></a><span class="lineno">  290</span> </div>
 393 <div class="line"><a id="l00291" name="l00291"></a><span class="lineno">  291</span>    _REG_(SIO_TMDS_POP_SINGLE_OFFSET) <span class="comment">// SIO_TMDS_POP_SINGLE</span></div>
 394 <div class="line"><a id="l00292" name="l00292"></a><span class="lineno">  292</span>    <span class="comment">// Get the encoding of one pixel&#39;s worth of colour data, packed into a 32-bit value</span></div>
 395 <div class="line"><a id="l00293" name="l00293"></a><span class="lineno">  293</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_POP_SINGLE (0x00000000) </span></div>
 396 <div class="line"><a id="l00294" name="l00294"></a><span class="lineno">  294</span>    io_ro_32 tmds_pop_single;</div>
 397 <div class="line"><a id="l00295" name="l00295"></a><span class="lineno">  295</span> </div>
 398 <div class="line"><a id="l00296" name="l00296"></a><span class="lineno">  296</span>    _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) <span class="comment">// SIO_TMDS_PEEK_DOUBLE_L0</span></div>
 399 <div class="line"><a id="l00297" name="l00297"></a><span class="lineno">  297</span>    <span class="comment">// Get lane 0 of the encoding of two pixels&#39; worth of colour data</span></div>
 400 <div class="line"><a id="l00298" name="l00298"></a><span class="lineno">  298</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_PEEK_DOUBLE_L0 (0x00000000) </span></div>
 401 <div class="line"><a id="l00299" name="l00299"></a><span class="lineno">  299</span>    io_ro_32 tmds_peek_double_l0;</div>
 402 <div class="line"><a id="l00300" name="l00300"></a><span class="lineno">  300</span> </div>
 403 <div class="line"><a id="l00301" name="l00301"></a><span class="lineno">  301</span>    _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) <span class="comment">// SIO_TMDS_POP_DOUBLE_L0</span></div>
 404 <div class="line"><a id="l00302" name="l00302"></a><span class="lineno">  302</span>    <span class="comment">// Get lane 0 of the encoding of two pixels&#39; worth of colour data</span></div>
 405 <div class="line"><a id="l00303" name="l00303"></a><span class="lineno">  303</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_POP_DOUBLE_L0 (0x00000000) </span></div>
 406 <div class="line"><a id="l00304" name="l00304"></a><span class="lineno">  304</span>    io_ro_32 tmds_pop_double_l0;</div>
 407 <div class="line"><a id="l00305" name="l00305"></a><span class="lineno">  305</span> </div>
 408 <div class="line"><a id="l00306" name="l00306"></a><span class="lineno">  306</span>    _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) <span class="comment">// SIO_TMDS_PEEK_DOUBLE_L1</span></div>
 409 <div class="line"><a id="l00307" name="l00307"></a><span class="lineno">  307</span>    <span class="comment">// Get lane 1 of the encoding of two pixels&#39; worth of colour data</span></div>
 410 <div class="line"><a id="l00308" name="l00308"></a><span class="lineno">  308</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_PEEK_DOUBLE_L1 (0x00000000) </span></div>
 411 <div class="line"><a id="l00309" name="l00309"></a><span class="lineno">  309</span>    io_ro_32 tmds_peek_double_l1;</div>
 412 <div class="line"><a id="l00310" name="l00310"></a><span class="lineno">  310</span> </div>
 413 <div class="line"><a id="l00311" name="l00311"></a><span class="lineno">  311</span>    _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) <span class="comment">// SIO_TMDS_POP_DOUBLE_L1</span></div>
 414 <div class="line"><a id="l00312" name="l00312"></a><span class="lineno">  312</span>    <span class="comment">// Get lane 1 of the encoding of two pixels&#39; worth of colour data</span></div>
 415 <div class="line"><a id="l00313" name="l00313"></a><span class="lineno">  313</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_POP_DOUBLE_L1 (0x00000000) </span></div>
 416 <div class="line"><a id="l00314" name="l00314"></a><span class="lineno">  314</span>    io_ro_32 tmds_pop_double_l1;</div>
 417 <div class="line"><a id="l00315" name="l00315"></a><span class="lineno">  315</span> </div>
 418 <div class="line"><a id="l00316" name="l00316"></a><span class="lineno">  316</span>    _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) <span class="comment">// SIO_TMDS_PEEK_DOUBLE_L2</span></div>
 419 <div class="line"><a id="l00317" name="l00317"></a><span class="lineno">  317</span>    <span class="comment">// Get lane 2 of the encoding of two pixels&#39; worth of colour data</span></div>
 420 <div class="line"><a id="l00318" name="l00318"></a><span class="lineno">  318</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_PEEK_DOUBLE_L2 (0x00000000) </span></div>
 421 <div class="line"><a id="l00319" name="l00319"></a><span class="lineno">  319</span>    io_ro_32 tmds_peek_double_l2;</div>
 422 <div class="line"><a id="l00320" name="l00320"></a><span class="lineno">  320</span> </div>
 423 <div class="line"><a id="l00321" name="l00321"></a><span class="lineno">  321</span>    _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) <span class="comment">// SIO_TMDS_POP_DOUBLE_L2</span></div>
 424 <div class="line"><a id="l00322" name="l00322"></a><span class="lineno">  322</span>    <span class="comment">// Get lane 2 of the encoding of two pixels&#39; worth of colour data</span></div>
 425 <div class="line"><a id="l00323" name="l00323"></a><span class="lineno">  323</span>    <span class="comment">// 0xffffffff [31:0]  TMDS_POP_DOUBLE_L2 (0x00000000) </span></div>
 426 <div class="line"><a id="l00324" name="l00324"></a><span class="lineno">  324</span>    io_ro_32 tmds_pop_double_l2;</div>
 427 <div class="line"><a id="l00325" name="l00325"></a><span class="lineno">  325</span> </div>
 428 <div class="line"><a id="l00326" name="l00326"></a><span class="lineno">  326</span>} <a class="code hl_struct" href="structsio__hw__t.html">sio_hw_t</a>;</div>
 429 <div class="line"><a id="l00327" name="l00327"></a><span class="lineno">  327</span> </div>
 430 <div class="line"><a id="l00328" name="l00328"></a><span class="lineno">  328</span><span class="preprocessor">#define sio_hw ((sio_hw_t *)SIO_BASE)</span></div>
 431 <div class="line"><a id="l00329" name="l00329"></a><span class="lineno">  329</span><span class="preprocessor">#define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE)</span></div>
 432 <div class="line"><a id="l00330" name="l00330"></a><span class="lineno">  330</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structsio__hw__t.html">sio_hw_t</a>) == 0x01e8, <span class="stringliteral">&quot;&quot;</span>);</div>
 433 <div class="line"><a id="l00331" name="l00331"></a><span class="lineno">  331</span> </div>
 434 <div class="line"><a id="l00332" name="l00332"></a><span class="lineno">  332</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_SIO_H</span></div>
 435 <div class="line"><a id="l00333" name="l00333"></a><span class="lineno">  333</span> </div>
 436 <div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
 437 <div class="ttc" id="astructinterp__hw__t_html"><div class="ttname"><a href="structinterp__hw__t.html">interp_hw_t</a></div><div class="ttdef"><b>Definition:</b> interp.h:22</div></div>
 438 <div class="ttc" id="astructsio__hw__t_html"><div class="ttname"><a href="structsio__hw__t.html">sio_hw_t</a></div><div class="ttdef"><b>Definition:</b> sio.h:24</div></div>
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