Aric Cyr [Mon, 21 Oct 2024 01:41:45 +0000 (21:41 -0400)]
drm/amd/display: 3.2.307
This version brings along following fixes:
- Fix polling DSC registers during S0i3
- Fix idle optimizations entry log
- Change MPC Tree visual confirm colours
- Fix underflow when playing 8K video in full screen mode
- Optimize power up sequence for specific OLED
Samson Tam [Fri, 18 Oct 2024 04:26:41 +0000 (00:26 -0400)]
drm/amd/display: store sharpness 1dlut table in dscl_prog_data
[Why]
Previously dscl_prog_data stored pointer to sharpness 1dlut table.
SPL had four pre-generated tables, one for each setup. This allowed
us to minimize number of times we had to recalculate table when
switching between setups.
However, with dual display, this becomes an issue because for a given
setup, we could have a different per app sharpness value than the
global sharpness value. So the pre-generated table will change
but both displays may point to the same table and one of them
will have the wrong sharpness setting.
[How]
Store the sharpness 1dlut table in dscl_prog_data. This ensures
that each display can have its own sharpness setting.
Ovidiu Bunea [Tue, 15 Oct 2024 22:20:54 +0000 (18:20 -0400)]
drm/amd/display: Do not read DSC state if not in use
[why & how]
DSC may be power gated when coming out of S0i3, so avoid polling
DSC registers since it will fail anyways. Only read if it is known
that DSC is in use.
Aurabindo Pillai [Wed, 16 Oct 2024 17:08:02 +0000 (13:08 -0400)]
drm/amd/display: Fix idle optimizations entry log
[Why & How]
Whether we really enter idle optimizations are decided within DC.
Printing into dmesg before calling the DC API gives an incorrect
indication that we are entering idle optimization in cases where its
disabled manually.
To fix this, remove the print in DM and add them in DC
Joshua Aberback [Thu, 17 Oct 2024 19:56:30 +0000 (15:56 -0400)]
drm/amd/display: Change MPC Tree visual confirm colours
[Why]
MPC background colours that use fractional components look different if
MPC OGAM is in use vs in bypass mode. The current red and orange colours
look very similar when OGAM is in bypass, so the colours need to change
to be consistently very easy to tell apart.
[How]
Use colours that only have 0 or MAX values in each component
Alex Hung [Wed, 16 Oct 2024 18:18:39 +0000 (12:18 -0600)]
drm/amd/display: Remove useless assignments and variables
[WHAT & HOW]
misc0, temp and split_pipe are assigned but immediately re-assigned
to other values. The early assignments are useless and are removed.
Unused variables are removed as well.
This fixes 5 UNUSED_VALUE issues reported by Coverity.
Samson Tam [Wed, 16 Oct 2024 18:11:35 +0000 (14:11 -0400)]
drm/amd/display: fix handling of max_downscale_src_width fail check in SPL
[Why]
If max_downscale_src_width check fails, we exit early from
spl_calculate_scaler_params but dscl_prog_data is not fully
populated. If viewport is left at 0, it can cause crash in dml.
[How]
Call spl_set_dscl_prog_data before we exit early from
spl_calculate_scaler_params to populate dscl_prog_data
Populate taps in spl_get_optimal_number_of_taps
Leo Ma [Fri, 11 Oct 2024 18:08:34 +0000 (14:08 -0400)]
drm/amd/display: Fix underflow when playing 8K video in full screen mode
[Why&How]
Flickering observed while playing 8k HEVC-10 bit video in full screen
mode with black border. We didn't support this case for subvp.
Make change to the existing check to disable subvp for this corner case.
Fangzhi Zuo [Tue, 15 Oct 2024 18:22:32 +0000 (14:22 -0400)]
drm/amd/display: Reduce HPD Detection Interval for IPS
Fix DP Compliance test 4.2.1.3, 4.2.2.8, 4.3.1.12, 4.3.1.13
when IPS enabled.
Original HPD detection interval is set to 5s which violates DP
compliance.
Reduce the interval parameter, such that link training can be
finished within 5 seconds.
This reverts
commit 9dad21f910fc ("drm/amd/display: update DML2 policy EnhancedPrefetchScheduleAccelerationFinal DCN35")
[why & how]
The offending commit exposes a hang with lid close/open behavior.
Both issues seem to be related to ODM 2:1 mode switching, so there
is another issue generic to that sequence that needs to be
investigated.
Hansen Dsouza [Tue, 15 Oct 2024 21:33:15 +0000 (17:33 -0400)]
drm/amd/display: Add a boot option to reduce phy ssc for HBR3
[Why]
Spread on DPREFCLK by 0.3 percent can have a negative effect on sink
when PHY SSC is also spread by 0.3 percent
[How]
Add boot option for DMU to lower PHY SSC
Ovidiu Bunea [Fri, 11 Oct 2024 18:55:52 +0000 (14:55 -0400)]
drm/amd/display: Optimize power up sequence for specific OLED
[why & how]
OLED power up sequence takes an extra 150ms via hardcoded delay,
but there is a strict requirement on DisplayOn resume time.
For customer panel, remove these delays to meet target until a
cleaner solution is can be put in place.
Christian König [Tue, 8 Oct 2024 15:23:22 +0000 (17:23 +0200)]
drm/amdgpu: drop volatile from ring buffer
Volatile only prevents the compiler from re-ordering reads and writes.
Since we always only modify the ring buffer from one CPU thread and have
an explicit barrier before signaling the HW this should have no effect at
all and just prevents compiler optimisations.
Rodrigo Siqueira [Thu, 17 Oct 2024 03:34:27 +0000 (21:34 -0600)]
Documentation/gpu/amdgpu: Add programming model for DCN
One of the challenges to contributing to the display code is the
complexity of the DC component. This commit adds a documentation page
that discusses the programming model used by DCN and an overview of how
the display code is organized.
Rodrigo Siqueira [Thu, 17 Oct 2024 03:34:26 +0000 (21:34 -0600)]
Documentation/gpu: Document how to narrow down display issues
The amdgpu driver is composed of multiple components, each of which can
be a source of some specific problem that the user/developer can see.
This commit introduces steps to narrow down and collect display
information.
Kent Russell [Wed, 16 Oct 2024 18:26:33 +0000 (14:26 -0400)]
amdgpu: Don't print L2 status if there's nothing to print
If a 2nd fault comes in before the 1st is handled, the 1st fault will
clear out the FAULT STATUS registers before the 2nd fault is handled.
Thus we get a lot of zeroes. If status=0, just skip the L2 fault status
information, to avoid confusion of why some VM fault status prints in
dmesg are all zeroes.
Melissa Wen [Wed, 23 Oct 2024 13:53:17 +0000 (10:53 -0300)]
drm/amd/display: add missing tracepoint event in DM atomic_commit_tail
There are two events to trace the beginning and the end of
amdgpu_dm_atomic_commit_tail, but only the one ate the beginning was
placed. Place amdgpu_dm_atomic_commit_tail_finish tracepoint at the end
than.
Jonathan Kim [Fri, 20 Sep 2024 15:46:05 +0000 (11:46 -0400)]
drm/amdkfd: sever xgmi io link if host driver has disable sharing
Host drivers can create partial hives per guest by disabling xgmi sharing
between certain peers in the main hive.
Typically, these partial hives are fully connected per guest session.
In the event that the host makes a mistake by adding a non-shared node
to a guest session, have the KFD reflect sharing disabled by severing
the IO link.
Lijo Lazar [Thu, 17 Oct 2024 09:02:12 +0000 (14:32 +0530)]
drm/amdgpu: Fix the logic for NPS request failure
On a hive, NPS request is placed by the first one for all devices in the
hive. If the request fails, mark the mode as UNKNOWN so that subsequent
devices on unload don't request it. Also, fix the mutex double lock
issue in error condition, should have been mutex_unlock.
Lijo Lazar [Tue, 15 Oct 2024 03:13:45 +0000 (08:43 +0530)]
drm/amdgpu: Save VCN shared memory with init reset
VCN shared memory is in framebuffer and there are some flags initialized
during sw_init. Ideally, such programming should be during hw_init.
Make sure the flags are saved during reset on initialization since that
reset will affect frame buffer region. For clarity, separate it out to
another function.
drm/amd/display: Disable PSR-SU on Parade 08-01 TCON too
Stuart Hayhurst has found that both at bootup and fullscreen VA-API video
is leading to black screens for around 1 second and kernel WARNING [1] traces
when calling dmub_psr_enable() with Parade 08-01 TCON.
These symptoms all go away with PSR-SU disabled for this TCON, so disable
it for now while DMUB traces [2] from the failure can be analyzed and the failure
state properly root caused.
Victor Lu [Thu, 18 Jul 2024 22:01:23 +0000 (18:01 -0400)]
drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih
Port this change to vega20_ih.c:
commit afbf7955ff01 ("drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts")
Original commit message:
"Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear the RB_OVERFLOW."
This commit adds the cleaner shader microcode for GFX9.4.2 GPUs. The
cleaner shader is a piece of GPU code that is used to clear or
initialize certain GPU resources, such as Local Data Share (LDS), Vector
General Purpose Registers (VGPRs), and Scalar General Purpose Registers
(SGPRs).
Clearing these resources is important for ensuring data isolation
between different workloads running on the GPU. Without the cleaner
shader, residual data from a previous workload could potentially be
accessed by a subsequent workload, leading to data leaks and incorrect
computation results.
The cleaner shader microcode is represented as an array of 32-bit words
(`gfx_9_4_2_cleaner_shader_hex`). This array is the binary
representation of the cleaner shader code, which is written in a
low-level GPU instruction set.
Also, this patch updates the `gfx_v9_0_sw_init` function to initialize
the cleaner shader if the MEC firmware version is 88 or higher. It sets
the `cleaner_shader_ptr` and `cleaner_shader_size` to the appropriate
values and attempts to initialize the cleaner shader.
When the cleaner shader feature is enabled, the AMDGPU driver loads this
array into a specific location in the GPU memory. The GPU then reads
this memory location to fetch and execute the cleaner shader
instructions.
The cleaner shader is executed automatically by the GPU at the end of
each workload, before the next workload starts. This ensures that all
GPU resources are in a clean state before the start of each workload.
This change ensures that the GPU memory is properly cleared between
different processes, preventing data leakage and enhancing security. It
also aligns with the serialization mechanism between KGD and KFD,
ensuring that the GPU state is consistent across different workloads.
Aric Cyr [Mon, 14 Oct 2024 00:21:39 +0000 (20:21 -0400)]
drm/amd/display: 3.2.306
This version brings along following fixes:
- Fix dcn401 idle optimization problem
- Fix cursor corruption on dcn35
- Fix DP LL compliance failures
- Fix SubVP Phantom VBlank End calculation
Samson Tam [Wed, 9 Oct 2024 14:00:04 +0000 (10:00 -0400)]
drm/amd/display: update fullscreen status to SPL
[Why]
Current fullscreen check in SPL using dm_helpers is out-of-sync
with dc state. This causes an issue during minimal transition
where we pick an invalid intermediate state because the pre and
post fullscreen status are different.
[How]
Add sharpening_required flag to dc_stream_state. Use this flag to
indicate if we are in fullscreen or not. Propagate flag to SPL for
fullscreen status. Remove workaround in DML
Dillon Varone [Tue, 8 Oct 2024 19:25:45 +0000 (15:25 -0400)]
drm/amd/display: Recalculate SubVP Phantom VBlank End in dml21
[WHY]
The phantom stream timing is copied from the main stream as most
parameters are identical, however some need to be recalculated.
Currently VBlank End is not recalculated and copied from the main
incorrectly.
[HOW]
Recalculate VBlank End for phantom stream timing.
drm/amd/display: temp w/a for DP Link Layer compliance
[Why&How]
Disabling P-State support on full updates for DCN401 results in
introducing additional communication with SMU. A UCLK hard min message
to SMU takes 4 seconds to go through, which was due to DCN not allowing
pstate switch, which was caused by incorrect value for TTU watermark
before blanking the HUBP prior to DPG on for servicing the test request.
Fix the issue temporarily by disallowing pstate changes for compliance
test while test request handler is reworked for a proper fix.
Yihan Zhu [Mon, 7 Oct 2024 18:32:59 +0000 (14:32 -0400)]
drm/amd/display: w/a to program DISPCLK_R_GATE_DISABLE DCN35
[WHY & HOW]
Cursor corruption observed on USBC display with specific system setup with a
reboot. Cursor memory might still in the lightsleep state due to voltage
issue, we need program DISPCLK_R_GATE_DISABLE to avoid this issue only on
DCN35.
drm/amd/display: temp w/a for dGPU to enter idle optimizations
[Why&How]
vblank immediate disable currently does not work for all asics. On
DCN401, the vblank interrupts never stop coming, and hence we never
get a chance to trigger idle optimizations.
Add a workaround to enable immediate disable only on APUs for now. This
adds a 2-frame delay for triggering idle optimization, which is a
negligible overhead.
Fixes: 58a261bfc967 ("drm/amd/display: use a more lax vblank enable policy for older ASICs") Fixes: e45b6716de4b ("drm/amd/display: use a more lax vblank enable policy for DCN35+") Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
drm/amd/display: Add hpd_source index check for dcn401 link encoder setup
This patch adds a boundary check for the hpd_source index during the
link encoder creation process for all dcn401 ip. The check ensures that the
index is within the valid range of the link_enc_hpd_regs array to
prevent out-of-bounds access.
drm/amd/display: Add hpd_source index check for dcn10 link encoder setup
This patch adds a boundary check for the hpd_source index during the
link encoder creation process for all dcn10 ip. The check ensures that the
index is within the valid range of the link_enc_hpd_regs array to
prevent out-of-bounds access.
drm/amd/display: Add hpd_source index check for DCE60/80/100/110/112/120 link encoders
This patch adds a boundary check for the hpd_source index during the
link encoder creation process for all DCExxx IP's. The check ensures
that the index is within the valid range of the link_enc_hpd_regs array
to prevent out-of-bounds access.
Lijo Lazar [Mon, 14 Oct 2024 07:40:13 +0000 (13:10 +0530)]
drm/amdgpu: Use SPX as default in partition config
In certain cases - ex: when a reset is required on initialization - XCP
manager won't have a valid partition mode. In such cases, use SPX as the
default selected mode for which partition configuration details are
populated.
drm/amd/display: Ensure HPD source index is valid for dcn20/dcn201 link encoders
This patch adds a boundary check for the hpd_source index during the
link encoder creation process for dcn20/dcn201 IP's. The check ensures
that the index is within the valid range of the link_enc_hpd_regs array
to prevent out-of-bounds access.
Alex Deucher [Tue, 1 Oct 2024 14:31:26 +0000 (10:31 -0400)]
drm/amdgpu/swsmu: add automatic parameter to set_soft_freq_range
On chips that support it, you can specificy 0 and 0xffff for
min and max and the PMFW will use that to determine the optimal
min and max. This enables optimal performance when the
user manually switches between performance levels using sysfs.
Previously we'd set soft min/max which could limit performance.
Alex Deucher [Thu, 3 Oct 2024 13:57:38 +0000 (09:57 -0400)]
drm/amdgpu/swsmu: default to fullscreen 3D profile for dGPUs
This uses more aggressive hueristics than the the bootup default
profile. On windows the OS has a special fullscreen 3D mode
where this is used. Since we don't have the equivalent on Linux
default to this profile for dGPUs.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3618 Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1500 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3131 Fixes: c50fe289ed72 ("drm/amdgpu/swsmu: always force a state reprogram on init") Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Ville Syrjälä [Mon, 14 Oct 2024 16:09:36 +0000 (19:09 +0300)]
drm/radeon: Fix encoder->possible_clones
Include the encoder itself in its possible_clones bitmask.
In the past nothing validated that drivers were populating
possible_clones correctly, but that changed in commit 74d2aacbe840 ("drm: Validate encoder->possible_clones").
Looks like radeon never got the memo and is still not
following the rules 100% correctly.
This results in some warnings during driver initialization:
Bogus possible_clones: [ENCODER:46:TV-46] possible_clones=0x4 (full encoder mask=0x7)
WARNING: CPU: 0 PID: 170 at drivers/gpu/drm/drm_mode_config.c:615 drm_mode_config_validate+0x113/0x39c
...
Joshua Aberback [Thu, 3 Oct 2024 21:28:11 +0000 (17:28 -0400)]
drm/amd/display: Clear pipe pointers on pipe reset
[Why]
We want to clean up unnecessary asserts, one of which is an assert in
resource_is_pipe_type that fires if a pipe has no stream and still has
pointers to other pipes ("dangling state"). This gets hit because pipes
are not properly cleaned up in reset_back_end_for_pipe. When resetting a
pipe, the existing MPCC / ODM combine pointers are no longer valid,
especially when we put ODM in bypass.
[How]
- reset pipe pointers in reset_back_end_for_pipe
- remove useless code to avoid confusion
(a long time ago it had a reason to be there, not anymore)
Leo Chen [Thu, 3 Oct 2024 16:20:23 +0000 (12:20 -0400)]
drm/amd/display: Full exit out of IPS2 when all allow signals have been cleared
[Why]
A race condition occurs between cursor movement and vertical interrupt control
thread from OS, with both threads trying to exit IPS2.
Vertical interrupt control thread clears the prev driver allow signal while not fully
finishing the IPS2 exit process.
[How]
We want to detect all the allow signals have been cleared before we perform the full exit.
[Why]
There is a known HW bug that causes the internal 3DLUT fetch signal to
be lost at VREADY, regardless of whether the OTG lock is being held or
not. A workaround is necessary to make sure that this internal signal
stays up after OTG unlock.
[How]
Set the 3DLUT_ENABLE bit immediately before and after the unlock. Also
use VUPDATE_KEEPOUT to prevent lock transition in the region between
VSTARTUP and VREADY, which could cause issues with this WA sequence.
Also including misc. 3DLUT DMA-related sequence fixes to address a few
regressions causing corruption.
Roman Li [Mon, 30 Sep 2024 22:18:35 +0000 (18:18 -0400)]
drm/amd/display: Add check for headless for idle optimization
[Why]
Currently idle worker thread that checks for HPD while system is in IPS2
only supports headless and static screen use-cases.
In other display-off scenarios hotplug may not work.
[How]
For display-off only allow idle optimization when no display is connected.
Alex Hung [Mon, 30 Sep 2024 17:45:12 +0000 (11:45 -0600)]
drm/amd/display: Check status from dpcd_get_tunneling_device_data
[WHAT & HOW]
dpcd_get_tunneling_device_data calls core_link_read_dpcd which can
fail. The status from core_link_read_dpcd should be checked and error
messages is printed in case of failures.
This fixes 1 UNUSED_VALUE issue reported by Coverity.
Lijo Lazar [Mon, 7 Oct 2024 08:19:45 +0000 (13:49 +0530)]
drm/amdgpu: Wait for reset on init completion
When reset on initialization is requested, wait for the reset to finish.
In cases where module is loaded after boot, this makes sure all
initialization work is done after a successful return of modprobe.
Philip Yang [Fri, 4 Oct 2024 20:28:07 +0000 (16:28 -0400)]
drm/amdkfd: Accounting pdd vram_usage for svm
Process device data pdd->vram_usage is read by rocm-smi via sysfs, this
is currently missing the svm_bo usage accounting, so "rocm-smi
--showpids" per process VRAM usage report is incorrect.
Add pdd->vram_usage accounting when svm_bo allocation and release,
change to atomic64_t type because it is updated outside process mutex
now.
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