]> Git Repo - linux.git/commitdiff
drm/amd: Add the capability to mark certain firmware as "required"
authorMario Limonciello <[email protected]>
Tue, 3 Dec 2024 17:28:54 +0000 (11:28 -0600)
committerAlex Deucher <[email protected]>
Tue, 10 Dec 2024 15:26:51 +0000 (10:26 -0500)
Some of the firmware that is loaded by amdgpu is not actually required.
For example the ISP firmware on some SoCs is optional, and if it's not
present the ISP IP block just won't be initialized.

The firmware loader core however will show a warning when this happens
like this:
```
Direct firmware load for amdgpu/isp_4_1_0.bin failed with error -2
```

To avoid confusion for non-required firmware, adjust the amd-ucode helper
to take an extra argument indicating if the firmware is required or
optional.

On optional firmware use firmware_request_nowarn() instead of
request_firmware() to avoid the warnings.

Reviewed-by: Alex Deucher <[email protected]>
Link: https://lore.kernel.org/amd-gfx/[email protected]/T/#t
Signed-off-by: Mario Limonciello <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
35 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

index 16153d275d7ae5154f3fce4933fe434fc3291249..68bce6a6d09d1f77023eb8748d7e6382d9dfe467 100644 (file)
@@ -414,7 +414,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
                                return -EINVAL;
                        }
 
-                       err = amdgpu_ucode_request(adev, &adev->pm.fw, "%s", fw_name);
+                       err = amdgpu_ucode_request(adev, &adev->pm.fw,
+                                                  AMDGPU_UCODE_REQUIRED,
+                                                  "%s", fw_name);
                        if (err) {
                                DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
                                amdgpu_ucode_release(&adev->pm.fw);
index 63b1f1c0eb34d6ae4c61f44d427563e8430635d2..144295da9e4cc2bcf7fd3b68209fcf646314a735 100644 (file)
@@ -2485,6 +2485,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
        }
 
        err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw,
+                                  AMDGPU_UCODE_OPTIONAL,
                                   "amdgpu/%s_gpu_info.bin", chip_name);
        if (err) {
                dev_err(adev->dev,
index d52f183939707acc08207fc97eac9165412ddf8d..732744488b033653b610756038de50d650af2084 100644 (file)
@@ -77,7 +77,8 @@ static int isp_load_fw_by_psp(struct amdgpu_device *adev)
                                       sizeof(ucode_prefix));
 
        /* read isp fw */
-       r = amdgpu_ucode_request(adev, &adev->isp.fw, "amdgpu/%s.bin", ucode_prefix);
+       r = amdgpu_ucode_request(adev, &adev->isp.fw, AMDGPU_UCODE_OPTIONAL,
+                               "amdgpu/%s.bin", ucode_prefix);
        if (r) {
                amdgpu_ucode_release(&adev->isp.fw);
                return r;
index 59ec20b07a6af32f336f84856d437254577b9a72..32b27a1658e7823c4813301977c403cfb738b111 100644 (file)
@@ -1610,10 +1610,12 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)
                         pipe == AMDGPU_MES_SCHED_PIPE ? "" : "1");
        }
 
-       r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], "%s", fw_name);
+       r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], AMDGPU_UCODE_REQUIRED,
+                                "%s", fw_name);
        if (r && need_retry && pipe == AMDGPU_MES_SCHED_PIPE) {
                dev_info(adev->dev, "try to fall back to %s_mes.bin\n", ucode_prefix);
                r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe],
+                                        AMDGPU_UCODE_REQUIRED,
                                         "amdgpu/%s_mes.bin", ucode_prefix);
        }
 
index e08fd07ce707e6f2b274857801f6668d9625e46c..8ba2d5b8d523ad0a7af06f766322a37a220f6002 100644 (file)
@@ -3290,7 +3290,8 @@ int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
        const struct psp_firmware_header_v1_0 *asd_hdr;
        int err = 0;
 
-       err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, "amdgpu/%s_asd.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_asd.bin", chip_name);
        if (err)
                goto out;
 
@@ -3312,7 +3313,8 @@ int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
        const struct psp_firmware_header_v1_0 *toc_hdr;
        int err = 0;
 
-       err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, "amdgpu/%s_toc.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_toc.bin", chip_name);
        if (err)
                goto out;
 
@@ -3475,7 +3477,8 @@ int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
        uint8_t *ucode_array_start_addr;
        int err = 0;
 
-       err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, "amdgpu/%s_sos.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_sos.bin", chip_name);
        if (err)
                goto out;
 
@@ -3751,7 +3754,8 @@ int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
        struct amdgpu_device *adev = psp->adev;
        int err;
 
-       err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, "amdgpu/%s_ta.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_ta.bin", chip_name);
        if (err)
                return err;
 
@@ -3786,7 +3790,8 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
                return -EINVAL;
        }
 
-       err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, "amdgpu/%s_cap.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, AMDGPU_UCODE_OPTIONAL,
+                                  "amdgpu/%s_cap.bin", chip_name);
        if (err) {
                if (err == -ENODEV) {
                        dev_warn(adev->dev, "cap microcode does not exist, skip\n");
@@ -3909,7 +3914,8 @@ static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
        if (!drm_dev_enter(ddev, &idx))
                return -ENODEV;
 
-       ret = amdgpu_ucode_request(adev, &usbc_pd_fw, "amdgpu/%s", buf);
+       ret = amdgpu_ucode_request(adev, &usbc_pd_fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s", buf);
        if (ret)
                goto fail;
 
index 113f0d2426187e75a8d184f466ca32ebeaaa62a5..b3c032f249f5334f06a241988697c11c7bbaa9b6 100644 (file)
@@ -219,9 +219,11 @@ int amdgpu_sdma_init_microcode(struct amdgpu_device *adev,
        amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix));
        if (instance == 0)
                err = amdgpu_ucode_request(adev, &adev->sdma.instance[instance].fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s.bin", ucode_prefix);
        else
                err = amdgpu_ucode_request(adev, &adev->sdma.instance[instance].fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s%d.bin", ucode_prefix, instance);
        if (err)
                goto out;
index d3cd76c6dab3b7ce92d7a4416148dd6d4dfbb3fe..ffbb3377e0f67325140a46939229d741a3012a5e 100644 (file)
@@ -1434,6 +1434,7 @@ void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type,
  *
  * @adev: amdgpu device
  * @fw: pointer to load firmware to
+ * @required: whether the firmware is required
  * @fmt: firmware name format string
  * @...: variable arguments
  *
@@ -1442,7 +1443,7 @@ void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type,
  * the error code to -ENODEV, so that early_init functions will fail to load.
  */
 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
-                        const char *fmt, ...)
+                        enum amdgpu_ucode_required required, const char *fmt, ...)
 {
        char fname[AMDGPU_UCODE_NAME_MAX];
        va_list ap;
@@ -1456,7 +1457,10 @@ int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
                return -EOVERFLOW;
        }
 
-       r = request_firmware(fw, fname, adev->dev);
+       if (required == AMDGPU_UCODE_REQUIRED)
+               r = request_firmware(fw, fname, adev->dev);
+       else
+               r = firmware_request_nowarn(fw, fname, adev->dev);
        if (r)
                return -ENODEV;
 
index 4150ec0aa10d65ca66da5088c5d0ecbf43434283..9d0393f88bc2ae1cb7c9003a7d54f48cacb00510 100644 (file)
@@ -551,6 +551,11 @@ enum amdgpu_firmware_load_type {
        AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
 };
 
+enum amdgpu_ucode_required {
+       AMDGPU_UCODE_OPTIONAL,
+       AMDGPU_UCODE_REQUIRED,
+};
+
 /* conform to smu_ucode_xfer_cz.h */
 #define AMDGPU_SDMA0_UCODE_LOADED      0x00000001
 #define AMDGPU_SDMA1_UCODE_LOADED      0x00000002
@@ -604,9 +609,9 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
-__printf(3, 4)
+__printf(4, 5)
 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
-                        const char *fmt, ...);
+                        enum amdgpu_ucode_required required, const char *fmt, ...);
 void amdgpu_ucode_release(const struct firmware **fw);
 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
                                uint16_t hdr_major, uint16_t hdr_minor);
index bd2d3863c3ed1f03f2d5d9d0ae1a28a84e24e4be..dde15c6a96e1ae1939de40425af4fc85aa4b8b64 100644 (file)
@@ -587,7 +587,8 @@ int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch)
                break;
        }
 
-       r = amdgpu_ucode_request(adev, &adev->umsch_mm.fw, "%s", fw_name);
+       r = amdgpu_ucode_request(adev, &adev->umsch_mm.fw, AMDGPU_UCODE_REQUIRED,
+                                "%s", fw_name);
        if (r) {
                release_firmware(adev->umsch_mm.fw);
                adev->umsch_mm.fw = NULL;
index 65bb26215e867a9841e73c1bbb711adf33f4c379..74758b5ffc6c8fb28081e7a5242c247b169a955f 100644 (file)
@@ -260,7 +260,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
                return -EINVAL;
        }
 
-       r = amdgpu_ucode_request(adev, &adev->uvd.fw, "%s", fw_name);
+       r = amdgpu_ucode_request(adev, &adev->uvd.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name);
        if (r) {
                dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
                        fw_name);
index 599d3ca4e0ef9e20e55ae8a76840705f9f894326..65387f6943b4c51b65bae3f5f7dcc98d77314910 100644 (file)
@@ -158,7 +158,7 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
                return -EINVAL;
        }
 
-       r = amdgpu_ucode_request(adev, &adev->vce.fw, "%s", fw_name);
+       r = amdgpu_ucode_request(adev, &adev->vce.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name);
        if (r) {
                dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n",
                        fw_name);
index 05f01f50194bccd0c661e091b309a8df5aea4bf1..2455cc126e591ea5096e5b302b490667fcfc5276 100644 (file)
@@ -99,9 +99,13 @@ int amdgpu_vcn_early_init(struct amdgpu_device *adev)
        amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
        for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
                if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) ==  IP_VERSION(4, 0, 6))
-                       r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s_%d.bin", ucode_prefix, i);
+                       r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
+                                                AMDGPU_UCODE_REQUIRED,
+                                                "amdgpu/%s_%d.bin", ucode_prefix, i);
                else
-                       r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s.bin", ucode_prefix);
+                       r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
+                                                AMDGPU_UCODE_REQUIRED,
+                                                "amdgpu/%s.bin", ucode_prefix);
                if (r) {
                        amdgpu_ucode_release(&adev->vcn.inst[i].fw);
                        return r;
index 83cb9f565fe560a56441894c58fcaa34a15b2652..2c12840ea4443b0c5ab8b38575e83ce46879d17e 100644 (file)
@@ -236,7 +236,8 @@ int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)
        int ret;
 
        amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix));
-       ret = amdgpu_ucode_request(adev, &adev->vpe.fw, "amdgpu/%s.bin", fw_prefix);
+       ret = amdgpu_ucode_request(adev, &adev->vpe.fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s.bin", fw_prefix);
        if (ret)
                goto out;
 
index 1563e35da0fe2c6a09404526070ab1794c8652a6..a5cd950c94be4509f8147c4069d85cbbb68f94bf 100644 (file)
@@ -133,9 +133,11 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev)
        for (i = 0; i < adev->sdma.num_instances; i++) {
                if (i == 0)
                        err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_sdma.bin", chip_name);
                else
                        err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_sdma1.bin", chip_name);
                if (err)
                        goto out;
index f1b35b4a73ffb7d95cdc6ae5d54bec58808ddb3d..c4e15418e187ea9d8623c008a9534ad5413a3106 100644 (file)
@@ -4138,18 +4138,21 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
        amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 
        err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
        if (err)
                goto out;
        amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_me%s.bin", ucode_prefix, wks);
        if (err)
                goto out;
        amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
        if (err)
                goto out;
@@ -4173,6 +4176,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
        }
 
        err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
        if (err)
                goto out;
@@ -4180,6 +4184,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
        amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
        if (!err) {
                amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
index 11347b857bc9ce36edff6cee99826be06261c60e..f72ca5e4a44b95c4735a28fb74b02c89624de807 100644 (file)
@@ -639,6 +639,7 @@ static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *
        int err = 0;
 
        err = amdgpu_ucode_request(adev, &adev->psp.toc_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_toc.bin", ucode_prefix);
        if (err)
                goto out;
@@ -688,6 +689,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
 
        amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
        err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_pfp.bin", ucode_prefix);
        if (err)
                goto out;
@@ -705,6 +707,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
        }
 
        err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_me.bin", ucode_prefix);
        if (err)
                goto out;
@@ -720,9 +723,11 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
                if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) &&
                    adev->pdev->revision == 0xCE)
                        err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/gc_11_0_0_rlc_1.bin");
                else
                        err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_rlc.bin", ucode_prefix);
                if (err)
                        goto out;
@@ -735,6 +740,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
        }
 
        err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_mec.bin", ucode_prefix);
        if (err)
                goto out;
index 6fc67d2171774e39074e159c1f1bfdafd64753ac..ad5c4a5c95576a31ebf1c422a0792327ca61e3bc 100644 (file)
@@ -537,6 +537,7 @@ static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *
        int err = 0;
 
        err = amdgpu_ucode_request(adev, &adev->psp.toc_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_toc.bin", ucode_prefix);
        if (err)
                goto out;
@@ -566,6 +567,7 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
        amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 
        err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_pfp.bin", ucode_prefix);
        if (err)
                goto out;
@@ -573,6 +575,7 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
        amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_me.bin", ucode_prefix);
        if (err)
                goto out;
@@ -581,6 +584,7 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
 
        if (!amdgpu_sriov_vf(adev)) {
                err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_rlc.bin", ucode_prefix);
                if (err)
                        goto out;
@@ -593,6 +597,7 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
        }
 
        err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_mec.bin", ucode_prefix);
        if (err)
                goto out;
index 81c185a8b3a0735d0d228863770b4a44c1dc0cff..1b4c0dcee7e18ed9618f9b478709c715d1359cc7 100644 (file)
@@ -337,6 +337,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
        }
 
        err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_pfp.bin", chip_name);
        if (err)
                goto out;
@@ -345,6 +346,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
        adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_me.bin", chip_name);
        if (err)
                goto out;
@@ -353,6 +355,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
        adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_ce.bin", chip_name);
        if (err)
                goto out;
@@ -361,6 +364,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
        adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_rlc.bin", chip_name);
        if (err)
                goto out;
index 60931396f76b52a91e4f149e458438d308601ef7..17a07e1adffa7fc32926c7b64b484b84c06d13eb 100644 (file)
@@ -934,33 +934,39 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
        }
 
        err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_pfp.bin", chip_name);
        if (err)
                goto out;
 
        err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_me.bin", chip_name);
        if (err)
                goto out;
 
        err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_ce.bin", chip_name);
        if (err)
                goto out;
 
        err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_mec.bin", chip_name);
        if (err)
                goto out;
 
        if (adev->asic_type == CHIP_KAVERI) {
                err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_mec2.bin", chip_name);
                if (err)
                        goto out;
        }
 
        err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_rlc.bin", chip_name);
 out:
        if (err) {
index f15beb217b481ca44cd7a6a2ad1fcc3cff5880a0..576d21858c9436569e235e1d1463ee2a368a7e65 100644 (file)
@@ -982,13 +982,16 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 
        if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
                err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                          AMDGPU_UCODE_OPTIONAL,
                                           "amdgpu/%s_pfp_2.bin", chip_name);
                if (err == -ENODEV) {
                        err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_pfp.bin", chip_name);
                }
        } else {
                err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_pfp.bin", chip_name);
        }
        if (err)
@@ -999,13 +1002,16 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 
        if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
                err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                          AMDGPU_UCODE_OPTIONAL,
                                           "amdgpu/%s_me_2.bin", chip_name);
                if (err == -ENODEV) {
                        err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_me.bin", chip_name);
                }
        } else {
                err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_me.bin", chip_name);
        }
        if (err)
@@ -1017,13 +1023,16 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 
        if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
                err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
+                                          AMDGPU_UCODE_OPTIONAL,
                                           "amdgpu/%s_ce_2.bin", chip_name);
                if (err == -ENODEV) {
                        err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_ce.bin", chip_name);
                }
        } else {
                err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_ce.bin", chip_name);
        }
        if (err)
@@ -1044,6 +1053,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
                adev->virt.chained_ib_support = false;
 
        err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_rlc.bin", chip_name);
        if (err)
                goto out;
@@ -1093,13 +1103,16 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 
        if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
                err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
+                                          AMDGPU_UCODE_OPTIONAL,
                                           "amdgpu/%s_mec_2.bin", chip_name);
                if (err == -ENODEV) {
                        err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_mec.bin", chip_name);
                }
        } else {
                err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_mec.bin", chip_name);
        }
        if (err)
@@ -1112,13 +1125,16 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
            (adev->asic_type != CHIP_TOPAZ)) {
                if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
                        err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
+                                                  AMDGPU_UCODE_OPTIONAL,
                                                   "amdgpu/%s_mec2_2.bin", chip_name);
                        if (err == -ENODEV) {
                                err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
+                                                          AMDGPU_UCODE_REQUIRED,
                                                           "amdgpu/%s_mec2.bin", chip_name);
                        }
                } else {
                        err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_mec2.bin", chip_name);
                }
                if (!err) {
index 4e27528b7e571276dfdf45c02fec21f1b15fc093..30d9b6dacb6ef5bca604b453369d51a55190e521 100644 (file)
@@ -1429,18 +1429,21 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
        int err;
 
        err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_pfp.bin", chip_name);
        if (err)
                goto out;
        amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_me.bin", chip_name);
        if (err)
                goto out;
        amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 
        err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_ce.bin", chip_name);
        if (err)
                goto out;
@@ -1476,6 +1479,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
                (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
                ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
                err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_rlc_am4.bin", chip_name);
        else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) &&
                (smu_version >= 0x41e2b))
@@ -1483,9 +1487,11 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
                *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.
                */
                err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_kicker_rlc.bin", chip_name);
        else
                err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_rlc.bin", chip_name);
        if (err)
                goto out;
@@ -1518,9 +1524,11 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
 
        if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN))
                err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
-                                          "amdgpu/%s_sjt_mec.bin", chip_name);
+                                  AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_sjt_mec.bin", chip_name);
        else
                err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
+                                          AMDGPU_UCODE_REQUIRED,
                                           "amdgpu/%s_mec.bin", chip_name);
        if (err)
                goto out;
@@ -1531,9 +1539,11 @@ static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
        if (gfx_v9_0_load_mec2_fw_bin_support(adev)) {
                if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN))
                        err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_sjt_mec2.bin", chip_name);
                else
                        err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_mec2.bin", chip_name);
                if (!err) {
                        amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
index a7ad30357dab8fc1d5547ff6304378ff12e0877b..cb93fd85c19e7c6948e891db463a53d0c5abda94 100644 (file)
@@ -551,6 +551,7 @@ static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,
 
 
        err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+                                  AMDGPU_UCODE_REQUIRED,
                                   "amdgpu/%s_rlc.bin", chip_name);
        if (err)
                goto out;
@@ -584,10 +585,12 @@ static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,
 
        if (amdgpu_sriov_vf(adev))
                err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
-                               "amdgpu/%s_sjt_mec.bin", chip_name);
+                                          AMDGPU_UCODE_REQUIRED,
+                                          "amdgpu/%s_sjt_mec.bin", chip_name);
        else
                err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
-                               "amdgpu/%s_mec.bin", chip_name);
+                                          AMDGPU_UCODE_REQUIRED,
+                                          "amdgpu/%s_mec.bin", chip_name);
        if (err)
                goto out;
        amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
index 8e878ab44e76826956b543bc74ef9bc2013ba23d..2245dda92021c3b9f82bb82104391bd25251828e 100644 (file)
@@ -131,7 +131,8 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
        if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
                chip_name = "si58";
 
-       err = amdgpu_ucode_request(adev, &adev->gmc.fw, "amdgpu/%s_mc.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_mc.bin", chip_name);
        if (err) {
                dev_err(adev->dev,
                       "si_mc: Failed to load firmware \"%s_mc.bin\"\n",
index 347bccd92696f8a75637537d5b8c54107f748a69..9aac4b1101e3aa744e39614f534e14743efcfc04 100644 (file)
@@ -157,7 +157,8 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
                return -EINVAL;
        }
 
-       err = amdgpu_ucode_request(adev, &adev->gmc.fw, "amdgpu/%s_mc.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_mc.bin", chip_name);
        if (err) {
                pr_err("cik_mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name);
                amdgpu_ucode_release(&adev->gmc.fw);
index 29ce36038b3f3ec6453b381eb17f5ea8223be89e..d06585207c331b34716c591c20a57dadc3757330 100644 (file)
@@ -259,7 +259,8 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
                return -EINVAL;
        }
 
-       err = amdgpu_ucode_request(adev, &adev->gmc.fw, "amdgpu/%s_mc.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_mc.bin", chip_name);
        if (err) {
                pr_err("mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name);
                amdgpu_ucode_release(&adev->gmc.fw);
index d4f72e47ae9e2082ae9041ad050b6fa559b00092..aeca5c08ea2f2bd820149391df37bffccdfb4829 100644 (file)
@@ -50,7 +50,8 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
        DRM_DEBUG("\n");
 
        amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
-       err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, "amdgpu/%s_imu.bin", ucode_prefix);
+       err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_imu.bin", ucode_prefix);
        if (err)
                goto out;
 
index 1341f02920314e60d766e3df127c4236e32604a3..df898dbb746e3f848378c5b96c261afba97fe977 100644 (file)
@@ -47,7 +47,8 @@ static int imu_v12_0_init_microcode(struct amdgpu_device *adev)
        DRM_DEBUG("\n");
 
        amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
-       err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, "amdgpu/%s_imu.bin", ucode_prefix);
+       err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_imu.bin", ucode_prefix);
        if (err)
                goto out;
 
index c6af318908e4bbaf2ea2e2f847a2214f20ad9184..269bf1e3337b654e67f10f1ca714895b0d532a5d 100644 (file)
@@ -145,9 +145,11 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
        for (i = 0; i < adev->sdma.num_instances; i++) {
                if (i == 0)
                        err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_sdma.bin", chip_name);
                else
                        err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_sdma1.bin", chip_name);
                if (err)
                        goto out;
index d438f2f7a40804f5362c5e32e86a700e1265c07d..c9ad9ec48688ecb90133cbe65785d2d3aa076046 100644 (file)
@@ -305,9 +305,11 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
        for (i = 0; i < adev->sdma.num_instances; i++) {
                if (i == 0)
                        err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_sdma.bin", chip_name);
                else
                        err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
+                                                  AMDGPU_UCODE_REQUIRED,
                                                   "amdgpu/%s_sdma1.bin", chip_name);
                if (err)
                        goto out;
index cb869f5e99059ff2f61f221946eaacc615ca0832..34b480cb8914858df5dbaaeb458c6156aac5b85b 100644 (file)
@@ -2338,7 +2338,8 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
                return 0;
        }
 
-       r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, "%s", fw_name_dmcu);
+       r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED,
+                                "%s", fw_name_dmcu);
        if (r == -ENODEV) {
                /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
                DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
@@ -5306,7 +5307,8 @@ static int dm_init_microcode(struct amdgpu_device *adev)
                /* ASIC doesn't support DMUB. */
                return 0;
        }
-       r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, "%s", fw_name_dmub);
+       r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, AMDGPU_UCODE_REQUIRED,
+                                "%s", fw_name_dmub);
        return r;
 }
 
index 2bed85ba835ee7e4a983990cfa85e5152dae35fc..a87dcf0974bc1cd92bb6eb80fb6aa4f70649ed18 100644 (file)
@@ -7709,7 +7709,8 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev)
        default: BUG();
        }
 
-       err = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s_smc.bin", chip_name);
+       err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s_smc.bin", chip_name);
        if (err) {
                DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n",
                          err, chip_name);
index 480cf3cb204d2dc03e62c19bf268ad0e11af69a5..189c6a32b6bdb4b065ef5f551dcd3d6503e84972 100644 (file)
@@ -105,7 +105,8 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
                return 0;
 
        amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
-       err = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
+       err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s.bin", ucode_prefix);
        if (err)
                goto out;
 
index bb506d15d787f3f8e62807b292c74f6e176c1f91..7bb45ff6d5c856014c5c08cf5649a6587e3a4cb0 100644 (file)
@@ -103,7 +103,8 @@ int smu_v13_0_init_microcode(struct smu_context *smu)
                return 0;
 
        amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
-       err = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
+       err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s.bin", ucode_prefix);
        if (err)
                goto out;
 
index 8344f54e6674bfcd410435224c946611bdc813ab..5b86df0c8536efe69a8afa924299c7851bc21247 100644 (file)
@@ -305,7 +305,8 @@ static int smu_v13_0_6_init_microcode(struct smu_context *smu)
 
        amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
                                       sizeof(ucode_prefix));
-       ret  = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
+       ret  = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
+                                   "amdgpu/%s.bin", ucode_prefix);
        if (ret)
                goto out;
 
index 4d083f7f772e68efce29ed9ba6e4a219940ca2e0..9b2f4fe1578b8db32d8cf5db0768d3d80461c1e9 100644 (file)
@@ -79,7 +79,8 @@ int smu_v14_0_init_microcode(struct smu_context *smu)
                return 0;
 
        amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
-       err = amdgpu_ucode_request(adev, &adev->pm.fw, "amdgpu/%s.bin", ucode_prefix);
+       err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
+                                  "amdgpu/%s.bin", ucode_prefix);
        if (err)
                goto out;
 
This page took 0.120364 seconds and 4 git commands to generate.