drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <linux/dmi.h>
  30 #include <linux/pci.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drm_drv.h>
  33
  34 #include "amdgpu.h"
  35 #include "amdgpu_pm.h"
  36 #include "amdgpu_vcn.h"
  37 #include "soc15d.h"
  38
  39 /* Firmware Names */
  40 #define FIRMWARE_RAVEN                  "amdgpu/raven_vcn.bin"
  41 #define FIRMWARE_PICASSO                "amdgpu/picasso_vcn.bin"
  42 #define FIRMWARE_RAVEN2                 "amdgpu/raven2_vcn.bin"
  43 #define FIRMWARE_ARCTURUS               "amdgpu/arcturus_vcn.bin"
  44 #define FIRMWARE_RENOIR                 "amdgpu/renoir_vcn.bin"
  45 #define FIRMWARE_GREEN_SARDINE          "amdgpu/green_sardine_vcn.bin"
  46 #define FIRMWARE_NAVI10                 "amdgpu/navi10_vcn.bin"
  47 #define FIRMWARE_NAVI14                 "amdgpu/navi14_vcn.bin"
  48 #define FIRMWARE_NAVI12                 "amdgpu/navi12_vcn.bin"
  49 #define FIRMWARE_SIENNA_CICHLID         "amdgpu/sienna_cichlid_vcn.bin"
  50 #define FIRMWARE_NAVY_FLOUNDER          "amdgpu/navy_flounder_vcn.bin"
  51 #define FIRMWARE_VANGOGH                "amdgpu/vangogh_vcn.bin"
  52 #define FIRMWARE_DIMGREY_CAVEFISH       "amdgpu/dimgrey_cavefish_vcn.bin"
  53 #define FIRMWARE_ALDEBARAN              "amdgpu/aldebaran_vcn.bin"
  54 #define FIRMWARE_BEIGE_GOBY             "amdgpu/beige_goby_vcn.bin"
  55 #define FIRMWARE_YELLOW_CARP            "amdgpu/yellow_carp_vcn.bin"
  56 #define FIRMWARE_VCN_3_1_2              "amdgpu/vcn_3_1_2.bin"
  57 #define FIRMWARE_VCN4_0_0               "amdgpu/vcn_4_0_0.bin"
  58 #define FIRMWARE_VCN4_0_2               "amdgpu/vcn_4_0_2.bin"
  59 #define FIRMWARE_VCN4_0_3               "amdgpu/vcn_4_0_3.bin"
  60 #define FIRMWARE_VCN4_0_4               "amdgpu/vcn_4_0_4.bin"
  61 #define FIRMWARE_VCN4_0_5               "amdgpu/vcn_4_0_5.bin"
  62 #define FIRMWARE_VCN4_0_6               "amdgpu/vcn_4_0_6.bin"
  63 #define FIRMWARE_VCN4_0_6_1             "amdgpu/vcn_4_0_6_1.bin"
  64 #define FIRMWARE_VCN5_0_0               "amdgpu/vcn_5_0_0.bin"
  65
  66 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  67 MODULE_FIRMWARE(FIRMWARE_PICASSO);
  68 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
  69 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
  70 MODULE_FIRMWARE(FIRMWARE_RENOIR);
  71 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
  72 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
  73 MODULE_FIRMWARE(FIRMWARE_NAVI10);
  74 MODULE_FIRMWARE(FIRMWARE_NAVI14);
  75 MODULE_FIRMWARE(FIRMWARE_NAVI12);
  76 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
  77 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
  78 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
  79 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
  80 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
  81 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
  82 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
  83 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
  84 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
  85 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3);
  86 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
  87 MODULE_FIRMWARE(FIRMWARE_VCN4_0_5);
  88 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6);
  89 MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1);
  90 MODULE_FIRMWARE(FIRMWARE_VCN5_0_0);
  91
  92 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  93
  94 int amdgpu_vcn_early_init(struct amdgpu_device *adev)
  95 {
  96         char ucode_prefix[25];
  97         int r, i;
  98
  99         amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
 100         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 101                 if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) ==  IP_VERSION(4, 0, 6))
 102                         r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
 103                                                  AMDGPU_UCODE_REQUIRED,
 104                                                  "amdgpu/%s_%d.bin", ucode_prefix, i);
 105                 else
 106                         r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
 107                                                  AMDGPU_UCODE_REQUIRED,
 108                                                  "amdgpu/%s.bin", ucode_prefix);
 109                 if (r) {
 110                         amdgpu_ucode_release(&adev->vcn.inst[i].fw);
 111                         return r;
 112                 }
 113         }
 114         return r;
 115 }
 116
 117 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 118 {
 119         unsigned long bo_size;
 120         const struct common_firmware_header *hdr;
 121         unsigned char fw_check;
 122         unsigned int fw_shared_size, log_offset;
 123         int i, r;
 124
 125         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
 126         mutex_init(&adev->vcn.vcn_pg_lock);
 127         mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
 128         atomic_set(&adev->vcn.total_submission_cnt, 0);
 129         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
 130                 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
 131
 132         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 133             (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 134                 adev->vcn.indirect_sram = true;
 135
 136         /*
 137          * Some Steam Deck's BIOS versions are incompatible with the
 138          * indirect SRAM mode, leading to amdgpu being unable to get
 139          * properly probed (and even potentially crashing the kernel).
 140          * Hence, check for these versions here - notice this is
 141          * restricted to Vangogh (Deck's APU).
 142          */
 143         if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 0, 2)) {
 144                 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
 145
 146                 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) ||
 147                      !strncmp("F7A0114", bios_ver, 7))) {
 148                         adev->vcn.indirect_sram = false;
 149                         dev_info(adev->dev,
 150                                 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);
 151                 }
 152         }
 153
 154         /* from vcn4 and above, only unified queue is used */
 155         adev->vcn.using_unified_queue =
 156                 amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0);
 157
 158         hdr = (const struct common_firmware_header *)adev->vcn.inst[0].fw->data;
 159         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
 160
 161         /* Bit 20-23, it is encode major and non-zero for new naming convention.
 162          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
 163          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
 164          * is zero in old naming convention, this field is always zero so far.
 165          * These four bits are used to tell which naming convention is present.
 166          */
 167         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
 168         if (fw_check) {
 169                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
 170
 171                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
 172                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
 173                 enc_major = fw_check;
 174                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 175                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 176                 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
 177                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 178         } else {
 179                 unsigned int version_major, version_minor, family_id;
 180
 181                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 182                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 183                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 184                 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
 185                         version_major, version_minor, family_id);
 186         }
 187
 188         bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
 189         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 190                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 191
 192         if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) {
 193                 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared));
 194                 log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log);
 195         } else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) {
 196                 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
 197                 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
 198         } else {
 199                 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 200                 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
 201         }
 202
 203         bo_size += fw_shared_size;
 204
 205         if (amdgpu_vcnfw_log)
 206                 bo_size += AMDGPU_VCNFW_LOG_SIZE;
 207
 208         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 209                 if (adev->vcn.harvest_config & (1 << i))
 210                         continue;
 211
 212                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 213                                             AMDGPU_GEM_DOMAIN_VRAM |
 214                                             AMDGPU_GEM_DOMAIN_GTT,
 215                                             &adev->vcn.inst[i].vcpu_bo,
 216                                             &adev->vcn.inst[i].gpu_addr,
 217                                             &adev->vcn.inst[i].cpu_addr);
 218                 if (r) {
 219                         dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 220                         return r;
 221                 }
 222
 223                 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
 224                                 bo_size - fw_shared_size;
 225                 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
 226                                 bo_size - fw_shared_size;
 227
 228                 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
 229
 230                 if (amdgpu_vcnfw_log) {
 231                         adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
 232                         adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
 233                         adev->vcn.inst[i].fw_shared.log_offset = log_offset;
 234                 }
 235
 236                 if (adev->vcn.indirect_sram) {
 237                         r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
 238                                         AMDGPU_GEM_DOMAIN_VRAM |
 239                                         AMDGPU_GEM_DOMAIN_GTT,
 240                                         &adev->vcn.inst[i].dpg_sram_bo,
 241                                         &adev->vcn.inst[i].dpg_sram_gpu_addr,
 242                                         &adev->vcn.inst[i].dpg_sram_cpu_addr);
 243                         if (r) {
 244                                 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
 245                                 return r;
 246                         }
 247                 }
 248         }
 249
 250         return 0;
 251 }
 252
 253 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 254 {
 255         int i, j;
 256
 257         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 258                 if (adev->vcn.harvest_config & (1 << j))
 259                         continue;
 260
 261                 amdgpu_bo_free_kernel(
 262                         &adev->vcn.inst[j].dpg_sram_bo,
 263                         &adev->vcn.inst[j].dpg_sram_gpu_addr,
 264                         (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
 265
 266                 kvfree(adev->vcn.inst[j].saved_bo);
 267
 268                 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
 269                                           &adev->vcn.inst[j].gpu_addr,
 270                                           (void **)&adev->vcn.inst[j].cpu_addr);
 271
 272                 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
 273
 274                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 275                         amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
 276
 277                 amdgpu_ucode_release(&adev->vcn.inst[j].fw);
 278         }
 279
 280         mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
 281         mutex_destroy(&adev->vcn.vcn_pg_lock);
 282
 283         return 0;
 284 }
 285
 286 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
 287 {
 288         bool ret = false;
 289         int vcn_config = adev->vcn.inst[vcn_instance].vcn_config;
 290
 291         if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK))
 292                 ret = true;
 293         else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK))
 294                 ret = true;
 295         else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK))
 296                 ret = true;
 297
 298         return ret;
 299 }
 300
 301 int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev)
 302 {
 303         unsigned int size;
 304         void *ptr;
 305         int i, idx;
 306
 307         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 308                 if (adev->vcn.harvest_config & (1 << i))
 309                         continue;
 310                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 311                         return 0;
 312
 313                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 314                 ptr = adev->vcn.inst[i].cpu_addr;
 315
 316                 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
 317                 if (!adev->vcn.inst[i].saved_bo)
 318                         return -ENOMEM;
 319
 320                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 321                         memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
 322                         drm_dev_exit(idx);
 323                 }
 324         }
 325
 326         return 0;
 327 }
 328
 329 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 330 {
 331         bool in_ras_intr = amdgpu_ras_intr_triggered();
 332
 333         cancel_delayed_work_sync(&adev->vcn.idle_work);
 334
 335         /* err_event_athub will corrupt VCPU buffer, so we need to
 336          * restore fw data and clear buffer in amdgpu_vcn_resume() */
 337         if (in_ras_intr)
 338                 return 0;
 339
 340         return amdgpu_vcn_save_vcpu_bo(adev);
 341 }
 342
 343 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 344 {
 345         unsigned int size;
 346         void *ptr;
 347         int i, idx;
 348
 349         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 350                 if (adev->vcn.harvest_config & (1 << i))
 351                         continue;
 352                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 353                         return -EINVAL;
 354
 355                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 356                 ptr = adev->vcn.inst[i].cpu_addr;
 357
 358                 if (adev->vcn.inst[i].saved_bo != NULL) {
 359                         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 360                                 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
 361                                 drm_dev_exit(idx);
 362                         }
 363                         kvfree(adev->vcn.inst[i].saved_bo);
 364                         adev->vcn.inst[i].saved_bo = NULL;
 365                 } else {
 366                         const struct common_firmware_header *hdr;
 367                         unsigned int offset;
 368
 369                         hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
 370                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 371                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 372                                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 373                                         memcpy_toio(adev->vcn.inst[i].cpu_addr,
 374                                                     adev->vcn.inst[i].fw->data + offset,
 375                                                     le32_to_cpu(hdr->ucode_size_bytes));
 376                                         drm_dev_exit(idx);
 377                                 }
 378                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 379                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 380                         }
 381                         memset_io(ptr, 0, size);
 382                 }
 383         }
 384         return 0;
 385 }
 386
 387 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 388 {
 389         struct amdgpu_device *adev =
 390                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 391         unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
 392         unsigned int i, j;
 393         int r = 0;
 394
 395         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 396                 if (adev->vcn.harvest_config & (1 << j))
 397                         continue;
 398
 399                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 400                         fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
 401
 402                 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
 403                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
 404                     !adev->vcn.using_unified_queue) {
 405                         struct dpg_pause_state new_state;
 406
 407                         if (fence[j] ||
 408                                 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
 409                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 410                         else
 411                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 412
 413                         adev->vcn.pause_dpg_mode(adev, j, &new_state);
 414                 }
 415
 416                 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
 417                 fences += fence[j];
 418         }
 419
 420         if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
 421                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 422                        AMD_PG_STATE_GATE);
 423                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 424                                 false);
 425                 if (r)
 426                         dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
 427         } else {
 428                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 429         }
 430 }
 431
 432 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 433 {
 434         struct amdgpu_device *adev = ring->adev;
 435         int r = 0;
 436
 437         atomic_inc(&adev->vcn.total_submission_cnt);
 438
 439         if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
 440                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 441                                 true);
 442                 if (r)
 443                         dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
 444         }
 445
 446         mutex_lock(&adev->vcn.vcn_pg_lock);
 447         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 448                AMD_PG_STATE_UNGATE);
 449
 450         /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
 451         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
 452             !adev->vcn.using_unified_queue) {
 453                 struct dpg_pause_state new_state;
 454
 455                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
 456                         atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 457                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 458                 } else {
 459                         unsigned int fences = 0;
 460                         unsigned int i;
 461
 462                         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 463                                 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
 464
 465                         if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
 466                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 467                         else
 468                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 469                 }
 470
 471                 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
 472         }
 473         mutex_unlock(&adev->vcn.vcn_pg_lock);
 474 }
 475
 476 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 477 {
 478         struct amdgpu_device *adev = ring->adev;
 479
 480         /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
 481         if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
 482             ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC &&
 483             !adev->vcn.using_unified_queue)
 484                 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 485
 486         atomic_dec(&ring->adev->vcn.total_submission_cnt);
 487
 488         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 489 }
 490
 491 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 492 {
 493         struct amdgpu_device *adev = ring->adev;
 494         uint32_t tmp = 0;
 495         unsigned int i;
 496         int r;
 497
 498         /* VCN in SRIOV does not support direct register read/write */
 499         if (amdgpu_sriov_vf(adev))
 500                 return 0;
 501
 502         WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
 503         r = amdgpu_ring_alloc(ring, 3);
 504         if (r)
 505                 return r;
 506         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
 507         amdgpu_ring_write(ring, 0xDEADBEEF);
 508         amdgpu_ring_commit(ring);
 509         for (i = 0; i < adev->usec_timeout; i++) {
 510                 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
 511                 if (tmp == 0xDEADBEEF)
 512                         break;
 513                 udelay(1);
 514         }
 515
 516         if (i >= adev->usec_timeout)
 517                 r = -ETIMEDOUT;
 518
 519         return r;
 520 }
 521
 522 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
 523 {
 524         struct amdgpu_device *adev = ring->adev;
 525         uint32_t rptr;
 526         unsigned int i;
 527         int r;
 528
 529         if (amdgpu_sriov_vf(adev))
 530                 return 0;
 531
 532         r = amdgpu_ring_alloc(ring, 16);
 533         if (r)
 534                 return r;
 535
 536         rptr = amdgpu_ring_get_rptr(ring);
 537
 538         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
 539         amdgpu_ring_commit(ring);
 540
 541         for (i = 0; i < adev->usec_timeout; i++) {
 542                 if (amdgpu_ring_get_rptr(ring) != rptr)
 543                         break;
 544                 udelay(1);
 545         }
 546
 547         if (i >= adev->usec_timeout)
 548                 r = -ETIMEDOUT;
 549
 550         return r;
 551 }
 552
 553 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 554                                    struct amdgpu_ib *ib_msg,
 555                                    struct dma_fence **fence)
 556 {
 557         u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 558         struct amdgpu_device *adev = ring->adev;
 559         struct dma_fence *f = NULL;
 560         struct amdgpu_job *job;
 561         struct amdgpu_ib *ib;
 562         int i, r;
 563
 564         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 565                                      64, AMDGPU_IB_POOL_DIRECT,
 566                                      &job);
 567         if (r)
 568                 goto err;
 569
 570         ib = &job->ibs[0];
 571         ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
 572         ib->ptr[1] = addr;
 573         ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
 574         ib->ptr[3] = addr >> 32;
 575         ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
 576         ib->ptr[5] = 0;
 577         for (i = 6; i < 16; i += 2) {
 578                 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
 579                 ib->ptr[i+1] = 0;
 580         }
 581         ib->length_dw = 16;
 582
 583         r = amdgpu_job_submit_direct(job, ring, &f);
 584         if (r)
 585                 goto err_free;
 586
 587         amdgpu_ib_free(adev, ib_msg, f);
 588
 589         if (fence)
 590                 *fence = dma_fence_get(f);
 591         dma_fence_put(f);
 592
 593         return 0;
 594
 595 err_free:
 596         amdgpu_job_free(job);
 597 err:
 598         amdgpu_ib_free(adev, ib_msg, f);
 599         return r;
 600 }
 601
 602 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 603                 struct amdgpu_ib *ib)
 604 {
 605         struct amdgpu_device *adev = ring->adev;
 606         uint32_t *msg;
 607         int r, i;
 608
 609         memset(ib, 0, sizeof(*ib));
 610         r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
 611                         AMDGPU_IB_POOL_DIRECT,
 612                         ib);
 613         if (r)
 614                 return r;
 615
 616         msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
 617         msg[0] = cpu_to_le32(0x00000028);
 618         msg[1] = cpu_to_le32(0x00000038);
 619         msg[2] = cpu_to_le32(0x00000001);
 620         msg[3] = cpu_to_le32(0x00000000);
 621         msg[4] = cpu_to_le32(handle);
 622         msg[5] = cpu_to_le32(0x00000000);
 623         msg[6] = cpu_to_le32(0x00000001);
 624         msg[7] = cpu_to_le32(0x00000028);
 625         msg[8] = cpu_to_le32(0x00000010);
 626         msg[9] = cpu_to_le32(0x00000000);
 627         msg[10] = cpu_to_le32(0x00000007);
 628         msg[11] = cpu_to_le32(0x00000000);
 629         msg[12] = cpu_to_le32(0x00000780);
 630         msg[13] = cpu_to_le32(0x00000440);
 631         for (i = 14; i < 1024; ++i)
 632                 msg[i] = cpu_to_le32(0x0);
 633
 634         return 0;
 635 }
 636
 637 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 638                                           struct amdgpu_ib *ib)
 639 {
 640         struct amdgpu_device *adev = ring->adev;
 641         uint32_t *msg;
 642         int r, i;
 643
 644         memset(ib, 0, sizeof(*ib));
 645         r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
 646                         AMDGPU_IB_POOL_DIRECT,
 647                         ib);
 648         if (r)
 649                 return r;
 650
 651         msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
 652         msg[0] = cpu_to_le32(0x00000028);
 653         msg[1] = cpu_to_le32(0x00000018);
 654         msg[2] = cpu_to_le32(0x00000000);
 655         msg[3] = cpu_to_le32(0x00000002);
 656         msg[4] = cpu_to_le32(handle);
 657         msg[5] = cpu_to_le32(0x00000000);
 658         for (i = 6; i < 1024; ++i)
 659                 msg[i] = cpu_to_le32(0x0);
 660
 661         return 0;
 662 }
 663
 664 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 665 {
 666         struct dma_fence *fence = NULL;
 667         struct amdgpu_ib ib;
 668         long r;
 669
 670         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
 671         if (r)
 672                 goto error;
 673
 674         r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
 675         if (r)
 676                 goto error;
 677         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
 678         if (r)
 679                 goto error;
 680
 681         r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
 682         if (r)
 683                 goto error;
 684
 685         r = dma_fence_wait_timeout(fence, false, timeout);
 686         if (r == 0)
 687                 r = -ETIMEDOUT;
 688         else if (r > 0)
 689                 r = 0;
 690
 691         dma_fence_put(fence);
 692 error:
 693         return r;
 694 }
 695
 696 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
 697                                                 uint32_t ib_pack_in_dw, bool enc)
 698 {
 699         uint32_t *ib_checksum;
 700
 701         ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
 702         ib->ptr[ib->length_dw++] = 0x30000002;
 703         ib_checksum = &ib->ptr[ib->length_dw++];
 704         ib->ptr[ib->length_dw++] = ib_pack_in_dw;
 705
 706         ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
 707         ib->ptr[ib->length_dw++] = 0x30000001;
 708         ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
 709         ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
 710
 711         return ib_checksum;
 712 }
 713
 714 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
 715                                                 uint32_t ib_pack_in_dw)
 716 {
 717         uint32_t i;
 718         uint32_t checksum = 0;
 719
 720         for (i = 0; i < ib_pack_in_dw; i++)
 721                 checksum += *(*ib_checksum + 2 + i);
 722
 723         **ib_checksum = checksum;
 724 }
 725
 726 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 727                                       struct amdgpu_ib *ib_msg,
 728                                       struct dma_fence **fence)
 729 {
 730         struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
 731         unsigned int ib_size_dw = 64;
 732         struct amdgpu_device *adev = ring->adev;
 733         struct dma_fence *f = NULL;
 734         struct amdgpu_job *job;
 735         struct amdgpu_ib *ib;
 736         uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 737         uint32_t *ib_checksum;
 738         uint32_t ib_pack_in_dw;
 739         int i, r;
 740
 741         if (adev->vcn.using_unified_queue)
 742                 ib_size_dw += 8;
 743
 744         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 745                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 746                                      &job);
 747         if (r)
 748                 goto err;
 749
 750         ib = &job->ibs[0];
 751         ib->length_dw = 0;
 752
 753         /* single queue headers */
 754         if (adev->vcn.using_unified_queue) {
 755                 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
 756                                                 + 4 + 2; /* engine info + decoding ib in dw */
 757                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
 758         }
 759
 760         ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
 761         ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
 762         decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
 763         ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
 764         memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
 765
 766         decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
 767         decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
 768         decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
 769
 770         for (i = ib->length_dw; i < ib_size_dw; ++i)
 771                 ib->ptr[i] = 0x0;
 772
 773         if (adev->vcn.using_unified_queue)
 774                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
 775
 776         r = amdgpu_job_submit_direct(job, ring, &f);
 777         if (r)
 778                 goto err_free;
 779
 780         amdgpu_ib_free(adev, ib_msg, f);
 781
 782         if (fence)
 783                 *fence = dma_fence_get(f);
 784         dma_fence_put(f);
 785
 786         return 0;
 787
 788 err_free:
 789         amdgpu_job_free(job);
 790 err:
 791         amdgpu_ib_free(adev, ib_msg, f);
 792         return r;
 793 }
 794
 795 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 796 {
 797         struct dma_fence *fence = NULL;
 798         struct amdgpu_ib ib;
 799         long r;
 800
 801         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
 802         if (r)
 803                 goto error;
 804
 805         r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
 806         if (r)
 807                 goto error;
 808         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
 809         if (r)
 810                 goto error;
 811
 812         r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
 813         if (r)
 814                 goto error;
 815
 816         r = dma_fence_wait_timeout(fence, false, timeout);
 817         if (r == 0)
 818                 r = -ETIMEDOUT;
 819         else if (r > 0)
 820                 r = 0;
 821
 822         dma_fence_put(fence);
 823 error:
 824         return r;
 825 }
 826
 827 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 828 {
 829         struct amdgpu_device *adev = ring->adev;
 830         uint32_t rptr;
 831         unsigned int i;
 832         int r;
 833
 834         if (amdgpu_sriov_vf(adev))
 835                 return 0;
 836
 837         r = amdgpu_ring_alloc(ring, 16);
 838         if (r)
 839                 return r;
 840
 841         rptr = amdgpu_ring_get_rptr(ring);
 842
 843         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 844         amdgpu_ring_commit(ring);
 845
 846         for (i = 0; i < adev->usec_timeout; i++) {
 847                 if (amdgpu_ring_get_rptr(ring) != rptr)
 848                         break;
 849                 udelay(1);
 850         }
 851
 852         if (i >= adev->usec_timeout)
 853                 r = -ETIMEDOUT;
 854
 855         return r;
 856 }
 857
 858 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 859                                          struct amdgpu_ib *ib_msg,
 860                                          struct dma_fence **fence)
 861 {
 862         unsigned int ib_size_dw = 16;
 863         struct amdgpu_device *adev = ring->adev;
 864         struct amdgpu_job *job;
 865         struct amdgpu_ib *ib;
 866         struct dma_fence *f = NULL;
 867         uint32_t *ib_checksum = NULL;
 868         uint64_t addr;
 869         int i, r;
 870
 871         if (adev->vcn.using_unified_queue)
 872                 ib_size_dw += 8;
 873
 874         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 875                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 876                                      &job);
 877         if (r)
 878                 return r;
 879
 880         ib = &job->ibs[0];
 881         addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 882
 883         ib->length_dw = 0;
 884
 885         if (adev->vcn.using_unified_queue)
 886                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
 887
 888         ib->ptr[ib->length_dw++] = 0x00000018;
 889         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 890         ib->ptr[ib->length_dw++] = handle;
 891         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 892         ib->ptr[ib->length_dw++] = addr;
 893         ib->ptr[ib->length_dw++] = 0x00000000;
 894
 895         ib->ptr[ib->length_dw++] = 0x00000014;
 896         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 897         ib->ptr[ib->length_dw++] = 0x0000001c;
 898         ib->ptr[ib->length_dw++] = 0x00000000;
 899         ib->ptr[ib->length_dw++] = 0x00000000;
 900
 901         ib->ptr[ib->length_dw++] = 0x00000008;
 902         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 903
 904         for (i = ib->length_dw; i < ib_size_dw; ++i)
 905                 ib->ptr[i] = 0x0;
 906
 907         if (adev->vcn.using_unified_queue)
 908                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
 909
 910         r = amdgpu_job_submit_direct(job, ring, &f);
 911         if (r)
 912                 goto err;
 913
 914         if (fence)
 915                 *fence = dma_fence_get(f);
 916         dma_fence_put(f);
 917
 918         return 0;
 919
 920 err:
 921         amdgpu_job_free(job);
 922         return r;
 923 }
 924
 925 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 926                                           struct amdgpu_ib *ib_msg,
 927                                           struct dma_fence **fence)
 928 {
 929         unsigned int ib_size_dw = 16;
 930         struct amdgpu_device *adev = ring->adev;
 931         struct amdgpu_job *job;
 932         struct amdgpu_ib *ib;
 933         struct dma_fence *f = NULL;
 934         uint32_t *ib_checksum = NULL;
 935         uint64_t addr;
 936         int i, r;
 937
 938         if (adev->vcn.using_unified_queue)
 939                 ib_size_dw += 8;
 940
 941         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 942                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 943                                      &job);
 944         if (r)
 945                 return r;
 946
 947         ib = &job->ibs[0];
 948         addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 949
 950         ib->length_dw = 0;
 951
 952         if (adev->vcn.using_unified_queue)
 953                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
 954
 955         ib->ptr[ib->length_dw++] = 0x00000018;
 956         ib->ptr[ib->length_dw++] = 0x00000001;
 957         ib->ptr[ib->length_dw++] = handle;
 958         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 959         ib->ptr[ib->length_dw++] = addr;
 960         ib->ptr[ib->length_dw++] = 0x00000000;
 961
 962         ib->ptr[ib->length_dw++] = 0x00000014;
 963         ib->ptr[ib->length_dw++] = 0x00000002;
 964         ib->ptr[ib->length_dw++] = 0x0000001c;
 965         ib->ptr[ib->length_dw++] = 0x00000000;
 966         ib->ptr[ib->length_dw++] = 0x00000000;
 967
 968         ib->ptr[ib->length_dw++] = 0x00000008;
 969         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 970
 971         for (i = ib->length_dw; i < ib_size_dw; ++i)
 972                 ib->ptr[i] = 0x0;
 973
 974         if (adev->vcn.using_unified_queue)
 975                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
 976
 977         r = amdgpu_job_submit_direct(job, ring, &f);
 978         if (r)
 979                 goto err;
 980
 981         if (fence)
 982                 *fence = dma_fence_get(f);
 983         dma_fence_put(f);
 984
 985         return 0;
 986
 987 err:
 988         amdgpu_job_free(job);
 989         return r;
 990 }
 991
 992 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 993 {
 994         struct amdgpu_device *adev = ring->adev;
 995         struct dma_fence *fence = NULL;
 996         struct amdgpu_ib ib;
 997         long r;
 998
 999         memset(&ib, 0, sizeof(ib));
1000         r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
1001                         AMDGPU_IB_POOL_DIRECT,
1002                         &ib);
1003         if (r)
1004                 return r;
1005
1006         r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
1007         if (r)
1008                 goto error;
1009
1010         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
1011         if (r)
1012                 goto error;
1013
1014         r = dma_fence_wait_timeout(fence, false, timeout);
1015         if (r == 0)
1016                 r = -ETIMEDOUT;
1017         else if (r > 0)
1018                 r = 0;
1019
1020 error:
1021         amdgpu_ib_free(adev, &ib, fence);
1022         dma_fence_put(fence);
1023
1024         return r;
1025 }
1026
1027 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1028 {
1029         struct amdgpu_device *adev = ring->adev;
1030         long r;
1031
1032         if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) {
1033                 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
1034                 if (r)
1035                         goto error;
1036         }
1037
1038         r =  amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
1039
1040 error:
1041         return r;
1042 }
1043
1044 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
1045 {
1046         switch (ring) {
1047         case 0:
1048                 return AMDGPU_RING_PRIO_0;
1049         case 1:
1050                 return AMDGPU_RING_PRIO_1;
1051         case 2:
1052                 return AMDGPU_RING_PRIO_2;
1053         default:
1054                 return AMDGPU_RING_PRIO_0;
1055         }
1056 }
1057
1058 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1059 {
1060         int i;
1061         unsigned int idx;
1062
1063         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1064                 const struct common_firmware_header *hdr;
1065
1066                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1067                         if (adev->vcn.harvest_config & (1 << i))
1068                                 continue;
1069
1070                         hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
1071                         /* currently only support 2 FW instances */
1072                         if (i >= 2) {
1073                                 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1074                                 break;
1075                         }
1076                         idx = AMDGPU_UCODE_ID_VCN + i;
1077                         adev->firmware.ucode[idx].ucode_id = idx;
1078                         adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;
1079                         adev->firmware.fw_size +=
1080                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1081
1082                         if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
1083                             IP_VERSION(4, 0, 3))
1084                                 break;
1085                 }
1086         }
1087 }
1088
1089 /*
1090  * debugfs for mapping vcn firmware log buffer.
1091  */
1092 #if defined(CONFIG_DEBUG_FS)
1093 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1094                                              size_t size, loff_t *pos)
1095 {
1096         struct amdgpu_vcn_inst *vcn;
1097         void *log_buf;
1098         volatile struct amdgpu_vcn_fwlog *plog;
1099         unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1100         unsigned int read_num[2] = {0};
1101
1102         vcn = file_inode(f)->i_private;
1103         if (!vcn)
1104                 return -ENODEV;
1105
1106         if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1107                 return -EFAULT;
1108
1109         log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1110
1111         plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1112         read_pos = plog->rptr;
1113         write_pos = plog->wptr;
1114
1115         if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1116                 return -EFAULT;
1117
1118         if (!size || (read_pos == write_pos))
1119                 return 0;
1120
1121         if (write_pos > read_pos) {
1122                 available = write_pos - read_pos;
1123                 read_num[0] = min_t(size_t, size, available);
1124         } else {
1125                 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1126                 available = read_num[0] + write_pos - plog->header_size;
1127                 if (size > available)
1128                         read_num[1] = write_pos - plog->header_size;
1129                 else if (size > read_num[0])
1130                         read_num[1] = size - read_num[0];
1131                 else
1132                         read_num[0] = size;
1133         }
1134
1135         for (i = 0; i < 2; i++) {
1136                 if (read_num[i]) {
1137                         if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1138                                 read_pos = plog->header_size;
1139                         if (read_num[i] == copy_to_user((buf + read_bytes),
1140                                                         (log_buf + read_pos), read_num[i]))
1141                                 return -EFAULT;
1142
1143                         read_bytes += read_num[i];
1144                         read_pos += read_num[i];
1145                 }
1146         }
1147
1148         plog->rptr = read_pos;
1149         *pos += read_bytes;
1150         return read_bytes;
1151 }
1152
1153 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1154         .owner = THIS_MODULE,
1155         .read = amdgpu_debugfs_vcn_fwlog_read,
1156         .llseek = default_llseek
1157 };
1158 #endif
1159
1160 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1161                                    struct amdgpu_vcn_inst *vcn)
1162 {
1163 #if defined(CONFIG_DEBUG_FS)
1164         struct drm_minor *minor = adev_to_drm(adev)->primary;
1165         struct dentry *root = minor->debugfs_root;
1166         char name[32];
1167
1168         sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1169         debugfs_create_file_size(name, S_IFREG | 0444, root, vcn,
1170                                  &amdgpu_debugfs_vcnfwlog_fops,
1171                                  AMDGPU_VCNFW_LOG_SIZE);
1172 #endif
1173 }
1174
1175 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1176 {
1177 #if defined(CONFIG_DEBUG_FS)
1178         volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1179         void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1180         uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1181         volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1182         volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1183                                                          + vcn->fw_shared.log_offset;
1184         *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1185         fw_log->is_enabled = 1;
1186         fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1187         fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1188         fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1189
1190         log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1191         log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1192         log_buf->rptr = log_buf->header_size;
1193         log_buf->wptr = log_buf->header_size;
1194         log_buf->wrapped = 0;
1195 #endif
1196 }
1197
1198 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1199                                 struct amdgpu_irq_src *source,
1200                                 struct amdgpu_iv_entry *entry)
1201 {
1202         struct ras_common_if *ras_if = adev->vcn.ras_if;
1203         struct ras_dispatch_if ih_data = {
1204                 .entry = entry,
1205         };
1206
1207         if (!ras_if)
1208                 return 0;
1209
1210         if (!amdgpu_sriov_vf(adev)) {
1211                 ih_data.head = *ras_if;
1212                 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1213         } else {
1214                 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
1215                         adev->virt.ops->ras_poison_handler(adev, ras_if->block);
1216                 else
1217                         dev_warn(adev->dev,
1218                                 "No ras_poison_handler interface in SRIOV for VCN!\n");
1219         }
1220
1221         return 0;
1222 }
1223
1224 int amdgpu_vcn_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
1225 {
1226         int r, i;
1227
1228         r = amdgpu_ras_block_late_init(adev, ras_block);
1229         if (r)
1230                 return r;
1231
1232         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
1233                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1234                         if (adev->vcn.harvest_config & (1 << i) ||
1235                             !adev->vcn.inst[i].ras_poison_irq.funcs)
1236                                 continue;
1237
1238                         r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
1239                         if (r)
1240                                 goto late_fini;
1241                 }
1242         }
1243         return 0;
1244
1245 late_fini:
1246         amdgpu_ras_block_late_fini(adev, ras_block);
1247         return r;
1248 }
1249
1250 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
1251 {
1252         int err;
1253         struct amdgpu_vcn_ras *ras;
1254
1255         if (!adev->vcn.ras)
1256                 return 0;
1257
1258         ras = adev->vcn.ras;
1259         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
1260         if (err) {
1261                 dev_err(adev->dev, "Failed to register vcn ras block!\n");
1262                 return err;
1263         }
1264
1265         strcpy(ras->ras_block.ras_comm.name, "vcn");
1266         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
1267         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
1268         adev->vcn.ras_if = &ras->ras_block.ras_comm;
1269
1270         if (!ras->ras_block.ras_late_init)
1271                 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init;
1272
1273         return 0;
1274 }
1275
1276 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
1277                                enum AMDGPU_UCODE_ID ucode_id)
1278 {
1279         struct amdgpu_firmware_info ucode = {
1280                 .ucode_id = (ucode_id ? ucode_id :
1281                             (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1282                                         AMDGPU_UCODE_ID_VCN0_RAM)),
1283                 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1284                 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1285                               (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
1286         };
1287
1288         return psp_execute_ip_fw_load(&adev->psp, &ucode);
1289 }
1290
1291 static ssize_t amdgpu_get_vcn_reset_mask(struct device *dev,
1292                                                 struct device_attribute *attr,
1293                                                 char *buf)
1294 {
1295         struct drm_device *ddev = dev_get_drvdata(dev);
1296         struct amdgpu_device *adev = drm_to_adev(ddev);
1297
1298         if (!adev)
1299                 return -ENODEV;
1300
1301         return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset);
1302 }
1303
1304 static DEVICE_ATTR(vcn_reset_mask, 0444,
1305                    amdgpu_get_vcn_reset_mask, NULL);
1306
1307 int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev)
1308 {
1309         int r = 0;
1310
1311         if (adev->vcn.num_vcn_inst) {
1312                 r = device_create_file(adev->dev, &dev_attr_vcn_reset_mask);
1313                 if (r)
1314                         return r;
1315         }
1316
1317         return r;
1318 }
1319
1320 void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev)
1321 {
1322         if (adev->dev->kobj.sd) {
1323                 if (adev->vcn.num_vcn_inst)
1324                         device_remove_file(adev->dev, &dev_attr_vcn_reset_mask);
1325         }
1326 }
1327
1328 /*
1329  * debugfs to enable/disable vcn job submission to specific core or
1330  * instance. It is created only if the queue type is unified.
1331  */
1332 #if defined(CONFIG_DEBUG_FS)
1333 static int amdgpu_debugfs_vcn_sched_mask_set(void *data, u64 val)
1334 {
1335         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1336         u32 i;
1337         u64 mask;
1338         struct amdgpu_ring *ring;
1339
1340         if (!adev)
1341                 return -ENODEV;
1342
1343         mask = (1ULL << adev->vcn.num_vcn_inst) - 1;
1344         if ((val & mask) == 0)
1345                 return -EINVAL;
1346         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1347                 ring = &adev->vcn.inst[i].ring_enc[0];
1348                 if (val & (1ULL << i))
1349                         ring->sched.ready = true;
1350                 else
1351                         ring->sched.ready = false;
1352         }
1353         /* publish sched.ready flag update effective immediately across smp */
1354         smp_rmb();
1355         return 0;
1356 }
1357
1358 static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val)
1359 {
1360         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1361         u32 i;
1362         u64 mask = 0;
1363         struct amdgpu_ring *ring;
1364
1365         if (!adev)
1366                 return -ENODEV;
1367         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1368                 ring = &adev->vcn.inst[i].ring_enc[0];
1369                 if (ring->sched.ready)
1370                         mask |= 1ULL << i;
1371                 }
1372         *val = mask;
1373         return 0;
1374 }
1375
1376 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops,
1377                          amdgpu_debugfs_vcn_sched_mask_get,
1378                          amdgpu_debugfs_vcn_sched_mask_set, "%llx\n");
1379 #endif
1380
1381 void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev)
1382 {
1383 #if defined(CONFIG_DEBUG_FS)
1384         struct drm_minor *minor = adev_to_drm(adev)->primary;
1385         struct dentry *root = minor->debugfs_root;
1386         char name[32];
1387
1388         if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.using_unified_queue)
1389                 return;
1390         sprintf(name, "amdgpu_vcn_sched_mask");
1391         debugfs_create_file(name, 0600, root, adev,
1392                             &amdgpu_debugfs_vcn_sched_mask_fops);
1393 #endif
1394 }