drm/amd/amdgpu: Map ISP interrupts as generic IRQs

Map ISP IH interrupts to Linux generic IRQ for ISP driver to
handle the interrupts using MFD IORESOURCE_IRQ resource.

Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Mario Limonciello <[email protected]>
Signed-off-by: Pratap Nirujogi <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 013ff373e06721a25662b25ddafaff1c1517587c..19ce4da285e8d9502c7c880297a0f6bade3d9884 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -466,7 +466,8 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
        } else  if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
                DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
 
-       } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
+       } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) ||
+                   (client_id == SOC15_IH_CLIENTID_ISP)) &&
                   adev->irq.virq[src_id]) {
                generic_handle_domain_irq(adev->irq.domain, src_id);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
index 25e88661ac602dbf07e1055ba6865b66b2a50e53..52e53d2b87482baa048610c625c470ec177b87a1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
@@ -31,6 +31,8 @@
 #include "amdgpu.h"
 #include "amdgpu_isp.h"
 
+#include "ivsrcid/isp/irqsrcs_isp_4_1.h"
+
 #define mmDAGB0_WRCLI5_V4_1    0x6811C
 #define mmDAGB0_WRCLI9_V4_1    0x6812C
 #define mmDAGB0_WRCLI10_V4_1   0x68130
@@ -38,6 +40,17 @@
 #define mmDAGB0_WRCLI19_V4_1   0x68154
 #define mmDAGB0_WRCLI20_V4_1   0x68158
 
+static const unsigned int isp_int_srcid[MAX_ISP_INT_SRC] = {
+       ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9,
+       ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10,
+       ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11,
+       ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12,
+       ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13,
+       ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14,
+       ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15,
+       ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16
+};
+
 static int isp_sw_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -69,11 +82,12 @@ static int isp_sw_fini(void *handle)
  */
 static int isp_hw_init(void *handle)
 {
-       int r;
-       u64 isp_base;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        const struct amdgpu_ip_block *ip_block =
                amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ISP);
+       u64 isp_base;
+       int int_idx;
+       int r;
 
        if (!ip_block)
                return -EINVAL;
@@ -90,7 +104,7 @@ static int isp_hw_init(void *handle)
                goto failure;
        }
 
-       adev->isp.isp_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL);
+       adev->isp.isp_res = kcalloc(9, sizeof(struct resource), GFP_KERNEL);
        if (!adev->isp.isp_res) {
                r = -ENOMEM;
                DRM_ERROR("%s: isp mfd res alloc failed\n", __func__);
@@ -114,8 +128,17 @@ static int isp_hw_init(void *handle)
        adev->isp.isp_res[0].start = isp_base;
        adev->isp.isp_res[0].end = isp_base + ISP_REGS_OFFSET_END;
 
+       for (int_idx = 0; int_idx < MAX_ISP_INT_SRC; int_idx++) {
+               adev->isp.isp_res[int_idx + 1].name = "isp_irq";
+               adev->isp.isp_res[int_idx + 1].flags = IORESOURCE_IRQ;
+               adev->isp.isp_res[int_idx + 1].start =
+                       amdgpu_irq_create_mapping(adev, isp_int_srcid[int_idx]);
+               adev->isp.isp_res[int_idx + 1].end =
+                       adev->isp.isp_res[int_idx + 1].start;
+       }
+
        adev->isp.isp_cell[0].name = "amd_isp_capture";
-       adev->isp.isp_cell[0].num_resources = 1;
+       adev->isp.isp_cell[0].num_resources = 9;
        adev->isp.isp_cell[0].resources = &adev->isp.isp_res[0];
        adev->isp.isp_cell[0].platform_data = adev->isp.isp_pdata;
        adev->isp.isp_cell[0].pdata_size = sizeof(struct isp_platform_data);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h
index a11ec0543b9320b83239dbf34b91d37015d8924a..764d70beb9e912a7c4c1205c3c7a7997445083ea 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h
@@ -30,6 +30,8 @@
 
 #define ISP_REGS_OFFSET_END 0x629A4
 
+#define MAX_ISP_INT_SRC 8
+
 struct isp_platform_data {
        void *adev;
        u32 asic_type;

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index 0fbf5fa7b0f87f6ffd73d9b0005e2930b75565e2..2e0469feca1e92b232fe64a028995cdd5c64f057 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -535,6 +535,12 @@ static void ih_v6_1_set_self_irq_funcs(struct amdgpu_device *adev)
 static int ih_v6_1_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       int ret;
+
+       ret = amdgpu_irq_add_domain(adev);
+       if (ret) {
+               return ret;
+       }
 
        ih_v6_1_set_interrupt_funcs(adev);
        ih_v6_1_set_self_irq_funcs(adev);

diff --git a/drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h b/drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h
new file mode 100644 (file)
index 0000000..2ecdfd4
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2024 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __IRQSRCS_ISP_4_1_H__
+#define __IRQSRCS_ISP_4_1_H__
+
+
+#define ISP_4_1__SRCID__ISP_SEMA_WAIT_FAIL_TIMEOUT                     0x12    // Semaphore wait fail timeout
+#define ISP_4_1__SRCID__ISP_SEMA_WAIT_INCOMPLETE_TIMEOUT               0x13    // Semaphore wait incomplete timeout
+#define ISP_4_1__SRCID__ISP_SEMA_SIGNAL_INCOMPLETE_TIMEOUT             0x14    // Semaphore signal incomplete timeout
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE5_CHANGED                   0x15    // Ringbuffer base5 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT5                            0x16    // Ringbuffer write point 5 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE6_CHANGED                   0x17    // Ringbuffer base6 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT6                            0x18    // Ringbuffer write point 6 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE7_CHANGED                   0x19    // Ringbuffer base7 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT7                            0x1A    // Ringbuffer write point 7 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE8_CHANGED                   0x1B    // Ringbuffer base8 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT8                            0x1C    // Ringbuffer write point 8 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE9_CHANGED                   0x00    // Ringbuffer base9 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9                            0x01    // Ringbuffer write point 9 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE10_CHANGED                  0x02    // Ringbuffer base10 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10                           0x03    // Ringbuffer write point 10 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE11_CHANGED                  0x04    // Ringbuffer base11 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11                           0x05    // Ringbuffer write point 11 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE12_CHANGED                  0x06    // Ringbuffer base12 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12                           0x07    // Ringbuffer write point 12 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE13_CHANGED                  0x08    // Ringbuffer base13 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13                           0x09    // Ringbuffer write point 13 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE14_CHANGED                  0x0A    // Ringbuffer base14 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14                           0x0B    // Ringbuffer write point 14 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE15_CHANGED                  0x0C    // Ringbuffer base15 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15                           0x0D    // Ringbuffer write point 15 changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE16_CHANGED                  0x0E    // Ringbuffer base16 address changed
+#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16                           0x0F    // Ringbuffer write point 16 changed
+#define ISP_4_1__SRCID__ISP_MIPI0                                      0x29    // MIPI0 interrupt
+#define ISP_4_1__SRCID__ISP_MIPI1                                      0x2A    // MIPI1 interrupt
+#define ISP_4_1__SRCID__ISP_I2C0                                       0x2B    // I2C0 PAD interrupt
+#define ISP_4_1__SRCID__ISP_I2C1                                       0x2C    // I2C1 PAD interrupt
+#define ISP_4_1__SRCID__ISP_FLASH0                                     0x2D    // Flash0 interrupt
+#define ISP_4_1__SRCID__ISP_FLASH1                                     0x2E    // Flash1 interrupt
+#define ISP_4_1__SRCID__ISP_DEBUG                                      0x2F    // Debug information
+
+#endif