drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h

   1 /*
   2  * Copyright 2024 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __IRQSRCS_ISP_4_1_H__
  24 #define __IRQSRCS_ISP_4_1_H__
  25
  26
  27 #define ISP_4_1__SRCID__ISP_SEMA_WAIT_FAIL_TIMEOUT                      0x12    // Semaphore wait fail timeout
  28 #define ISP_4_1__SRCID__ISP_SEMA_WAIT_INCOMPLETE_TIMEOUT                0x13    // Semaphore wait incomplete timeout
  29 #define ISP_4_1__SRCID__ISP_SEMA_SIGNAL_INCOMPLETE_TIMEOUT              0x14    // Semaphore signal incomplete timeout
  30 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE5_CHANGED                    0x15    // Ringbuffer base5 address changed
  31 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT5                             0x16    // Ringbuffer write point 5 changed
  32 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE6_CHANGED                    0x17    // Ringbuffer base6 address changed
  33 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT6                             0x18    // Ringbuffer write point 6 changed
  34 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE7_CHANGED                    0x19    // Ringbuffer base7 address changed
  35 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT7                             0x1A    // Ringbuffer write point 7 changed
  36 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE8_CHANGED                    0x1B    // Ringbuffer base8 address changed
  37 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT8                             0x1C    // Ringbuffer write point 8 changed
  38 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE9_CHANGED                    0x00    // Ringbuffer base9 address changed
  39 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9                             0x01    // Ringbuffer write point 9 changed
  40 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE10_CHANGED                   0x02    // Ringbuffer base10 address changed
  41 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10                            0x03    // Ringbuffer write point 10 changed
  42 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE11_CHANGED                   0x04    // Ringbuffer base11 address changed
  43 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11                            0x05    // Ringbuffer write point 11 changed
  44 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE12_CHANGED                   0x06    // Ringbuffer base12 address changed
  45 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12                            0x07    // Ringbuffer write point 12 changed
  46 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE13_CHANGED                   0x08    // Ringbuffer base13 address changed
  47 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13                            0x09    // Ringbuffer write point 13 changed
  48 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE14_CHANGED                   0x0A    // Ringbuffer base14 address changed
  49 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14                            0x0B    // Ringbuffer write point 14 changed
  50 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE15_CHANGED                   0x0C    // Ringbuffer base15 address changed
  51 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15                            0x0D    // Ringbuffer write point 15 changed
  52 #define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE16_CHANGED                   0x0E    // Ringbuffer base16 address changed
  53 #define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16                            0x0F    // Ringbuffer write point 16 changed
  54 #define ISP_4_1__SRCID__ISP_MIPI0                                       0x29    // MIPI0 interrupt
  55 #define ISP_4_1__SRCID__ISP_MIPI1                                       0x2A    // MIPI1 interrupt
  56 #define ISP_4_1__SRCID__ISP_I2C0                                        0x2B    // I2C0 PAD interrupt
  57 #define ISP_4_1__SRCID__ISP_I2C1                                        0x2C    // I2C1 PAD interrupt
  58 #define ISP_4_1__SRCID__ISP_FLASH0                                      0x2D    // Flash0 interrupt
  59 #define ISP_4_1__SRCID__ISP_FLASH1                                      0x2E    // Flash1 interrupt
  60 #define ISP_4_1__SRCID__ISP_DEBUG                                       0x2F    // Debug information
  61
  62 #endif