drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_gpu_instance *gpu_instance;
  49         int i;
  50
  51         mutex_lock(&mgpu_info.mutex);
  52
  53         for (i = 0; i < mgpu_info.num_gpu; i++) {
  54                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  55                 if (gpu_instance->adev == adev) {
  56                         mgpu_info.gpu_ins[i] =
  57                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  58                         mgpu_info.num_gpu--;
  59                         if (adev->flags & AMD_IS_APU)
  60                                 mgpu_info.num_apu--;
  61                         else
  62                                 mgpu_info.num_dgpu--;
  63                         break;
  64                 }
  65         }
  66
  67         mutex_unlock(&mgpu_info.mutex);
  68 }
  69
  70 /**
  71  * amdgpu_driver_unload_kms - Main unload function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  *
  75  * This is the main unload function for KMS (all asics).
  76  * Returns 0 on success.
  77  */
  78 void amdgpu_driver_unload_kms(struct drm_device *dev)
  79 {
  80         struct amdgpu_device *adev = drm_to_adev(dev);
  81
  82         if (adev == NULL)
  83                 return;
  84
  85         amdgpu_unregister_gpu_instance(adev);
  86
  87         if (adev->rmmio == NULL)
  88                 return;
  89
  90         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  91                 DRM_WARN("smart shift update failed\n");
  92
  93         amdgpu_acpi_fini(adev);
  94         amdgpu_device_fini_hw(adev);
  95 }
  96
  97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
  98 {
  99         struct amdgpu_gpu_instance *gpu_instance;
 100
 101         mutex_lock(&mgpu_info.mutex);
 102
 103         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 104                 DRM_ERROR("Cannot register more gpu instance\n");
 105                 mutex_unlock(&mgpu_info.mutex);
 106                 return;
 107         }
 108
 109         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 110         gpu_instance->adev = adev;
 111         gpu_instance->mgpu_fan_enabled = 0;
 112
 113         mgpu_info.num_gpu++;
 114         if (adev->flags & AMD_IS_APU)
 115                 mgpu_info.num_apu++;
 116         else
 117                 mgpu_info.num_dgpu++;
 118
 119         mutex_unlock(&mgpu_info.mutex);
 120 }
 121
 122 /**
 123  * amdgpu_driver_load_kms - Main load function for KMS.
 124  *
 125  * @adev: pointer to struct amdgpu_device
 126  * @flags: device flags
 127  *
 128  * This is the main load function for KMS (all asics).
 129  * Returns 0 on success, error on failure.
 130  */
 131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 132 {
 133         struct drm_device *dev;
 134         int r, acpi_status;
 135
 136         dev = adev_to_drm(adev);
 137
 138         /* amdgpu_device_init should report only fatal error
 139          * like memory allocation failure or iomapping failure,
 140          * or memory manager initialization failure, it must
 141          * properly initialize the GPU MC controller and permit
 142          * VRAM allocation
 143          */
 144         r = amdgpu_device_init(adev, flags);
 145         if (r) {
 146                 dev_err(dev->dev, "Fatal error during GPU init\n");
 147                 goto out;
 148         }
 149
 150         adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
 151         if (amdgpu_device_supports_px(dev) &&
 152             (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
 153                 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
 154                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 155         } else if (amdgpu_device_supports_boco(dev) &&
 156                    (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
 157                 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
 158                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 159         } else if (amdgpu_device_supports_baco(dev) &&
 160                    (amdgpu_runtime_pm != 0)) {
 161                 switch (adev->asic_type) {
 162                 case CHIP_VEGA20:
 163                 case CHIP_ARCTURUS:
 164                         /* enable BACO as runpm mode if runpm=1 */
 165                         if (amdgpu_runtime_pm > 0)
 166                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 167                         break;
 168                 case CHIP_VEGA10:
 169                         /* enable BACO as runpm mode if noretry=0 */
 170                         if (!adev->gmc.noretry)
 171                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 172                         break;
 173                 default:
 174                         /* enable BACO as runpm mode on CI+ */
 175                         adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 176                         break;
 177                 }
 178
 179                 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
 180                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 181         }
 182
 183         /* Call ACPI methods: require modeset init
 184          * but failure is not fatal
 185          */
 186
 187         acpi_status = amdgpu_acpi_init(adev);
 188         if (acpi_status)
 189                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 190
 191         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 192                 DRM_WARN("smart shift update failed\n");
 193
 194 out:
 195         if (r)
 196                 amdgpu_driver_unload_kms(dev);
 197
 198         return r;
 199 }
 200
 201 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 202                                 struct drm_amdgpu_query_fw *query_fw,
 203                                 struct amdgpu_device *adev)
 204 {
 205         switch (query_fw->fw_type) {
 206         case AMDGPU_INFO_FW_VCE:
 207                 fw_info->ver = adev->vce.fw_version;
 208                 fw_info->feature = adev->vce.fb_version;
 209                 break;
 210         case AMDGPU_INFO_FW_UVD:
 211                 fw_info->ver = adev->uvd.fw_version;
 212                 fw_info->feature = 0;
 213                 break;
 214         case AMDGPU_INFO_FW_VCN:
 215                 fw_info->ver = adev->vcn.fw_version;
 216                 fw_info->feature = 0;
 217                 break;
 218         case AMDGPU_INFO_FW_GMC:
 219                 fw_info->ver = adev->gmc.fw_version;
 220                 fw_info->feature = 0;
 221                 break;
 222         case AMDGPU_INFO_FW_GFX_ME:
 223                 fw_info->ver = adev->gfx.me_fw_version;
 224                 fw_info->feature = adev->gfx.me_feature_version;
 225                 break;
 226         case AMDGPU_INFO_FW_GFX_PFP:
 227                 fw_info->ver = adev->gfx.pfp_fw_version;
 228                 fw_info->feature = adev->gfx.pfp_feature_version;
 229                 break;
 230         case AMDGPU_INFO_FW_GFX_CE:
 231                 fw_info->ver = adev->gfx.ce_fw_version;
 232                 fw_info->feature = adev->gfx.ce_feature_version;
 233                 break;
 234         case AMDGPU_INFO_FW_GFX_RLC:
 235                 fw_info->ver = adev->gfx.rlc_fw_version;
 236                 fw_info->feature = adev->gfx.rlc_feature_version;
 237                 break;
 238         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 239                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 240                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 241                 break;
 242         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 243                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 244                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 245                 break;
 246         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 247                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 248                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 249                 break;
 250         case AMDGPU_INFO_FW_GFX_MEC:
 251                 if (query_fw->index == 0) {
 252                         fw_info->ver = adev->gfx.mec_fw_version;
 253                         fw_info->feature = adev->gfx.mec_feature_version;
 254                 } else if (query_fw->index == 1) {
 255                         fw_info->ver = adev->gfx.mec2_fw_version;
 256                         fw_info->feature = adev->gfx.mec2_feature_version;
 257                 } else
 258                         return -EINVAL;
 259                 break;
 260         case AMDGPU_INFO_FW_SMC:
 261                 fw_info->ver = adev->pm.fw_version;
 262                 fw_info->feature = 0;
 263                 break;
 264         case AMDGPU_INFO_FW_TA:
 265                 switch (query_fw->index) {
 266                 case TA_FW_TYPE_PSP_XGMI:
 267                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 268                         fw_info->feature = adev->psp.xgmi_context.context
 269                                                    .bin_desc.feature_version;
 270                         break;
 271                 case TA_FW_TYPE_PSP_RAS:
 272                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 273                         fw_info->feature = adev->psp.ras_context.context
 274                                                    .bin_desc.feature_version;
 275                         break;
 276                 case TA_FW_TYPE_PSP_HDCP:
 277                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 278                         fw_info->feature = adev->psp.hdcp_context.context
 279                                                    .bin_desc.feature_version;
 280                         break;
 281                 case TA_FW_TYPE_PSP_DTM:
 282                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 283                         fw_info->feature = adev->psp.dtm_context.context
 284                                                    .bin_desc.feature_version;
 285                         break;
 286                 case TA_FW_TYPE_PSP_RAP:
 287                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 288                         fw_info->feature = adev->psp.rap_context.context
 289                                                    .bin_desc.feature_version;
 290                         break;
 291                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 292                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 293                         fw_info->feature =
 294                                 adev->psp.securedisplay_context.context.bin_desc
 295                                         .feature_version;
 296                         break;
 297                 default:
 298                         return -EINVAL;
 299                 }
 300                 break;
 301         case AMDGPU_INFO_FW_SDMA:
 302                 if (query_fw->index >= adev->sdma.num_instances)
 303                         return -EINVAL;
 304                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 305                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 306                 break;
 307         case AMDGPU_INFO_FW_SOS:
 308                 fw_info->ver = adev->psp.sos.fw_version;
 309                 fw_info->feature = adev->psp.sos.feature_version;
 310                 break;
 311         case AMDGPU_INFO_FW_ASD:
 312                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 313                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 314                 break;
 315         case AMDGPU_INFO_FW_DMCU:
 316                 fw_info->ver = adev->dm.dmcu_fw_version;
 317                 fw_info->feature = 0;
 318                 break;
 319         case AMDGPU_INFO_FW_DMCUB:
 320                 fw_info->ver = adev->dm.dmcub_fw_version;
 321                 fw_info->feature = 0;
 322                 break;
 323         case AMDGPU_INFO_FW_TOC:
 324                 fw_info->ver = adev->psp.toc.fw_version;
 325                 fw_info->feature = adev->psp.toc.feature_version;
 326                 break;
 327         case AMDGPU_INFO_FW_CAP:
 328                 fw_info->ver = adev->psp.cap_fw_version;
 329                 fw_info->feature = adev->psp.cap_feature_version;
 330                 break;
 331         default:
 332                 return -EINVAL;
 333         }
 334         return 0;
 335 }
 336
 337 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 338                              struct drm_amdgpu_info *info,
 339                              struct drm_amdgpu_info_hw_ip *result)
 340 {
 341         uint32_t ib_start_alignment = 0;
 342         uint32_t ib_size_alignment = 0;
 343         enum amd_ip_block_type type;
 344         unsigned int num_rings = 0;
 345         unsigned int i, j;
 346
 347         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 348                 return -EINVAL;
 349
 350         switch (info->query_hw_ip.type) {
 351         case AMDGPU_HW_IP_GFX:
 352                 type = AMD_IP_BLOCK_TYPE_GFX;
 353                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 354                         if (adev->gfx.gfx_ring[i].sched.ready)
 355                                 ++num_rings;
 356                 ib_start_alignment = 32;
 357                 ib_size_alignment = 32;
 358                 break;
 359         case AMDGPU_HW_IP_COMPUTE:
 360                 type = AMD_IP_BLOCK_TYPE_GFX;
 361                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 362                         if (adev->gfx.compute_ring[i].sched.ready)
 363                                 ++num_rings;
 364                 ib_start_alignment = 32;
 365                 ib_size_alignment = 32;
 366                 break;
 367         case AMDGPU_HW_IP_DMA:
 368                 type = AMD_IP_BLOCK_TYPE_SDMA;
 369                 for (i = 0; i < adev->sdma.num_instances; i++)
 370                         if (adev->sdma.instance[i].ring.sched.ready)
 371                                 ++num_rings;
 372                 ib_start_alignment = 256;
 373                 ib_size_alignment = 4;
 374                 break;
 375         case AMDGPU_HW_IP_UVD:
 376                 type = AMD_IP_BLOCK_TYPE_UVD;
 377                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 378                         if (adev->uvd.harvest_config & (1 << i))
 379                                 continue;
 380
 381                         if (adev->uvd.inst[i].ring.sched.ready)
 382                                 ++num_rings;
 383                 }
 384                 ib_start_alignment = 64;
 385                 ib_size_alignment = 64;
 386                 break;
 387         case AMDGPU_HW_IP_VCE:
 388                 type = AMD_IP_BLOCK_TYPE_VCE;
 389                 for (i = 0; i < adev->vce.num_rings; i++)
 390                         if (adev->vce.ring[i].sched.ready)
 391                                 ++num_rings;
 392                 ib_start_alignment = 4;
 393                 ib_size_alignment = 1;
 394                 break;
 395         case AMDGPU_HW_IP_UVD_ENC:
 396                 type = AMD_IP_BLOCK_TYPE_UVD;
 397                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 398                         if (adev->uvd.harvest_config & (1 << i))
 399                                 continue;
 400
 401                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 402                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 403                                         ++num_rings;
 404                 }
 405                 ib_start_alignment = 64;
 406                 ib_size_alignment = 64;
 407                 break;
 408         case AMDGPU_HW_IP_VCN_DEC:
 409                 type = AMD_IP_BLOCK_TYPE_VCN;
 410                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 411                         if (adev->uvd.harvest_config & (1 << i))
 412                                 continue;
 413
 414                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 415                                 ++num_rings;
 416                 }
 417                 ib_start_alignment = 16;
 418                 ib_size_alignment = 16;
 419                 break;
 420         case AMDGPU_HW_IP_VCN_ENC:
 421                 type = AMD_IP_BLOCK_TYPE_VCN;
 422                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 423                         if (adev->uvd.harvest_config & (1 << i))
 424                                 continue;
 425
 426                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 427                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 428                                         ++num_rings;
 429                 }
 430                 ib_start_alignment = 64;
 431                 ib_size_alignment = 1;
 432                 break;
 433         case AMDGPU_HW_IP_VCN_JPEG:
 434                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 435                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 436
 437                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 438                         if (adev->jpeg.harvest_config & (1 << i))
 439                                 continue;
 440
 441                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 442                                 ++num_rings;
 443                 }
 444                 ib_start_alignment = 16;
 445                 ib_size_alignment = 16;
 446                 break;
 447         default:
 448                 return -EINVAL;
 449         }
 450
 451         for (i = 0; i < adev->num_ip_blocks; i++)
 452                 if (adev->ip_blocks[i].version->type == type &&
 453                     adev->ip_blocks[i].status.valid)
 454                         break;
 455
 456         if (i == adev->num_ip_blocks)
 457                 return 0;
 458
 459         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 460                         num_rings);
 461
 462         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 463         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 464
 465         if (adev->asic_type >= CHIP_VEGA10) {
 466                 switch (type) {
 467                 case AMD_IP_BLOCK_TYPE_GFX:
 468                         result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
 469                         break;
 470                 case AMD_IP_BLOCK_TYPE_SDMA:
 471                         result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
 472                         break;
 473                 case AMD_IP_BLOCK_TYPE_UVD:
 474                 case AMD_IP_BLOCK_TYPE_VCN:
 475                 case AMD_IP_BLOCK_TYPE_JPEG:
 476                         result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
 477                         break;
 478                 case AMD_IP_BLOCK_TYPE_VCE:
 479                         result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
 480                         break;
 481                 default:
 482                         result->ip_discovery_version = 0;
 483                         break;
 484                 }
 485         } else {
 486                 result->ip_discovery_version = 0;
 487         }
 488         result->capabilities_flags = 0;
 489         result->available_rings = (1 << num_rings) - 1;
 490         result->ib_start_alignment = ib_start_alignment;
 491         result->ib_size_alignment = ib_size_alignment;
 492         return 0;
 493 }
 494
 495 /*
 496  * Userspace get information ioctl
 497  */
 498 /**
 499  * amdgpu_info_ioctl - answer a device specific request.
 500  *
 501  * @dev: drm device pointer
 502  * @data: request object
 503  * @filp: drm filp
 504  *
 505  * This function is used to pass device specific parameters to the userspace
 506  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 507  * etc. (all asics).
 508  * Returns 0 on success, -EINVAL on failure.
 509  */
 510 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 511 {
 512         struct amdgpu_device *adev = drm_to_adev(dev);
 513         struct drm_amdgpu_info *info = data;
 514         struct amdgpu_mode_info *minfo = &adev->mode_info;
 515         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 516         uint32_t size = info->return_size;
 517         struct drm_crtc *crtc;
 518         uint32_t ui32 = 0;
 519         uint64_t ui64 = 0;
 520         int i, found;
 521         int ui32_size = sizeof(ui32);
 522
 523         if (!info->return_size || !info->return_pointer)
 524                 return -EINVAL;
 525
 526         switch (info->query) {
 527         case AMDGPU_INFO_ACCEL_WORKING:
 528                 ui32 = adev->accel_working;
 529                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 530         case AMDGPU_INFO_CRTC_FROM_ID:
 531                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 532                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 533                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 534                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 535                                 ui32 = amdgpu_crtc->crtc_id;
 536                                 found = 1;
 537                                 break;
 538                         }
 539                 }
 540                 if (!found) {
 541                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 542                         return -EINVAL;
 543                 }
 544                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 545         case AMDGPU_INFO_HW_IP_INFO: {
 546                 struct drm_amdgpu_info_hw_ip ip = {};
 547                 int ret;
 548
 549                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 550                 if (ret)
 551                         return ret;
 552
 553                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 554                 return ret ? -EFAULT : 0;
 555         }
 556         case AMDGPU_INFO_HW_IP_COUNT: {
 557                 enum amd_ip_block_type type;
 558                 uint32_t count = 0;
 559
 560                 switch (info->query_hw_ip.type) {
 561                 case AMDGPU_HW_IP_GFX:
 562                         type = AMD_IP_BLOCK_TYPE_GFX;
 563                         break;
 564                 case AMDGPU_HW_IP_COMPUTE:
 565                         type = AMD_IP_BLOCK_TYPE_GFX;
 566                         break;
 567                 case AMDGPU_HW_IP_DMA:
 568                         type = AMD_IP_BLOCK_TYPE_SDMA;
 569                         break;
 570                 case AMDGPU_HW_IP_UVD:
 571                         type = AMD_IP_BLOCK_TYPE_UVD;
 572                         break;
 573                 case AMDGPU_HW_IP_VCE:
 574                         type = AMD_IP_BLOCK_TYPE_VCE;
 575                         break;
 576                 case AMDGPU_HW_IP_UVD_ENC:
 577                         type = AMD_IP_BLOCK_TYPE_UVD;
 578                         break;
 579                 case AMDGPU_HW_IP_VCN_DEC:
 580                 case AMDGPU_HW_IP_VCN_ENC:
 581                         type = AMD_IP_BLOCK_TYPE_VCN;
 582                         break;
 583                 case AMDGPU_HW_IP_VCN_JPEG:
 584                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 585                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 586                         break;
 587                 default:
 588                         return -EINVAL;
 589                 }
 590
 591                 for (i = 0; i < adev->num_ip_blocks; i++)
 592                         if (adev->ip_blocks[i].version->type == type &&
 593                             adev->ip_blocks[i].status.valid &&
 594                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 595                                 count++;
 596
 597                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 598         }
 599         case AMDGPU_INFO_TIMESTAMP:
 600                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 601                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 602         case AMDGPU_INFO_FW_VERSION: {
 603                 struct drm_amdgpu_info_firmware fw_info;
 604                 int ret;
 605
 606                 /* We only support one instance of each IP block right now. */
 607                 if (info->query_fw.ip_instance != 0)
 608                         return -EINVAL;
 609
 610                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 611                 if (ret)
 612                         return ret;
 613
 614                 return copy_to_user(out, &fw_info,
 615                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 616         }
 617         case AMDGPU_INFO_NUM_BYTES_MOVED:
 618                 ui64 = atomic64_read(&adev->num_bytes_moved);
 619                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 620         case AMDGPU_INFO_NUM_EVICTIONS:
 621                 ui64 = atomic64_read(&adev->num_evictions);
 622                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 623         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 624                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 625                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 626         case AMDGPU_INFO_VRAM_USAGE:
 627                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 628                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 629         case AMDGPU_INFO_VIS_VRAM_USAGE:
 630                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 631                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 632         case AMDGPU_INFO_GTT_USAGE:
 633                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 634                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 635         case AMDGPU_INFO_GDS_CONFIG: {
 636                 struct drm_amdgpu_info_gds gds_info;
 637
 638                 memset(&gds_info, 0, sizeof(gds_info));
 639                 gds_info.compute_partition_size = adev->gds.gds_size;
 640                 gds_info.gds_total_size = adev->gds.gds_size;
 641                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 642                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 643                 return copy_to_user(out, &gds_info,
 644                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 645         }
 646         case AMDGPU_INFO_VRAM_GTT: {
 647                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 648
 649                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 650                         atomic64_read(&adev->vram_pin_size) -
 651                         AMDGPU_VM_RESERVED_VRAM;
 652                 vram_gtt.vram_cpu_accessible_size =
 653                         min(adev->gmc.visible_vram_size -
 654                             atomic64_read(&adev->visible_pin_size),
 655                             vram_gtt.vram_size);
 656                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 657                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 658                 return copy_to_user(out, &vram_gtt,
 659                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 660         }
 661         case AMDGPU_INFO_MEMORY: {
 662                 struct drm_amdgpu_memory_info mem;
 663                 struct ttm_resource_manager *gtt_man =
 664                         &adev->mman.gtt_mgr.manager;
 665                 struct ttm_resource_manager *vram_man =
 666                         &adev->mman.vram_mgr.manager;
 667
 668                 memset(&mem, 0, sizeof(mem));
 669                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 670                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 671                         atomic64_read(&adev->vram_pin_size) -
 672                         AMDGPU_VM_RESERVED_VRAM;
 673                 mem.vram.heap_usage =
 674                         ttm_resource_manager_usage(vram_man);
 675                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 676
 677                 mem.cpu_accessible_vram.total_heap_size =
 678                         adev->gmc.visible_vram_size;
 679                 mem.cpu_accessible_vram.usable_heap_size =
 680                         min(adev->gmc.visible_vram_size -
 681                             atomic64_read(&adev->visible_pin_size),
 682                             mem.vram.usable_heap_size);
 683                 mem.cpu_accessible_vram.heap_usage =
 684                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 685                 mem.cpu_accessible_vram.max_allocation =
 686                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 687
 688                 mem.gtt.total_heap_size = gtt_man->size;
 689                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 690                         atomic64_read(&adev->gart_pin_size);
 691                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 692                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 693
 694                 return copy_to_user(out, &mem,
 695                                     min((size_t)size, sizeof(mem)))
 696                                     ? -EFAULT : 0;
 697         }
 698         case AMDGPU_INFO_READ_MMR_REG: {
 699                 unsigned n, alloc_size;
 700                 uint32_t *regs;
 701                 unsigned se_num = (info->read_mmr_reg.instance >>
 702                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 703                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 704                 unsigned sh_num = (info->read_mmr_reg.instance >>
 705                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 706                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 707
 708                 /* set full masks if the userspace set all bits
 709                  * in the bitfields */
 710                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 711                         se_num = 0xffffffff;
 712                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 713                         return -EINVAL;
 714                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 715                         sh_num = 0xffffffff;
 716                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 717                         return -EINVAL;
 718
 719                 if (info->read_mmr_reg.count > 128)
 720                         return -EINVAL;
 721
 722                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 723                 if (!regs)
 724                         return -ENOMEM;
 725                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 726
 727                 amdgpu_gfx_off_ctrl(adev, false);
 728                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 729                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 730                                                       info->read_mmr_reg.dword_offset + i,
 731                                                       &regs[i])) {
 732                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 733                                               info->read_mmr_reg.dword_offset + i);
 734                                 kfree(regs);
 735                                 amdgpu_gfx_off_ctrl(adev, true);
 736                                 return -EFAULT;
 737                         }
 738                 }
 739                 amdgpu_gfx_off_ctrl(adev, true);
 740                 n = copy_to_user(out, regs, min(size, alloc_size));
 741                 kfree(regs);
 742                 return n ? -EFAULT : 0;
 743         }
 744         case AMDGPU_INFO_DEV_INFO: {
 745                 struct drm_amdgpu_info_device *dev_info;
 746                 uint64_t vm_size;
 747                 int ret;
 748
 749                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 750                 if (!dev_info)
 751                         return -ENOMEM;
 752
 753                 dev_info->device_id = adev->pdev->device;
 754                 dev_info->chip_rev = adev->rev_id;
 755                 dev_info->external_rev = adev->external_rev_id;
 756                 dev_info->pci_rev = adev->pdev->revision;
 757                 dev_info->family = adev->family;
 758                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 759                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 760                 /* return all clocks in KHz */
 761                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 762                 if (adev->pm.dpm_enabled) {
 763                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 764                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 765                 } else {
 766                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 767                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 768                 }
 769                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 770                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 771                         adev->gfx.config.max_shader_engines;
 772                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 773                 dev_info->_pad = 0;
 774                 dev_info->ids_flags = 0;
 775                 if (adev->flags & AMD_IS_APU)
 776                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 777                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 778                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 779                 if (amdgpu_is_tmz(adev))
 780                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 781
 782                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 783                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 784
 785                 /* Older VCE FW versions are buggy and can handle only 40bits */
 786                 if (adev->vce.fw_version &&
 787                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 788                         vm_size = min(vm_size, 1ULL << 40);
 789
 790                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 791                 dev_info->virtual_address_max =
 792                         min(vm_size, AMDGPU_GMC_HOLE_START);
 793
 794                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 795                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 796                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 797                 }
 798                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 799                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 800                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 801                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 802                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 803                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 804                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 805                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 806                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 807                        sizeof(adev->gfx.cu_info.bitmap));
 808                 dev_info->vram_type = adev->gmc.vram_type;
 809                 dev_info->vram_bit_width = adev->gmc.vram_width;
 810                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 811                 dev_info->gc_double_offchip_lds_buf =
 812                         adev->gfx.config.double_offchip_lds_buf;
 813                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 814                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 815                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 816                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 817                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 818                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 819                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 820
 821                 if (adev->family >= AMDGPU_FAMILY_NV)
 822                         dev_info->pa_sc_tile_steering_override =
 823                                 adev->gfx.config.pa_sc_tile_steering_override;
 824
 825                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 826
 827                 ret = copy_to_user(out, dev_info,
 828                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 829                 kfree(dev_info);
 830                 return ret;
 831         }
 832         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 833                 unsigned i;
 834                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 835                 struct amd_vce_state *vce_state;
 836
 837                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 838                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 839                         if (vce_state) {
 840                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 841                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 842                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 843                                 vce_clk_table.num_valid_entries++;
 844                         }
 845                 }
 846
 847                 return copy_to_user(out, &vce_clk_table,
 848                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 849         }
 850         case AMDGPU_INFO_VBIOS: {
 851                 uint32_t bios_size = adev->bios_size;
 852
 853                 switch (info->vbios_info.type) {
 854                 case AMDGPU_INFO_VBIOS_SIZE:
 855                         return copy_to_user(out, &bios_size,
 856                                         min((size_t)size, sizeof(bios_size)))
 857                                         ? -EFAULT : 0;
 858                 case AMDGPU_INFO_VBIOS_IMAGE: {
 859                         uint8_t *bios;
 860                         uint32_t bios_offset = info->vbios_info.offset;
 861
 862                         if (bios_offset >= bios_size)
 863                                 return -EINVAL;
 864
 865                         bios = adev->bios + bios_offset;
 866                         return copy_to_user(out, bios,
 867                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 868                                         ? -EFAULT : 0;
 869                 }
 870                 case AMDGPU_INFO_VBIOS_INFO: {
 871                         struct drm_amdgpu_info_vbios vbios_info = {};
 872                         struct atom_context *atom_context;
 873
 874                         atom_context = adev->mode_info.atom_context;
 875                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 876                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 877                         vbios_info.version = atom_context->version;
 878                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 879                                                 sizeof(atom_context->vbios_ver_str));
 880                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 881
 882                         return copy_to_user(out, &vbios_info,
 883                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 884                 }
 885                 default:
 886                         DRM_DEBUG_KMS("Invalid request %d\n",
 887                                         info->vbios_info.type);
 888                         return -EINVAL;
 889                 }
 890         }
 891         case AMDGPU_INFO_NUM_HANDLES: {
 892                 struct drm_amdgpu_info_num_handles handle;
 893
 894                 switch (info->query_hw_ip.type) {
 895                 case AMDGPU_HW_IP_UVD:
 896                         /* Starting Polaris, we support unlimited UVD handles */
 897                         if (adev->asic_type < CHIP_POLARIS10) {
 898                                 handle.uvd_max_handles = adev->uvd.max_handles;
 899                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 900
 901                                 return copy_to_user(out, &handle,
 902                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 903                         } else {
 904                                 return -ENODATA;
 905                         }
 906
 907                         break;
 908                 default:
 909                         return -EINVAL;
 910                 }
 911         }
 912         case AMDGPU_INFO_SENSOR: {
 913                 if (!adev->pm.dpm_enabled)
 914                         return -ENOENT;
 915
 916                 switch (info->sensor_info.type) {
 917                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 918                         /* get sclk in Mhz */
 919                         if (amdgpu_dpm_read_sensor(adev,
 920                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 921                                                    (void *)&ui32, &ui32_size)) {
 922                                 return -EINVAL;
 923                         }
 924                         ui32 /= 100;
 925                         break;
 926                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 927                         /* get mclk in Mhz */
 928                         if (amdgpu_dpm_read_sensor(adev,
 929                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 930                                                    (void *)&ui32, &ui32_size)) {
 931                                 return -EINVAL;
 932                         }
 933                         ui32 /= 100;
 934                         break;
 935                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 936                         /* get temperature in millidegrees C */
 937                         if (amdgpu_dpm_read_sensor(adev,
 938                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 939                                                    (void *)&ui32, &ui32_size)) {
 940                                 return -EINVAL;
 941                         }
 942                         break;
 943                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 944                         /* get GPU load */
 945                         if (amdgpu_dpm_read_sensor(adev,
 946                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 947                                                    (void *)&ui32, &ui32_size)) {
 948                                 return -EINVAL;
 949                         }
 950                         break;
 951                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 952                         /* get average GPU power */
 953                         if (amdgpu_dpm_read_sensor(adev,
 954                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 955                                                    (void *)&ui32, &ui32_size)) {
 956                                 return -EINVAL;
 957                         }
 958                         ui32 >>= 8;
 959                         break;
 960                 case AMDGPU_INFO_SENSOR_VDDNB:
 961                         /* get VDDNB in millivolts */
 962                         if (amdgpu_dpm_read_sensor(adev,
 963                                                    AMDGPU_PP_SENSOR_VDDNB,
 964                                                    (void *)&ui32, &ui32_size)) {
 965                                 return -EINVAL;
 966                         }
 967                         break;
 968                 case AMDGPU_INFO_SENSOR_VDDGFX:
 969                         /* get VDDGFX in millivolts */
 970                         if (amdgpu_dpm_read_sensor(adev,
 971                                                    AMDGPU_PP_SENSOR_VDDGFX,
 972                                                    (void *)&ui32, &ui32_size)) {
 973                                 return -EINVAL;
 974                         }
 975                         break;
 976                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 977                         /* get stable pstate sclk in Mhz */
 978                         if (amdgpu_dpm_read_sensor(adev,
 979                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 980                                                    (void *)&ui32, &ui32_size)) {
 981                                 return -EINVAL;
 982                         }
 983                         ui32 /= 100;
 984                         break;
 985                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 986                         /* get stable pstate mclk in Mhz */
 987                         if (amdgpu_dpm_read_sensor(adev,
 988                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 989                                                    (void *)&ui32, &ui32_size)) {
 990                                 return -EINVAL;
 991                         }
 992                         ui32 /= 100;
 993                         break;
 994                 default:
 995                         DRM_DEBUG_KMS("Invalid request %d\n",
 996                                       info->sensor_info.type);
 997                         return -EINVAL;
 998                 }
 999                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1000         }
1001         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1002                 ui32 = atomic_read(&adev->vram_lost_counter);
1003                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1004         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1005                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1006                 uint64_t ras_mask;
1007
1008                 if (!ras)
1009                         return -EINVAL;
1010                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1011
1012                 return copy_to_user(out, &ras_mask,
1013                                 min_t(u64, size, sizeof(ras_mask))) ?
1014                         -EFAULT : 0;
1015         }
1016         case AMDGPU_INFO_VIDEO_CAPS: {
1017                 const struct amdgpu_video_codecs *codecs;
1018                 struct drm_amdgpu_info_video_caps *caps;
1019                 int r;
1020
1021                 switch (info->video_cap.type) {
1022                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1023                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1024                         if (r)
1025                                 return -EINVAL;
1026                         break;
1027                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1028                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1029                         if (r)
1030                                 return -EINVAL;
1031                         break;
1032                 default:
1033                         DRM_DEBUG_KMS("Invalid request %d\n",
1034                                       info->video_cap.type);
1035                         return -EINVAL;
1036                 }
1037
1038                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1039                 if (!caps)
1040                         return -ENOMEM;
1041
1042                 for (i = 0; i < codecs->codec_count; i++) {
1043                         int idx = codecs->codec_array[i].codec_type;
1044
1045                         switch (idx) {
1046                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1047                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1048                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1049                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1050                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1051                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1052                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1053                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1054                                 caps->codec_info[idx].valid = 1;
1055                                 caps->codec_info[idx].max_width =
1056                                         codecs->codec_array[i].max_width;
1057                                 caps->codec_info[idx].max_height =
1058                                         codecs->codec_array[i].max_height;
1059                                 caps->codec_info[idx].max_pixels_per_frame =
1060                                         codecs->codec_array[i].max_pixels_per_frame;
1061                                 caps->codec_info[idx].max_level =
1062                                         codecs->codec_array[i].max_level;
1063                                 break;
1064                         default:
1065                                 break;
1066                         }
1067                 }
1068                 r = copy_to_user(out, caps,
1069                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1070                 kfree(caps);
1071                 return r;
1072         }
1073         default:
1074                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1075                 return -EINVAL;
1076         }
1077         return 0;
1078 }
1079
1080
1081 /*
1082  * Outdated mess for old drm with Xorg being in charge (void function now).
1083  */
1084 /**
1085  * amdgpu_driver_lastclose_kms - drm callback for last close
1086  *
1087  * @dev: drm dev pointer
1088  *
1089  * Switch vga_switcheroo state after last close (all asics).
1090  */
1091 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1092 {
1093         drm_fb_helper_lastclose(dev);
1094         vga_switcheroo_process_delayed_switch();
1095 }
1096
1097 /**
1098  * amdgpu_driver_open_kms - drm callback for open
1099  *
1100  * @dev: drm dev pointer
1101  * @file_priv: drm file
1102  *
1103  * On device open, init vm on cayman+ (all asics).
1104  * Returns 0 on success, error on failure.
1105  */
1106 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1107 {
1108         struct amdgpu_device *adev = drm_to_adev(dev);
1109         struct amdgpu_fpriv *fpriv;
1110         int r, pasid;
1111
1112         /* Ensure IB tests are run on ring */
1113         flush_delayed_work(&adev->delayed_init_work);
1114
1115
1116         if (amdgpu_ras_intr_triggered()) {
1117                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1118                 return -EHWPOISON;
1119         }
1120
1121         file_priv->driver_priv = NULL;
1122
1123         r = pm_runtime_get_sync(dev->dev);
1124         if (r < 0)
1125                 goto pm_put;
1126
1127         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1128         if (unlikely(!fpriv)) {
1129                 r = -ENOMEM;
1130                 goto out_suspend;
1131         }
1132
1133         pasid = amdgpu_pasid_alloc(16);
1134         if (pasid < 0) {
1135                 dev_warn(adev->dev, "No more PASIDs available!");
1136                 pasid = 0;
1137         }
1138
1139         r = amdgpu_vm_init(adev, &fpriv->vm);
1140         if (r)
1141                 goto error_pasid;
1142
1143         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1144         if (r)
1145                 goto error_vm;
1146
1147         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1148         if (!fpriv->prt_va) {
1149                 r = -ENOMEM;
1150                 goto error_vm;
1151         }
1152
1153         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1154                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1155
1156                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1157                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1158                 if (r)
1159                         goto error_vm;
1160         }
1161
1162         mutex_init(&fpriv->bo_list_lock);
1163         idr_init(&fpriv->bo_list_handles);
1164
1165         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1166
1167         file_priv->driver_priv = fpriv;
1168         goto out_suspend;
1169
1170 error_vm:
1171         amdgpu_vm_fini(adev, &fpriv->vm);
1172
1173 error_pasid:
1174         if (pasid) {
1175                 amdgpu_pasid_free(pasid);
1176                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1177         }
1178
1179         kfree(fpriv);
1180
1181 out_suspend:
1182         pm_runtime_mark_last_busy(dev->dev);
1183 pm_put:
1184         pm_runtime_put_autosuspend(dev->dev);
1185
1186         return r;
1187 }
1188
1189 /**
1190  * amdgpu_driver_postclose_kms - drm callback for post close
1191  *
1192  * @dev: drm dev pointer
1193  * @file_priv: drm file
1194  *
1195  * On device post close, tear down vm on cayman+ (all asics).
1196  */
1197 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1198                                  struct drm_file *file_priv)
1199 {
1200         struct amdgpu_device *adev = drm_to_adev(dev);
1201         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1202         struct amdgpu_bo_list *list;
1203         struct amdgpu_bo *pd;
1204         u32 pasid;
1205         int handle;
1206
1207         if (!fpriv)
1208                 return;
1209
1210         pm_runtime_get_sync(dev->dev);
1211
1212         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1213                 amdgpu_uvd_free_handles(adev, file_priv);
1214         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1215                 amdgpu_vce_free_handles(adev, file_priv);
1216
1217         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1218                 /* TODO: how to handle reserve failure */
1219                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1220                 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1221                 fpriv->csa_va = NULL;
1222                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1223         }
1224
1225         pasid = fpriv->vm.pasid;
1226         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1227         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1228                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1229                 amdgpu_bo_unreserve(pd);
1230         }
1231
1232         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1233         amdgpu_vm_fini(adev, &fpriv->vm);
1234
1235         if (pasid)
1236                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1237         amdgpu_bo_unref(&pd);
1238
1239         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1240                 amdgpu_bo_list_put(list);
1241
1242         idr_destroy(&fpriv->bo_list_handles);
1243         mutex_destroy(&fpriv->bo_list_lock);
1244
1245         kfree(fpriv);
1246         file_priv->driver_priv = NULL;
1247
1248         pm_runtime_mark_last_busy(dev->dev);
1249         pm_runtime_put_autosuspend(dev->dev);
1250 }
1251
1252
1253 void amdgpu_driver_release_kms(struct drm_device *dev)
1254 {
1255         struct amdgpu_device *adev = drm_to_adev(dev);
1256
1257         amdgpu_device_fini_sw(adev);
1258         pci_set_drvdata(adev->pdev, NULL);
1259 }
1260
1261 /*
1262  * VBlank related functions.
1263  */
1264 /**
1265  * amdgpu_get_vblank_counter_kms - get frame count
1266  *
1267  * @crtc: crtc to get the frame count from
1268  *
1269  * Gets the frame count on the requested crtc (all asics).
1270  * Returns frame count on success, -EINVAL on failure.
1271  */
1272 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1273 {
1274         struct drm_device *dev = crtc->dev;
1275         unsigned int pipe = crtc->index;
1276         struct amdgpu_device *adev = drm_to_adev(dev);
1277         int vpos, hpos, stat;
1278         u32 count;
1279
1280         if (pipe >= adev->mode_info.num_crtc) {
1281                 DRM_ERROR("Invalid crtc %u\n", pipe);
1282                 return -EINVAL;
1283         }
1284
1285         /* The hw increments its frame counter at start of vsync, not at start
1286          * of vblank, as is required by DRM core vblank counter handling.
1287          * Cook the hw count here to make it appear to the caller as if it
1288          * incremented at start of vblank. We measure distance to start of
1289          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1290          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1291          * result by 1 to give the proper appearance to caller.
1292          */
1293         if (adev->mode_info.crtcs[pipe]) {
1294                 /* Repeat readout if needed to provide stable result if
1295                  * we cross start of vsync during the queries.
1296                  */
1297                 do {
1298                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1299                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1300                          * vpos as distance to start of vblank, instead of
1301                          * regular vertical scanout pos.
1302                          */
1303                         stat = amdgpu_display_get_crtc_scanoutpos(
1304                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1305                                 &vpos, &hpos, NULL, NULL,
1306                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1307                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1308
1309                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1310                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1311                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1312                 } else {
1313                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1314                                       pipe, vpos);
1315
1316                         /* Bump counter if we are at >= leading edge of vblank,
1317                          * but before vsync where vpos would turn negative and
1318                          * the hw counter really increments.
1319                          */
1320                         if (vpos >= 0)
1321                                 count++;
1322                 }
1323         } else {
1324                 /* Fallback to use value as is. */
1325                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1326                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1327         }
1328
1329         return count;
1330 }
1331
1332 /**
1333  * amdgpu_enable_vblank_kms - enable vblank interrupt
1334  *
1335  * @crtc: crtc to enable vblank interrupt for
1336  *
1337  * Enable the interrupt on the requested crtc (all asics).
1338  * Returns 0 on success, -EINVAL on failure.
1339  */
1340 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1341 {
1342         struct drm_device *dev = crtc->dev;
1343         unsigned int pipe = crtc->index;
1344         struct amdgpu_device *adev = drm_to_adev(dev);
1345         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1346
1347         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1348 }
1349
1350 /**
1351  * amdgpu_disable_vblank_kms - disable vblank interrupt
1352  *
1353  * @crtc: crtc to disable vblank interrupt for
1354  *
1355  * Disable the interrupt on the requested crtc (all asics).
1356  */
1357 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1358 {
1359         struct drm_device *dev = crtc->dev;
1360         unsigned int pipe = crtc->index;
1361         struct amdgpu_device *adev = drm_to_adev(dev);
1362         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1363
1364         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1365 }
1366
1367 /*
1368  * Debugfs info
1369  */
1370 #if defined(CONFIG_DEBUG_FS)
1371
1372 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1373 {
1374         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1375         struct drm_amdgpu_info_firmware fw_info;
1376         struct drm_amdgpu_query_fw query_fw;
1377         struct atom_context *ctx = adev->mode_info.atom_context;
1378         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1379         int ret, i;
1380
1381         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1382 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1383                 TA_FW_NAME(XGMI),
1384                 TA_FW_NAME(RAS),
1385                 TA_FW_NAME(HDCP),
1386                 TA_FW_NAME(DTM),
1387                 TA_FW_NAME(RAP),
1388                 TA_FW_NAME(SECUREDISPLAY),
1389 #undef TA_FW_NAME
1390         };
1391
1392         /* VCE */
1393         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1394         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1395         if (ret)
1396                 return ret;
1397         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1398                    fw_info.feature, fw_info.ver);
1399
1400         /* UVD */
1401         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1402         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1403         if (ret)
1404                 return ret;
1405         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1406                    fw_info.feature, fw_info.ver);
1407
1408         /* GMC */
1409         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1410         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1411         if (ret)
1412                 return ret;
1413         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1414                    fw_info.feature, fw_info.ver);
1415
1416         /* ME */
1417         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1418         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1419         if (ret)
1420                 return ret;
1421         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1422                    fw_info.feature, fw_info.ver);
1423
1424         /* PFP */
1425         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1426         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1427         if (ret)
1428                 return ret;
1429         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1430                    fw_info.feature, fw_info.ver);
1431
1432         /* CE */
1433         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1434         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1435         if (ret)
1436                 return ret;
1437         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1438                    fw_info.feature, fw_info.ver);
1439
1440         /* RLC */
1441         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1442         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1443         if (ret)
1444                 return ret;
1445         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1446                    fw_info.feature, fw_info.ver);
1447
1448         /* RLC SAVE RESTORE LIST CNTL */
1449         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1450         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1451         if (ret)
1452                 return ret;
1453         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1454                    fw_info.feature, fw_info.ver);
1455
1456         /* RLC SAVE RESTORE LIST GPM MEM */
1457         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1458         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1459         if (ret)
1460                 return ret;
1461         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1462                    fw_info.feature, fw_info.ver);
1463
1464         /* RLC SAVE RESTORE LIST SRM MEM */
1465         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1466         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1467         if (ret)
1468                 return ret;
1469         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1470                    fw_info.feature, fw_info.ver);
1471
1472         /* MEC */
1473         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1474         query_fw.index = 0;
1475         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1476         if (ret)
1477                 return ret;
1478         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1479                    fw_info.feature, fw_info.ver);
1480
1481         /* MEC2 */
1482         if (adev->gfx.mec2_fw) {
1483                 query_fw.index = 1;
1484                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1485                 if (ret)
1486                         return ret;
1487                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1488                            fw_info.feature, fw_info.ver);
1489         }
1490
1491         /* PSP SOS */
1492         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1493         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1494         if (ret)
1495                 return ret;
1496         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1497                    fw_info.feature, fw_info.ver);
1498
1499
1500         /* PSP ASD */
1501         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1502         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1503         if (ret)
1504                 return ret;
1505         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1506                    fw_info.feature, fw_info.ver);
1507
1508         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1509         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1510                 query_fw.index = i;
1511                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1512                 if (ret)
1513                         continue;
1514
1515                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1516                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1517         }
1518
1519         /* SMC */
1520         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1521         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1522         if (ret)
1523                 return ret;
1524         smu_program = (fw_info.ver >> 24) & 0xff;
1525         smu_major = (fw_info.ver >> 16) & 0xff;
1526         smu_minor = (fw_info.ver >> 8) & 0xff;
1527         smu_debug = (fw_info.ver >> 0) & 0xff;
1528         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1529                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1530
1531         /* SDMA */
1532         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1533         for (i = 0; i < adev->sdma.num_instances; i++) {
1534                 query_fw.index = i;
1535                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1536                 if (ret)
1537                         return ret;
1538                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1539                            i, fw_info.feature, fw_info.ver);
1540         }
1541
1542         /* VCN */
1543         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1544         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1545         if (ret)
1546                 return ret;
1547         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1548                    fw_info.feature, fw_info.ver);
1549
1550         /* DMCU */
1551         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1552         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1553         if (ret)
1554                 return ret;
1555         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1556                    fw_info.feature, fw_info.ver);
1557
1558         /* DMCUB */
1559         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1560         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1561         if (ret)
1562                 return ret;
1563         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1564                    fw_info.feature, fw_info.ver);
1565
1566         /* TOC */
1567         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1568         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1569         if (ret)
1570                 return ret;
1571         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1572                    fw_info.feature, fw_info.ver);
1573
1574         /* CAP */
1575         if (adev->psp.cap_fw) {
1576                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1577                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1578                 if (ret)
1579                         return ret;
1580                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1581                                 fw_info.feature, fw_info.ver);
1582         }
1583
1584         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1585
1586         return 0;
1587 }
1588
1589 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1590
1591 #endif
1592
1593 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1594 {
1595 #if defined(CONFIG_DEBUG_FS)
1596         struct drm_minor *minor = adev_to_drm(adev)->primary;
1597         struct dentry *root = minor->debugfs_root;
1598
1599         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1600                             adev, &amdgpu_debugfs_firmware_info_fops);
1601
1602 #endif
1603 }