drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46 #include "amdgpu_reset.h"
  47 #include "amd_pcie.h"
  48
  49 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  50 {
  51         struct amdgpu_gpu_instance *gpu_instance;
  52         int i;
  53
  54         mutex_lock(&mgpu_info.mutex);
  55
  56         for (i = 0; i < mgpu_info.num_gpu; i++) {
  57                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  58                 if (gpu_instance->adev == adev) {
  59                         mgpu_info.gpu_ins[i] =
  60                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  61                         mgpu_info.num_gpu--;
  62                         if (adev->flags & AMD_IS_APU)
  63                                 mgpu_info.num_apu--;
  64                         else
  65                                 mgpu_info.num_dgpu--;
  66                         break;
  67                 }
  68         }
  69
  70         mutex_unlock(&mgpu_info.mutex);
  71 }
  72
  73 /**
  74  * amdgpu_driver_unload_kms - Main unload function for KMS.
  75  *
  76  * @dev: drm dev pointer
  77  *
  78  * This is the main unload function for KMS (all asics).
  79  * Returns 0 on success.
  80  */
  81 void amdgpu_driver_unload_kms(struct drm_device *dev)
  82 {
  83         struct amdgpu_device *adev = drm_to_adev(dev);
  84
  85         if (adev == NULL)
  86                 return;
  87
  88         amdgpu_unregister_gpu_instance(adev);
  89
  90         if (adev->rmmio == NULL)
  91                 return;
  92
  93         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  94                 DRM_WARN("smart shift update failed\n");
  95
  96         amdgpu_acpi_fini(adev);
  97         amdgpu_device_fini_hw(adev);
  98 }
  99
 100 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 101 {
 102         struct amdgpu_gpu_instance *gpu_instance;
 103
 104         mutex_lock(&mgpu_info.mutex);
 105
 106         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 107                 DRM_ERROR("Cannot register more gpu instance\n");
 108                 mutex_unlock(&mgpu_info.mutex);
 109                 return;
 110         }
 111
 112         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 113         gpu_instance->adev = adev;
 114         gpu_instance->mgpu_fan_enabled = 0;
 115
 116         mgpu_info.num_gpu++;
 117         if (adev->flags & AMD_IS_APU)
 118                 mgpu_info.num_apu++;
 119         else
 120                 mgpu_info.num_dgpu++;
 121
 122         mutex_unlock(&mgpu_info.mutex);
 123 }
 124
 125 /**
 126  * amdgpu_driver_load_kms - Main load function for KMS.
 127  *
 128  * @adev: pointer to struct amdgpu_device
 129  * @flags: device flags
 130  *
 131  * This is the main load function for KMS (all asics).
 132  * Returns 0 on success, error on failure.
 133  */
 134 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 135 {
 136         struct drm_device *dev;
 137         int r, acpi_status;
 138
 139         dev = adev_to_drm(adev);
 140
 141         /* amdgpu_device_init should report only fatal error
 142          * like memory allocation failure or iomapping failure,
 143          * or memory manager initialization failure, it must
 144          * properly initialize the GPU MC controller and permit
 145          * VRAM allocation
 146          */
 147         r = amdgpu_device_init(adev, flags);
 148         if (r) {
 149                 dev_err(dev->dev, "Fatal error during GPU init\n");
 150                 goto out;
 151         }
 152
 153         amdgpu_device_detect_runtime_pm_mode(adev);
 154
 155         /* Call ACPI methods: require modeset init
 156          * but failure is not fatal
 157          */
 158
 159         acpi_status = amdgpu_acpi_init(adev);
 160         if (acpi_status)
 161                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 162
 163         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 164                 DRM_WARN("smart shift update failed\n");
 165
 166 out:
 167         if (r)
 168                 amdgpu_driver_unload_kms(dev);
 169
 170         return r;
 171 }
 172
 173 static enum amd_ip_block_type
 174         amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip)
 175 {
 176         enum amd_ip_block_type type;
 177
 178         switch (ip) {
 179         case AMDGPU_HW_IP_GFX:
 180                 type = AMD_IP_BLOCK_TYPE_GFX;
 181                 break;
 182         case AMDGPU_HW_IP_COMPUTE:
 183                 type = AMD_IP_BLOCK_TYPE_GFX;
 184                 break;
 185         case AMDGPU_HW_IP_DMA:
 186                 type = AMD_IP_BLOCK_TYPE_SDMA;
 187                 break;
 188         case AMDGPU_HW_IP_UVD:
 189         case AMDGPU_HW_IP_UVD_ENC:
 190                 type = AMD_IP_BLOCK_TYPE_UVD;
 191                 break;
 192         case AMDGPU_HW_IP_VCE:
 193                 type = AMD_IP_BLOCK_TYPE_VCE;
 194                 break;
 195         case AMDGPU_HW_IP_VCN_DEC:
 196         case AMDGPU_HW_IP_VCN_ENC:
 197                 type = AMD_IP_BLOCK_TYPE_VCN;
 198                 break;
 199         case AMDGPU_HW_IP_VCN_JPEG:
 200                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 201                                    AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 202                 break;
 203         default:
 204                 type = AMD_IP_BLOCK_TYPE_NUM;
 205                 break;
 206         }
 207
 208         return type;
 209 }
 210
 211 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 212                                 struct drm_amdgpu_query_fw *query_fw,
 213                                 struct amdgpu_device *adev)
 214 {
 215         switch (query_fw->fw_type) {
 216         case AMDGPU_INFO_FW_VCE:
 217                 fw_info->ver = adev->vce.fw_version;
 218                 fw_info->feature = adev->vce.fb_version;
 219                 break;
 220         case AMDGPU_INFO_FW_UVD:
 221                 fw_info->ver = adev->uvd.fw_version;
 222                 fw_info->feature = 0;
 223                 break;
 224         case AMDGPU_INFO_FW_VCN:
 225                 fw_info->ver = adev->vcn.fw_version;
 226                 fw_info->feature = 0;
 227                 break;
 228         case AMDGPU_INFO_FW_GMC:
 229                 fw_info->ver = adev->gmc.fw_version;
 230                 fw_info->feature = 0;
 231                 break;
 232         case AMDGPU_INFO_FW_GFX_ME:
 233                 fw_info->ver = adev->gfx.me_fw_version;
 234                 fw_info->feature = adev->gfx.me_feature_version;
 235                 break;
 236         case AMDGPU_INFO_FW_GFX_PFP:
 237                 fw_info->ver = adev->gfx.pfp_fw_version;
 238                 fw_info->feature = adev->gfx.pfp_feature_version;
 239                 break;
 240         case AMDGPU_INFO_FW_GFX_CE:
 241                 fw_info->ver = adev->gfx.ce_fw_version;
 242                 fw_info->feature = adev->gfx.ce_feature_version;
 243                 break;
 244         case AMDGPU_INFO_FW_GFX_RLC:
 245                 fw_info->ver = adev->gfx.rlc_fw_version;
 246                 fw_info->feature = adev->gfx.rlc_feature_version;
 247                 break;
 248         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 249                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 250                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 253                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 254                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 257                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 258                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_RLCP:
 261                 fw_info->ver = adev->gfx.rlcp_ucode_version;
 262                 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
 263                 break;
 264         case AMDGPU_INFO_FW_GFX_RLCV:
 265                 fw_info->ver = adev->gfx.rlcv_ucode_version;
 266                 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
 267                 break;
 268         case AMDGPU_INFO_FW_GFX_MEC:
 269                 if (query_fw->index == 0) {
 270                         fw_info->ver = adev->gfx.mec_fw_version;
 271                         fw_info->feature = adev->gfx.mec_feature_version;
 272                 } else if (query_fw->index == 1) {
 273                         fw_info->ver = adev->gfx.mec2_fw_version;
 274                         fw_info->feature = adev->gfx.mec2_feature_version;
 275                 } else
 276                         return -EINVAL;
 277                 break;
 278         case AMDGPU_INFO_FW_SMC:
 279                 fw_info->ver = adev->pm.fw_version;
 280                 fw_info->feature = 0;
 281                 break;
 282         case AMDGPU_INFO_FW_TA:
 283                 switch (query_fw->index) {
 284                 case TA_FW_TYPE_PSP_XGMI:
 285                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 286                         fw_info->feature = adev->psp.xgmi_context.context
 287                                                    .bin_desc.feature_version;
 288                         break;
 289                 case TA_FW_TYPE_PSP_RAS:
 290                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 291                         fw_info->feature = adev->psp.ras_context.context
 292                                                    .bin_desc.feature_version;
 293                         break;
 294                 case TA_FW_TYPE_PSP_HDCP:
 295                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 296                         fw_info->feature = adev->psp.hdcp_context.context
 297                                                    .bin_desc.feature_version;
 298                         break;
 299                 case TA_FW_TYPE_PSP_DTM:
 300                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 301                         fw_info->feature = adev->psp.dtm_context.context
 302                                                    .bin_desc.feature_version;
 303                         break;
 304                 case TA_FW_TYPE_PSP_RAP:
 305                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 306                         fw_info->feature = adev->psp.rap_context.context
 307                                                    .bin_desc.feature_version;
 308                         break;
 309                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 310                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 311                         fw_info->feature =
 312                                 adev->psp.securedisplay_context.context.bin_desc
 313                                         .feature_version;
 314                         break;
 315                 default:
 316                         return -EINVAL;
 317                 }
 318                 break;
 319         case AMDGPU_INFO_FW_SDMA:
 320                 if (query_fw->index >= adev->sdma.num_instances)
 321                         return -EINVAL;
 322                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 323                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 324                 break;
 325         case AMDGPU_INFO_FW_SOS:
 326                 fw_info->ver = adev->psp.sos.fw_version;
 327                 fw_info->feature = adev->psp.sos.feature_version;
 328                 break;
 329         case AMDGPU_INFO_FW_ASD:
 330                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 331                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 332                 break;
 333         case AMDGPU_INFO_FW_DMCU:
 334                 fw_info->ver = adev->dm.dmcu_fw_version;
 335                 fw_info->feature = 0;
 336                 break;
 337         case AMDGPU_INFO_FW_DMCUB:
 338                 fw_info->ver = adev->dm.dmcub_fw_version;
 339                 fw_info->feature = 0;
 340                 break;
 341         case AMDGPU_INFO_FW_TOC:
 342                 fw_info->ver = adev->psp.toc.fw_version;
 343                 fw_info->feature = adev->psp.toc.feature_version;
 344                 break;
 345         case AMDGPU_INFO_FW_CAP:
 346                 fw_info->ver = adev->psp.cap_fw_version;
 347                 fw_info->feature = adev->psp.cap_feature_version;
 348                 break;
 349         case AMDGPU_INFO_FW_MES_KIQ:
 350                 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
 351                 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
 352                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 353                 break;
 354         case AMDGPU_INFO_FW_MES:
 355                 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
 356                 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
 357                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 358                 break;
 359         case AMDGPU_INFO_FW_IMU:
 360                 fw_info->ver = adev->gfx.imu_fw_version;
 361                 fw_info->feature = 0;
 362                 break;
 363         case AMDGPU_INFO_FW_VPE:
 364                 fw_info->ver = adev->vpe.fw_version;
 365                 fw_info->feature = adev->vpe.feature_version;
 366                 break;
 367         default:
 368                 return -EINVAL;
 369         }
 370         return 0;
 371 }
 372
 373 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 374                              struct drm_amdgpu_info *info,
 375                              struct drm_amdgpu_info_hw_ip *result)
 376 {
 377         uint32_t ib_start_alignment = 0;
 378         uint32_t ib_size_alignment = 0;
 379         enum amd_ip_block_type type;
 380         unsigned int num_rings = 0;
 381         unsigned int i, j;
 382
 383         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 384                 return -EINVAL;
 385
 386         switch (info->query_hw_ip.type) {
 387         case AMDGPU_HW_IP_GFX:
 388                 type = AMD_IP_BLOCK_TYPE_GFX;
 389                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 390                         if (adev->gfx.gfx_ring[i].sched.ready)
 391                                 ++num_rings;
 392                 ib_start_alignment = 32;
 393                 ib_size_alignment = 32;
 394                 break;
 395         case AMDGPU_HW_IP_COMPUTE:
 396                 type = AMD_IP_BLOCK_TYPE_GFX;
 397                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 398                         if (adev->gfx.compute_ring[i].sched.ready)
 399                                 ++num_rings;
 400                 ib_start_alignment = 32;
 401                 ib_size_alignment = 32;
 402                 break;
 403         case AMDGPU_HW_IP_DMA:
 404                 type = AMD_IP_BLOCK_TYPE_SDMA;
 405                 for (i = 0; i < adev->sdma.num_instances; i++)
 406                         if (adev->sdma.instance[i].ring.sched.ready)
 407                                 ++num_rings;
 408                 ib_start_alignment = 256;
 409                 ib_size_alignment = 4;
 410                 break;
 411         case AMDGPU_HW_IP_UVD:
 412                 type = AMD_IP_BLOCK_TYPE_UVD;
 413                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 414                         if (adev->uvd.harvest_config & (1 << i))
 415                                 continue;
 416
 417                         if (adev->uvd.inst[i].ring.sched.ready)
 418                                 ++num_rings;
 419                 }
 420                 ib_start_alignment = 256;
 421                 ib_size_alignment = 64;
 422                 break;
 423         case AMDGPU_HW_IP_VCE:
 424                 type = AMD_IP_BLOCK_TYPE_VCE;
 425                 for (i = 0; i < adev->vce.num_rings; i++)
 426                         if (adev->vce.ring[i].sched.ready)
 427                                 ++num_rings;
 428                 ib_start_alignment = 256;
 429                 ib_size_alignment = 4;
 430                 break;
 431         case AMDGPU_HW_IP_UVD_ENC:
 432                 type = AMD_IP_BLOCK_TYPE_UVD;
 433                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 434                         if (adev->uvd.harvest_config & (1 << i))
 435                                 continue;
 436
 437                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 438                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 439                                         ++num_rings;
 440                 }
 441                 ib_start_alignment = 256;
 442                 ib_size_alignment = 4;
 443                 break;
 444         case AMDGPU_HW_IP_VCN_DEC:
 445                 type = AMD_IP_BLOCK_TYPE_VCN;
 446                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 447                         if (adev->vcn.harvest_config & (1 << i))
 448                                 continue;
 449
 450                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 451                                 ++num_rings;
 452                 }
 453                 ib_start_alignment = 256;
 454                 ib_size_alignment = 64;
 455                 break;
 456         case AMDGPU_HW_IP_VCN_ENC:
 457                 type = AMD_IP_BLOCK_TYPE_VCN;
 458                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 459                         if (adev->vcn.harvest_config & (1 << i))
 460                                 continue;
 461
 462                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 463                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 464                                         ++num_rings;
 465                 }
 466                 ib_start_alignment = 256;
 467                 ib_size_alignment = 4;
 468                 break;
 469         case AMDGPU_HW_IP_VCN_JPEG:
 470                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 471                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 472
 473                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 474                         if (adev->jpeg.harvest_config & (1 << i))
 475                                 continue;
 476
 477                         for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
 478                                 if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
 479                                         ++num_rings;
 480                 }
 481                 ib_start_alignment = 256;
 482                 ib_size_alignment = 64;
 483                 break;
 484         case AMDGPU_HW_IP_VPE:
 485                 type = AMD_IP_BLOCK_TYPE_VPE;
 486                 if (adev->vpe.ring.sched.ready)
 487                         ++num_rings;
 488                 ib_start_alignment = 256;
 489                 ib_size_alignment = 4;
 490                 break;
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         for (i = 0; i < adev->num_ip_blocks; i++)
 496                 if (adev->ip_blocks[i].version->type == type &&
 497                     adev->ip_blocks[i].status.valid)
 498                         break;
 499
 500         if (i == adev->num_ip_blocks)
 501                 return 0;
 502
 503         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 504                         num_rings);
 505
 506         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 507         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 508
 509         if (adev->asic_type >= CHIP_VEGA10) {
 510                 switch (type) {
 511                 case AMD_IP_BLOCK_TYPE_GFX:
 512                         result->ip_discovery_version =
 513                                 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0));
 514                         break;
 515                 case AMD_IP_BLOCK_TYPE_SDMA:
 516                         result->ip_discovery_version =
 517                                 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0));
 518                         break;
 519                 case AMD_IP_BLOCK_TYPE_UVD:
 520                 case AMD_IP_BLOCK_TYPE_VCN:
 521                 case AMD_IP_BLOCK_TYPE_JPEG:
 522                         result->ip_discovery_version =
 523                                 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0));
 524                         break;
 525                 case AMD_IP_BLOCK_TYPE_VCE:
 526                         result->ip_discovery_version =
 527                                 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0));
 528                         break;
 529                 case AMD_IP_BLOCK_TYPE_VPE:
 530                         result->ip_discovery_version =
 531                                 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0));
 532                         break;
 533                 default:
 534                         result->ip_discovery_version = 0;
 535                         break;
 536                 }
 537         } else {
 538                 result->ip_discovery_version = 0;
 539         }
 540         result->capabilities_flags = 0;
 541         result->available_rings = (1 << num_rings) - 1;
 542         result->ib_start_alignment = ib_start_alignment;
 543         result->ib_size_alignment = ib_size_alignment;
 544         return 0;
 545 }
 546
 547 /*
 548  * Userspace get information ioctl
 549  */
 550 /**
 551  * amdgpu_info_ioctl - answer a device specific request.
 552  *
 553  * @dev: drm device pointer
 554  * @data: request object
 555  * @filp: drm filp
 556  *
 557  * This function is used to pass device specific parameters to the userspace
 558  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 559  * etc. (all asics).
 560  * Returns 0 on success, -EINVAL on failure.
 561  */
 562 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 563 {
 564         struct amdgpu_device *adev = drm_to_adev(dev);
 565         struct drm_amdgpu_info *info = data;
 566         struct amdgpu_mode_info *minfo = &adev->mode_info;
 567         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 568         struct amdgpu_fpriv *fpriv;
 569         struct amdgpu_ip_block *ip_block;
 570         enum amd_ip_block_type type;
 571         struct amdgpu_xcp *xcp;
 572         u32 count, inst_mask;
 573         uint32_t size = info->return_size;
 574         struct drm_crtc *crtc;
 575         uint32_t ui32 = 0;
 576         uint64_t ui64 = 0;
 577         int i, found, ret;
 578         int ui32_size = sizeof(ui32);
 579
 580         if (!info->return_size || !info->return_pointer)
 581                 return -EINVAL;
 582
 583         switch (info->query) {
 584         case AMDGPU_INFO_ACCEL_WORKING:
 585                 ui32 = adev->accel_working;
 586                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 587         case AMDGPU_INFO_CRTC_FROM_ID:
 588                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 589                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 590                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 591                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 592
 593                                 ui32 = amdgpu_crtc->crtc_id;
 594                                 found = 1;
 595                                 break;
 596                         }
 597                 }
 598                 if (!found) {
 599                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 600                         return -EINVAL;
 601                 }
 602                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 603         case AMDGPU_INFO_HW_IP_INFO: {
 604                 struct drm_amdgpu_info_hw_ip ip = {};
 605
 606                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 607                 if (ret)
 608                         return ret;
 609
 610                 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
 611                 return ret ? -EFAULT : 0;
 612         }
 613         case AMDGPU_INFO_HW_IP_COUNT: {
 614                 fpriv = (struct amdgpu_fpriv *)filp->driver_priv;
 615                 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
 616                 ip_block = amdgpu_device_ip_get_ip_block(adev, type);
 617
 618                 if (!ip_block || !ip_block->status.valid)
 619                         return -EINVAL;
 620
 621                 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 &&
 622                     fpriv->xcp_id < adev->xcp_mgr->num_xcps) {
 623                         xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id];
 624                         switch (type) {
 625                         case AMD_IP_BLOCK_TYPE_GFX:
 626                                 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
 627                                 if (ret)
 628                                         return ret;
 629                                 count = hweight32(inst_mask);
 630                                 break;
 631                         case AMD_IP_BLOCK_TYPE_SDMA:
 632                                 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask);
 633                                 if (ret)
 634                                         return ret;
 635                                 count = hweight32(inst_mask);
 636                                 break;
 637                         case AMD_IP_BLOCK_TYPE_JPEG:
 638                                 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
 639                                 if (ret)
 640                                         return ret;
 641                                 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings;
 642                                 break;
 643                         case AMD_IP_BLOCK_TYPE_VCN:
 644                                 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
 645                                 if (ret)
 646                                         return ret;
 647                                 count = hweight32(inst_mask);
 648                                 break;
 649                         default:
 650                                 return -EINVAL;
 651                         }
 652
 653                         return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 654                 }
 655
 656                 switch (type) {
 657                 case AMD_IP_BLOCK_TYPE_GFX:
 658                 case AMD_IP_BLOCK_TYPE_VCE:
 659                         count = 1;
 660                         break;
 661                 case AMD_IP_BLOCK_TYPE_SDMA:
 662                         count = adev->sdma.num_instances;
 663                         break;
 664                 case AMD_IP_BLOCK_TYPE_JPEG:
 665                         count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings;
 666                         break;
 667                 case AMD_IP_BLOCK_TYPE_VCN:
 668                         count = adev->vcn.num_vcn_inst;
 669                         break;
 670                 case AMD_IP_BLOCK_TYPE_UVD:
 671                         count = adev->uvd.num_uvd_inst;
 672                         break;
 673                 /* For all other IP block types not listed in the switch statement
 674                  * the ip status is valid here and the instance count is one.
 675                  */
 676                 default:
 677                         count = 1;
 678                         break;
 679                 }
 680
 681                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 682         }
 683         case AMDGPU_INFO_TIMESTAMP:
 684                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 685                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 686         case AMDGPU_INFO_FW_VERSION: {
 687                 struct drm_amdgpu_info_firmware fw_info;
 688
 689                 /* We only support one instance of each IP block right now. */
 690                 if (info->query_fw.ip_instance != 0)
 691                         return -EINVAL;
 692
 693                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 694                 if (ret)
 695                         return ret;
 696
 697                 return copy_to_user(out, &fw_info,
 698                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 699         }
 700         case AMDGPU_INFO_NUM_BYTES_MOVED:
 701                 ui64 = atomic64_read(&adev->num_bytes_moved);
 702                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 703         case AMDGPU_INFO_NUM_EVICTIONS:
 704                 ui64 = atomic64_read(&adev->num_evictions);
 705                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 706         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 707                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 708                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 709         case AMDGPU_INFO_VRAM_USAGE:
 710                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 711                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 712         case AMDGPU_INFO_VIS_VRAM_USAGE:
 713                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 714                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 715         case AMDGPU_INFO_GTT_USAGE:
 716                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 717                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 718         case AMDGPU_INFO_GDS_CONFIG: {
 719                 struct drm_amdgpu_info_gds gds_info;
 720
 721                 memset(&gds_info, 0, sizeof(gds_info));
 722                 gds_info.compute_partition_size = adev->gds.gds_size;
 723                 gds_info.gds_total_size = adev->gds.gds_size;
 724                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 725                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 726                 return copy_to_user(out, &gds_info,
 727                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 728         }
 729         case AMDGPU_INFO_VRAM_GTT: {
 730                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 731
 732                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 733                         atomic64_read(&adev->vram_pin_size) -
 734                         AMDGPU_VM_RESERVED_VRAM;
 735                 vram_gtt.vram_cpu_accessible_size =
 736                         min(adev->gmc.visible_vram_size -
 737                             atomic64_read(&adev->visible_pin_size),
 738                             vram_gtt.vram_size);
 739                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 740                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 741                 return copy_to_user(out, &vram_gtt,
 742                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 743         }
 744         case AMDGPU_INFO_MEMORY: {
 745                 struct drm_amdgpu_memory_info mem;
 746                 struct ttm_resource_manager *gtt_man =
 747                         &adev->mman.gtt_mgr.manager;
 748                 struct ttm_resource_manager *vram_man =
 749                         &adev->mman.vram_mgr.manager;
 750
 751                 memset(&mem, 0, sizeof(mem));
 752                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 753                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 754                         atomic64_read(&adev->vram_pin_size) -
 755                         AMDGPU_VM_RESERVED_VRAM;
 756                 mem.vram.heap_usage =
 757                         ttm_resource_manager_usage(vram_man);
 758                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 759
 760                 mem.cpu_accessible_vram.total_heap_size =
 761                         adev->gmc.visible_vram_size;
 762                 mem.cpu_accessible_vram.usable_heap_size =
 763                         min(adev->gmc.visible_vram_size -
 764                             atomic64_read(&adev->visible_pin_size),
 765                             mem.vram.usable_heap_size);
 766                 mem.cpu_accessible_vram.heap_usage =
 767                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 768                 mem.cpu_accessible_vram.max_allocation =
 769                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 770
 771                 mem.gtt.total_heap_size = gtt_man->size;
 772                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 773                         atomic64_read(&adev->gart_pin_size);
 774                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 775                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 776
 777                 return copy_to_user(out, &mem,
 778                                     min((size_t)size, sizeof(mem)))
 779                                     ? -EFAULT : 0;
 780         }
 781         case AMDGPU_INFO_READ_MMR_REG: {
 782                 int ret = 0;
 783                 unsigned int n, alloc_size;
 784                 uint32_t *regs;
 785                 unsigned int se_num = (info->read_mmr_reg.instance >>
 786                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 787                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 788                 unsigned int sh_num = (info->read_mmr_reg.instance >>
 789                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 790                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 791
 792                 if (!down_read_trylock(&adev->reset_domain->sem))
 793                         return -ENOENT;
 794
 795                 /* set full masks if the userspace set all bits
 796                  * in the bitfields
 797                  */
 798                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) {
 799                         se_num = 0xffffffff;
 800                 } else if (se_num >= AMDGPU_GFX_MAX_SE) {
 801                         ret = -EINVAL;
 802                         goto out;
 803                 }
 804
 805                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) {
 806                         sh_num = 0xffffffff;
 807                 } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) {
 808                         ret = -EINVAL;
 809                         goto out;
 810                 }
 811
 812                 if (info->read_mmr_reg.count > 128) {
 813                         ret = -EINVAL;
 814                         goto out;
 815                 }
 816
 817                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 818                 if (!regs) {
 819                         ret = -ENOMEM;
 820                         goto out;
 821                 }
 822
 823                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 824
 825                 amdgpu_gfx_off_ctrl(adev, false);
 826                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 827                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 828                                                       info->read_mmr_reg.dword_offset + i,
 829                                                       &regs[i])) {
 830                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 831                                               info->read_mmr_reg.dword_offset + i);
 832                                 kfree(regs);
 833                                 amdgpu_gfx_off_ctrl(adev, true);
 834                                 ret = -EFAULT;
 835                                 goto out;
 836                         }
 837                 }
 838                 amdgpu_gfx_off_ctrl(adev, true);
 839                 n = copy_to_user(out, regs, min(size, alloc_size));
 840                 kfree(regs);
 841                 ret = (n ? -EFAULT : 0);
 842 out:
 843                 up_read(&adev->reset_domain->sem);
 844                 return ret;
 845         }
 846         case AMDGPU_INFO_DEV_INFO: {
 847                 struct drm_amdgpu_info_device *dev_info;
 848                 uint64_t vm_size;
 849                 uint32_t pcie_gen_mask, pcie_width_mask;
 850
 851                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 852                 if (!dev_info)
 853                         return -ENOMEM;
 854
 855                 dev_info->device_id = adev->pdev->device;
 856                 dev_info->chip_rev = adev->rev_id;
 857                 dev_info->external_rev = adev->external_rev_id;
 858                 dev_info->pci_rev = adev->pdev->revision;
 859                 dev_info->family = adev->family;
 860                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 861                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 862                 /* return all clocks in KHz */
 863                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 864                 if (adev->pm.dpm_enabled) {
 865                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 866                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 867                         dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
 868                         dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
 869                 } else {
 870                         dev_info->max_engine_clock =
 871                                 dev_info->min_engine_clock =
 872                                         adev->clock.default_sclk * 10;
 873                         dev_info->max_memory_clock =
 874                                 dev_info->min_memory_clock =
 875                                         adev->clock.default_mclk * 10;
 876                 }
 877                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 878                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 879                         adev->gfx.config.max_shader_engines;
 880                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 881                 dev_info->ids_flags = 0;
 882                 if (adev->flags & AMD_IS_APU)
 883                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 884                 if (adev->gfx.mcbp)
 885                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 886                 if (amdgpu_is_tmz(adev))
 887                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 888                 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
 889                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
 890
 891                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 892                 vm_size -= AMDGPU_VA_RESERVED_TOP;
 893
 894                 /* Older VCE FW versions are buggy and can handle only 40bits */
 895                 if (adev->vce.fw_version &&
 896                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 897                         vm_size = min(vm_size, 1ULL << 40);
 898
 899                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM;
 900                 dev_info->virtual_address_max =
 901                         min(vm_size, AMDGPU_GMC_HOLE_START);
 902
 903                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 904                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 905                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 906                 }
 907                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 908                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 909                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 910                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 911                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 912                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 913                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 914                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 915                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 916                        sizeof(dev_info->cu_bitmap));
 917                 dev_info->vram_type = adev->gmc.vram_type;
 918                 dev_info->vram_bit_width = adev->gmc.vram_width;
 919                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 920                 dev_info->gc_double_offchip_lds_buf =
 921                         adev->gfx.config.double_offchip_lds_buf;
 922                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 923                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 924                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 925                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 926                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 927                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 928                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 929
 930                 if (adev->family >= AMDGPU_FAMILY_NV)
 931                         dev_info->pa_sc_tile_steering_override =
 932                                 adev->gfx.config.pa_sc_tile_steering_override;
 933
 934                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 935
 936                 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
 937                 pcie_gen_mask = adev->pm.pcie_gen_mask &
 938                         (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT);
 939                 pcie_width_mask = adev->pm.pcie_mlw_mask &
 940                         (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT);
 941                 dev_info->pcie_gen = fls(pcie_gen_mask);
 942                 dev_info->pcie_num_lanes =
 943                         pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
 944                         pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
 945                         pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
 946                         pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
 947                         pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
 948                         pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
 949
 950                 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
 951                 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
 952                 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
 953                 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
 954                 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
 955                                             adev->gfx.config.gc_gl1c_per_sa;
 956                 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
 957                 dev_info->mall_size = adev->gmc.mall_size;
 958
 959
 960                 if (adev->gfx.funcs->get_gfx_shadow_info) {
 961                         struct amdgpu_gfx_shadow_info shadow_info;
 962
 963                         ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
 964                         if (!ret) {
 965                                 dev_info->shadow_size = shadow_info.shadow_size;
 966                                 dev_info->shadow_alignment = shadow_info.shadow_alignment;
 967                                 dev_info->csa_size = shadow_info.csa_size;
 968                                 dev_info->csa_alignment = shadow_info.csa_alignment;
 969                         }
 970                 }
 971
 972                 ret = copy_to_user(out, dev_info,
 973                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 974                 kfree(dev_info);
 975                 return ret;
 976         }
 977         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 978                 unsigned int i;
 979                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 980                 struct amd_vce_state *vce_state;
 981
 982                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 983                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 984                         if (vce_state) {
 985                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 986                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 987                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 988                                 vce_clk_table.num_valid_entries++;
 989                         }
 990                 }
 991
 992                 return copy_to_user(out, &vce_clk_table,
 993                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 994         }
 995         case AMDGPU_INFO_VBIOS: {
 996                 uint32_t bios_size = adev->bios_size;
 997
 998                 switch (info->vbios_info.type) {
 999                 case AMDGPU_INFO_VBIOS_SIZE:
1000                         return copy_to_user(out, &bios_size,
1001                                         min((size_t)size, sizeof(bios_size)))
1002                                         ? -EFAULT : 0;
1003                 case AMDGPU_INFO_VBIOS_IMAGE: {
1004                         uint8_t *bios;
1005                         uint32_t bios_offset = info->vbios_info.offset;
1006
1007                         if (bios_offset >= bios_size)
1008                                 return -EINVAL;
1009
1010                         bios = adev->bios + bios_offset;
1011                         return copy_to_user(out, bios,
1012                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
1013                                         ? -EFAULT : 0;
1014                 }
1015                 case AMDGPU_INFO_VBIOS_INFO: {
1016                         struct drm_amdgpu_info_vbios vbios_info = {};
1017                         struct atom_context *atom_context;
1018
1019                         atom_context = adev->mode_info.atom_context;
1020                         if (atom_context) {
1021                                 memcpy(vbios_info.name, atom_context->name,
1022                                        sizeof(atom_context->name));
1023                                 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
1024                                        sizeof(atom_context->vbios_pn));
1025                                 vbios_info.version = atom_context->version;
1026                                 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
1027                                        sizeof(atom_context->vbios_ver_str));
1028                                 memcpy(vbios_info.date, atom_context->date,
1029                                        sizeof(atom_context->date));
1030                         }
1031
1032                         return copy_to_user(out, &vbios_info,
1033                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
1034                 }
1035                 default:
1036                         DRM_DEBUG_KMS("Invalid request %d\n",
1037                                         info->vbios_info.type);
1038                         return -EINVAL;
1039                 }
1040         }
1041         case AMDGPU_INFO_NUM_HANDLES: {
1042                 struct drm_amdgpu_info_num_handles handle;
1043
1044                 switch (info->query_hw_ip.type) {
1045                 case AMDGPU_HW_IP_UVD:
1046                         /* Starting Polaris, we support unlimited UVD handles */
1047                         if (adev->asic_type < CHIP_POLARIS10) {
1048                                 handle.uvd_max_handles = adev->uvd.max_handles;
1049                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
1050
1051                                 return copy_to_user(out, &handle,
1052                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
1053                         } else {
1054                                 return -ENODATA;
1055                         }
1056
1057                         break;
1058                 default:
1059                         return -EINVAL;
1060                 }
1061         }
1062         case AMDGPU_INFO_SENSOR: {
1063                 if (!adev->pm.dpm_enabled)
1064                         return -ENOENT;
1065
1066                 switch (info->sensor_info.type) {
1067                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
1068                         /* get sclk in Mhz */
1069                         if (amdgpu_dpm_read_sensor(adev,
1070                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
1071                                                    (void *)&ui32, &ui32_size)) {
1072                                 return -EINVAL;
1073                         }
1074                         ui32 /= 100;
1075                         break;
1076                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
1077                         /* get mclk in Mhz */
1078                         if (amdgpu_dpm_read_sensor(adev,
1079                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
1080                                                    (void *)&ui32, &ui32_size)) {
1081                                 return -EINVAL;
1082                         }
1083                         ui32 /= 100;
1084                         break;
1085                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1086                         /* get temperature in millidegrees C */
1087                         if (amdgpu_dpm_read_sensor(adev,
1088                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
1089                                                    (void *)&ui32, &ui32_size)) {
1090                                 return -EINVAL;
1091                         }
1092                         break;
1093                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1094                         /* get GPU load */
1095                         if (amdgpu_dpm_read_sensor(adev,
1096                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
1097                                                    (void *)&ui32, &ui32_size)) {
1098                                 return -EINVAL;
1099                         }
1100                         break;
1101                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1102                         /* get average GPU power */
1103                         if (amdgpu_dpm_read_sensor(adev,
1104                                                    AMDGPU_PP_SENSOR_GPU_AVG_POWER,
1105                                                    (void *)&ui32, &ui32_size)) {
1106                                 /* fall back to input power for backwards compat */
1107                                 if (amdgpu_dpm_read_sensor(adev,
1108                                                            AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1109                                                            (void *)&ui32, &ui32_size)) {
1110                                         return -EINVAL;
1111                                 }
1112                         }
1113                         ui32 >>= 8;
1114                         break;
1115                 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER:
1116                         /* get input GPU power */
1117                         if (amdgpu_dpm_read_sensor(adev,
1118                                                    AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1119                                                    (void *)&ui32, &ui32_size)) {
1120                                 return -EINVAL;
1121                         }
1122                         ui32 >>= 8;
1123                         break;
1124                 case AMDGPU_INFO_SENSOR_VDDNB:
1125                         /* get VDDNB in millivolts */
1126                         if (amdgpu_dpm_read_sensor(adev,
1127                                                    AMDGPU_PP_SENSOR_VDDNB,
1128                                                    (void *)&ui32, &ui32_size)) {
1129                                 return -EINVAL;
1130                         }
1131                         break;
1132                 case AMDGPU_INFO_SENSOR_VDDGFX:
1133                         /* get VDDGFX in millivolts */
1134                         if (amdgpu_dpm_read_sensor(adev,
1135                                                    AMDGPU_PP_SENSOR_VDDGFX,
1136                                                    (void *)&ui32, &ui32_size)) {
1137                                 return -EINVAL;
1138                         }
1139                         break;
1140                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1141                         /* get stable pstate sclk in Mhz */
1142                         if (amdgpu_dpm_read_sensor(adev,
1143                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1144                                                    (void *)&ui32, &ui32_size)) {
1145                                 return -EINVAL;
1146                         }
1147                         ui32 /= 100;
1148                         break;
1149                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1150                         /* get stable pstate mclk in Mhz */
1151                         if (amdgpu_dpm_read_sensor(adev,
1152                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1153                                                    (void *)&ui32, &ui32_size)) {
1154                                 return -EINVAL;
1155                         }
1156                         ui32 /= 100;
1157                         break;
1158                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1159                         /* get peak pstate sclk in Mhz */
1160                         if (amdgpu_dpm_read_sensor(adev,
1161                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1162                                                    (void *)&ui32, &ui32_size)) {
1163                                 return -EINVAL;
1164                         }
1165                         ui32 /= 100;
1166                         break;
1167                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1168                         /* get peak pstate mclk in Mhz */
1169                         if (amdgpu_dpm_read_sensor(adev,
1170                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1171                                                    (void *)&ui32, &ui32_size)) {
1172                                 return -EINVAL;
1173                         }
1174                         ui32 /= 100;
1175                         break;
1176                 default:
1177                         DRM_DEBUG_KMS("Invalid request %d\n",
1178                                       info->sensor_info.type);
1179                         return -EINVAL;
1180                 }
1181                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1182         }
1183         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1184                 ui32 = atomic_read(&adev->vram_lost_counter);
1185                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1186         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1187                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1188                 uint64_t ras_mask;
1189
1190                 if (!ras)
1191                         return -EINVAL;
1192                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1193
1194                 return copy_to_user(out, &ras_mask,
1195                                 min_t(u64, size, sizeof(ras_mask))) ?
1196                         -EFAULT : 0;
1197         }
1198         case AMDGPU_INFO_VIDEO_CAPS: {
1199                 const struct amdgpu_video_codecs *codecs;
1200                 struct drm_amdgpu_info_video_caps *caps;
1201                 int r;
1202
1203                 if (!adev->asic_funcs->query_video_codecs)
1204                         return -EINVAL;
1205
1206                 switch (info->video_cap.type) {
1207                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1208                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1209                         if (r)
1210                                 return -EINVAL;
1211                         break;
1212                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1213                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1214                         if (r)
1215                                 return -EINVAL;
1216                         break;
1217                 default:
1218                         DRM_DEBUG_KMS("Invalid request %d\n",
1219                                       info->video_cap.type);
1220                         return -EINVAL;
1221                 }
1222
1223                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1224                 if (!caps)
1225                         return -ENOMEM;
1226
1227                 for (i = 0; i < codecs->codec_count; i++) {
1228                         int idx = codecs->codec_array[i].codec_type;
1229
1230                         switch (idx) {
1231                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1232                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1233                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1234                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1235                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1236                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1237                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1238                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1239                                 caps->codec_info[idx].valid = 1;
1240                                 caps->codec_info[idx].max_width =
1241                                         codecs->codec_array[i].max_width;
1242                                 caps->codec_info[idx].max_height =
1243                                         codecs->codec_array[i].max_height;
1244                                 caps->codec_info[idx].max_pixels_per_frame =
1245                                         codecs->codec_array[i].max_pixels_per_frame;
1246                                 caps->codec_info[idx].max_level =
1247                                         codecs->codec_array[i].max_level;
1248                                 break;
1249                         default:
1250                                 break;
1251                         }
1252                 }
1253                 r = copy_to_user(out, caps,
1254                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1255                 kfree(caps);
1256                 return r;
1257         }
1258         case AMDGPU_INFO_MAX_IBS: {
1259                 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1260
1261                 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1262                         max_ibs[i] = amdgpu_ring_max_ibs(i);
1263
1264                 return copy_to_user(out, max_ibs,
1265                                     min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1266         }
1267         case AMDGPU_INFO_GPUVM_FAULT: {
1268                 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1269                 struct amdgpu_vm *vm = &fpriv->vm;
1270                 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault;
1271                 unsigned long flags;
1272
1273                 if (!vm)
1274                         return -EINVAL;
1275
1276                 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault));
1277
1278                 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
1279                 gpuvm_fault.addr = vm->fault_info.addr;
1280                 gpuvm_fault.status = vm->fault_info.status;
1281                 gpuvm_fault.vmhub = vm->fault_info.vmhub;
1282                 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
1283
1284                 return copy_to_user(out, &gpuvm_fault,
1285                                     min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0;
1286         }
1287         default:
1288                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1289                 return -EINVAL;
1290         }
1291         return 0;
1292 }
1293
1294 /**
1295  * amdgpu_driver_open_kms - drm callback for open
1296  *
1297  * @dev: drm dev pointer
1298  * @file_priv: drm file
1299  *
1300  * On device open, init vm on cayman+ (all asics).
1301  * Returns 0 on success, error on failure.
1302  */
1303 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1304 {
1305         struct amdgpu_device *adev = drm_to_adev(dev);
1306         struct amdgpu_fpriv *fpriv;
1307         int r, pasid;
1308
1309         /* Ensure IB tests are run on ring */
1310         flush_delayed_work(&adev->delayed_init_work);
1311
1312
1313         if (amdgpu_ras_intr_triggered()) {
1314                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1315                 return -EHWPOISON;
1316         }
1317
1318         file_priv->driver_priv = NULL;
1319
1320         r = pm_runtime_get_sync(dev->dev);
1321         if (r < 0)
1322                 goto pm_put;
1323
1324         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1325         if (unlikely(!fpriv)) {
1326                 r = -ENOMEM;
1327                 goto out_suspend;
1328         }
1329
1330         pasid = amdgpu_pasid_alloc(16);
1331         if (pasid < 0) {
1332                 dev_warn(adev->dev, "No more PASIDs available!");
1333                 pasid = 0;
1334         }
1335
1336         r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
1337         if (r)
1338                 goto error_pasid;
1339
1340         r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id);
1341         if (r)
1342                 goto error_pasid;
1343
1344         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1345         if (r)
1346                 goto error_vm;
1347
1348         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1349         if (!fpriv->prt_va) {
1350                 r = -ENOMEM;
1351                 goto error_vm;
1352         }
1353
1354         if (adev->gfx.mcbp) {
1355                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1356
1357                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1358                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1359                 if (r)
1360                         goto error_vm;
1361         }
1362
1363         r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va);
1364         if (r)
1365                 goto error_vm;
1366
1367         mutex_init(&fpriv->bo_list_lock);
1368         idr_init_base(&fpriv->bo_list_handles, 1);
1369
1370         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1371
1372         file_priv->driver_priv = fpriv;
1373         goto out_suspend;
1374
1375 error_vm:
1376         amdgpu_vm_fini(adev, &fpriv->vm);
1377
1378 error_pasid:
1379         if (pasid) {
1380                 amdgpu_pasid_free(pasid);
1381                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1382         }
1383
1384         kfree(fpriv);
1385
1386 out_suspend:
1387         pm_runtime_mark_last_busy(dev->dev);
1388 pm_put:
1389         pm_runtime_put_autosuspend(dev->dev);
1390
1391         return r;
1392 }
1393
1394 /**
1395  * amdgpu_driver_postclose_kms - drm callback for post close
1396  *
1397  * @dev: drm dev pointer
1398  * @file_priv: drm file
1399  *
1400  * On device post close, tear down vm on cayman+ (all asics).
1401  */
1402 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1403                                  struct drm_file *file_priv)
1404 {
1405         struct amdgpu_device *adev = drm_to_adev(dev);
1406         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1407         struct amdgpu_bo_list *list;
1408         struct amdgpu_bo *pd;
1409         u32 pasid;
1410         int handle;
1411
1412         if (!fpriv)
1413                 return;
1414
1415         pm_runtime_get_sync(dev->dev);
1416
1417         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1418                 amdgpu_uvd_free_handles(adev, file_priv);
1419         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1420                 amdgpu_vce_free_handles(adev, file_priv);
1421
1422         if (fpriv->csa_va) {
1423                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1424
1425                 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1426                                                 fpriv->csa_va, csa_addr));
1427                 fpriv->csa_va = NULL;
1428         }
1429
1430         amdgpu_seq64_unmap(adev, fpriv);
1431
1432         pasid = fpriv->vm.pasid;
1433         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1434         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1435                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1436                 amdgpu_bo_unreserve(pd);
1437         }
1438
1439         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1440         amdgpu_vm_fini(adev, &fpriv->vm);
1441
1442         if (pasid)
1443                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1444         amdgpu_bo_unref(&pd);
1445
1446         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1447                 amdgpu_bo_list_put(list);
1448
1449         idr_destroy(&fpriv->bo_list_handles);
1450         mutex_destroy(&fpriv->bo_list_lock);
1451
1452         kfree(fpriv);
1453         file_priv->driver_priv = NULL;
1454
1455         pm_runtime_mark_last_busy(dev->dev);
1456         pm_runtime_put_autosuspend(dev->dev);
1457 }
1458
1459
1460 void amdgpu_driver_release_kms(struct drm_device *dev)
1461 {
1462         struct amdgpu_device *adev = drm_to_adev(dev);
1463
1464         amdgpu_device_fini_sw(adev);
1465         pci_set_drvdata(adev->pdev, NULL);
1466 }
1467
1468 /*
1469  * VBlank related functions.
1470  */
1471 /**
1472  * amdgpu_get_vblank_counter_kms - get frame count
1473  *
1474  * @crtc: crtc to get the frame count from
1475  *
1476  * Gets the frame count on the requested crtc (all asics).
1477  * Returns frame count on success, -EINVAL on failure.
1478  */
1479 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1480 {
1481         struct drm_device *dev = crtc->dev;
1482         unsigned int pipe = crtc->index;
1483         struct amdgpu_device *adev = drm_to_adev(dev);
1484         int vpos, hpos, stat;
1485         u32 count;
1486
1487         if (pipe >= adev->mode_info.num_crtc) {
1488                 DRM_ERROR("Invalid crtc %u\n", pipe);
1489                 return -EINVAL;
1490         }
1491
1492         /* The hw increments its frame counter at start of vsync, not at start
1493          * of vblank, as is required by DRM core vblank counter handling.
1494          * Cook the hw count here to make it appear to the caller as if it
1495          * incremented at start of vblank. We measure distance to start of
1496          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1497          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1498          * result by 1 to give the proper appearance to caller.
1499          */
1500         if (adev->mode_info.crtcs[pipe]) {
1501                 /* Repeat readout if needed to provide stable result if
1502                  * we cross start of vsync during the queries.
1503                  */
1504                 do {
1505                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1506                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1507                          * vpos as distance to start of vblank, instead of
1508                          * regular vertical scanout pos.
1509                          */
1510                         stat = amdgpu_display_get_crtc_scanoutpos(
1511                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1512                                 &vpos, &hpos, NULL, NULL,
1513                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1514                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1515
1516                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1517                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1518                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1519                 } else {
1520                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1521                                       pipe, vpos);
1522
1523                         /* Bump counter if we are at >= leading edge of vblank,
1524                          * but before vsync where vpos would turn negative and
1525                          * the hw counter really increments.
1526                          */
1527                         if (vpos >= 0)
1528                                 count++;
1529                 }
1530         } else {
1531                 /* Fallback to use value as is. */
1532                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1533                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1534         }
1535
1536         return count;
1537 }
1538
1539 /**
1540  * amdgpu_enable_vblank_kms - enable vblank interrupt
1541  *
1542  * @crtc: crtc to enable vblank interrupt for
1543  *
1544  * Enable the interrupt on the requested crtc (all asics).
1545  * Returns 0 on success, -EINVAL on failure.
1546  */
1547 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1548 {
1549         struct drm_device *dev = crtc->dev;
1550         unsigned int pipe = crtc->index;
1551         struct amdgpu_device *adev = drm_to_adev(dev);
1552         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1553
1554         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1555 }
1556
1557 /**
1558  * amdgpu_disable_vblank_kms - disable vblank interrupt
1559  *
1560  * @crtc: crtc to disable vblank interrupt for
1561  *
1562  * Disable the interrupt on the requested crtc (all asics).
1563  */
1564 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1565 {
1566         struct drm_device *dev = crtc->dev;
1567         unsigned int pipe = crtc->index;
1568         struct amdgpu_device *adev = drm_to_adev(dev);
1569         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1570
1571         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1572 }
1573
1574 /*
1575  * Debugfs info
1576  */
1577 #if defined(CONFIG_DEBUG_FS)
1578
1579 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1580 {
1581         struct amdgpu_device *adev = m->private;
1582         struct drm_amdgpu_info_firmware fw_info;
1583         struct drm_amdgpu_query_fw query_fw;
1584         struct atom_context *ctx = adev->mode_info.atom_context;
1585         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1586         int ret, i;
1587
1588         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1589 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1590                 TA_FW_NAME(XGMI),
1591                 TA_FW_NAME(RAS),
1592                 TA_FW_NAME(HDCP),
1593                 TA_FW_NAME(DTM),
1594                 TA_FW_NAME(RAP),
1595                 TA_FW_NAME(SECUREDISPLAY),
1596 #undef TA_FW_NAME
1597         };
1598
1599         /* VCE */
1600         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1601         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1602         if (ret)
1603                 return ret;
1604         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1605                    fw_info.feature, fw_info.ver);
1606
1607         /* UVD */
1608         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1609         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1610         if (ret)
1611                 return ret;
1612         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1613                    fw_info.feature, fw_info.ver);
1614
1615         /* GMC */
1616         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1617         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1618         if (ret)
1619                 return ret;
1620         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1621                    fw_info.feature, fw_info.ver);
1622
1623         /* ME */
1624         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1625         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1626         if (ret)
1627                 return ret;
1628         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1629                    fw_info.feature, fw_info.ver);
1630
1631         /* PFP */
1632         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1633         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1634         if (ret)
1635                 return ret;
1636         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1637                    fw_info.feature, fw_info.ver);
1638
1639         /* CE */
1640         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1641         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1642         if (ret)
1643                 return ret;
1644         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1645                    fw_info.feature, fw_info.ver);
1646
1647         /* RLC */
1648         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1649         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1650         if (ret)
1651                 return ret;
1652         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1653                    fw_info.feature, fw_info.ver);
1654
1655         /* RLC SAVE RESTORE LIST CNTL */
1656         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1657         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1658         if (ret)
1659                 return ret;
1660         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1661                    fw_info.feature, fw_info.ver);
1662
1663         /* RLC SAVE RESTORE LIST GPM MEM */
1664         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1665         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1666         if (ret)
1667                 return ret;
1668         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1669                    fw_info.feature, fw_info.ver);
1670
1671         /* RLC SAVE RESTORE LIST SRM MEM */
1672         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1673         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1674         if (ret)
1675                 return ret;
1676         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1677                    fw_info.feature, fw_info.ver);
1678
1679         /* RLCP */
1680         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1681         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1682         if (ret)
1683                 return ret;
1684         seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1685                    fw_info.feature, fw_info.ver);
1686
1687         /* RLCV */
1688         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1689         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1690         if (ret)
1691                 return ret;
1692         seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1693                    fw_info.feature, fw_info.ver);
1694
1695         /* MEC */
1696         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1697         query_fw.index = 0;
1698         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1699         if (ret)
1700                 return ret;
1701         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1702                    fw_info.feature, fw_info.ver);
1703
1704         /* MEC2 */
1705         if (adev->gfx.mec2_fw) {
1706                 query_fw.index = 1;
1707                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1708                 if (ret)
1709                         return ret;
1710                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1711                            fw_info.feature, fw_info.ver);
1712         }
1713
1714         /* IMU */
1715         query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1716         query_fw.index = 0;
1717         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1718         if (ret)
1719                 return ret;
1720         seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1721                    fw_info.feature, fw_info.ver);
1722
1723         /* PSP SOS */
1724         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1725         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1726         if (ret)
1727                 return ret;
1728         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1729                    fw_info.feature, fw_info.ver);
1730
1731
1732         /* PSP ASD */
1733         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1734         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1735         if (ret)
1736                 return ret;
1737         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1738                    fw_info.feature, fw_info.ver);
1739
1740         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1741         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1742                 query_fw.index = i;
1743                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1744                 if (ret)
1745                         continue;
1746
1747                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1748                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1749         }
1750
1751         /* SMC */
1752         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1753         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1754         if (ret)
1755                 return ret;
1756         smu_program = (fw_info.ver >> 24) & 0xff;
1757         smu_major = (fw_info.ver >> 16) & 0xff;
1758         smu_minor = (fw_info.ver >> 8) & 0xff;
1759         smu_debug = (fw_info.ver >> 0) & 0xff;
1760         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1761                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1762
1763         /* SDMA */
1764         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1765         for (i = 0; i < adev->sdma.num_instances; i++) {
1766                 query_fw.index = i;
1767                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1768                 if (ret)
1769                         return ret;
1770                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1771                            i, fw_info.feature, fw_info.ver);
1772         }
1773
1774         /* VCN */
1775         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1776         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1777         if (ret)
1778                 return ret;
1779         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1780                    fw_info.feature, fw_info.ver);
1781
1782         /* DMCU */
1783         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1784         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1785         if (ret)
1786                 return ret;
1787         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1788                    fw_info.feature, fw_info.ver);
1789
1790         /* DMCUB */
1791         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1792         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1793         if (ret)
1794                 return ret;
1795         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1796                    fw_info.feature, fw_info.ver);
1797
1798         /* TOC */
1799         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1800         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1801         if (ret)
1802                 return ret;
1803         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1804                    fw_info.feature, fw_info.ver);
1805
1806         /* CAP */
1807         if (adev->psp.cap_fw) {
1808                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1809                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1810                 if (ret)
1811                         return ret;
1812                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1813                                 fw_info.feature, fw_info.ver);
1814         }
1815
1816         /* MES_KIQ */
1817         query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1818         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1819         if (ret)
1820                 return ret;
1821         seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1822                    fw_info.feature, fw_info.ver);
1823
1824         /* MES */
1825         query_fw.fw_type = AMDGPU_INFO_FW_MES;
1826         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1827         if (ret)
1828                 return ret;
1829         seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1830                    fw_info.feature, fw_info.ver);
1831
1832         /* VPE */
1833         query_fw.fw_type = AMDGPU_INFO_FW_VPE;
1834         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1835         if (ret)
1836                 return ret;
1837         seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n",
1838                    fw_info.feature, fw_info.ver);
1839
1840         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
1841
1842         return 0;
1843 }
1844
1845 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1846
1847 #endif
1848
1849 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1850 {
1851 #if defined(CONFIG_DEBUG_FS)
1852         struct drm_minor *minor = adev_to_drm(adev)->primary;
1853         struct dentry *root = minor->debugfs_root;
1854
1855         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1856                             adev, &amdgpu_debugfs_firmware_info_fops);
1857
1858 #endif
1859 }