drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 static void amdgpu_runtime_pm_quirk(struct amdgpu_device *adev)
  47 {
  48         /*
  49          * Add below quirk on several sienna_cichlid cards to disable
  50          * runtime pm to fix EMI failures.
  51          */
  52         if (((adev->pdev->device == 0x73A1) && (adev->pdev->revision == 0x00)) ||
  53             ((adev->pdev->device == 0x73BF) && (adev->pdev->revision == 0xCF)))
  54                 adev->runpm = false;
  55 }
  56
  57 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  58 {
  59         struct amdgpu_gpu_instance *gpu_instance;
  60         int i;
  61
  62         mutex_lock(&mgpu_info.mutex);
  63
  64         for (i = 0; i < mgpu_info.num_gpu; i++) {
  65                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  66                 if (gpu_instance->adev == adev) {
  67                         mgpu_info.gpu_ins[i] =
  68                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  69                         mgpu_info.num_gpu--;
  70                         if (adev->flags & AMD_IS_APU)
  71                                 mgpu_info.num_apu--;
  72                         else
  73                                 mgpu_info.num_dgpu--;
  74                         break;
  75                 }
  76         }
  77
  78         mutex_unlock(&mgpu_info.mutex);
  79 }
  80
  81 /**
  82  * amdgpu_driver_unload_kms - Main unload function for KMS.
  83  *
  84  * @dev: drm dev pointer
  85  *
  86  * This is the main unload function for KMS (all asics).
  87  * Returns 0 on success.
  88  */
  89 void amdgpu_driver_unload_kms(struct drm_device *dev)
  90 {
  91         struct amdgpu_device *adev = drm_to_adev(dev);
  92
  93         if (adev == NULL)
  94                 return;
  95
  96         amdgpu_unregister_gpu_instance(adev);
  97
  98         if (adev->rmmio == NULL)
  99                 return;
 100
 101         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
 102                 DRM_WARN("smart shift update failed\n");
 103
 104         amdgpu_acpi_fini(adev);
 105         amdgpu_device_fini_hw(adev);
 106 }
 107
 108 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 109 {
 110         struct amdgpu_gpu_instance *gpu_instance;
 111
 112         mutex_lock(&mgpu_info.mutex);
 113
 114         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 115                 DRM_ERROR("Cannot register more gpu instance\n");
 116                 mutex_unlock(&mgpu_info.mutex);
 117                 return;
 118         }
 119
 120         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 121         gpu_instance->adev = adev;
 122         gpu_instance->mgpu_fan_enabled = 0;
 123
 124         mgpu_info.num_gpu++;
 125         if (adev->flags & AMD_IS_APU)
 126                 mgpu_info.num_apu++;
 127         else
 128                 mgpu_info.num_dgpu++;
 129
 130         mutex_unlock(&mgpu_info.mutex);
 131 }
 132
 133 /**
 134  * amdgpu_driver_load_kms - Main load function for KMS.
 135  *
 136  * @adev: pointer to struct amdgpu_device
 137  * @flags: device flags
 138  *
 139  * This is the main load function for KMS (all asics).
 140  * Returns 0 on success, error on failure.
 141  */
 142 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 143 {
 144         struct drm_device *dev;
 145         int r, acpi_status;
 146
 147         dev = adev_to_drm(adev);
 148
 149         /* amdgpu_device_init should report only fatal error
 150          * like memory allocation failure or iomapping failure,
 151          * or memory manager initialization failure, it must
 152          * properly initialize the GPU MC controller and permit
 153          * VRAM allocation
 154          */
 155         r = amdgpu_device_init(adev, flags);
 156         if (r) {
 157                 dev_err(dev->dev, "Fatal error during GPU init\n");
 158                 goto out;
 159         }
 160
 161         if (amdgpu_device_supports_px(dev) &&
 162             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
 163                 adev->runpm = true;
 164                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 165         } else if (amdgpu_device_supports_boco(dev) &&
 166                    (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 167                 adev->runpm = true;
 168                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 169         } else if (amdgpu_device_supports_baco(dev) &&
 170                    (amdgpu_runtime_pm != 0)) {
 171                 switch (adev->asic_type) {
 172                 case CHIP_VEGA20:
 173                 case CHIP_ARCTURUS:
 174                         /* enable runpm if runpm=1 */
 175                         if (amdgpu_runtime_pm > 0)
 176                                 adev->runpm = true;
 177                         break;
 178                 case CHIP_VEGA10:
 179                         /* turn runpm on if noretry=0 */
 180                         if (!adev->gmc.noretry)
 181                                 adev->runpm = true;
 182                         break;
 183                 default:
 184                         /* enable runpm on CI+ */
 185                         adev->runpm = true;
 186                         break;
 187                 }
 188                 /* XXX: disable runtime pm if we are the primary adapter
 189                  * to avoid displays being re-enabled after DPMS.
 190                  * This needs to be sorted out and fixed properly.
 191                  */
 192                 if (adev->is_fw_fb)
 193                         adev->runpm = false;
 194
 195                 amdgpu_runtime_pm_quirk(adev);
 196
 197                 if (adev->runpm)
 198                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 199         }
 200
 201         /* Call ACPI methods: require modeset init
 202          * but failure is not fatal
 203          */
 204
 205         acpi_status = amdgpu_acpi_init(adev);
 206         if (acpi_status)
 207                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 208
 209         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 210                 DRM_WARN("smart shift update failed\n");
 211
 212 out:
 213         if (r)
 214                 amdgpu_driver_unload_kms(dev);
 215
 216         return r;
 217 }
 218
 219 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 220                                 struct drm_amdgpu_query_fw *query_fw,
 221                                 struct amdgpu_device *adev)
 222 {
 223         switch (query_fw->fw_type) {
 224         case AMDGPU_INFO_FW_VCE:
 225                 fw_info->ver = adev->vce.fw_version;
 226                 fw_info->feature = adev->vce.fb_version;
 227                 break;
 228         case AMDGPU_INFO_FW_UVD:
 229                 fw_info->ver = adev->uvd.fw_version;
 230                 fw_info->feature = 0;
 231                 break;
 232         case AMDGPU_INFO_FW_VCN:
 233                 fw_info->ver = adev->vcn.fw_version;
 234                 fw_info->feature = 0;
 235                 break;
 236         case AMDGPU_INFO_FW_GMC:
 237                 fw_info->ver = adev->gmc.fw_version;
 238                 fw_info->feature = 0;
 239                 break;
 240         case AMDGPU_INFO_FW_GFX_ME:
 241                 fw_info->ver = adev->gfx.me_fw_version;
 242                 fw_info->feature = adev->gfx.me_feature_version;
 243                 break;
 244         case AMDGPU_INFO_FW_GFX_PFP:
 245                 fw_info->ver = adev->gfx.pfp_fw_version;
 246                 fw_info->feature = adev->gfx.pfp_feature_version;
 247                 break;
 248         case AMDGPU_INFO_FW_GFX_CE:
 249                 fw_info->ver = adev->gfx.ce_fw_version;
 250                 fw_info->feature = adev->gfx.ce_feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_GFX_RLC:
 253                 fw_info->ver = adev->gfx.rlc_fw_version;
 254                 fw_info->feature = adev->gfx.rlc_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 257                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 258                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 261                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 262                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 263                 break;
 264         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 265                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 266                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 267                 break;
 268         case AMDGPU_INFO_FW_GFX_MEC:
 269                 if (query_fw->index == 0) {
 270                         fw_info->ver = adev->gfx.mec_fw_version;
 271                         fw_info->feature = adev->gfx.mec_feature_version;
 272                 } else if (query_fw->index == 1) {
 273                         fw_info->ver = adev->gfx.mec2_fw_version;
 274                         fw_info->feature = adev->gfx.mec2_feature_version;
 275                 } else
 276                         return -EINVAL;
 277                 break;
 278         case AMDGPU_INFO_FW_SMC:
 279                 fw_info->ver = adev->pm.fw_version;
 280                 fw_info->feature = 0;
 281                 break;
 282         case AMDGPU_INFO_FW_TA:
 283                 switch (query_fw->index) {
 284                 case TA_FW_TYPE_PSP_XGMI:
 285                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 286                         fw_info->feature = adev->psp.xgmi_context.context
 287                                                    .bin_desc.feature_version;
 288                         break;
 289                 case TA_FW_TYPE_PSP_RAS:
 290                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 291                         fw_info->feature = adev->psp.ras_context.context
 292                                                    .bin_desc.feature_version;
 293                         break;
 294                 case TA_FW_TYPE_PSP_HDCP:
 295                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 296                         fw_info->feature = adev->psp.hdcp_context.context
 297                                                    .bin_desc.feature_version;
 298                         break;
 299                 case TA_FW_TYPE_PSP_DTM:
 300                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 301                         fw_info->feature = adev->psp.dtm_context.context
 302                                                    .bin_desc.feature_version;
 303                         break;
 304                 case TA_FW_TYPE_PSP_RAP:
 305                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 306                         fw_info->feature = adev->psp.rap_context.context
 307                                                    .bin_desc.feature_version;
 308                         break;
 309                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 310                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 311                         fw_info->feature =
 312                                 adev->psp.securedisplay_context.context.bin_desc
 313                                         .feature_version;
 314                         break;
 315                 default:
 316                         return -EINVAL;
 317                 }
 318                 break;
 319         case AMDGPU_INFO_FW_SDMA:
 320                 if (query_fw->index >= adev->sdma.num_instances)
 321                         return -EINVAL;
 322                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 323                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 324                 break;
 325         case AMDGPU_INFO_FW_SOS:
 326                 fw_info->ver = adev->psp.sos.fw_version;
 327                 fw_info->feature = adev->psp.sos.feature_version;
 328                 break;
 329         case AMDGPU_INFO_FW_ASD:
 330                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 331                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 332                 break;
 333         case AMDGPU_INFO_FW_DMCU:
 334                 fw_info->ver = adev->dm.dmcu_fw_version;
 335                 fw_info->feature = 0;
 336                 break;
 337         case AMDGPU_INFO_FW_DMCUB:
 338                 fw_info->ver = adev->dm.dmcub_fw_version;
 339                 fw_info->feature = 0;
 340                 break;
 341         case AMDGPU_INFO_FW_TOC:
 342                 fw_info->ver = adev->psp.toc.fw_version;
 343                 fw_info->feature = adev->psp.toc.feature_version;
 344                 break;
 345         case AMDGPU_INFO_FW_CAP:
 346                 fw_info->ver = adev->psp.cap_fw_version;
 347                 fw_info->feature = adev->psp.cap_feature_version;
 348                 break;
 349         default:
 350                 return -EINVAL;
 351         }
 352         return 0;
 353 }
 354
 355 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 356                              struct drm_amdgpu_info *info,
 357                              struct drm_amdgpu_info_hw_ip *result)
 358 {
 359         uint32_t ib_start_alignment = 0;
 360         uint32_t ib_size_alignment = 0;
 361         enum amd_ip_block_type type;
 362         unsigned int num_rings = 0;
 363         unsigned int i, j;
 364
 365         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 366                 return -EINVAL;
 367
 368         switch (info->query_hw_ip.type) {
 369         case AMDGPU_HW_IP_GFX:
 370                 type = AMD_IP_BLOCK_TYPE_GFX;
 371                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 372                         if (adev->gfx.gfx_ring[i].sched.ready)
 373                                 ++num_rings;
 374                 ib_start_alignment = 32;
 375                 ib_size_alignment = 32;
 376                 break;
 377         case AMDGPU_HW_IP_COMPUTE:
 378                 type = AMD_IP_BLOCK_TYPE_GFX;
 379                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 380                         if (adev->gfx.compute_ring[i].sched.ready)
 381                                 ++num_rings;
 382                 ib_start_alignment = 32;
 383                 ib_size_alignment = 32;
 384                 break;
 385         case AMDGPU_HW_IP_DMA:
 386                 type = AMD_IP_BLOCK_TYPE_SDMA;
 387                 for (i = 0; i < adev->sdma.num_instances; i++)
 388                         if (adev->sdma.instance[i].ring.sched.ready)
 389                                 ++num_rings;
 390                 ib_start_alignment = 256;
 391                 ib_size_alignment = 4;
 392                 break;
 393         case AMDGPU_HW_IP_UVD:
 394                 type = AMD_IP_BLOCK_TYPE_UVD;
 395                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 396                         if (adev->uvd.harvest_config & (1 << i))
 397                                 continue;
 398
 399                         if (adev->uvd.inst[i].ring.sched.ready)
 400                                 ++num_rings;
 401                 }
 402                 ib_start_alignment = 64;
 403                 ib_size_alignment = 64;
 404                 break;
 405         case AMDGPU_HW_IP_VCE:
 406                 type = AMD_IP_BLOCK_TYPE_VCE;
 407                 for (i = 0; i < adev->vce.num_rings; i++)
 408                         if (adev->vce.ring[i].sched.ready)
 409                                 ++num_rings;
 410                 ib_start_alignment = 4;
 411                 ib_size_alignment = 1;
 412                 break;
 413         case AMDGPU_HW_IP_UVD_ENC:
 414                 type = AMD_IP_BLOCK_TYPE_UVD;
 415                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 416                         if (adev->uvd.harvest_config & (1 << i))
 417                                 continue;
 418
 419                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 420                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 421                                         ++num_rings;
 422                 }
 423                 ib_start_alignment = 64;
 424                 ib_size_alignment = 64;
 425                 break;
 426         case AMDGPU_HW_IP_VCN_DEC:
 427                 type = AMD_IP_BLOCK_TYPE_VCN;
 428                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 429                         if (adev->uvd.harvest_config & (1 << i))
 430                                 continue;
 431
 432                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 433                                 ++num_rings;
 434                 }
 435                 ib_start_alignment = 16;
 436                 ib_size_alignment = 16;
 437                 break;
 438         case AMDGPU_HW_IP_VCN_ENC:
 439                 type = AMD_IP_BLOCK_TYPE_VCN;
 440                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 441                         if (adev->uvd.harvest_config & (1 << i))
 442                                 continue;
 443
 444                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 445                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 446                                         ++num_rings;
 447                 }
 448                 ib_start_alignment = 64;
 449                 ib_size_alignment = 1;
 450                 break;
 451         case AMDGPU_HW_IP_VCN_JPEG:
 452                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 453                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 454
 455                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 456                         if (adev->jpeg.harvest_config & (1 << i))
 457                                 continue;
 458
 459                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 460                                 ++num_rings;
 461                 }
 462                 ib_start_alignment = 16;
 463                 ib_size_alignment = 16;
 464                 break;
 465         default:
 466                 return -EINVAL;
 467         }
 468
 469         for (i = 0; i < adev->num_ip_blocks; i++)
 470                 if (adev->ip_blocks[i].version->type == type &&
 471                     adev->ip_blocks[i].status.valid)
 472                         break;
 473
 474         if (i == adev->num_ip_blocks)
 475                 return 0;
 476
 477         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 478                         num_rings);
 479
 480         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 481         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 482         result->capabilities_flags = 0;
 483         result->available_rings = (1 << num_rings) - 1;
 484         result->ib_start_alignment = ib_start_alignment;
 485         result->ib_size_alignment = ib_size_alignment;
 486         return 0;
 487 }
 488
 489 /*
 490  * Userspace get information ioctl
 491  */
 492 /**
 493  * amdgpu_info_ioctl - answer a device specific request.
 494  *
 495  * @dev: drm device pointer
 496  * @data: request object
 497  * @filp: drm filp
 498  *
 499  * This function is used to pass device specific parameters to the userspace
 500  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 501  * etc. (all asics).
 502  * Returns 0 on success, -EINVAL on failure.
 503  */
 504 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 505 {
 506         struct amdgpu_device *adev = drm_to_adev(dev);
 507         struct drm_amdgpu_info *info = data;
 508         struct amdgpu_mode_info *minfo = &adev->mode_info;
 509         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 510         uint32_t size = info->return_size;
 511         struct drm_crtc *crtc;
 512         uint32_t ui32 = 0;
 513         uint64_t ui64 = 0;
 514         int i, found;
 515         int ui32_size = sizeof(ui32);
 516
 517         if (!info->return_size || !info->return_pointer)
 518                 return -EINVAL;
 519
 520         switch (info->query) {
 521         case AMDGPU_INFO_ACCEL_WORKING:
 522                 ui32 = adev->accel_working;
 523                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 524         case AMDGPU_INFO_CRTC_FROM_ID:
 525                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 526                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 527                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 528                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 529                                 ui32 = amdgpu_crtc->crtc_id;
 530                                 found = 1;
 531                                 break;
 532                         }
 533                 }
 534                 if (!found) {
 535                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 536                         return -EINVAL;
 537                 }
 538                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 539         case AMDGPU_INFO_HW_IP_INFO: {
 540                 struct drm_amdgpu_info_hw_ip ip = {};
 541                 int ret;
 542
 543                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 544                 if (ret)
 545                         return ret;
 546
 547                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 548                 return ret ? -EFAULT : 0;
 549         }
 550         case AMDGPU_INFO_HW_IP_COUNT: {
 551                 enum amd_ip_block_type type;
 552                 uint32_t count = 0;
 553
 554                 switch (info->query_hw_ip.type) {
 555                 case AMDGPU_HW_IP_GFX:
 556                         type = AMD_IP_BLOCK_TYPE_GFX;
 557                         break;
 558                 case AMDGPU_HW_IP_COMPUTE:
 559                         type = AMD_IP_BLOCK_TYPE_GFX;
 560                         break;
 561                 case AMDGPU_HW_IP_DMA:
 562                         type = AMD_IP_BLOCK_TYPE_SDMA;
 563                         break;
 564                 case AMDGPU_HW_IP_UVD:
 565                         type = AMD_IP_BLOCK_TYPE_UVD;
 566                         break;
 567                 case AMDGPU_HW_IP_VCE:
 568                         type = AMD_IP_BLOCK_TYPE_VCE;
 569                         break;
 570                 case AMDGPU_HW_IP_UVD_ENC:
 571                         type = AMD_IP_BLOCK_TYPE_UVD;
 572                         break;
 573                 case AMDGPU_HW_IP_VCN_DEC:
 574                 case AMDGPU_HW_IP_VCN_ENC:
 575                         type = AMD_IP_BLOCK_TYPE_VCN;
 576                         break;
 577                 case AMDGPU_HW_IP_VCN_JPEG:
 578                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 579                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 580                         break;
 581                 default:
 582                         return -EINVAL;
 583                 }
 584
 585                 for (i = 0; i < adev->num_ip_blocks; i++)
 586                         if (adev->ip_blocks[i].version->type == type &&
 587                             adev->ip_blocks[i].status.valid &&
 588                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 589                                 count++;
 590
 591                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 592         }
 593         case AMDGPU_INFO_TIMESTAMP:
 594                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 595                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 596         case AMDGPU_INFO_FW_VERSION: {
 597                 struct drm_amdgpu_info_firmware fw_info;
 598                 int ret;
 599
 600                 /* We only support one instance of each IP block right now. */
 601                 if (info->query_fw.ip_instance != 0)
 602                         return -EINVAL;
 603
 604                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 605                 if (ret)
 606                         return ret;
 607
 608                 return copy_to_user(out, &fw_info,
 609                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 610         }
 611         case AMDGPU_INFO_NUM_BYTES_MOVED:
 612                 ui64 = atomic64_read(&adev->num_bytes_moved);
 613                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 614         case AMDGPU_INFO_NUM_EVICTIONS:
 615                 ui64 = atomic64_read(&adev->num_evictions);
 616                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 617         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 618                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 619                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 620         case AMDGPU_INFO_VRAM_USAGE:
 621                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 622                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 623         case AMDGPU_INFO_VIS_VRAM_USAGE:
 624                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 625                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 626         case AMDGPU_INFO_GTT_USAGE:
 627                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 628                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 629         case AMDGPU_INFO_GDS_CONFIG: {
 630                 struct drm_amdgpu_info_gds gds_info;
 631
 632                 memset(&gds_info, 0, sizeof(gds_info));
 633                 gds_info.compute_partition_size = adev->gds.gds_size;
 634                 gds_info.gds_total_size = adev->gds.gds_size;
 635                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 636                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 637                 return copy_to_user(out, &gds_info,
 638                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 639         }
 640         case AMDGPU_INFO_VRAM_GTT: {
 641                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 642
 643                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 644                         atomic64_read(&adev->vram_pin_size) -
 645                         AMDGPU_VM_RESERVED_VRAM;
 646                 vram_gtt.vram_cpu_accessible_size =
 647                         min(adev->gmc.visible_vram_size -
 648                             atomic64_read(&adev->visible_pin_size),
 649                             vram_gtt.vram_size);
 650                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 651                 vram_gtt.gtt_size *= PAGE_SIZE;
 652                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 653                 return copy_to_user(out, &vram_gtt,
 654                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 655         }
 656         case AMDGPU_INFO_MEMORY: {
 657                 struct drm_amdgpu_memory_info mem;
 658                 struct ttm_resource_manager *gtt_man =
 659                         &adev->mman.gtt_mgr.manager;
 660                 struct ttm_resource_manager *vram_man =
 661                         &adev->mman.vram_mgr.manager;
 662
 663                 memset(&mem, 0, sizeof(mem));
 664                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 665                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 666                         atomic64_read(&adev->vram_pin_size) -
 667                         AMDGPU_VM_RESERVED_VRAM;
 668                 mem.vram.heap_usage =
 669                         ttm_resource_manager_usage(vram_man);
 670                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 671
 672                 mem.cpu_accessible_vram.total_heap_size =
 673                         adev->gmc.visible_vram_size;
 674                 mem.cpu_accessible_vram.usable_heap_size =
 675                         min(adev->gmc.visible_vram_size -
 676                             atomic64_read(&adev->visible_pin_size),
 677                             mem.vram.usable_heap_size);
 678                 mem.cpu_accessible_vram.heap_usage =
 679                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 680                 mem.cpu_accessible_vram.max_allocation =
 681                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 682
 683                 mem.gtt.total_heap_size = gtt_man->size;
 684                 mem.gtt.total_heap_size *= PAGE_SIZE;
 685                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 686                         atomic64_read(&adev->gart_pin_size);
 687                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 688                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 689
 690                 return copy_to_user(out, &mem,
 691                                     min((size_t)size, sizeof(mem)))
 692                                     ? -EFAULT : 0;
 693         }
 694         case AMDGPU_INFO_READ_MMR_REG: {
 695                 unsigned n, alloc_size;
 696                 uint32_t *regs;
 697                 unsigned se_num = (info->read_mmr_reg.instance >>
 698                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 699                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 700                 unsigned sh_num = (info->read_mmr_reg.instance >>
 701                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 702                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 703
 704                 /* set full masks if the userspace set all bits
 705                  * in the bitfields */
 706                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 707                         se_num = 0xffffffff;
 708                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 709                         return -EINVAL;
 710                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 711                         sh_num = 0xffffffff;
 712                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 713                         return -EINVAL;
 714
 715                 if (info->read_mmr_reg.count > 128)
 716                         return -EINVAL;
 717
 718                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 719                 if (!regs)
 720                         return -ENOMEM;
 721                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 722
 723                 amdgpu_gfx_off_ctrl(adev, false);
 724                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 725                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 726                                                       info->read_mmr_reg.dword_offset + i,
 727                                                       &regs[i])) {
 728                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 729                                               info->read_mmr_reg.dword_offset + i);
 730                                 kfree(regs);
 731                                 amdgpu_gfx_off_ctrl(adev, true);
 732                                 return -EFAULT;
 733                         }
 734                 }
 735                 amdgpu_gfx_off_ctrl(adev, true);
 736                 n = copy_to_user(out, regs, min(size, alloc_size));
 737                 kfree(regs);
 738                 return n ? -EFAULT : 0;
 739         }
 740         case AMDGPU_INFO_DEV_INFO: {
 741                 struct drm_amdgpu_info_device *dev_info;
 742                 uint64_t vm_size;
 743                 int ret;
 744
 745                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 746                 if (!dev_info)
 747                         return -ENOMEM;
 748
 749                 dev_info->device_id = adev->pdev->device;
 750                 dev_info->chip_rev = adev->rev_id;
 751                 dev_info->external_rev = adev->external_rev_id;
 752                 dev_info->pci_rev = adev->pdev->revision;
 753                 dev_info->family = adev->family;
 754                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 755                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 756                 /* return all clocks in KHz */
 757                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 758                 if (adev->pm.dpm_enabled) {
 759                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 760                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 761                 } else {
 762                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 763                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 764                 }
 765                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 766                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 767                         adev->gfx.config.max_shader_engines;
 768                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 769                 dev_info->_pad = 0;
 770                 dev_info->ids_flags = 0;
 771                 if (adev->flags & AMD_IS_APU)
 772                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 773                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 774                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 775                 if (amdgpu_is_tmz(adev))
 776                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 777
 778                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 779                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 780
 781                 /* Older VCE FW versions are buggy and can handle only 40bits */
 782                 if (adev->vce.fw_version &&
 783                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 784                         vm_size = min(vm_size, 1ULL << 40);
 785
 786                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 787                 dev_info->virtual_address_max =
 788                         min(vm_size, AMDGPU_GMC_HOLE_START);
 789
 790                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 791                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 792                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 793                 }
 794                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 795                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 796                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 797                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 798                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 799                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 800                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 801                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 802                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 803                        sizeof(adev->gfx.cu_info.bitmap));
 804                 dev_info->vram_type = adev->gmc.vram_type;
 805                 dev_info->vram_bit_width = adev->gmc.vram_width;
 806                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 807                 dev_info->gc_double_offchip_lds_buf =
 808                         adev->gfx.config.double_offchip_lds_buf;
 809                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 810                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 811                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 812                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 813                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 814                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 815                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 816
 817                 if (adev->family >= AMDGPU_FAMILY_NV)
 818                         dev_info->pa_sc_tile_steering_override =
 819                                 adev->gfx.config.pa_sc_tile_steering_override;
 820
 821                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 822
 823                 ret = copy_to_user(out, dev_info,
 824                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 825                 kfree(dev_info);
 826                 return ret;
 827         }
 828         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 829                 unsigned i;
 830                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 831                 struct amd_vce_state *vce_state;
 832
 833                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 834                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 835                         if (vce_state) {
 836                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 837                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 838                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 839                                 vce_clk_table.num_valid_entries++;
 840                         }
 841                 }
 842
 843                 return copy_to_user(out, &vce_clk_table,
 844                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 845         }
 846         case AMDGPU_INFO_VBIOS: {
 847                 uint32_t bios_size = adev->bios_size;
 848
 849                 switch (info->vbios_info.type) {
 850                 case AMDGPU_INFO_VBIOS_SIZE:
 851                         return copy_to_user(out, &bios_size,
 852                                         min((size_t)size, sizeof(bios_size)))
 853                                         ? -EFAULT : 0;
 854                 case AMDGPU_INFO_VBIOS_IMAGE: {
 855                         uint8_t *bios;
 856                         uint32_t bios_offset = info->vbios_info.offset;
 857
 858                         if (bios_offset >= bios_size)
 859                                 return -EINVAL;
 860
 861                         bios = adev->bios + bios_offset;
 862                         return copy_to_user(out, bios,
 863                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 864                                         ? -EFAULT : 0;
 865                 }
 866                 case AMDGPU_INFO_VBIOS_INFO: {
 867                         struct drm_amdgpu_info_vbios vbios_info = {};
 868                         struct atom_context *atom_context;
 869
 870                         atom_context = adev->mode_info.atom_context;
 871                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 872                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 873                         vbios_info.version = atom_context->version;
 874                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 875                                                 sizeof(atom_context->vbios_ver_str));
 876                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 877
 878                         return copy_to_user(out, &vbios_info,
 879                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 880                 }
 881                 default:
 882                         DRM_DEBUG_KMS("Invalid request %d\n",
 883                                         info->vbios_info.type);
 884                         return -EINVAL;
 885                 }
 886         }
 887         case AMDGPU_INFO_NUM_HANDLES: {
 888                 struct drm_amdgpu_info_num_handles handle;
 889
 890                 switch (info->query_hw_ip.type) {
 891                 case AMDGPU_HW_IP_UVD:
 892                         /* Starting Polaris, we support unlimited UVD handles */
 893                         if (adev->asic_type < CHIP_POLARIS10) {
 894                                 handle.uvd_max_handles = adev->uvd.max_handles;
 895                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 896
 897                                 return copy_to_user(out, &handle,
 898                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 899                         } else {
 900                                 return -ENODATA;
 901                         }
 902
 903                         break;
 904                 default:
 905                         return -EINVAL;
 906                 }
 907         }
 908         case AMDGPU_INFO_SENSOR: {
 909                 if (!adev->pm.dpm_enabled)
 910                         return -ENOENT;
 911
 912                 switch (info->sensor_info.type) {
 913                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 914                         /* get sclk in Mhz */
 915                         if (amdgpu_dpm_read_sensor(adev,
 916                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 917                                                    (void *)&ui32, &ui32_size)) {
 918                                 return -EINVAL;
 919                         }
 920                         ui32 /= 100;
 921                         break;
 922                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 923                         /* get mclk in Mhz */
 924                         if (amdgpu_dpm_read_sensor(adev,
 925                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 926                                                    (void *)&ui32, &ui32_size)) {
 927                                 return -EINVAL;
 928                         }
 929                         ui32 /= 100;
 930                         break;
 931                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 932                         /* get temperature in millidegrees C */
 933                         if (amdgpu_dpm_read_sensor(adev,
 934                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 935                                                    (void *)&ui32, &ui32_size)) {
 936                                 return -EINVAL;
 937                         }
 938                         break;
 939                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 940                         /* get GPU load */
 941                         if (amdgpu_dpm_read_sensor(adev,
 942                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 943                                                    (void *)&ui32, &ui32_size)) {
 944                                 return -EINVAL;
 945                         }
 946                         break;
 947                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 948                         /* get average GPU power */
 949                         if (amdgpu_dpm_read_sensor(adev,
 950                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 951                                                    (void *)&ui32, &ui32_size)) {
 952                                 return -EINVAL;
 953                         }
 954                         ui32 >>= 8;
 955                         break;
 956                 case AMDGPU_INFO_SENSOR_VDDNB:
 957                         /* get VDDNB in millivolts */
 958                         if (amdgpu_dpm_read_sensor(adev,
 959                                                    AMDGPU_PP_SENSOR_VDDNB,
 960                                                    (void *)&ui32, &ui32_size)) {
 961                                 return -EINVAL;
 962                         }
 963                         break;
 964                 case AMDGPU_INFO_SENSOR_VDDGFX:
 965                         /* get VDDGFX in millivolts */
 966                         if (amdgpu_dpm_read_sensor(adev,
 967                                                    AMDGPU_PP_SENSOR_VDDGFX,
 968                                                    (void *)&ui32, &ui32_size)) {
 969                                 return -EINVAL;
 970                         }
 971                         break;
 972                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 973                         /* get stable pstate sclk in Mhz */
 974                         if (amdgpu_dpm_read_sensor(adev,
 975                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 976                                                    (void *)&ui32, &ui32_size)) {
 977                                 return -EINVAL;
 978                         }
 979                         ui32 /= 100;
 980                         break;
 981                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 982                         /* get stable pstate mclk in Mhz */
 983                         if (amdgpu_dpm_read_sensor(adev,
 984                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 985                                                    (void *)&ui32, &ui32_size)) {
 986                                 return -EINVAL;
 987                         }
 988                         ui32 /= 100;
 989                         break;
 990                 default:
 991                         DRM_DEBUG_KMS("Invalid request %d\n",
 992                                       info->sensor_info.type);
 993                         return -EINVAL;
 994                 }
 995                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 996         }
 997         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 998                 ui32 = atomic_read(&adev->vram_lost_counter);
 999                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1000         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1001                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1002                 uint64_t ras_mask;
1003
1004                 if (!ras)
1005                         return -EINVAL;
1006                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1007
1008                 return copy_to_user(out, &ras_mask,
1009                                 min_t(u64, size, sizeof(ras_mask))) ?
1010                         -EFAULT : 0;
1011         }
1012         case AMDGPU_INFO_VIDEO_CAPS: {
1013                 const struct amdgpu_video_codecs *codecs;
1014                 struct drm_amdgpu_info_video_caps *caps;
1015                 int r;
1016
1017                 switch (info->video_cap.type) {
1018                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1019                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1020                         if (r)
1021                                 return -EINVAL;
1022                         break;
1023                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1024                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1025                         if (r)
1026                                 return -EINVAL;
1027                         break;
1028                 default:
1029                         DRM_DEBUG_KMS("Invalid request %d\n",
1030                                       info->video_cap.type);
1031                         return -EINVAL;
1032                 }
1033
1034                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1035                 if (!caps)
1036                         return -ENOMEM;
1037
1038                 for (i = 0; i < codecs->codec_count; i++) {
1039                         int idx = codecs->codec_array[i].codec_type;
1040
1041                         switch (idx) {
1042                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1043                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1044                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1045                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1046                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1047                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1048                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1049                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1050                                 caps->codec_info[idx].valid = 1;
1051                                 caps->codec_info[idx].max_width =
1052                                         codecs->codec_array[i].max_width;
1053                                 caps->codec_info[idx].max_height =
1054                                         codecs->codec_array[i].max_height;
1055                                 caps->codec_info[idx].max_pixels_per_frame =
1056                                         codecs->codec_array[i].max_pixels_per_frame;
1057                                 caps->codec_info[idx].max_level =
1058                                         codecs->codec_array[i].max_level;
1059                                 break;
1060                         default:
1061                                 break;
1062                         }
1063                 }
1064                 r = copy_to_user(out, caps,
1065                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1066                 kfree(caps);
1067                 return r;
1068         }
1069         default:
1070                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1071                 return -EINVAL;
1072         }
1073         return 0;
1074 }
1075
1076
1077 /*
1078  * Outdated mess for old drm with Xorg being in charge (void function now).
1079  */
1080 /**
1081  * amdgpu_driver_lastclose_kms - drm callback for last close
1082  *
1083  * @dev: drm dev pointer
1084  *
1085  * Switch vga_switcheroo state after last close (all asics).
1086  */
1087 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1088 {
1089         drm_fb_helper_lastclose(dev);
1090         vga_switcheroo_process_delayed_switch();
1091 }
1092
1093 /**
1094  * amdgpu_driver_open_kms - drm callback for open
1095  *
1096  * @dev: drm dev pointer
1097  * @file_priv: drm file
1098  *
1099  * On device open, init vm on cayman+ (all asics).
1100  * Returns 0 on success, error on failure.
1101  */
1102 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1103 {
1104         struct amdgpu_device *adev = drm_to_adev(dev);
1105         struct amdgpu_fpriv *fpriv;
1106         int r, pasid;
1107
1108         /* Ensure IB tests are run on ring */
1109         flush_delayed_work(&adev->delayed_init_work);
1110
1111
1112         if (amdgpu_ras_intr_triggered()) {
1113                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1114                 return -EHWPOISON;
1115         }
1116
1117         file_priv->driver_priv = NULL;
1118
1119         r = pm_runtime_get_sync(dev->dev);
1120         if (r < 0)
1121                 goto pm_put;
1122
1123         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1124         if (unlikely(!fpriv)) {
1125                 r = -ENOMEM;
1126                 goto out_suspend;
1127         }
1128
1129         pasid = amdgpu_pasid_alloc(16);
1130         if (pasid < 0) {
1131                 dev_warn(adev->dev, "No more PASIDs available!");
1132                 pasid = 0;
1133         }
1134
1135         r = amdgpu_vm_init(adev, &fpriv->vm);
1136         if (r)
1137                 goto error_pasid;
1138
1139         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1140         if (r)
1141                 goto error_vm;
1142
1143         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1144         if (!fpriv->prt_va) {
1145                 r = -ENOMEM;
1146                 goto error_vm;
1147         }
1148
1149         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1150                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1151
1152                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1153                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1154                 if (r)
1155                         goto error_vm;
1156         }
1157
1158         mutex_init(&fpriv->bo_list_lock);
1159         idr_init(&fpriv->bo_list_handles);
1160
1161         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1162
1163         file_priv->driver_priv = fpriv;
1164         goto out_suspend;
1165
1166 error_vm:
1167         amdgpu_vm_fini(adev, &fpriv->vm);
1168
1169 error_pasid:
1170         if (pasid) {
1171                 amdgpu_pasid_free(pasid);
1172                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1173         }
1174
1175         kfree(fpriv);
1176
1177 out_suspend:
1178         pm_runtime_mark_last_busy(dev->dev);
1179 pm_put:
1180         pm_runtime_put_autosuspend(dev->dev);
1181
1182         return r;
1183 }
1184
1185 /**
1186  * amdgpu_driver_postclose_kms - drm callback for post close
1187  *
1188  * @dev: drm dev pointer
1189  * @file_priv: drm file
1190  *
1191  * On device post close, tear down vm on cayman+ (all asics).
1192  */
1193 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1194                                  struct drm_file *file_priv)
1195 {
1196         struct amdgpu_device *adev = drm_to_adev(dev);
1197         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1198         struct amdgpu_bo_list *list;
1199         struct amdgpu_bo *pd;
1200         u32 pasid;
1201         int handle;
1202
1203         if (!fpriv)
1204                 return;
1205
1206         pm_runtime_get_sync(dev->dev);
1207
1208         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1209                 amdgpu_uvd_free_handles(adev, file_priv);
1210         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1211                 amdgpu_vce_free_handles(adev, file_priv);
1212
1213         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1214                 /* TODO: how to handle reserve failure */
1215                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1216                 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1217                 fpriv->csa_va = NULL;
1218                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1219         }
1220
1221         pasid = fpriv->vm.pasid;
1222         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1223         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1224                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1225                 amdgpu_bo_unreserve(pd);
1226         }
1227
1228         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1229         amdgpu_vm_fini(adev, &fpriv->vm);
1230
1231         if (pasid)
1232                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1233         amdgpu_bo_unref(&pd);
1234
1235         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1236                 amdgpu_bo_list_put(list);
1237
1238         idr_destroy(&fpriv->bo_list_handles);
1239         mutex_destroy(&fpriv->bo_list_lock);
1240
1241         kfree(fpriv);
1242         file_priv->driver_priv = NULL;
1243
1244         pm_runtime_mark_last_busy(dev->dev);
1245         pm_runtime_put_autosuspend(dev->dev);
1246 }
1247
1248
1249 void amdgpu_driver_release_kms(struct drm_device *dev)
1250 {
1251         struct amdgpu_device *adev = drm_to_adev(dev);
1252
1253         amdgpu_device_fini_sw(adev);
1254         pci_set_drvdata(adev->pdev, NULL);
1255 }
1256
1257 /*
1258  * VBlank related functions.
1259  */
1260 /**
1261  * amdgpu_get_vblank_counter_kms - get frame count
1262  *
1263  * @crtc: crtc to get the frame count from
1264  *
1265  * Gets the frame count on the requested crtc (all asics).
1266  * Returns frame count on success, -EINVAL on failure.
1267  */
1268 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1269 {
1270         struct drm_device *dev = crtc->dev;
1271         unsigned int pipe = crtc->index;
1272         struct amdgpu_device *adev = drm_to_adev(dev);
1273         int vpos, hpos, stat;
1274         u32 count;
1275
1276         if (pipe >= adev->mode_info.num_crtc) {
1277                 DRM_ERROR("Invalid crtc %u\n", pipe);
1278                 return -EINVAL;
1279         }
1280
1281         /* The hw increments its frame counter at start of vsync, not at start
1282          * of vblank, as is required by DRM core vblank counter handling.
1283          * Cook the hw count here to make it appear to the caller as if it
1284          * incremented at start of vblank. We measure distance to start of
1285          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1286          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1287          * result by 1 to give the proper appearance to caller.
1288          */
1289         if (adev->mode_info.crtcs[pipe]) {
1290                 /* Repeat readout if needed to provide stable result if
1291                  * we cross start of vsync during the queries.
1292                  */
1293                 do {
1294                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1295                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1296                          * vpos as distance to start of vblank, instead of
1297                          * regular vertical scanout pos.
1298                          */
1299                         stat = amdgpu_display_get_crtc_scanoutpos(
1300                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1301                                 &vpos, &hpos, NULL, NULL,
1302                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1303                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1304
1305                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1306                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1307                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1308                 } else {
1309                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1310                                       pipe, vpos);
1311
1312                         /* Bump counter if we are at >= leading edge of vblank,
1313                          * but before vsync where vpos would turn negative and
1314                          * the hw counter really increments.
1315                          */
1316                         if (vpos >= 0)
1317                                 count++;
1318                 }
1319         } else {
1320                 /* Fallback to use value as is. */
1321                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1322                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1323         }
1324
1325         return count;
1326 }
1327
1328 /**
1329  * amdgpu_enable_vblank_kms - enable vblank interrupt
1330  *
1331  * @crtc: crtc to enable vblank interrupt for
1332  *
1333  * Enable the interrupt on the requested crtc (all asics).
1334  * Returns 0 on success, -EINVAL on failure.
1335  */
1336 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1337 {
1338         struct drm_device *dev = crtc->dev;
1339         unsigned int pipe = crtc->index;
1340         struct amdgpu_device *adev = drm_to_adev(dev);
1341         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1342
1343         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1344 }
1345
1346 /**
1347  * amdgpu_disable_vblank_kms - disable vblank interrupt
1348  *
1349  * @crtc: crtc to disable vblank interrupt for
1350  *
1351  * Disable the interrupt on the requested crtc (all asics).
1352  */
1353 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1354 {
1355         struct drm_device *dev = crtc->dev;
1356         unsigned int pipe = crtc->index;
1357         struct amdgpu_device *adev = drm_to_adev(dev);
1358         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1359
1360         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1361 }
1362
1363 /*
1364  * Debugfs info
1365  */
1366 #if defined(CONFIG_DEBUG_FS)
1367
1368 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1369 {
1370         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1371         struct drm_amdgpu_info_firmware fw_info;
1372         struct drm_amdgpu_query_fw query_fw;
1373         struct atom_context *ctx = adev->mode_info.atom_context;
1374         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1375         int ret, i;
1376
1377         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1378 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1379                 TA_FW_NAME(XGMI),
1380                 TA_FW_NAME(RAS),
1381                 TA_FW_NAME(HDCP),
1382                 TA_FW_NAME(DTM),
1383                 TA_FW_NAME(RAP),
1384                 TA_FW_NAME(SECUREDISPLAY),
1385 #undef TA_FW_NAME
1386         };
1387
1388         /* VCE */
1389         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1390         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1391         if (ret)
1392                 return ret;
1393         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1394                    fw_info.feature, fw_info.ver);
1395
1396         /* UVD */
1397         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1398         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1399         if (ret)
1400                 return ret;
1401         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1402                    fw_info.feature, fw_info.ver);
1403
1404         /* GMC */
1405         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1406         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1407         if (ret)
1408                 return ret;
1409         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1410                    fw_info.feature, fw_info.ver);
1411
1412         /* ME */
1413         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1414         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1415         if (ret)
1416                 return ret;
1417         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1418                    fw_info.feature, fw_info.ver);
1419
1420         /* PFP */
1421         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1422         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1423         if (ret)
1424                 return ret;
1425         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1426                    fw_info.feature, fw_info.ver);
1427
1428         /* CE */
1429         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1430         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1431         if (ret)
1432                 return ret;
1433         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1434                    fw_info.feature, fw_info.ver);
1435
1436         /* RLC */
1437         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1438         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1439         if (ret)
1440                 return ret;
1441         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1442                    fw_info.feature, fw_info.ver);
1443
1444         /* RLC SAVE RESTORE LIST CNTL */
1445         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1446         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1447         if (ret)
1448                 return ret;
1449         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1450                    fw_info.feature, fw_info.ver);
1451
1452         /* RLC SAVE RESTORE LIST GPM MEM */
1453         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1454         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1455         if (ret)
1456                 return ret;
1457         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1458                    fw_info.feature, fw_info.ver);
1459
1460         /* RLC SAVE RESTORE LIST SRM MEM */
1461         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1462         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1463         if (ret)
1464                 return ret;
1465         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1466                    fw_info.feature, fw_info.ver);
1467
1468         /* MEC */
1469         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1470         query_fw.index = 0;
1471         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1472         if (ret)
1473                 return ret;
1474         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1475                    fw_info.feature, fw_info.ver);
1476
1477         /* MEC2 */
1478         if (adev->gfx.mec2_fw) {
1479                 query_fw.index = 1;
1480                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1481                 if (ret)
1482                         return ret;
1483                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1484                            fw_info.feature, fw_info.ver);
1485         }
1486
1487         /* PSP SOS */
1488         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1489         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1490         if (ret)
1491                 return ret;
1492         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1493                    fw_info.feature, fw_info.ver);
1494
1495
1496         /* PSP ASD */
1497         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1498         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1499         if (ret)
1500                 return ret;
1501         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1502                    fw_info.feature, fw_info.ver);
1503
1504         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1505         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1506                 query_fw.index = i;
1507                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1508                 if (ret)
1509                         continue;
1510
1511                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1512                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1513         }
1514
1515         /* SMC */
1516         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1517         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1518         if (ret)
1519                 return ret;
1520         smu_program = (fw_info.ver >> 24) & 0xff;
1521         smu_major = (fw_info.ver >> 16) & 0xff;
1522         smu_minor = (fw_info.ver >> 8) & 0xff;
1523         smu_debug = (fw_info.ver >> 0) & 0xff;
1524         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1525                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1526
1527         /* SDMA */
1528         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1529         for (i = 0; i < adev->sdma.num_instances; i++) {
1530                 query_fw.index = i;
1531                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1532                 if (ret)
1533                         return ret;
1534                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1535                            i, fw_info.feature, fw_info.ver);
1536         }
1537
1538         /* VCN */
1539         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1540         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1541         if (ret)
1542                 return ret;
1543         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1544                    fw_info.feature, fw_info.ver);
1545
1546         /* DMCU */
1547         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1548         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1549         if (ret)
1550                 return ret;
1551         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1552                    fw_info.feature, fw_info.ver);
1553
1554         /* DMCUB */
1555         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1556         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1557         if (ret)
1558                 return ret;
1559         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1560                    fw_info.feature, fw_info.ver);
1561
1562         /* TOC */
1563         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1564         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1565         if (ret)
1566                 return ret;
1567         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1568                    fw_info.feature, fw_info.ver);
1569
1570         /* CAP */
1571         if (adev->psp.cap_fw) {
1572                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1573                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1574                 if (ret)
1575                         return ret;
1576                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1577                                 fw_info.feature, fw_info.ver);
1578         }
1579
1580         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1581
1582         return 0;
1583 }
1584
1585 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1586
1587 #endif
1588
1589 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1590 {
1591 #if defined(CONFIG_DEBUG_FS)
1592         struct drm_minor *minor = adev_to_drm(adev)->primary;
1593         struct dentry *root = minor->debugfs_root;
1594
1595         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1596                             adev, &amdgpu_debugfs_firmware_info_fops);
1597
1598 #endif
1599 }