drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25
  26 #include <drm/drm_cache.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "gmc_v11_0.h"
  31 #include "umc_v8_10.h"
  32 #include "athub/athub_3_0_0_sh_mask.h"
  33 #include "athub/athub_3_0_0_offset.h"
  34 #include "dcn/dcn_3_2_0_offset.h"
  35 #include "dcn/dcn_3_2_0_sh_mask.h"
  36 #include "oss/osssys_6_0_0_offset.h"
  37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  38 #include "navi10_enum.h"
  39 #include "soc15.h"
  40 #include "soc15d.h"
  41 #include "soc15_common.h"
  42 #include "nbio_v4_3.h"
  43 #include "gfxhub_v3_0.h"
  44 #include "gfxhub_v3_0_3.h"
  45 #include "gfxhub_v11_5_0.h"
  46 #include "mmhub_v3_0.h"
  47 #include "mmhub_v3_0_1.h"
  48 #include "mmhub_v3_0_2.h"
  49 #include "mmhub_v3_3.h"
  50 #include "athub_v3_0.h"
  51
  52
  53 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev,
  54                                          struct amdgpu_irq_src *src,
  55                                          unsigned int type,
  56                                          enum amdgpu_interrupt_state state)
  57 {
  58         return 0;
  59 }
  60
  61 static int
  62 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  63                                    struct amdgpu_irq_src *src, unsigned int type,
  64                                    enum amdgpu_interrupt_state state)
  65 {
  66         switch (state) {
  67         case AMDGPU_IRQ_STATE_DISABLE:
  68                 /* MM HUB */
  69                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
  70                 /* GFX HUB */
  71                 /* This works because this interrupt is only
  72                  * enabled at init/resume and disabled in
  73                  * fini/suspend, so the overall state doesn't
  74                  * change over the course of suspend/resume.
  75                  */
  76                 if (!adev->in_s0ix)
  77                         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
  78                 break;
  79         case AMDGPU_IRQ_STATE_ENABLE:
  80                 /* MM HUB */
  81                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);
  82                 /* GFX HUB */
  83                 /* This works because this interrupt is only
  84                  * enabled at init/resume and disabled in
  85                  * fini/suspend, so the overall state doesn't
  86                  * change over the course of suspend/resume.
  87                  */
  88                 if (!adev->in_s0ix)
  89                         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);
  90                 break;
  91         default:
  92                 break;
  93         }
  94
  95         return 0;
  96 }
  97
  98 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,
  99                                        struct amdgpu_irq_src *source,
 100                                        struct amdgpu_iv_entry *entry)
 101 {
 102         uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ?
 103                                AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0);
 104         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index];
 105         uint32_t status = 0;
 106         u64 addr;
 107
 108         addr = (u64)entry->src_data[0] << 12;
 109         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 110
 111         if (!amdgpu_sriov_vf(adev)) {
 112                 /*
 113                  * Issue a dummy read to wait for the status register to
 114                  * be updated to avoid reading an incorrect value due to
 115                  * the new fast GRBM interface.
 116                  */
 117                 if (entry->vmid_src == AMDGPU_GFXHUB(0))
 118                         RREG32(hub->vm_l2_pro_fault_status);
 119
 120                 status = RREG32(hub->vm_l2_pro_fault_status);
 121                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 122         }
 123
 124         if (printk_ratelimit()) {
 125                 struct amdgpu_task_info task_info;
 126
 127                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 128                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 129
 130                 dev_err(adev->dev,
 131                         "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
 132                         entry->vmid_src ? "mmhub" : "gfxhub",
 133                         entry->src_id, entry->ring_id, entry->vmid,
 134                         entry->pasid, task_info.process_name, task_info.tgid,
 135                         task_info.task_name, task_info.pid);
 136                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 137                         addr, entry->client_id);
 138                 if (!amdgpu_sriov_vf(adev))
 139                         hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
 140         }
 141
 142         return 0;
 143 }
 144
 145 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = {
 146         .set = gmc_v11_0_vm_fault_interrupt_state,
 147         .process = gmc_v11_0_process_interrupt,
 148 };
 149
 150 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = {
 151         .set = gmc_v11_0_ecc_interrupt_state,
 152         .process = amdgpu_umc_process_ecc_irq,
 153 };
 154
 155 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 156 {
 157         adev->gmc.vm_fault.num_types = 1;
 158         adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;
 159
 160         if (!amdgpu_sriov_vf(adev)) {
 161                 adev->gmc.ecc_irq.num_types = 1;
 162                 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;
 163         }
 164 }
 165
 166 /**
 167  * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore
 168  *
 169  * @adev: amdgpu_device pointer
 170  * @vmhub: vmhub type
 171  *
 172  */
 173 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 174                                        uint32_t vmhub)
 175 {
 176         return ((vmhub == AMDGPU_MMHUB0(0)) &&
 177                 (!amdgpu_sriov_vf(adev)));
 178 }
 179
 180 static bool gmc_v11_0_get_vmid_pasid_mapping_info(
 181                                         struct amdgpu_device *adev,
 182                                         uint8_t vmid, uint16_t *p_pasid)
 183 {
 184         *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
 185
 186         return !!(*p_pasid);
 187 }
 188
 189 /**
 190  * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
 191  *
 192  * @adev: amdgpu_device pointer
 193  * @vmid: vm instance to flush
 194  * @vmhub: which hub to flush
 195  * @flush_type: the flush type
 196  *
 197  * Flush the TLB for the requested page table.
 198  */
 199 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 200                                         uint32_t vmhub, uint32_t flush_type)
 201 {
 202         bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub);
 203         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 204         u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 205         /* Use register 17 for GART */
 206         const unsigned int eng = 17;
 207         unsigned char hub_ip;
 208         u32 sem, req, ack;
 209         unsigned int i;
 210         u32 tmp;
 211
 212         if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron)
 213                 return;
 214
 215         sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
 216         req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 217         ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 218
 219         /* flush hdp cache */
 220         adev->hdp.funcs->flush_hdp(adev, NULL);
 221
 222         /* For SRIOV run time, driver shouldn't access the register through MMIO
 223          * Directly use kiq to do the vm invalidation instead
 224          */
 225         if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) &&
 226             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
 227                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 228                                 1 << vmid);
 229                 return;
 230         }
 231
 232         hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP;
 233
 234         spin_lock(&adev->gmc.invalidate_lock);
 235         /*
 236          * It may lose gpuvm invalidate acknowldege state across power-gating
 237          * off cycle, add semaphore acquire before invalidation and semaphore
 238          * release after invalidation to avoid entering power gated state
 239          * to WA the Issue
 240          */
 241
 242         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 243         if (use_semaphore) {
 244                 for (i = 0; i < adev->usec_timeout; i++) {
 245                         /* a read return value of 1 means semaphore acuqire */
 246                         tmp = RREG32_RLC_NO_KIQ(sem, hub_ip);
 247                         if (tmp & 0x1)
 248                                 break;
 249                         udelay(1);
 250                 }
 251
 252                 if (i >= adev->usec_timeout)
 253                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 254         }
 255
 256         WREG32_RLC_NO_KIQ(req, inv_req, hub_ip);
 257
 258         /* Wait for ACK with a delay.*/
 259         for (i = 0; i < adev->usec_timeout; i++) {
 260                 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip);
 261                 tmp &= 1 << vmid;
 262                 if (tmp)
 263                         break;
 264
 265                 udelay(1);
 266         }
 267
 268         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 269         if (use_semaphore)
 270                 WREG32_RLC_NO_KIQ(sem, 0, hub_ip);
 271
 272         /* Issue additional private vm invalidation to MMHUB */
 273         if ((vmhub != AMDGPU_GFXHUB(0)) &&
 274             (hub->vm_l2_bank_select_reserved_cid2) &&
 275                 !amdgpu_sriov_vf(adev)) {
 276                 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 277                 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */
 278                 inv_req |= (1 << 25);
 279                 /* Issue private invalidation */
 280                 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
 281                 /* Read back to ensure invalidation is done*/
 282                 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 283         }
 284
 285         spin_unlock(&adev->gmc.invalidate_lock);
 286
 287         if (i >= adev->usec_timeout)
 288                 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n");
 289 }
 290
 291 /**
 292  * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid
 293  *
 294  * @adev: amdgpu_device pointer
 295  * @pasid: pasid to be flush
 296  * @flush_type: the flush type
 297  * @all_hub: flush all hubs
 298  * @inst: is used to select which instance of KIQ to use for the invalidation
 299  *
 300  * Flush the TLB for the requested pasid.
 301  */
 302 static void gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 303                                           uint16_t pasid, uint32_t flush_type,
 304                                           bool all_hub, uint32_t inst)
 305 {
 306         uint16_t queried;
 307         int vmid, i;
 308
 309         for (vmid = 1; vmid < 16; vmid++) {
 310                 bool valid;
 311
 312                 valid = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid,
 313                                                               &queried);
 314                 if (!valid || queried == pasid)
 315                         continue;
 316
 317                 if (all_hub) {
 318                         for_each_set_bit(i, adev->vmhubs_mask,
 319                                          AMDGPU_MAX_VMHUBS)
 320                                 gmc_v11_0_flush_gpu_tlb(adev, vmid, i,
 321                                                         flush_type);
 322                 } else {
 323                         gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0),
 324                                                 flush_type);
 325                 }
 326         }
 327 }
 328
 329 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 330                                              unsigned int vmid, uint64_t pd_addr)
 331 {
 332         bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
 333         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
 334         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
 335         unsigned int eng = ring->vm_inv_eng;
 336
 337         /*
 338          * It may lose gpuvm invalidate acknowldege state across power-gating
 339          * off cycle, add semaphore acquire before invalidation and semaphore
 340          * release after invalidation to avoid entering power gated state
 341          * to WA the Issue
 342          */
 343
 344         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 345         if (use_semaphore)
 346                 /* a read return value of 1 means semaphore acuqire */
 347                 amdgpu_ring_emit_reg_wait(ring,
 348                                           hub->vm_inv_eng0_sem +
 349                                           hub->eng_distance * eng, 0x1, 0x1);
 350
 351         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 352                               (hub->ctx_addr_distance * vmid),
 353                               lower_32_bits(pd_addr));
 354
 355         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 356                               (hub->ctx_addr_distance * vmid),
 357                               upper_32_bits(pd_addr));
 358
 359         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 360                                             hub->eng_distance * eng,
 361                                             hub->vm_inv_eng0_ack +
 362                                             hub->eng_distance * eng,
 363                                             req, 1 << vmid);
 364
 365         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 366         if (use_semaphore)
 367                 /*
 368                  * add semaphore release after invalidation,
 369                  * write with 0 means semaphore release
 370                  */
 371                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 372                                       hub->eng_distance * eng, 0);
 373
 374         return pd_addr;
 375 }
 376
 377 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
 378                                          unsigned int pasid)
 379 {
 380         struct amdgpu_device *adev = ring->adev;
 381         uint32_t reg;
 382
 383         /* MES fw manages IH_VMID_x_LUT updating */
 384         if (ring->is_mes_queue)
 385                 return;
 386
 387         if (ring->vm_hub == AMDGPU_GFXHUB(0))
 388                 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
 389         else
 390                 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
 391
 392         amdgpu_ring_emit_wreg(ring, reg, pasid);
 393 }
 394
 395 /*
 396  * PTE format:
 397  * 63:59 reserved
 398  * 58:57 reserved
 399  * 56 F
 400  * 55 L
 401  * 54 reserved
 402  * 53:52 SW
 403  * 51 T
 404  * 50:48 mtype
 405  * 47:12 4k physical page base address
 406  * 11:7 fragment
 407  * 6 write
 408  * 5 read
 409  * 4 exe
 410  * 3 Z
 411  * 2 snooped
 412  * 1 system
 413  * 0 valid
 414  *
 415  * PDE format:
 416  * 63:59 block fragment size
 417  * 58:55 reserved
 418  * 54 P
 419  * 53:48 reserved
 420  * 47:6 physical base address of PD or PTE
 421  * 5:3 reserved
 422  * 2 C
 423  * 1 system
 424  * 0 valid
 425  */
 426
 427 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 428 {
 429         switch (flags) {
 430         case AMDGPU_VM_MTYPE_DEFAULT:
 431                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 432         case AMDGPU_VM_MTYPE_NC:
 433                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 434         case AMDGPU_VM_MTYPE_WC:
 435                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
 436         case AMDGPU_VM_MTYPE_CC:
 437                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
 438         case AMDGPU_VM_MTYPE_UC:
 439                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 440         default:
 441                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 442         }
 443 }
 444
 445 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,
 446                                  uint64_t *addr, uint64_t *flags)
 447 {
 448         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 449                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
 450         BUG_ON(*addr & 0xFFFF00000000003FULL);
 451
 452         if (!adev->gmc.translate_further)
 453                 return;
 454
 455         if (level == AMDGPU_VM_PDB1) {
 456                 /* Set the block fragment size */
 457                 if (!(*flags & AMDGPU_PDE_PTE))
 458                         *flags |= AMDGPU_PDE_BFS(0x9);
 459
 460         } else if (level == AMDGPU_VM_PDB0) {
 461                 if (*flags & AMDGPU_PDE_PTE)
 462                         *flags &= ~AMDGPU_PDE_PTE;
 463                 else
 464                         *flags |= AMDGPU_PTE_TF;
 465         }
 466 }
 467
 468 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
 469                                  struct amdgpu_bo_va_mapping *mapping,
 470                                  uint64_t *flags)
 471 {
 472         struct amdgpu_bo *bo = mapping->bo_va->base.bo;
 473
 474         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 475         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 476
 477         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
 478         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
 479
 480         *flags &= ~AMDGPU_PTE_NOALLOC;
 481         *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
 482
 483         if (mapping->flags & AMDGPU_PTE_PRT) {
 484                 *flags |= AMDGPU_PTE_PRT;
 485                 *flags |= AMDGPU_PTE_SNOOPED;
 486                 *flags |= AMDGPU_PTE_LOG;
 487                 *flags |= AMDGPU_PTE_SYSTEM;
 488                 *flags &= ~AMDGPU_PTE_VALID;
 489         }
 490
 491         if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
 492                                AMDGPU_GEM_CREATE_EXT_COHERENT |
 493                                AMDGPU_GEM_CREATE_UNCACHED))
 494                 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
 495                          AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 496 }
 497
 498 static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)
 499 {
 500         u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);
 501         unsigned int size;
 502
 503         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 504                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
 505         } else {
 506                 u32 viewport;
 507                 u32 pitch;
 508
 509                 viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 510                 pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);
 511                 size = (REG_GET_FIELD(viewport,
 512                                         HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 513                                 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
 514                                 4);
 515         }
 516
 517         return size;
 518 }
 519
 520 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
 521         .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb,
 522         .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid,
 523         .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb,
 524         .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping,
 525         .map_mtype = gmc_v11_0_map_mtype,
 526         .get_vm_pde = gmc_v11_0_get_vm_pde,
 527         .get_vm_pte = gmc_v11_0_get_vm_pte,
 528         .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size,
 529 };
 530
 531 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev)
 532 {
 533         adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;
 534 }
 535
 536 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
 537 {
 538         switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
 539         case IP_VERSION(8, 10, 0):
 540                 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;
 541                 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;
 542                 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
 543                 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;
 544                 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM;
 545                 if (adev->umc.node_inst_num == 4)
 546                         adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0];
 547                 else
 548                         adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0];
 549                 adev->umc.ras = &umc_v8_10_ras;
 550                 break;
 551         case IP_VERSION(8, 11, 0):
 552                 break;
 553         default:
 554                 break;
 555         }
 556 }
 557
 558
 559 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
 560 {
 561         switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
 562         case IP_VERSION(3, 0, 1):
 563                 adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
 564                 break;
 565         case IP_VERSION(3, 0, 2):
 566                 adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
 567                 break;
 568         case IP_VERSION(3, 3, 0):
 569                 adev->mmhub.funcs = &mmhub_v3_3_funcs;
 570                 break;
 571         default:
 572                 adev->mmhub.funcs = &mmhub_v3_0_funcs;
 573                 break;
 574         }
 575 }
 576
 577 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 578 {
 579         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 580         case IP_VERSION(11, 0, 3):
 581                 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs;
 582                 break;
 583         case IP_VERSION(11, 5, 0):
 584                 adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs;
 585                 break;
 586         default:
 587                 adev->gfxhub.funcs = &gfxhub_v3_0_funcs;
 588                 break;
 589         }
 590 }
 591
 592 static int gmc_v11_0_early_init(void *handle)
 593 {
 594         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 595
 596         gmc_v11_0_set_gfxhub_funcs(adev);
 597         gmc_v11_0_set_mmhub_funcs(adev);
 598         gmc_v11_0_set_gmc_funcs(adev);
 599         gmc_v11_0_set_irq_funcs(adev);
 600         gmc_v11_0_set_umc_funcs(adev);
 601
 602         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 603         adev->gmc.shared_aperture_end =
 604                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 605         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 606         adev->gmc.private_aperture_end =
 607                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 608         adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
 609
 610         return 0;
 611 }
 612
 613 static int gmc_v11_0_late_init(void *handle)
 614 {
 615         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 616         int r;
 617
 618         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 619         if (r)
 620                 return r;
 621
 622         r = amdgpu_gmc_ras_late_init(adev);
 623         if (r)
 624                 return r;
 625
 626         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 627 }
 628
 629 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev,
 630                                         struct amdgpu_gmc *mc)
 631 {
 632         u64 base = 0;
 633
 634         base = adev->mmhub.funcs->get_fb_location(adev);
 635
 636         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 637         amdgpu_gmc_gart_location(adev, mc);
 638         if (!amdgpu_sriov_vf(adev) ||
 639             (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)))
 640                 amdgpu_gmc_agp_location(adev, mc);
 641
 642         /* base offset of vram pages */
 643         if (amdgpu_sriov_vf(adev))
 644                 adev->vm_manager.vram_base_offset = 0;
 645         else
 646                 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
 647 }
 648
 649 /**
 650  * gmc_v11_0_mc_init - initialize the memory controller driver params
 651  *
 652  * @adev: amdgpu_device pointer
 653  *
 654  * Look up the amount of vram, vram width, and decide how to place
 655  * vram and gart within the GPU's physical address space.
 656  * Returns 0 for success.
 657  */
 658 static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
 659 {
 660         int r;
 661
 662         /* size in MB on si */
 663         adev->gmc.mc_vram_size =
 664                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 665         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 666
 667         if (!(adev->flags & AMD_IS_APU)) {
 668                 r = amdgpu_device_resize_fb_bar(adev);
 669                 if (r)
 670                         return r;
 671         }
 672         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 673         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 674
 675 #ifdef CONFIG_X86_64
 676         if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
 677                 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
 678                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 679         }
 680 #endif
 681         /* In case the PCI BAR is larger than the actual amount of vram */
 682         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 683         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 684                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 685
 686         /* set the gart size */
 687         if (amdgpu_gart_size == -1)
 688                 adev->gmc.gart_size = 512ULL << 20;
 689         else
 690                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 691
 692         gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
 693
 694         return 0;
 695 }
 696
 697 static int gmc_v11_0_gart_init(struct amdgpu_device *adev)
 698 {
 699         int r;
 700
 701         if (adev->gart.bo) {
 702                 WARN(1, "PCIE GART already initialized\n");
 703                 return 0;
 704         }
 705
 706         /* Initialize common gart structure */
 707         r = amdgpu_gart_init(adev);
 708         if (r)
 709                 return r;
 710
 711         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 712         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
 713                                  AMDGPU_PTE_EXECUTABLE;
 714
 715         return amdgpu_gart_table_vram_alloc(adev);
 716 }
 717
 718 static int gmc_v11_0_sw_init(void *handle)
 719 {
 720         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 721         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 722
 723         adev->mmhub.funcs->init(adev);
 724
 725         adev->gfxhub.funcs->init(adev);
 726
 727         spin_lock_init(&adev->gmc.invalidate_lock);
 728
 729         r = amdgpu_atomfirmware_get_vram_info(adev,
 730                                               &vram_width, &vram_type, &vram_vendor);
 731         adev->gmc.vram_width = vram_width;
 732
 733         adev->gmc.vram_type = vram_type;
 734         adev->gmc.vram_vendor = vram_vendor;
 735
 736         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 737         case IP_VERSION(11, 0, 0):
 738         case IP_VERSION(11, 0, 1):
 739         case IP_VERSION(11, 0, 2):
 740         case IP_VERSION(11, 0, 3):
 741         case IP_VERSION(11, 0, 4):
 742         case IP_VERSION(11, 5, 0):
 743                 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
 744                 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
 745                 /*
 746                  * To fulfill 4-level page support,
 747                  * vm size is 256TB (48bit), maximum size,
 748                  * block size 512 (9bit)
 749                  */
 750                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 751                 break;
 752         default:
 753                 break;
 754         }
 755
 756         /* This interrupt is VMC page fault.*/
 757         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC,
 758                               VMC_1_0__SRCID__VM_FAULT,
 759                               &adev->gmc.vm_fault);
 760
 761         if (r)
 762                 return r;
 763
 764         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
 765                               UTCL2_1_0__SRCID__FAULT,
 766                               &adev->gmc.vm_fault);
 767         if (r)
 768                 return r;
 769
 770         if (!amdgpu_sriov_vf(adev)) {
 771                 /* interrupt sent to DF. */
 772                 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
 773                                       &adev->gmc.ecc_irq);
 774                 if (r)
 775                         return r;
 776         }
 777
 778         /*
 779          * Set the internal MC address mask This is the max address of the GPU's
 780          * internal address space.
 781          */
 782         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 783
 784         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 785         if (r) {
 786                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 787                 return r;
 788         }
 789
 790         adev->need_swiotlb = drm_need_swiotlb(44);
 791
 792         r = gmc_v11_0_mc_init(adev);
 793         if (r)
 794                 return r;
 795
 796         amdgpu_gmc_get_vbios_allocations(adev);
 797
 798         /* Memory manager */
 799         r = amdgpu_bo_init(adev);
 800         if (r)
 801                 return r;
 802
 803         r = gmc_v11_0_gart_init(adev);
 804         if (r)
 805                 return r;
 806
 807         /*
 808          * number of VMs
 809          * VMID 0 is reserved for System
 810          * amdgpu graphics/compute will use VMIDs 1-7
 811          * amdkfd will use VMIDs 8-15
 812          */
 813         adev->vm_manager.first_kfd_vmid = 8;
 814
 815         amdgpu_vm_manager_init(adev);
 816
 817         r = amdgpu_gmc_ras_sw_init(adev);
 818         if (r)
 819                 return r;
 820
 821         return 0;
 822 }
 823
 824 /**
 825  * gmc_v11_0_gart_fini - vm fini callback
 826  *
 827  * @adev: amdgpu_device pointer
 828  *
 829  * Tears down the driver GART/VM setup (CIK).
 830  */
 831 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev)
 832 {
 833         amdgpu_gart_table_vram_free(adev);
 834 }
 835
 836 static int gmc_v11_0_sw_fini(void *handle)
 837 {
 838         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 839
 840         amdgpu_vm_manager_fini(adev);
 841         gmc_v11_0_gart_fini(adev);
 842         amdgpu_gem_force_release(adev);
 843         amdgpu_bo_fini(adev);
 844
 845         return 0;
 846 }
 847
 848 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev)
 849 {
 850         if (amdgpu_sriov_vf(adev)) {
 851                 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 852
 853                 WREG32(hub->vm_contexts_disable, 0);
 854                 return;
 855         }
 856 }
 857
 858 /**
 859  * gmc_v11_0_gart_enable - gart enable
 860  *
 861  * @adev: amdgpu_device pointer
 862  */
 863 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
 864 {
 865         int r;
 866         bool value;
 867
 868         if (adev->gart.bo == NULL) {
 869                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 870                 return -EINVAL;
 871         }
 872
 873         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 874
 875         r = adev->mmhub.funcs->gart_enable(adev);
 876         if (r)
 877                 return r;
 878
 879         /* Flush HDP after it is initialized */
 880         adev->hdp.funcs->flush_hdp(adev, NULL);
 881
 882         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
 883                 false : true;
 884
 885         adev->mmhub.funcs->set_fault_enable_default(adev, value);
 886         gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
 887
 888         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 889                  (unsigned int)(adev->gmc.gart_size >> 20),
 890                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
 891
 892         return 0;
 893 }
 894
 895 static int gmc_v11_0_hw_init(void *handle)
 896 {
 897         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 898         int r;
 899
 900         adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode;
 901
 902         /* The sequence of these two function calls matters.*/
 903         gmc_v11_0_init_golden_registers(adev);
 904
 905         r = gmc_v11_0_gart_enable(adev);
 906         if (r)
 907                 return r;
 908
 909         if (adev->umc.funcs && adev->umc.funcs->init_registers)
 910                 adev->umc.funcs->init_registers(adev);
 911
 912         return 0;
 913 }
 914
 915 /**
 916  * gmc_v11_0_gart_disable - gart disable
 917  *
 918  * @adev: amdgpu_device pointer
 919  *
 920  * This disables all VM page table.
 921  */
 922 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev)
 923 {
 924         adev->mmhub.funcs->gart_disable(adev);
 925 }
 926
 927 static int gmc_v11_0_hw_fini(void *handle)
 928 {
 929         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 930
 931         if (amdgpu_sriov_vf(adev)) {
 932                 /* full access mode, so don't touch any GMC register */
 933                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 934                 return 0;
 935         }
 936
 937         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 938         gmc_v11_0_gart_disable(adev);
 939
 940         return 0;
 941 }
 942
 943 static int gmc_v11_0_suspend(void *handle)
 944 {
 945         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 946
 947         gmc_v11_0_hw_fini(adev);
 948
 949         return 0;
 950 }
 951
 952 static int gmc_v11_0_resume(void *handle)
 953 {
 954         int r;
 955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 956
 957         r = gmc_v11_0_hw_init(adev);
 958         if (r)
 959                 return r;
 960
 961         amdgpu_vmid_reset_all(adev);
 962
 963         return 0;
 964 }
 965
 966 static bool gmc_v11_0_is_idle(void *handle)
 967 {
 968         /* MC is always ready in GMC v11.*/
 969         return true;
 970 }
 971
 972 static int gmc_v11_0_wait_for_idle(void *handle)
 973 {
 974         /* There is no need to wait for MC idle in GMC v11.*/
 975         return 0;
 976 }
 977
 978 static int gmc_v11_0_soft_reset(void *handle)
 979 {
 980         return 0;
 981 }
 982
 983 static int gmc_v11_0_set_clockgating_state(void *handle,
 984                                            enum amd_clockgating_state state)
 985 {
 986         int r;
 987         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 988
 989         r = adev->mmhub.funcs->set_clockgating(adev, state);
 990         if (r)
 991                 return r;
 992
 993         return athub_v3_0_set_clockgating(adev, state);
 994 }
 995
 996 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
 997 {
 998         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 999
1000         adev->mmhub.funcs->get_clockgating(adev, flags);
1001
1002         athub_v3_0_get_clockgating(adev, flags);
1003 }
1004
1005 static int gmc_v11_0_set_powergating_state(void *handle,
1006                                            enum amd_powergating_state state)
1007 {
1008         return 0;
1009 }
1010
1011 const struct amd_ip_funcs gmc_v11_0_ip_funcs = {
1012         .name = "gmc_v11_0",
1013         .early_init = gmc_v11_0_early_init,
1014         .sw_init = gmc_v11_0_sw_init,
1015         .hw_init = gmc_v11_0_hw_init,
1016         .late_init = gmc_v11_0_late_init,
1017         .sw_fini = gmc_v11_0_sw_fini,
1018         .hw_fini = gmc_v11_0_hw_fini,
1019         .suspend = gmc_v11_0_suspend,
1020         .resume = gmc_v11_0_resume,
1021         .is_idle = gmc_v11_0_is_idle,
1022         .wait_for_idle = gmc_v11_0_wait_for_idle,
1023         .soft_reset = gmc_v11_0_soft_reset,
1024         .set_clockgating_state = gmc_v11_0_set_clockgating_state,
1025         .set_powergating_state = gmc_v11_0_set_powergating_state,
1026         .get_clockgating_state = gmc_v11_0_get_clockgating_state,
1027 };
1028
1029 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = {
1030         .type = AMD_IP_BLOCK_TYPE_GMC,
1031         .major = 11,
1032         .minor = 0,
1033         .rev = 0,
1034         .funcs = &gmc_v11_0_ip_funcs,
1035 };