drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25
  26 #include <drm/drm_cache.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "gmc_v11_0.h"
  31 #include "umc_v8_10.h"
  32 #include "athub/athub_3_0_0_sh_mask.h"
  33 #include "athub/athub_3_0_0_offset.h"
  34 #include "dcn/dcn_3_2_0_offset.h"
  35 #include "dcn/dcn_3_2_0_sh_mask.h"
  36 #include "oss/osssys_6_0_0_offset.h"
  37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  38 #include "navi10_enum.h"
  39 #include "soc15.h"
  40 #include "soc15d.h"
  41 #include "soc15_common.h"
  42 #include "nbio_v4_3.h"
  43 #include "gfxhub_v3_0.h"
  44 #include "gfxhub_v3_0_3.h"
  45 #include "gfxhub_v11_5_0.h"
  46 #include "mmhub_v3_0.h"
  47 #include "mmhub_v3_0_1.h"
  48 #include "mmhub_v3_0_2.h"
  49 #include "mmhub_v3_3.h"
  50 #include "athub_v3_0.h"
  51
  52
  53 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev,
  54                                          struct amdgpu_irq_src *src,
  55                                          unsigned int type,
  56                                          enum amdgpu_interrupt_state state)
  57 {
  58         return 0;
  59 }
  60
  61 static int
  62 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  63                                    struct amdgpu_irq_src *src, unsigned int type,
  64                                    enum amdgpu_interrupt_state state)
  65 {
  66         switch (state) {
  67         case AMDGPU_IRQ_STATE_DISABLE:
  68                 /* MM HUB */
  69                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false);
  70                 /* GFX HUB */
  71                 /* This works because this interrupt is only
  72                  * enabled at init/resume and disabled in
  73                  * fini/suspend, so the overall state doesn't
  74                  * change over the course of suspend/resume.
  75                  */
  76                 if (!adev->in_s0ix && (adev->in_runpm || adev->in_suspend ||
  77                                                            amdgpu_in_reset(adev)))
  78                         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false);
  79                 break;
  80         case AMDGPU_IRQ_STATE_ENABLE:
  81                 /* MM HUB */
  82                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true);
  83                 /* GFX HUB */
  84                 /* This works because this interrupt is only
  85                  * enabled at init/resume and disabled in
  86                  * fini/suspend, so the overall state doesn't
  87                  * change over the course of suspend/resume.
  88                  */
  89                 if (!adev->in_s0ix)
  90                         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true);
  91                 break;
  92         default:
  93                 break;
  94         }
  95
  96         return 0;
  97 }
  98
  99 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,
 100                                        struct amdgpu_irq_src *source,
 101                                        struct amdgpu_iv_entry *entry)
 102 {
 103         uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ?
 104                                AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0);
 105         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index];
 106         uint32_t status = 0;
 107         u64 addr;
 108
 109         addr = (u64)entry->src_data[0] << 12;
 110         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 111
 112         if (!amdgpu_sriov_vf(adev)) {
 113                 /*
 114                  * Issue a dummy read to wait for the status register to
 115                  * be updated to avoid reading an incorrect value due to
 116                  * the new fast GRBM interface.
 117                  */
 118                 if (entry->vmid_src == AMDGPU_GFXHUB(0))
 119                         RREG32(hub->vm_l2_pro_fault_status);
 120
 121                 status = RREG32(hub->vm_l2_pro_fault_status);
 122                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 123
 124                 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status,
 125                                              entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0));
 126         }
 127
 128         if (printk_ratelimit()) {
 129                 struct amdgpu_task_info *task_info;
 130
 131                 dev_err(adev->dev,
 132                         "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
 133                         entry->vmid_src ? "mmhub" : "gfxhub",
 134                         entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
 135                 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
 136                 if (task_info) {
 137                         dev_err(adev->dev,
 138                                 " in process %s pid %d thread %s pid %d)\n",
 139                                 task_info->process_name, task_info->tgid,
 140                                 task_info->task_name, task_info->pid);
 141                         amdgpu_vm_put_task_info(task_info);
 142                 }
 143
 144                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 145                                 addr, entry->client_id);
 146
 147                 /* Only print L2 fault status if the status register could be read and
 148                  * contains useful information
 149                  */
 150                 if (status != 0)
 151                         hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
 152         }
 153
 154         return 0;
 155 }
 156
 157 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = {
 158         .set = gmc_v11_0_vm_fault_interrupt_state,
 159         .process = gmc_v11_0_process_interrupt,
 160 };
 161
 162 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = {
 163         .set = gmc_v11_0_ecc_interrupt_state,
 164         .process = amdgpu_umc_process_ecc_irq,
 165 };
 166
 167 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 168 {
 169         adev->gmc.vm_fault.num_types = 1;
 170         adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;
 171
 172         if (!amdgpu_sriov_vf(adev)) {
 173                 adev->gmc.ecc_irq.num_types = 1;
 174                 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;
 175         }
 176 }
 177
 178 /**
 179  * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore
 180  *
 181  * @adev: amdgpu_device pointer
 182  * @vmhub: vmhub type
 183  *
 184  */
 185 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 186                                        uint32_t vmhub)
 187 {
 188         return ((vmhub == AMDGPU_MMHUB0(0)) &&
 189                 (!amdgpu_sriov_vf(adev)));
 190 }
 191
 192 static bool gmc_v11_0_get_vmid_pasid_mapping_info(
 193                                         struct amdgpu_device *adev,
 194                                         uint8_t vmid, uint16_t *p_pasid)
 195 {
 196         *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
 197
 198         return !!(*p_pasid);
 199 }
 200
 201 /**
 202  * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
 203  *
 204  * @adev: amdgpu_device pointer
 205  * @vmid: vm instance to flush
 206  * @vmhub: which hub to flush
 207  * @flush_type: the flush type
 208  *
 209  * Flush the TLB for the requested page table.
 210  */
 211 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 212                                         uint32_t vmhub, uint32_t flush_type)
 213 {
 214         bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub);
 215         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 216         u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 217         /* Use register 17 for GART */
 218         const unsigned int eng = 17;
 219         unsigned char hub_ip;
 220         u32 sem, req, ack;
 221         unsigned int i;
 222         u32 tmp;
 223
 224         if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron)
 225                 return;
 226
 227         sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
 228         req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 229         ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 230
 231         /* flush hdp cache */
 232         adev->hdp.funcs->flush_hdp(adev, NULL);
 233
 234         /* This is necessary for SRIOV as well as for GFXOFF to function
 235          * properly under bare metal
 236          */
 237         if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) &&
 238             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
 239                 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
 240                                                  1 << vmid, GET_INST(GC, 0));
 241                 return;
 242         }
 243
 244         /* This path is needed before KIQ/MES/GFXOFF are set up */
 245         hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP;
 246
 247         spin_lock(&adev->gmc.invalidate_lock);
 248         /*
 249          * It may lose gpuvm invalidate acknowldege state across power-gating
 250          * off cycle, add semaphore acquire before invalidation and semaphore
 251          * release after invalidation to avoid entering power gated state
 252          * to WA the Issue
 253          */
 254
 255         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 256         if (use_semaphore) {
 257                 for (i = 0; i < adev->usec_timeout; i++) {
 258                         /* a read return value of 1 means semaphore acuqire */
 259                         tmp = RREG32_RLC_NO_KIQ(sem, hub_ip);
 260                         if (tmp & 0x1)
 261                                 break;
 262                         udelay(1);
 263                 }
 264
 265                 if (i >= adev->usec_timeout)
 266                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 267         }
 268
 269         WREG32_RLC_NO_KIQ(req, inv_req, hub_ip);
 270
 271         /* Wait for ACK with a delay.*/
 272         for (i = 0; i < adev->usec_timeout; i++) {
 273                 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip);
 274                 tmp &= 1 << vmid;
 275                 if (tmp)
 276                         break;
 277
 278                 udelay(1);
 279         }
 280
 281         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 282         if (use_semaphore)
 283                 WREG32_RLC_NO_KIQ(sem, 0, hub_ip);
 284
 285         /* Issue additional private vm invalidation to MMHUB */
 286         if ((vmhub != AMDGPU_GFXHUB(0)) &&
 287             (hub->vm_l2_bank_select_reserved_cid2) &&
 288                 !amdgpu_sriov_vf(adev)) {
 289                 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 290                 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */
 291                 inv_req |= (1 << 25);
 292                 /* Issue private invalidation */
 293                 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
 294                 /* Read back to ensure invalidation is done*/
 295                 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 296         }
 297
 298         spin_unlock(&adev->gmc.invalidate_lock);
 299
 300         if (i >= adev->usec_timeout)
 301                 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n");
 302 }
 303
 304 /**
 305  * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid
 306  *
 307  * @adev: amdgpu_device pointer
 308  * @pasid: pasid to be flush
 309  * @flush_type: the flush type
 310  * @all_hub: flush all hubs
 311  * @inst: is used to select which instance of KIQ to use for the invalidation
 312  *
 313  * Flush the TLB for the requested pasid.
 314  */
 315 static void gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 316                                           uint16_t pasid, uint32_t flush_type,
 317                                           bool all_hub, uint32_t inst)
 318 {
 319         uint16_t queried;
 320         int vmid, i;
 321
 322         for (vmid = 1; vmid < 16; vmid++) {
 323                 bool valid;
 324
 325                 valid = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid,
 326                                                               &queried);
 327                 if (!valid || queried != pasid)
 328                         continue;
 329
 330                 if (all_hub) {
 331                         for_each_set_bit(i, adev->vmhubs_mask,
 332                                          AMDGPU_MAX_VMHUBS)
 333                                 gmc_v11_0_flush_gpu_tlb(adev, vmid, i,
 334                                                         flush_type);
 335                 } else {
 336                         gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0),
 337                                                 flush_type);
 338                 }
 339         }
 340 }
 341
 342 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 343                                              unsigned int vmid, uint64_t pd_addr)
 344 {
 345         bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
 346         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
 347         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
 348         unsigned int eng = ring->vm_inv_eng;
 349
 350         /*
 351          * It may lose gpuvm invalidate acknowldege state across power-gating
 352          * off cycle, add semaphore acquire before invalidation and semaphore
 353          * release after invalidation to avoid entering power gated state
 354          * to WA the Issue
 355          */
 356
 357         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 358         if (use_semaphore)
 359                 /* a read return value of 1 means semaphore acuqire */
 360                 amdgpu_ring_emit_reg_wait(ring,
 361                                           hub->vm_inv_eng0_sem +
 362                                           hub->eng_distance * eng, 0x1, 0x1);
 363
 364         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 365                               (hub->ctx_addr_distance * vmid),
 366                               lower_32_bits(pd_addr));
 367
 368         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 369                               (hub->ctx_addr_distance * vmid),
 370                               upper_32_bits(pd_addr));
 371
 372         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 373                                             hub->eng_distance * eng,
 374                                             hub->vm_inv_eng0_ack +
 375                                             hub->eng_distance * eng,
 376                                             req, 1 << vmid);
 377
 378         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 379         if (use_semaphore)
 380                 /*
 381                  * add semaphore release after invalidation,
 382                  * write with 0 means semaphore release
 383                  */
 384                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 385                                       hub->eng_distance * eng, 0);
 386
 387         return pd_addr;
 388 }
 389
 390 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
 391                                          unsigned int pasid)
 392 {
 393         struct amdgpu_device *adev = ring->adev;
 394         uint32_t reg;
 395
 396         /* MES fw manages IH_VMID_x_LUT updating */
 397         if (ring->is_mes_queue)
 398                 return;
 399
 400         if (ring->vm_hub == AMDGPU_GFXHUB(0))
 401                 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
 402         else
 403                 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
 404
 405         amdgpu_ring_emit_wreg(ring, reg, pasid);
 406 }
 407
 408 /*
 409  * PTE format:
 410  * 63:59 reserved
 411  * 58:57 reserved
 412  * 56 F
 413  * 55 L
 414  * 54 reserved
 415  * 53:52 SW
 416  * 51 T
 417  * 50:48 mtype
 418  * 47:12 4k physical page base address
 419  * 11:7 fragment
 420  * 6 write
 421  * 5 read
 422  * 4 exe
 423  * 3 Z
 424  * 2 snooped
 425  * 1 system
 426  * 0 valid
 427  *
 428  * PDE format:
 429  * 63:59 block fragment size
 430  * 58:55 reserved
 431  * 54 P
 432  * 53:48 reserved
 433  * 47:6 physical base address of PD or PTE
 434  * 5:3 reserved
 435  * 2 C
 436  * 1 system
 437  * 0 valid
 438  */
 439
 440 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 441 {
 442         switch (flags) {
 443         case AMDGPU_VM_MTYPE_DEFAULT:
 444                 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC);
 445         case AMDGPU_VM_MTYPE_NC:
 446                 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC);
 447         case AMDGPU_VM_MTYPE_WC:
 448                 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_WC);
 449         case AMDGPU_VM_MTYPE_CC:
 450                 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_CC);
 451         case AMDGPU_VM_MTYPE_UC:
 452                 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC);
 453         default:
 454                 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC);
 455         }
 456 }
 457
 458 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,
 459                                  uint64_t *addr, uint64_t *flags)
 460 {
 461         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 462                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
 463         BUG_ON(*addr & 0xFFFF00000000003FULL);
 464
 465         if (!adev->gmc.translate_further)
 466                 return;
 467
 468         if (level == AMDGPU_VM_PDB1) {
 469                 /* Set the block fragment size */
 470                 if (!(*flags & AMDGPU_PDE_PTE))
 471                         *flags |= AMDGPU_PDE_BFS(0x9);
 472
 473         } else if (level == AMDGPU_VM_PDB0) {
 474                 if (*flags & AMDGPU_PDE_PTE)
 475                         *flags &= ~AMDGPU_PDE_PTE;
 476                 else
 477                         *flags |= AMDGPU_PTE_TF;
 478         }
 479 }
 480
 481 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
 482                                  struct amdgpu_bo_va_mapping *mapping,
 483                                  uint64_t *flags)
 484 {
 485         struct amdgpu_bo *bo = mapping->bo_va->base.bo;
 486
 487         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 488         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 489
 490         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
 491         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
 492
 493         *flags &= ~AMDGPU_PTE_NOALLOC;
 494         *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
 495
 496         if (mapping->flags & AMDGPU_PTE_PRT) {
 497                 *flags |= AMDGPU_PTE_PRT;
 498                 *flags |= AMDGPU_PTE_SNOOPED;
 499                 *flags |= AMDGPU_PTE_LOG;
 500                 *flags |= AMDGPU_PTE_SYSTEM;
 501                 *flags &= ~AMDGPU_PTE_VALID;
 502         }
 503
 504         if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
 505                                AMDGPU_GEM_CREATE_EXT_COHERENT |
 506                                AMDGPU_GEM_CREATE_UNCACHED))
 507                 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC);
 508 }
 509
 510 static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)
 511 {
 512         u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);
 513         unsigned int size;
 514
 515         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 516                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
 517         } else {
 518                 u32 viewport;
 519                 u32 pitch;
 520
 521                 viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 522                 pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);
 523                 size = (REG_GET_FIELD(viewport,
 524                                         HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 525                                 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
 526                                 4);
 527         }
 528
 529         return size;
 530 }
 531
 532 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
 533         .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb,
 534         .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid,
 535         .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb,
 536         .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping,
 537         .map_mtype = gmc_v11_0_map_mtype,
 538         .get_vm_pde = gmc_v11_0_get_vm_pde,
 539         .get_vm_pte = gmc_v11_0_get_vm_pte,
 540         .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size,
 541 };
 542
 543 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev)
 544 {
 545         adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;
 546 }
 547
 548 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
 549 {
 550         switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
 551         case IP_VERSION(8, 10, 0):
 552                 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;
 553                 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;
 554                 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
 555                 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;
 556                 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM;
 557                 if (adev->umc.node_inst_num == 4)
 558                         adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0];
 559                 else
 560                         adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0];
 561                 adev->umc.ras = &umc_v8_10_ras;
 562                 break;
 563         case IP_VERSION(8, 11, 0):
 564                 break;
 565         default:
 566                 break;
 567         }
 568 }
 569
 570
 571 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
 572 {
 573         switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
 574         case IP_VERSION(3, 0, 1):
 575                 adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
 576                 break;
 577         case IP_VERSION(3, 0, 2):
 578                 adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
 579                 break;
 580         case IP_VERSION(3, 3, 0):
 581         case IP_VERSION(3, 3, 1):
 582                 adev->mmhub.funcs = &mmhub_v3_3_funcs;
 583                 break;
 584         default:
 585                 adev->mmhub.funcs = &mmhub_v3_0_funcs;
 586                 break;
 587         }
 588 }
 589
 590 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 591 {
 592         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 593         case IP_VERSION(11, 0, 3):
 594                 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs;
 595                 break;
 596         case IP_VERSION(11, 5, 0):
 597         case IP_VERSION(11, 5, 1):
 598         case IP_VERSION(11, 5, 2):
 599                 adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs;
 600                 break;
 601         default:
 602                 adev->gfxhub.funcs = &gfxhub_v3_0_funcs;
 603                 break;
 604         }
 605 }
 606
 607 static int gmc_v11_0_early_init(struct amdgpu_ip_block *ip_block)
 608 {
 609         struct amdgpu_device *adev = ip_block->adev;
 610
 611         gmc_v11_0_set_gfxhub_funcs(adev);
 612         gmc_v11_0_set_mmhub_funcs(adev);
 613         gmc_v11_0_set_gmc_funcs(adev);
 614         gmc_v11_0_set_irq_funcs(adev);
 615         gmc_v11_0_set_umc_funcs(adev);
 616
 617         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 618         adev->gmc.shared_aperture_end =
 619                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 620         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 621         adev->gmc.private_aperture_end =
 622                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 623         adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
 624
 625         return 0;
 626 }
 627
 628 static int gmc_v11_0_late_init(struct amdgpu_ip_block *ip_block)
 629 {
 630         struct amdgpu_device *adev = ip_block->adev;
 631         int r;
 632
 633         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 634         if (r)
 635                 return r;
 636
 637         r = amdgpu_gmc_ras_late_init(adev);
 638         if (r)
 639                 return r;
 640
 641         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 642 }
 643
 644 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev,
 645                                         struct amdgpu_gmc *mc)
 646 {
 647         u64 base = 0;
 648
 649         base = adev->mmhub.funcs->get_fb_location(adev);
 650
 651         amdgpu_gmc_set_agp_default(adev, mc);
 652         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 653         amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH);
 654         if (!amdgpu_sriov_vf(adev) &&
 655             (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) &&
 656             (amdgpu_agp == 1))
 657                 amdgpu_gmc_agp_location(adev, mc);
 658
 659         /* base offset of vram pages */
 660         if (amdgpu_sriov_vf(adev))
 661                 adev->vm_manager.vram_base_offset = 0;
 662         else
 663                 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
 664 }
 665
 666 /**
 667  * gmc_v11_0_mc_init - initialize the memory controller driver params
 668  *
 669  * @adev: amdgpu_device pointer
 670  *
 671  * Look up the amount of vram, vram width, and decide how to place
 672  * vram and gart within the GPU's physical address space.
 673  * Returns 0 for success.
 674  */
 675 static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
 676 {
 677         int r;
 678
 679         /* size in MB on si */
 680         adev->gmc.mc_vram_size =
 681                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 682         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 683
 684         if (!(adev->flags & AMD_IS_APU)) {
 685                 r = amdgpu_device_resize_fb_bar(adev);
 686                 if (r)
 687                         return r;
 688         }
 689         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 690         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 691
 692 #ifdef CONFIG_X86_64
 693         if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
 694                 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
 695                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 696         }
 697 #endif
 698         /* In case the PCI BAR is larger than the actual amount of vram */
 699         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 700         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 701                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 702
 703         /* set the gart size */
 704         if (amdgpu_gart_size == -1)
 705                 adev->gmc.gart_size = 512ULL << 20;
 706         else
 707                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 708
 709         gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
 710
 711         return 0;
 712 }
 713
 714 static int gmc_v11_0_gart_init(struct amdgpu_device *adev)
 715 {
 716         int r;
 717
 718         if (adev->gart.bo) {
 719                 WARN(1, "PCIE GART already initialized\n");
 720                 return 0;
 721         }
 722
 723         /* Initialize common gart structure */
 724         r = amdgpu_gart_init(adev);
 725         if (r)
 726                 return r;
 727
 728         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 729         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) |
 730                                  AMDGPU_PTE_EXECUTABLE;
 731
 732         return amdgpu_gart_table_vram_alloc(adev);
 733 }
 734
 735 static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
 736 {
 737         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 738         struct amdgpu_device *adev = ip_block->adev;
 739
 740         adev->mmhub.funcs->init(adev);
 741
 742         adev->gfxhub.funcs->init(adev);
 743
 744         spin_lock_init(&adev->gmc.invalidate_lock);
 745
 746         r = amdgpu_atomfirmware_get_vram_info(adev,
 747                                               &vram_width, &vram_type, &vram_vendor);
 748         adev->gmc.vram_width = vram_width;
 749
 750         adev->gmc.vram_type = vram_type;
 751         adev->gmc.vram_vendor = vram_vendor;
 752
 753         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 754         case IP_VERSION(11, 0, 0):
 755         case IP_VERSION(11, 0, 1):
 756         case IP_VERSION(11, 0, 2):
 757         case IP_VERSION(11, 0, 3):
 758         case IP_VERSION(11, 0, 4):
 759         case IP_VERSION(11, 5, 0):
 760         case IP_VERSION(11, 5, 1):
 761         case IP_VERSION(11, 5, 2):
 762                 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
 763                 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
 764                 /*
 765                  * To fulfill 4-level page support,
 766                  * vm size is 256TB (48bit), maximum size,
 767                  * block size 512 (9bit)
 768                  */
 769                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 770                 break;
 771         default:
 772                 break;
 773         }
 774
 775         /* This interrupt is VMC page fault.*/
 776         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC,
 777                               VMC_1_0__SRCID__VM_FAULT,
 778                               &adev->gmc.vm_fault);
 779
 780         if (r)
 781                 return r;
 782
 783         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
 784                               UTCL2_1_0__SRCID__FAULT,
 785                               &adev->gmc.vm_fault);
 786         if (r)
 787                 return r;
 788
 789         if (!amdgpu_sriov_vf(adev)) {
 790                 /* interrupt sent to DF. */
 791                 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
 792                                       &adev->gmc.ecc_irq);
 793                 if (r)
 794                         return r;
 795         }
 796
 797         /*
 798          * Set the internal MC address mask This is the max address of the GPU's
 799          * internal address space.
 800          */
 801         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 802
 803         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 804         if (r) {
 805                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 806                 return r;
 807         }
 808
 809         adev->need_swiotlb = drm_need_swiotlb(44);
 810
 811         r = gmc_v11_0_mc_init(adev);
 812         if (r)
 813                 return r;
 814
 815         amdgpu_gmc_get_vbios_allocations(adev);
 816
 817         /* Memory manager */
 818         r = amdgpu_bo_init(adev);
 819         if (r)
 820                 return r;
 821
 822         r = gmc_v11_0_gart_init(adev);
 823         if (r)
 824                 return r;
 825
 826         /*
 827          * number of VMs
 828          * VMID 0 is reserved for System
 829          * amdgpu graphics/compute will use VMIDs 1-7
 830          * amdkfd will use VMIDs 8-15
 831          */
 832         adev->vm_manager.first_kfd_vmid = 8;
 833
 834         amdgpu_vm_manager_init(adev);
 835
 836         r = amdgpu_gmc_ras_sw_init(adev);
 837         if (r)
 838                 return r;
 839
 840         return 0;
 841 }
 842
 843 /**
 844  * gmc_v11_0_gart_fini - vm fini callback
 845  *
 846  * @adev: amdgpu_device pointer
 847  *
 848  * Tears down the driver GART/VM setup (CIK).
 849  */
 850 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev)
 851 {
 852         amdgpu_gart_table_vram_free(adev);
 853 }
 854
 855 static int gmc_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)
 856 {
 857         struct amdgpu_device *adev = ip_block->adev;
 858
 859         amdgpu_vm_manager_fini(adev);
 860         gmc_v11_0_gart_fini(adev);
 861         amdgpu_gem_force_release(adev);
 862         amdgpu_bo_fini(adev);
 863
 864         return 0;
 865 }
 866
 867 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev)
 868 {
 869         if (amdgpu_sriov_vf(adev)) {
 870                 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 871
 872                 WREG32(hub->vm_contexts_disable, 0);
 873                 return;
 874         }
 875 }
 876
 877 /**
 878  * gmc_v11_0_gart_enable - gart enable
 879  *
 880  * @adev: amdgpu_device pointer
 881  */
 882 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
 883 {
 884         int r;
 885         bool value;
 886
 887         if (adev->gart.bo == NULL) {
 888                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 889                 return -EINVAL;
 890         }
 891
 892         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 893
 894         r = adev->mmhub.funcs->gart_enable(adev);
 895         if (r)
 896                 return r;
 897
 898         /* Flush HDP after it is initialized */
 899         adev->hdp.funcs->flush_hdp(adev, NULL);
 900
 901         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
 902                 false : true;
 903
 904         adev->mmhub.funcs->set_fault_enable_default(adev, value);
 905         gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
 906
 907         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 908                  (unsigned int)(adev->gmc.gart_size >> 20),
 909                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
 910
 911         return 0;
 912 }
 913
 914 static int gmc_v11_0_hw_init(struct amdgpu_ip_block *ip_block)
 915 {
 916         struct amdgpu_device *adev = ip_block->adev;
 917         int r;
 918
 919         adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode;
 920
 921         /* The sequence of these two function calls matters.*/
 922         gmc_v11_0_init_golden_registers(adev);
 923
 924         r = gmc_v11_0_gart_enable(adev);
 925         if (r)
 926                 return r;
 927
 928         if (adev->umc.funcs && adev->umc.funcs->init_registers)
 929                 adev->umc.funcs->init_registers(adev);
 930
 931         return 0;
 932 }
 933
 934 /**
 935  * gmc_v11_0_gart_disable - gart disable
 936  *
 937  * @adev: amdgpu_device pointer
 938  *
 939  * This disables all VM page table.
 940  */
 941 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev)
 942 {
 943         adev->mmhub.funcs->gart_disable(adev);
 944 }
 945
 946 static int gmc_v11_0_hw_fini(struct amdgpu_ip_block *ip_block)
 947 {
 948         struct amdgpu_device *adev = ip_block->adev;
 949
 950         if (amdgpu_sriov_vf(adev)) {
 951                 /* full access mode, so don't touch any GMC register */
 952                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 953                 return 0;
 954         }
 955
 956         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 957
 958         if (adev->gmc.ecc_irq.funcs &&
 959                 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
 960                 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
 961
 962         gmc_v11_0_gart_disable(adev);
 963
 964         return 0;
 965 }
 966
 967 static int gmc_v11_0_suspend(struct amdgpu_ip_block *ip_block)
 968 {
 969         gmc_v11_0_hw_fini(ip_block);
 970
 971         return 0;
 972 }
 973
 974 static int gmc_v11_0_resume(struct amdgpu_ip_block *ip_block)
 975 {
 976         int r;
 977
 978         r = gmc_v11_0_hw_init(ip_block);
 979         if (r)
 980                 return r;
 981
 982         amdgpu_vmid_reset_all(ip_block->adev);
 983
 984         return 0;
 985 }
 986
 987 static bool gmc_v11_0_is_idle(void *handle)
 988 {
 989         /* MC is always ready in GMC v11.*/
 990         return true;
 991 }
 992
 993 static int gmc_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
 994 {
 995         /* There is no need to wait for MC idle in GMC v11.*/
 996         return 0;
 997 }
 998
 999 static int gmc_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1000                                            enum amd_clockgating_state state)
1001 {
1002         int r;
1003         struct amdgpu_device *adev = ip_block->adev;
1004
1005         r = adev->mmhub.funcs->set_clockgating(adev, state);
1006         if (r)
1007                 return r;
1008
1009         return athub_v3_0_set_clockgating(adev, state);
1010 }
1011
1012 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
1013 {
1014         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1015
1016         adev->mmhub.funcs->get_clockgating(adev, flags);
1017
1018         athub_v3_0_get_clockgating(adev, flags);
1019 }
1020
1021 static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
1022                                            enum amd_powergating_state state)
1023 {
1024         return 0;
1025 }
1026
1027 const struct amd_ip_funcs gmc_v11_0_ip_funcs = {
1028         .name = "gmc_v11_0",
1029         .early_init = gmc_v11_0_early_init,
1030         .sw_init = gmc_v11_0_sw_init,
1031         .hw_init = gmc_v11_0_hw_init,
1032         .late_init = gmc_v11_0_late_init,
1033         .sw_fini = gmc_v11_0_sw_fini,
1034         .hw_fini = gmc_v11_0_hw_fini,
1035         .suspend = gmc_v11_0_suspend,
1036         .resume = gmc_v11_0_resume,
1037         .is_idle = gmc_v11_0_is_idle,
1038         .wait_for_idle = gmc_v11_0_wait_for_idle,
1039         .set_clockgating_state = gmc_v11_0_set_clockgating_state,
1040         .set_powergating_state = gmc_v11_0_set_powergating_state,
1041         .get_clockgating_state = gmc_v11_0_get_clockgating_state,
1042 };
1043
1044 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = {
1045         .type = AMD_IP_BLOCK_TYPE_GMC,
1046         .major = 11,
1047         .minor = 0,
1048         .rev = 0,
1049         .funcs = &gmc_v11_0_ip_funcs,
1050 };