drivers/net/can/rcar/rcar_canfd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Renesas R-Car CAN FD device driver
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corp.
   5  */
   6
   7 /* The R-Car CAN FD controller can operate in either one of the below two modes
   8  *  - CAN FD only mode
   9  *  - Classical CAN (CAN 2.0) only mode
  10  *
  11  * This driver puts the controller in CAN FD only mode by default. In this
  12  * mode, the controller acts as a CAN FD node that can also interoperate with
  13  * CAN 2.0 nodes.
  14  *
  15  * To switch the controller to Classical CAN (CAN 2.0) only mode, add
  16  * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
  17  * also required to switch modes.
  18  *
  19  * Note: The h/w manual register naming convention is clumsy and not acceptable
  20  * to use as it is in the driver. However, those names are added as comments
  21  * wherever it is modified to a readable name.
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/errno.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/can/led.h>
  33 #include <linux/can/dev.h>
  34 #include <linux/clk.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37 #include <linux/bitmap.h>
  38 #include <linux/bitops.h>
  39 #include <linux/iopoll.h>
  40 #include <linux/reset.h>
  41
  42 #define RCANFD_DRV_NAME                 "rcar_canfd"
  43
  44 enum rcanfd_chip_id {
  45         RENESAS_RCAR_GEN3 = 0,
  46         RENESAS_RZG2L,
  47 };
  48
  49 /* Global register bits */
  50
  51 /* RSCFDnCFDGRMCFG */
  52 #define RCANFD_GRMCFG_RCMC              BIT(0)
  53
  54 /* RSCFDnCFDGCFG / RSCFDnGCFG */
  55 #define RCANFD_GCFG_EEFE                BIT(6)
  56 #define RCANFD_GCFG_CMPOC               BIT(5)  /* CAN FD only */
  57 #define RCANFD_GCFG_DCS                 BIT(4)
  58 #define RCANFD_GCFG_DCE                 BIT(1)
  59 #define RCANFD_GCFG_TPRI                BIT(0)
  60
  61 /* RSCFDnCFDGCTR / RSCFDnGCTR */
  62 #define RCANFD_GCTR_TSRST               BIT(16)
  63 #define RCANFD_GCTR_CFMPOFIE            BIT(11) /* CAN FD only */
  64 #define RCANFD_GCTR_THLEIE              BIT(10)
  65 #define RCANFD_GCTR_MEIE                BIT(9)
  66 #define RCANFD_GCTR_DEIE                BIT(8)
  67 #define RCANFD_GCTR_GSLPR               BIT(2)
  68 #define RCANFD_GCTR_GMDC_MASK           (0x3)
  69 #define RCANFD_GCTR_GMDC_GOPM           (0x0)
  70 #define RCANFD_GCTR_GMDC_GRESET         (0x1)
  71 #define RCANFD_GCTR_GMDC_GTEST          (0x2)
  72
  73 /* RSCFDnCFDGSTS / RSCFDnGSTS */
  74 #define RCANFD_GSTS_GRAMINIT            BIT(3)
  75 #define RCANFD_GSTS_GSLPSTS             BIT(2)
  76 #define RCANFD_GSTS_GHLTSTS             BIT(1)
  77 #define RCANFD_GSTS_GRSTSTS             BIT(0)
  78 /* Non-operational status */
  79 #define RCANFD_GSTS_GNOPM               (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  80
  81 /* RSCFDnCFDGERFL / RSCFDnGERFL */
  82 #define RCANFD_GERFL_EEF1               BIT(17)
  83 #define RCANFD_GERFL_EEF0               BIT(16)
  84 #define RCANFD_GERFL_CMPOF              BIT(3)  /* CAN FD only */
  85 #define RCANFD_GERFL_THLES              BIT(2)
  86 #define RCANFD_GERFL_MES                BIT(1)
  87 #define RCANFD_GERFL_DEF                BIT(0)
  88
  89 #define RCANFD_GERFL_ERR(gpriv, x)      ((x) & (RCANFD_GERFL_EEF1 |\
  90                                         RCANFD_GERFL_EEF0 | RCANFD_GERFL_MES |\
  91                                         (gpriv->fdmode ?\
  92                                          RCANFD_GERFL_CMPOF : 0)))
  93
  94 /* AFL Rx rules registers */
  95
  96 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
  97 #define RCANFD_GAFLCFG_SETRNC(n, x)     (((x) & 0xff) << (24 - n * 8))
  98 #define RCANFD_GAFLCFG_GETRNC(n, x)     (((x) >> (24 - n * 8)) & 0xff)
  99
 100 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 101 #define RCANFD_GAFLECTR_AFLDAE          BIT(8)
 102 #define RCANFD_GAFLECTR_AFLPN(x)        ((x) & 0x1f)
 103
 104 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 105 #define RCANFD_GAFLID_GAFLLB            BIT(29)
 106
 107 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
 108 #define RCANFD_GAFLP1_GAFLFDP(x)        (1 << (x))
 109
 110 /* Channel register bits */
 111
 112 /* RSCFDnCmCFG - Classical CAN only */
 113 #define RCANFD_CFG_SJW(x)               (((x) & 0x3) << 24)
 114 #define RCANFD_CFG_TSEG2(x)             (((x) & 0x7) << 20)
 115 #define RCANFD_CFG_TSEG1(x)             (((x) & 0xf) << 16)
 116 #define RCANFD_CFG_BRP(x)               (((x) & 0x3ff) << 0)
 117
 118 /* RSCFDnCFDCmNCFG - CAN FD only */
 119 #define RCANFD_NCFG_NTSEG2(x)           (((x) & 0x1f) << 24)
 120 #define RCANFD_NCFG_NTSEG1(x)           (((x) & 0x7f) << 16)
 121 #define RCANFD_NCFG_NSJW(x)             (((x) & 0x1f) << 11)
 122 #define RCANFD_NCFG_NBRP(x)             (((x) & 0x3ff) << 0)
 123
 124 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 125 #define RCANFD_CCTR_CTME                BIT(24)
 126 #define RCANFD_CCTR_ERRD                BIT(23)
 127 #define RCANFD_CCTR_BOM_MASK            (0x3 << 21)
 128 #define RCANFD_CCTR_BOM_ISO             (0x0 << 21)
 129 #define RCANFD_CCTR_BOM_BENTRY          (0x1 << 21)
 130 #define RCANFD_CCTR_BOM_BEND            (0x2 << 21)
 131 #define RCANFD_CCTR_TDCVFIE             BIT(19)
 132 #define RCANFD_CCTR_SOCOIE              BIT(18)
 133 #define RCANFD_CCTR_EOCOIE              BIT(17)
 134 #define RCANFD_CCTR_TAIE                BIT(16)
 135 #define RCANFD_CCTR_ALIE                BIT(15)
 136 #define RCANFD_CCTR_BLIE                BIT(14)
 137 #define RCANFD_CCTR_OLIE                BIT(13)
 138 #define RCANFD_CCTR_BORIE               BIT(12)
 139 #define RCANFD_CCTR_BOEIE               BIT(11)
 140 #define RCANFD_CCTR_EPIE                BIT(10)
 141 #define RCANFD_CCTR_EWIE                BIT(9)
 142 #define RCANFD_CCTR_BEIE                BIT(8)
 143 #define RCANFD_CCTR_CSLPR               BIT(2)
 144 #define RCANFD_CCTR_CHMDC_MASK          (0x3)
 145 #define RCANFD_CCTR_CHDMC_COPM          (0x0)
 146 #define RCANFD_CCTR_CHDMC_CRESET        (0x1)
 147 #define RCANFD_CCTR_CHDMC_CHLT          (0x2)
 148
 149 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 150 #define RCANFD_CSTS_COMSTS              BIT(7)
 151 #define RCANFD_CSTS_RECSTS              BIT(6)
 152 #define RCANFD_CSTS_TRMSTS              BIT(5)
 153 #define RCANFD_CSTS_BOSTS               BIT(4)
 154 #define RCANFD_CSTS_EPSTS               BIT(3)
 155 #define RCANFD_CSTS_SLPSTS              BIT(2)
 156 #define RCANFD_CSTS_HLTSTS              BIT(1)
 157 #define RCANFD_CSTS_CRSTSTS             BIT(0)
 158
 159 #define RCANFD_CSTS_TECCNT(x)           (((x) >> 24) & 0xff)
 160 #define RCANFD_CSTS_RECCNT(x)           (((x) >> 16) & 0xff)
 161
 162 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 163 #define RCANFD_CERFL_ADERR              BIT(14)
 164 #define RCANFD_CERFL_B0ERR              BIT(13)
 165 #define RCANFD_CERFL_B1ERR              BIT(12)
 166 #define RCANFD_CERFL_CERR               BIT(11)
 167 #define RCANFD_CERFL_AERR               BIT(10)
 168 #define RCANFD_CERFL_FERR               BIT(9)
 169 #define RCANFD_CERFL_SERR               BIT(8)
 170 #define RCANFD_CERFL_ALF                BIT(7)
 171 #define RCANFD_CERFL_BLF                BIT(6)
 172 #define RCANFD_CERFL_OVLF               BIT(5)
 173 #define RCANFD_CERFL_BORF               BIT(4)
 174 #define RCANFD_CERFL_BOEF               BIT(3)
 175 #define RCANFD_CERFL_EPF                BIT(2)
 176 #define RCANFD_CERFL_EWF                BIT(1)
 177 #define RCANFD_CERFL_BEF                BIT(0)
 178
 179 #define RCANFD_CERFL_ERR(x)             ((x) & (0x7fff)) /* above bits 14:0 */
 180
 181 /* RSCFDnCFDCmDCFG */
 182 #define RCANFD_DCFG_DSJW(x)             (((x) & 0x7) << 24)
 183 #define RCANFD_DCFG_DTSEG2(x)           (((x) & 0x7) << 20)
 184 #define RCANFD_DCFG_DTSEG1(x)           (((x) & 0xf) << 16)
 185 #define RCANFD_DCFG_DBRP(x)             (((x) & 0xff) << 0)
 186
 187 /* RSCFDnCFDCmFDCFG */
 188 #define RCANFD_FDCFG_TDCE               BIT(9)
 189 #define RCANFD_FDCFG_TDCOC              BIT(8)
 190 #define RCANFD_FDCFG_TDCO(x)            (((x) & 0x7f) >> 16)
 191
 192 /* RSCFDnCFDRFCCx */
 193 #define RCANFD_RFCC_RFIM                BIT(12)
 194 #define RCANFD_RFCC_RFDC(x)             (((x) & 0x7) << 8)
 195 #define RCANFD_RFCC_RFPLS(x)            (((x) & 0x7) << 4)
 196 #define RCANFD_RFCC_RFIE                BIT(1)
 197 #define RCANFD_RFCC_RFE                 BIT(0)
 198
 199 /* RSCFDnCFDRFSTSx */
 200 #define RCANFD_RFSTS_RFIF               BIT(3)
 201 #define RCANFD_RFSTS_RFMLT              BIT(2)
 202 #define RCANFD_RFSTS_RFFLL              BIT(1)
 203 #define RCANFD_RFSTS_RFEMP              BIT(0)
 204
 205 /* RSCFDnCFDRFIDx */
 206 #define RCANFD_RFID_RFIDE               BIT(31)
 207 #define RCANFD_RFID_RFRTR               BIT(30)
 208
 209 /* RSCFDnCFDRFPTRx */
 210 #define RCANFD_RFPTR_RFDLC(x)           (((x) >> 28) & 0xf)
 211 #define RCANFD_RFPTR_RFPTR(x)           (((x) >> 16) & 0xfff)
 212 #define RCANFD_RFPTR_RFTS(x)            (((x) >> 0) & 0xffff)
 213
 214 /* RSCFDnCFDRFFDSTSx */
 215 #define RCANFD_RFFDSTS_RFFDF            BIT(2)
 216 #define RCANFD_RFFDSTS_RFBRS            BIT(1)
 217 #define RCANFD_RFFDSTS_RFESI            BIT(0)
 218
 219 /* Common FIFO bits */
 220
 221 /* RSCFDnCFDCFCCk */
 222 #define RCANFD_CFCC_CFTML(x)            (((x) & 0xf) << 20)
 223 #define RCANFD_CFCC_CFM(x)              (((x) & 0x3) << 16)
 224 #define RCANFD_CFCC_CFIM                BIT(12)
 225 #define RCANFD_CFCC_CFDC(x)             (((x) & 0x7) << 8)
 226 #define RCANFD_CFCC_CFPLS(x)            (((x) & 0x7) << 4)
 227 #define RCANFD_CFCC_CFTXIE              BIT(2)
 228 #define RCANFD_CFCC_CFE                 BIT(0)
 229
 230 /* RSCFDnCFDCFSTSk */
 231 #define RCANFD_CFSTS_CFMC(x)            (((x) >> 8) & 0xff)
 232 #define RCANFD_CFSTS_CFTXIF             BIT(4)
 233 #define RCANFD_CFSTS_CFMLT              BIT(2)
 234 #define RCANFD_CFSTS_CFFLL              BIT(1)
 235 #define RCANFD_CFSTS_CFEMP              BIT(0)
 236
 237 /* RSCFDnCFDCFIDk */
 238 #define RCANFD_CFID_CFIDE               BIT(31)
 239 #define RCANFD_CFID_CFRTR               BIT(30)
 240 #define RCANFD_CFID_CFID_MASK(x)        ((x) & 0x1fffffff)
 241
 242 /* RSCFDnCFDCFPTRk */
 243 #define RCANFD_CFPTR_CFDLC(x)           (((x) & 0xf) << 28)
 244 #define RCANFD_CFPTR_CFPTR(x)           (((x) & 0xfff) << 16)
 245 #define RCANFD_CFPTR_CFTS(x)            (((x) & 0xff) << 0)
 246
 247 /* RSCFDnCFDCFFDCSTSk */
 248 #define RCANFD_CFFDCSTS_CFFDF           BIT(2)
 249 #define RCANFD_CFFDCSTS_CFBRS           BIT(1)
 250 #define RCANFD_CFFDCSTS_CFESI           BIT(0)
 251
 252 /* This controller supports either Classical CAN only mode or CAN FD only mode.
 253  * These modes are supported in two separate set of register maps & names.
 254  * However, some of the register offsets are common for both modes. Those
 255  * offsets are listed below as Common registers.
 256  *
 257  * The CAN FD only mode specific registers & Classical CAN only mode specific
 258  * registers are listed separately. Their register names starts with
 259  * RCANFD_F_xxx & RCANFD_C_xxx respectively.
 260  */
 261
 262 /* Common registers */
 263
 264 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
 265 #define RCANFD_CCFG(m)                  (0x0000 + (0x10 * (m)))
 266 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 267 #define RCANFD_CCTR(m)                  (0x0004 + (0x10 * (m)))
 268 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 269 #define RCANFD_CSTS(m)                  (0x0008 + (0x10 * (m)))
 270 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 271 #define RCANFD_CERFL(m)                 (0x000C + (0x10 * (m)))
 272
 273 /* RSCFDnCFDGCFG / RSCFDnGCFG */
 274 #define RCANFD_GCFG                     (0x0084)
 275 /* RSCFDnCFDGCTR / RSCFDnGCTR */
 276 #define RCANFD_GCTR                     (0x0088)
 277 /* RSCFDnCFDGCTS / RSCFDnGCTS */
 278 #define RCANFD_GSTS                     (0x008c)
 279 /* RSCFDnCFDGERFL / RSCFDnGERFL */
 280 #define RCANFD_GERFL                    (0x0090)
 281 /* RSCFDnCFDGTSC / RSCFDnGTSC */
 282 #define RCANFD_GTSC                     (0x0094)
 283 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 284 #define RCANFD_GAFLECTR                 (0x0098)
 285 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
 286 #define RCANFD_GAFLCFG0                 (0x009c)
 287 /* RSCFDnCFDGAFLCFG1 / RSCFDnGAFLCFG1 */
 288 #define RCANFD_GAFLCFG1                 (0x00a0)
 289 /* RSCFDnCFDRMNB / RSCFDnRMNB */
 290 #define RCANFD_RMNB                     (0x00a4)
 291 /* RSCFDnCFDRMND / RSCFDnRMND */
 292 #define RCANFD_RMND(y)                  (0x00a8 + (0x04 * (y)))
 293
 294 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
 295 #define RCANFD_RFCC(x)                  (0x00b8 + (0x04 * (x)))
 296 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
 297 #define RCANFD_RFSTS(x)                 (0x00d8 + (0x04 * (x)))
 298 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
 299 #define RCANFD_RFPCTR(x)                (0x00f8 + (0x04 * (x)))
 300
 301 /* Common FIFO Control registers */
 302
 303 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
 304 #define RCANFD_CFCC(ch, idx)            (0x0118 + (0x0c * (ch)) + \
 305                                          (0x04 * (idx)))
 306 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
 307 #define RCANFD_CFSTS(ch, idx)           (0x0178 + (0x0c * (ch)) + \
 308                                          (0x04 * (idx)))
 309 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
 310 #define RCANFD_CFPCTR(ch, idx)          (0x01d8 + (0x0c * (ch)) + \
 311                                          (0x04 * (idx)))
 312
 313 /* RSCFDnCFDFESTS / RSCFDnFESTS */
 314 #define RCANFD_FESTS                    (0x0238)
 315 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
 316 #define RCANFD_FFSTS                    (0x023c)
 317 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
 318 #define RCANFD_FMSTS                    (0x0240)
 319 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
 320 #define RCANFD_RFISTS                   (0x0244)
 321 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
 322 #define RCANFD_CFRISTS                  (0x0248)
 323 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
 324 #define RCANFD_CFTISTS                  (0x024c)
 325
 326 /* RSCFDnCFDTMCp / RSCFDnTMCp */
 327 #define RCANFD_TMC(p)                   (0x0250 + (0x01 * (p)))
 328 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
 329 #define RCANFD_TMSTS(p)                 (0x02d0 + (0x01 * (p)))
 330
 331 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
 332 #define RCANFD_TMTRSTS(y)               (0x0350 + (0x04 * (y)))
 333 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
 334 #define RCANFD_TMTARSTS(y)              (0x0360 + (0x04 * (y)))
 335 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
 336 #define RCANFD_TMTCSTS(y)               (0x0370 + (0x04 * (y)))
 337 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
 338 #define RCANFD_TMTASTS(y)               (0x0380 + (0x04 * (y)))
 339 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
 340 #define RCANFD_TMIEC(y)                 (0x0390 + (0x04 * (y)))
 341
 342 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
 343 #define RCANFD_TXQCC(m)                 (0x03a0 + (0x04 * (m)))
 344 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
 345 #define RCANFD_TXQSTS(m)                (0x03c0 + (0x04 * (m)))
 346 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
 347 #define RCANFD_TXQPCTR(m)               (0x03e0 + (0x04 * (m)))
 348
 349 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
 350 #define RCANFD_THLCC(m)                 (0x0400 + (0x04 * (m)))
 351 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
 352 #define RCANFD_THLSTS(m)                (0x0420 + (0x04 * (m)))
 353 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
 354 #define RCANFD_THLPCTR(m)               (0x0440 + (0x04 * (m)))
 355
 356 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
 357 #define RCANFD_GTINTSTS0                (0x0460)
 358 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
 359 #define RCANFD_GTINTSTS1                (0x0464)
 360 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
 361 #define RCANFD_GTSTCFG                  (0x0468)
 362 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
 363 #define RCANFD_GTSTCTR                  (0x046c)
 364 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
 365 #define RCANFD_GLOCKK                   (0x047c)
 366 /* RSCFDnCFDGRMCFG */
 367 #define RCANFD_GRMCFG                   (0x04fc)
 368
 369 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 370 #define RCANFD_GAFLID(offset, j)        ((offset) + (0x10 * (j)))
 371 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
 372 #define RCANFD_GAFLM(offset, j)         ((offset) + 0x04 + (0x10 * (j)))
 373 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
 374 #define RCANFD_GAFLP0(offset, j)        ((offset) + 0x08 + (0x10 * (j)))
 375 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
 376 #define RCANFD_GAFLP1(offset, j)        ((offset) + 0x0c + (0x10 * (j)))
 377
 378 /* Classical CAN only mode register map */
 379
 380 /* RSCFDnGAFLXXXj offset */
 381 #define RCANFD_C_GAFL_OFFSET            (0x0500)
 382
 383 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
 384 #define RCANFD_C_RMID(q)                (0x0600 + (0x10 * (q)))
 385 #define RCANFD_C_RMPTR(q)               (0x0604 + (0x10 * (q)))
 386 #define RCANFD_C_RMDF0(q)               (0x0608 + (0x10 * (q)))
 387 #define RCANFD_C_RMDF1(q)               (0x060c + (0x10 * (q)))
 388
 389 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
 390 #define RCANFD_C_RFOFFSET               (0x0e00)
 391 #define RCANFD_C_RFID(x)                (RCANFD_C_RFOFFSET + (0x10 * (x)))
 392 #define RCANFD_C_RFPTR(x)               (RCANFD_C_RFOFFSET + 0x04 + \
 393                                          (0x10 * (x)))
 394 #define RCANFD_C_RFDF(x, df)            (RCANFD_C_RFOFFSET + 0x08 + \
 395                                          (0x10 * (x)) + (0x04 * (df)))
 396
 397 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
 398 #define RCANFD_C_CFOFFSET               (0x0e80)
 399 #define RCANFD_C_CFID(ch, idx)          (RCANFD_C_CFOFFSET + (0x30 * (ch)) + \
 400                                          (0x10 * (idx)))
 401 #define RCANFD_C_CFPTR(ch, idx)         (RCANFD_C_CFOFFSET + 0x04 + \
 402                                          (0x30 * (ch)) + (0x10 * (idx)))
 403 #define RCANFD_C_CFDF(ch, idx, df)      (RCANFD_C_CFOFFSET + 0x08 + \
 404                                          (0x30 * (ch)) + (0x10 * (idx)) + \
 405                                          (0x04 * (df)))
 406
 407 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
 408 #define RCANFD_C_TMID(p)                (0x1000 + (0x10 * (p)))
 409 #define RCANFD_C_TMPTR(p)               (0x1004 + (0x10 * (p)))
 410 #define RCANFD_C_TMDF0(p)               (0x1008 + (0x10 * (p)))
 411 #define RCANFD_C_TMDF1(p)               (0x100c + (0x10 * (p)))
 412
 413 /* RSCFDnTHLACCm */
 414 #define RCANFD_C_THLACC(m)              (0x1800 + (0x04 * (m)))
 415 /* RSCFDnRPGACCr */
 416 #define RCANFD_C_RPGACC(r)              (0x1900 + (0x04 * (r)))
 417
 418 /* CAN FD mode specific register map */
 419
 420 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
 421 #define RCANFD_F_DCFG(m)                (0x0500 + (0x20 * (m)))
 422 #define RCANFD_F_CFDCFG(m)              (0x0504 + (0x20 * (m)))
 423 #define RCANFD_F_CFDCTR(m)              (0x0508 + (0x20 * (m)))
 424 #define RCANFD_F_CFDSTS(m)              (0x050c + (0x20 * (m)))
 425 #define RCANFD_F_CFDCRC(m)              (0x0510 + (0x20 * (m)))
 426
 427 /* RSCFDnCFDGAFLXXXj offset */
 428 #define RCANFD_F_GAFL_OFFSET            (0x1000)
 429
 430 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
 431 #define RCANFD_F_RMID(q)                (0x2000 + (0x20 * (q)))
 432 #define RCANFD_F_RMPTR(q)               (0x2004 + (0x20 * (q)))
 433 #define RCANFD_F_RMFDSTS(q)             (0x2008 + (0x20 * (q)))
 434 #define RCANFD_F_RMDF(q, b)             (0x200c + (0x04 * (b)) + (0x20 * (q)))
 435
 436 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
 437 #define RCANFD_F_RFOFFSET               (0x3000)
 438 #define RCANFD_F_RFID(x)                (RCANFD_F_RFOFFSET + (0x80 * (x)))
 439 #define RCANFD_F_RFPTR(x)               (RCANFD_F_RFOFFSET + 0x04 + \
 440                                          (0x80 * (x)))
 441 #define RCANFD_F_RFFDSTS(x)             (RCANFD_F_RFOFFSET + 0x08 + \
 442                                          (0x80 * (x)))
 443 #define RCANFD_F_RFDF(x, df)            (RCANFD_F_RFOFFSET + 0x0c + \
 444                                          (0x80 * (x)) + (0x04 * (df)))
 445
 446 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
 447 #define RCANFD_F_CFOFFSET               (0x3400)
 448 #define RCANFD_F_CFID(ch, idx)          (RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
 449                                          (0x80 * (idx)))
 450 #define RCANFD_F_CFPTR(ch, idx)         (RCANFD_F_CFOFFSET + 0x04 + \
 451                                          (0x180 * (ch)) + (0x80 * (idx)))
 452 #define RCANFD_F_CFFDCSTS(ch, idx)      (RCANFD_F_CFOFFSET + 0x08 + \
 453                                          (0x180 * (ch)) + (0x80 * (idx)))
 454 #define RCANFD_F_CFDF(ch, idx, df)      (RCANFD_F_CFOFFSET + 0x0c + \
 455                                          (0x180 * (ch)) + (0x80 * (idx)) + \
 456                                          (0x04 * (df)))
 457
 458 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
 459 #define RCANFD_F_TMID(p)                (0x4000 + (0x20 * (p)))
 460 #define RCANFD_F_TMPTR(p)               (0x4004 + (0x20 * (p)))
 461 #define RCANFD_F_TMFDCTR(p)             (0x4008 + (0x20 * (p)))
 462 #define RCANFD_F_TMDF(p, b)             (0x400c + (0x20 * (p)) + (0x04 * (b)))
 463
 464 /* RSCFDnCFDTHLACCm */
 465 #define RCANFD_F_THLACC(m)              (0x6000 + (0x04 * (m)))
 466 /* RSCFDnCFDRPGACCr */
 467 #define RCANFD_F_RPGACC(r)              (0x6400 + (0x04 * (r)))
 468
 469 /* Constants */
 470 #define RCANFD_FIFO_DEPTH               8       /* Tx FIFO depth */
 471 #define RCANFD_NAPI_WEIGHT              8       /* Rx poll quota */
 472
 473 #define RCANFD_NUM_CHANNELS             2       /* Two channels max */
 474 #define RCANFD_CHANNELS_MASK            BIT((RCANFD_NUM_CHANNELS) - 1)
 475
 476 #define RCANFD_GAFL_PAGENUM(entry)      ((entry) / 16)
 477 #define RCANFD_CHANNEL_NUMRULES         1       /* only one rule per channel */
 478
 479 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
 480  * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
 481  * number is added to RFFIFO index.
 482  */
 483 #define RCANFD_RFFIFO_IDX               0
 484
 485 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
 486  * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
 487  */
 488 #define RCANFD_CFFIFO_IDX               0
 489
 490 /* fCAN clock select register settings */
 491 enum rcar_canfd_fcanclk {
 492         RCANFD_CANFDCLK = 0,            /* CANFD clock */
 493         RCANFD_EXTCLK,                  /* Externally input clock */
 494 };
 495
 496 struct rcar_canfd_global;
 497
 498 /* Channel priv data */
 499 struct rcar_canfd_channel {
 500         struct can_priv can;                    /* Must be the first member */
 501         struct net_device *ndev;
 502         struct rcar_canfd_global *gpriv;        /* Controller reference */
 503         void __iomem *base;                     /* Register base address */
 504         struct napi_struct napi;
 505         u8  tx_len[RCANFD_FIFO_DEPTH];          /* For net stats */
 506         u32 tx_head;                            /* Incremented on xmit */
 507         u32 tx_tail;                            /* Incremented on xmit done */
 508         u32 channel;                            /* Channel number */
 509         spinlock_t tx_lock;                     /* To protect tx path */
 510 };
 511
 512 /* Global priv data */
 513 struct rcar_canfd_global {
 514         struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
 515         void __iomem *base;             /* Register base address */
 516         struct platform_device *pdev;   /* Respective platform device */
 517         struct clk *clkp;               /* Peripheral clock */
 518         struct clk *can_clk;            /* fCAN clock */
 519         enum rcar_canfd_fcanclk fcan;   /* CANFD or Ext clock */
 520         unsigned long channels_mask;    /* Enabled channels mask */
 521         bool fdmode;                    /* CAN FD or Classical CAN only mode */
 522         struct reset_control *rstc1;
 523         struct reset_control *rstc2;
 524         enum rcanfd_chip_id chip_id;
 525 };
 526
 527 /* CAN FD mode nominal rate constants */
 528 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
 529         .name = RCANFD_DRV_NAME,
 530         .tseg1_min = 2,
 531         .tseg1_max = 128,
 532         .tseg2_min = 2,
 533         .tseg2_max = 32,
 534         .sjw_max = 32,
 535         .brp_min = 1,
 536         .brp_max = 1024,
 537         .brp_inc = 1,
 538 };
 539
 540 /* CAN FD mode data rate constants */
 541 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
 542         .name = RCANFD_DRV_NAME,
 543         .tseg1_min = 2,
 544         .tseg1_max = 16,
 545         .tseg2_min = 2,
 546         .tseg2_max = 8,
 547         .sjw_max = 8,
 548         .brp_min = 1,
 549         .brp_max = 256,
 550         .brp_inc = 1,
 551 };
 552
 553 /* Classical CAN mode bitrate constants */
 554 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
 555         .name = RCANFD_DRV_NAME,
 556         .tseg1_min = 4,
 557         .tseg1_max = 16,
 558         .tseg2_min = 2,
 559         .tseg2_max = 8,
 560         .sjw_max = 4,
 561         .brp_min = 1,
 562         .brp_max = 1024,
 563         .brp_inc = 1,
 564 };
 565
 566 /* Helper functions */
 567 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
 568 {
 569         u32 data = readl(reg);
 570
 571         data &= ~mask;
 572         data |= (val & mask);
 573         writel(data, reg);
 574 }
 575
 576 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
 577 {
 578         return readl(base + (offset));
 579 }
 580
 581 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
 582 {
 583         writel(val, base + (offset));
 584 }
 585
 586 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
 587 {
 588         rcar_canfd_update(val, val, base + (reg));
 589 }
 590
 591 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
 592 {
 593         rcar_canfd_update(val, 0, base + (reg));
 594 }
 595
 596 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
 597                                   u32 mask, u32 val)
 598 {
 599         rcar_canfd_update(mask, val, base + (reg));
 600 }
 601
 602 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
 603                                 struct canfd_frame *cf, u32 off)
 604 {
 605         u32 i, lwords;
 606
 607         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 608         for (i = 0; i < lwords; i++)
 609                 *((u32 *)cf->data + i) =
 610                         rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
 611 }
 612
 613 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
 614                                 struct canfd_frame *cf, u32 off)
 615 {
 616         u32 i, lwords;
 617
 618         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 619         for (i = 0; i < lwords; i++)
 620                 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
 621                                  *((u32 *)cf->data + i));
 622 }
 623
 624 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
 625 {
 626         u32 i;
 627
 628         for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
 629                 can_free_echo_skb(ndev, i, NULL);
 630 }
 631
 632 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 633 {
 634         u32 sts, ch;
 635         int err;
 636
 637         /* Check RAMINIT flag as CAN RAM initialization takes place
 638          * after the MCU reset
 639          */
 640         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 641                                  !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
 642         if (err) {
 643                 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
 644                 return err;
 645         }
 646
 647         /* Transition to Global Reset mode */
 648         rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
 649         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
 650                               RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
 651
 652         /* Ensure Global reset mode */
 653         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 654                                  (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
 655         if (err) {
 656                 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
 657                 return err;
 658         }
 659
 660         /* Reset Global error flags */
 661         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 662
 663         /* Set the controller into appropriate mode */
 664         if (gpriv->fdmode)
 665                 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 666                                    RCANFD_GRMCFG_RCMC);
 667         else
 668                 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
 669                                      RCANFD_GRMCFG_RCMC);
 670
 671         /* Transition all Channels to reset mode */
 672         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
 673                 rcar_canfd_clear_bit(gpriv->base,
 674                                      RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 675
 676                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 677                                       RCANFD_CCTR_CHMDC_MASK,
 678                                       RCANFD_CCTR_CHDMC_CRESET);
 679
 680                 /* Ensure Channel reset mode */
 681                 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
 682                                          (sts & RCANFD_CSTS_CRSTSTS),
 683                                          2, 500000);
 684                 if (err) {
 685                         dev_dbg(&gpriv->pdev->dev,
 686                                 "channel %u reset failed\n", ch);
 687                         return err;
 688                 }
 689         }
 690         return 0;
 691 }
 692
 693 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 694 {
 695         u32 cfg, ch;
 696
 697         /* Global configuration settings */
 698
 699         /* ECC Error flag Enable */
 700         cfg = RCANFD_GCFG_EEFE;
 701
 702         if (gpriv->fdmode)
 703                 /* Truncate payload to configured message size RFPLS */
 704                 cfg |= RCANFD_GCFG_CMPOC;
 705
 706         /* Set External Clock if selected */
 707         if (gpriv->fcan != RCANFD_CANFDCLK)
 708                 cfg |= RCANFD_GCFG_DCS;
 709
 710         rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 711
 712         /* Channel configuration settings */
 713         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
 714                 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
 715                                    RCANFD_CCTR_ERRD);
 716                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 717                                       RCANFD_CCTR_BOM_MASK,
 718                                       RCANFD_CCTR_BOM_BENTRY);
 719         }
 720 }
 721
 722 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 723                                            u32 ch)
 724 {
 725         u32 cfg;
 726         int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 727         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 728
 729         if (ch == 0) {
 730                 start = 0; /* Channel 0 always starts from 0th rule */
 731         } else {
 732                 /* Get number of Channel 0 rules and adjust */
 733                 cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
 734                 start = RCANFD_GAFLCFG_GETRNC(0, cfg);
 735         }
 736
 737         /* Enable write access to entry */
 738         page = RCANFD_GAFL_PAGENUM(start);
 739         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 740                            (RCANFD_GAFLECTR_AFLPN(page) |
 741                             RCANFD_GAFLECTR_AFLDAE));
 742
 743         /* Write number of rules for channel */
 744         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
 745                            RCANFD_GAFLCFG_SETRNC(ch, num_rules));
 746         if (gpriv->fdmode)
 747                 offset = RCANFD_F_GAFL_OFFSET;
 748         else
 749                 offset = RCANFD_C_GAFL_OFFSET;
 750
 751         /* Accept all IDs */
 752         rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
 753         /* IDE or RTR is not considered for matching */
 754         rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
 755         /* Any data length accepted */
 756         rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
 757         /* Place the msg in corresponding Rx FIFO entry */
 758         rcar_canfd_write(gpriv->base, RCANFD_GAFLP1(offset, start),
 759                          RCANFD_GAFLP1_GAFLFDP(ridx));
 760
 761         /* Disable write access to page */
 762         rcar_canfd_clear_bit(gpriv->base,
 763                              RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
 764 }
 765
 766 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 767 {
 768         /* Rx FIFO is used for reception */
 769         u32 cfg;
 770         u16 rfdc, rfpls;
 771
 772         /* Select Rx FIFO based on channel */
 773         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 774
 775         rfdc = 2;               /* b010 - 8 messages Rx FIFO depth */
 776         if (gpriv->fdmode)
 777                 rfpls = 7;      /* b111 - Max 64 bytes payload */
 778         else
 779                 rfpls = 0;      /* b000 - Max 8 bytes payload */
 780
 781         cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 782                 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 783         rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
 784 }
 785
 786 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 787 {
 788         /* Tx/Rx(Common) FIFO configured in Tx mode is
 789          * used for transmission
 790          *
 791          * Each channel has 3 Common FIFO dedicated to them.
 792          * Use the 1st (index 0) out of 3
 793          */
 794         u32 cfg;
 795         u16 cftml, cfm, cfdc, cfpls;
 796
 797         cftml = 0;              /* 0th buffer */
 798         cfm = 1;                /* b01 - Transmit mode */
 799         cfdc = 2;               /* b010 - 8 messages Tx FIFO depth */
 800         if (gpriv->fdmode)
 801                 cfpls = 7;      /* b111 - Max 64 bytes payload */
 802         else
 803                 cfpls = 0;      /* b000 - Max 8 bytes payload */
 804
 805         cfg = (RCANFD_CFCC_CFTML(cftml) | RCANFD_CFCC_CFM(cfm) |
 806                 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(cfdc) |
 807                 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
 808         rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
 809
 810         if (gpriv->fdmode)
 811                 /* Clear FD mode specific control/status register */
 812                 rcar_canfd_write(gpriv->base,
 813                                  RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
 814 }
 815
 816 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 817 {
 818         u32 ctr;
 819
 820         /* Clear any stray error interrupt flags */
 821         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 822
 823         /* Global interrupts setup */
 824         ctr = RCANFD_GCTR_MEIE;
 825         if (gpriv->fdmode)
 826                 ctr |= RCANFD_GCTR_CFMPOFIE;
 827
 828         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 829 }
 830
 831 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
 832                                                  *gpriv)
 833 {
 834         /* Disable all interrupts */
 835         rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
 836
 837         /* Clear any stray error interrupt flags */
 838         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 839 }
 840
 841 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
 842                                                  *priv)
 843 {
 844         u32 ctr, ch = priv->channel;
 845
 846         /* Clear any stray error flags */
 847         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 848
 849         /* Channel interrupts setup */
 850         ctr = (RCANFD_CCTR_TAIE |
 851                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 852                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 853                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 854                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 855         rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
 856 }
 857
 858 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
 859                                                   *priv)
 860 {
 861         u32 ctr, ch = priv->channel;
 862
 863         ctr = (RCANFD_CCTR_TAIE |
 864                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 865                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 866                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 867                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 868         rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
 869
 870         /* Clear any stray error flags */
 871         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 872 }
 873
 874 static void rcar_canfd_global_error(struct net_device *ndev)
 875 {
 876         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 877         struct rcar_canfd_global *gpriv = priv->gpriv;
 878         struct net_device_stats *stats = &ndev->stats;
 879         u32 ch = priv->channel;
 880         u32 gerfl, sts;
 881         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 882
 883         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
 884         if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
 885                 netdev_dbg(ndev, "Ch0: ECC Error flag\n");
 886                 stats->tx_dropped++;
 887         }
 888         if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
 889                 netdev_dbg(ndev, "Ch1: ECC Error flag\n");
 890                 stats->tx_dropped++;
 891         }
 892         if (gerfl & RCANFD_GERFL_MES) {
 893                 sts = rcar_canfd_read(priv->base,
 894                                       RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
 895                 if (sts & RCANFD_CFSTS_CFMLT) {
 896                         netdev_dbg(ndev, "Tx Message Lost flag\n");
 897                         stats->tx_dropped++;
 898                         rcar_canfd_write(priv->base,
 899                                          RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
 900                                          sts & ~RCANFD_CFSTS_CFMLT);
 901                 }
 902
 903                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
 904                 if (sts & RCANFD_RFSTS_RFMLT) {
 905                         netdev_dbg(ndev, "Rx Message Lost flag\n");
 906                         stats->rx_dropped++;
 907                         rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
 908                                          sts & ~RCANFD_RFSTS_RFMLT);
 909                 }
 910         }
 911         if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
 912                 /* Message Lost flag will be set for respective channel
 913                  * when this condition happens with counters and flags
 914                  * already updated.
 915                  */
 916                 netdev_dbg(ndev, "global payload overflow interrupt\n");
 917         }
 918
 919         /* Clear all global error interrupts. Only affected channels bits
 920          * get cleared
 921          */
 922         rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
 923 }
 924
 925 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
 926                              u16 txerr, u16 rxerr)
 927 {
 928         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 929         struct net_device_stats *stats = &ndev->stats;
 930         struct can_frame *cf;
 931         struct sk_buff *skb;
 932         u32 ch = priv->channel;
 933
 934         netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
 935
 936         /* Propagate the error condition to the CAN stack */
 937         skb = alloc_can_err_skb(ndev, &cf);
 938         if (!skb) {
 939                 stats->rx_dropped++;
 940                 return;
 941         }
 942
 943         /* Channel error interrupts */
 944         if (cerfl & RCANFD_CERFL_BEF) {
 945                 netdev_dbg(ndev, "Bus error\n");
 946                 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
 947                 cf->data[2] = CAN_ERR_PROT_UNSPEC;
 948                 priv->can.can_stats.bus_error++;
 949         }
 950         if (cerfl & RCANFD_CERFL_ADERR) {
 951                 netdev_dbg(ndev, "ACK Delimiter Error\n");
 952                 stats->tx_errors++;
 953                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
 954         }
 955         if (cerfl & RCANFD_CERFL_B0ERR) {
 956                 netdev_dbg(ndev, "Bit Error (dominant)\n");
 957                 stats->tx_errors++;
 958                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 959         }
 960         if (cerfl & RCANFD_CERFL_B1ERR) {
 961                 netdev_dbg(ndev, "Bit Error (recessive)\n");
 962                 stats->tx_errors++;
 963                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 964         }
 965         if (cerfl & RCANFD_CERFL_CERR) {
 966                 netdev_dbg(ndev, "CRC Error\n");
 967                 stats->rx_errors++;
 968                 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
 969         }
 970         if (cerfl & RCANFD_CERFL_AERR) {
 971                 netdev_dbg(ndev, "ACK Error\n");
 972                 stats->tx_errors++;
 973                 cf->can_id |= CAN_ERR_ACK;
 974                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
 975         }
 976         if (cerfl & RCANFD_CERFL_FERR) {
 977                 netdev_dbg(ndev, "Form Error\n");
 978                 stats->rx_errors++;
 979                 cf->data[2] |= CAN_ERR_PROT_FORM;
 980         }
 981         if (cerfl & RCANFD_CERFL_SERR) {
 982                 netdev_dbg(ndev, "Stuff Error\n");
 983                 stats->rx_errors++;
 984                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 985         }
 986         if (cerfl & RCANFD_CERFL_ALF) {
 987                 netdev_dbg(ndev, "Arbitration lost Error\n");
 988                 priv->can.can_stats.arbitration_lost++;
 989                 cf->can_id |= CAN_ERR_LOSTARB;
 990                 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
 991         }
 992         if (cerfl & RCANFD_CERFL_BLF) {
 993                 netdev_dbg(ndev, "Bus Lock Error\n");
 994                 stats->rx_errors++;
 995                 cf->can_id |= CAN_ERR_BUSERROR;
 996         }
 997         if (cerfl & RCANFD_CERFL_EWF) {
 998                 netdev_dbg(ndev, "Error warning interrupt\n");
 999                 priv->can.state = CAN_STATE_ERROR_WARNING;
1000                 priv->can.can_stats.error_warning++;
1001                 cf->can_id |= CAN_ERR_CRTL;
1002                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1003                         CAN_ERR_CRTL_RX_WARNING;
1004                 cf->data[6] = txerr;
1005                 cf->data[7] = rxerr;
1006         }
1007         if (cerfl & RCANFD_CERFL_EPF) {
1008                 netdev_dbg(ndev, "Error passive interrupt\n");
1009                 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1010                 priv->can.can_stats.error_passive++;
1011                 cf->can_id |= CAN_ERR_CRTL;
1012                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1013                         CAN_ERR_CRTL_RX_PASSIVE;
1014                 cf->data[6] = txerr;
1015                 cf->data[7] = rxerr;
1016         }
1017         if (cerfl & RCANFD_CERFL_BOEF) {
1018                 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1019                 rcar_canfd_tx_failure_cleanup(ndev);
1020                 priv->can.state = CAN_STATE_BUS_OFF;
1021                 priv->can.can_stats.bus_off++;
1022                 can_bus_off(ndev);
1023                 cf->can_id |= CAN_ERR_BUSOFF;
1024         }
1025         if (cerfl & RCANFD_CERFL_OVLF) {
1026                 netdev_dbg(ndev,
1027                            "Overload Frame Transmission error interrupt\n");
1028                 stats->tx_errors++;
1029                 cf->can_id |= CAN_ERR_PROT;
1030                 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1031         }
1032
1033         /* Clear channel error interrupts that are handled */
1034         rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1035                          RCANFD_CERFL_ERR(~cerfl));
1036         stats->rx_packets++;
1037         stats->rx_bytes += cf->len;
1038         netif_rx(skb);
1039 }
1040
1041 static void rcar_canfd_tx_done(struct net_device *ndev)
1042 {
1043         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1044         struct net_device_stats *stats = &ndev->stats;
1045         u32 sts;
1046         unsigned long flags;
1047         u32 ch = priv->channel;
1048
1049         do {
1050                 u8 unsent, sent;
1051
1052                 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1053                 stats->tx_packets++;
1054                 stats->tx_bytes += priv->tx_len[sent];
1055                 priv->tx_len[sent] = 0;
1056                 can_get_echo_skb(ndev, sent, NULL);
1057
1058                 spin_lock_irqsave(&priv->tx_lock, flags);
1059                 priv->tx_tail++;
1060                 sts = rcar_canfd_read(priv->base,
1061                                       RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1062                 unsent = RCANFD_CFSTS_CFMC(sts);
1063
1064                 /* Wake producer only when there is room */
1065                 if (unsent != RCANFD_FIFO_DEPTH)
1066                         netif_wake_queue(ndev);
1067
1068                 if (priv->tx_head - priv->tx_tail <= unsent) {
1069                         spin_unlock_irqrestore(&priv->tx_lock, flags);
1070                         break;
1071                 }
1072                 spin_unlock_irqrestore(&priv->tx_lock, flags);
1073
1074         } while (1);
1075
1076         /* Clear interrupt */
1077         rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
1078                          sts & ~RCANFD_CFSTS_CFTXIF);
1079         can_led_event(ndev, CAN_LED_EVENT_TX);
1080 }
1081
1082 static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1083 {
1084         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1085         struct net_device *ndev = priv->ndev;
1086         u32 gerfl;
1087
1088         /* Handle global error interrupts */
1089         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1090         if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1091                 rcar_canfd_global_error(ndev);
1092 }
1093
1094 static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1095 {
1096         struct rcar_canfd_global *gpriv = dev_id;
1097         u32 ch;
1098
1099         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1100                 rcar_canfd_handle_global_err(gpriv, ch);
1101
1102         return IRQ_HANDLED;
1103 }
1104
1105 static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1106 {
1107         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1108         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1109         u32 sts;
1110
1111         /* Handle Rx interrupts */
1112         sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1113         if (likely(sts & RCANFD_RFSTS_RFIF)) {
1114                 if (napi_schedule_prep(&priv->napi)) {
1115                         /* Disable Rx FIFO interrupts */
1116                         rcar_canfd_clear_bit(priv->base,
1117                                              RCANFD_RFCC(ridx),
1118                                              RCANFD_RFCC_RFIE);
1119                         __napi_schedule(&priv->napi);
1120                 }
1121         }
1122 }
1123
1124 static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1125 {
1126         struct rcar_canfd_global *gpriv = dev_id;
1127         u32 ch;
1128
1129         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1130                 rcar_canfd_handle_global_receive(gpriv, ch);
1131
1132         return IRQ_HANDLED;
1133 }
1134
1135 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1136 {
1137         struct rcar_canfd_global *gpriv = dev_id;
1138         u32 ch;
1139
1140         /* Global error interrupts still indicate a condition specific
1141          * to a channel. RxFIFO interrupt is a global interrupt.
1142          */
1143         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1144                 rcar_canfd_handle_global_err(gpriv, ch);
1145                 rcar_canfd_handle_global_receive(gpriv, ch);
1146         }
1147         return IRQ_HANDLED;
1148 }
1149
1150 static void rcar_canfd_state_change(struct net_device *ndev,
1151                                     u16 txerr, u16 rxerr)
1152 {
1153         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1154         struct net_device_stats *stats = &ndev->stats;
1155         enum can_state rx_state, tx_state, state = priv->can.state;
1156         struct can_frame *cf;
1157         struct sk_buff *skb;
1158
1159         /* Handle transition from error to normal states */
1160         if (txerr < 96 && rxerr < 96)
1161                 state = CAN_STATE_ERROR_ACTIVE;
1162         else if (txerr < 128 && rxerr < 128)
1163                 state = CAN_STATE_ERROR_WARNING;
1164
1165         if (state != priv->can.state) {
1166                 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1167                            state, priv->can.state, txerr, rxerr);
1168                 skb = alloc_can_err_skb(ndev, &cf);
1169                 if (!skb) {
1170                         stats->rx_dropped++;
1171                         return;
1172                 }
1173                 tx_state = txerr >= rxerr ? state : 0;
1174                 rx_state = txerr <= rxerr ? state : 0;
1175
1176                 can_change_state(ndev, cf, tx_state, rx_state);
1177                 stats->rx_packets++;
1178                 stats->rx_bytes += cf->len;
1179                 netif_rx(skb);
1180         }
1181 }
1182
1183 static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1184 {
1185         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1186         struct net_device *ndev = priv->ndev;
1187         u32 sts;
1188
1189         /* Handle Tx interrupts */
1190         sts = rcar_canfd_read(priv->base,
1191                               RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1192         if (likely(sts & RCANFD_CFSTS_CFTXIF))
1193                 rcar_canfd_tx_done(ndev);
1194 }
1195
1196 static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1197 {
1198         struct rcar_canfd_global *gpriv = dev_id;
1199         u32 ch;
1200
1201         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1202                 rcar_canfd_handle_channel_tx(gpriv, ch);
1203
1204         return IRQ_HANDLED;
1205 }
1206
1207 static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1208 {
1209         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1210         struct net_device *ndev = priv->ndev;
1211         u16 txerr, rxerr;
1212         u32 sts, cerfl;
1213
1214         /* Handle channel error interrupts */
1215         cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1216         sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1217         txerr = RCANFD_CSTS_TECCNT(sts);
1218         rxerr = RCANFD_CSTS_RECCNT(sts);
1219         if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1220                 rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1221
1222         /* Handle state change to lower states */
1223         if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1224                      priv->can.state != CAN_STATE_BUS_OFF))
1225                 rcar_canfd_state_change(ndev, txerr, rxerr);
1226 }
1227
1228 static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1229 {
1230         struct rcar_canfd_global *gpriv = dev_id;
1231         u32 ch;
1232
1233         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1234                 rcar_canfd_handle_channel_err(gpriv, ch);
1235
1236         return IRQ_HANDLED;
1237 }
1238
1239 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1240 {
1241         struct rcar_canfd_global *gpriv = dev_id;
1242         u32 ch;
1243
1244         /* Common FIFO is a per channel resource */
1245         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1246                 rcar_canfd_handle_channel_err(gpriv, ch);
1247                 rcar_canfd_handle_channel_tx(gpriv, ch);
1248         }
1249
1250         return IRQ_HANDLED;
1251 }
1252
1253 static void rcar_canfd_set_bittiming(struct net_device *dev)
1254 {
1255         struct rcar_canfd_channel *priv = netdev_priv(dev);
1256         const struct can_bittiming *bt = &priv->can.bittiming;
1257         const struct can_bittiming *dbt = &priv->can.data_bittiming;
1258         u16 brp, sjw, tseg1, tseg2;
1259         u32 cfg;
1260         u32 ch = priv->channel;
1261
1262         /* Nominal bit timing settings */
1263         brp = bt->brp - 1;
1264         sjw = bt->sjw - 1;
1265         tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1266         tseg2 = bt->phase_seg2 - 1;
1267
1268         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1269                 /* CAN FD only mode */
1270                 cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
1271                        RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
1272
1273                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1274                 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1275                            brp, sjw, tseg1, tseg2);
1276
1277                 /* Data bit timing settings */
1278                 brp = dbt->brp - 1;
1279                 sjw = dbt->sjw - 1;
1280                 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1281                 tseg2 = dbt->phase_seg2 - 1;
1282
1283                 cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
1284                        RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
1285
1286                 rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
1287                 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1288                            brp, sjw, tseg1, tseg2);
1289         } else {
1290                 /* Classical CAN only mode */
1291                 cfg = (RCANFD_CFG_TSEG1(tseg1) | RCANFD_CFG_BRP(brp) |
1292                         RCANFD_CFG_SJW(sjw) | RCANFD_CFG_TSEG2(tseg2));
1293
1294                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1295                 netdev_dbg(priv->ndev,
1296                            "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1297                            brp, sjw, tseg1, tseg2);
1298         }
1299 }
1300
1301 static int rcar_canfd_start(struct net_device *ndev)
1302 {
1303         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1304         int err = -EOPNOTSUPP;
1305         u32 sts, ch = priv->channel;
1306         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1307
1308         rcar_canfd_set_bittiming(ndev);
1309
1310         rcar_canfd_enable_channel_interrupts(priv);
1311
1312         /* Set channel to Operational mode */
1313         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1314                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1315
1316         /* Verify channel mode change */
1317         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1318                                  (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1319         if (err) {
1320                 netdev_err(ndev, "channel %u communication state failed\n", ch);
1321                 goto fail_mode_change;
1322         }
1323
1324         /* Enable Common & Rx FIFO */
1325         rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1326                            RCANFD_CFCC_CFE);
1327         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1328
1329         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1330         return 0;
1331
1332 fail_mode_change:
1333         rcar_canfd_disable_channel_interrupts(priv);
1334         return err;
1335 }
1336
1337 static int rcar_canfd_open(struct net_device *ndev)
1338 {
1339         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1340         struct rcar_canfd_global *gpriv = priv->gpriv;
1341         int err;
1342
1343         /* Peripheral clock is already enabled in probe */
1344         err = clk_prepare_enable(gpriv->can_clk);
1345         if (err) {
1346                 netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
1347                 goto out_clock;
1348         }
1349
1350         err = open_candev(ndev);
1351         if (err) {
1352                 netdev_err(ndev, "open_candev() failed, error %d\n", err);
1353                 goto out_can_clock;
1354         }
1355
1356         napi_enable(&priv->napi);
1357         err = rcar_canfd_start(ndev);
1358         if (err)
1359                 goto out_close;
1360         netif_start_queue(ndev);
1361         can_led_event(ndev, CAN_LED_EVENT_OPEN);
1362         return 0;
1363 out_close:
1364         napi_disable(&priv->napi);
1365         close_candev(ndev);
1366 out_can_clock:
1367         clk_disable_unprepare(gpriv->can_clk);
1368 out_clock:
1369         return err;
1370 }
1371
1372 static void rcar_canfd_stop(struct net_device *ndev)
1373 {
1374         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1375         int err;
1376         u32 sts, ch = priv->channel;
1377         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1378
1379         /* Transition to channel reset mode  */
1380         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1381                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1382
1383         /* Check Channel reset mode */
1384         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1385                                  (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1386         if (err)
1387                 netdev_err(ndev, "channel %u reset failed\n", ch);
1388
1389         rcar_canfd_disable_channel_interrupts(priv);
1390
1391         /* Disable Common & Rx FIFO */
1392         rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1393                              RCANFD_CFCC_CFE);
1394         rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1395
1396         /* Set the state as STOPPED */
1397         priv->can.state = CAN_STATE_STOPPED;
1398 }
1399
1400 static int rcar_canfd_close(struct net_device *ndev)
1401 {
1402         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1403         struct rcar_canfd_global *gpriv = priv->gpriv;
1404
1405         netif_stop_queue(ndev);
1406         rcar_canfd_stop(ndev);
1407         napi_disable(&priv->napi);
1408         clk_disable_unprepare(gpriv->can_clk);
1409         close_candev(ndev);
1410         can_led_event(ndev, CAN_LED_EVENT_STOP);
1411         return 0;
1412 }
1413
1414 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1415                                          struct net_device *ndev)
1416 {
1417         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1418         struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1419         u32 sts = 0, id, dlc;
1420         unsigned long flags;
1421         u32 ch = priv->channel;
1422
1423         if (can_dropped_invalid_skb(ndev, skb))
1424                 return NETDEV_TX_OK;
1425
1426         if (cf->can_id & CAN_EFF_FLAG) {
1427                 id = cf->can_id & CAN_EFF_MASK;
1428                 id |= RCANFD_CFID_CFIDE;
1429         } else {
1430                 id = cf->can_id & CAN_SFF_MASK;
1431         }
1432
1433         if (cf->can_id & CAN_RTR_FLAG)
1434                 id |= RCANFD_CFID_CFRTR;
1435
1436         dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1437
1438         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1439                 rcar_canfd_write(priv->base,
1440                                  RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
1441                 rcar_canfd_write(priv->base,
1442                                  RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1443
1444                 if (can_is_canfd_skb(skb)) {
1445                         /* CAN FD frame format */
1446                         sts |= RCANFD_CFFDCSTS_CFFDF;
1447                         if (cf->flags & CANFD_BRS)
1448                                 sts |= RCANFD_CFFDCSTS_CFBRS;
1449
1450                         if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1451                                 sts |= RCANFD_CFFDCSTS_CFESI;
1452                 }
1453
1454                 rcar_canfd_write(priv->base,
1455                                  RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
1456
1457                 rcar_canfd_put_data(priv, cf,
1458                                     RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1459         } else {
1460                 rcar_canfd_write(priv->base,
1461                                  RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1462                 rcar_canfd_write(priv->base,
1463                                  RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1464                 rcar_canfd_put_data(priv, cf,
1465                                     RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1466         }
1467
1468         priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
1469         can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1470
1471         spin_lock_irqsave(&priv->tx_lock, flags);
1472         priv->tx_head++;
1473
1474         /* Stop the queue if we've filled all FIFO entries */
1475         if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1476                 netif_stop_queue(ndev);
1477
1478         /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1479          * pointer for the Common FIFO
1480          */
1481         rcar_canfd_write(priv->base,
1482                          RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
1483
1484         spin_unlock_irqrestore(&priv->tx_lock, flags);
1485         return NETDEV_TX_OK;
1486 }
1487
1488 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1489 {
1490         struct net_device_stats *stats = &priv->ndev->stats;
1491         struct canfd_frame *cf;
1492         struct sk_buff *skb;
1493         u32 sts = 0, id, dlc;
1494         u32 ch = priv->channel;
1495         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1496
1497         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1498                 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
1499                 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
1500
1501                 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
1502                 if (sts & RCANFD_RFFDSTS_RFFDF)
1503                         skb = alloc_canfd_skb(priv->ndev, &cf);
1504                 else
1505                         skb = alloc_can_skb(priv->ndev,
1506                                             (struct can_frame **)&cf);
1507         } else {
1508                 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1509                 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1510                 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1511         }
1512
1513         if (!skb) {
1514                 stats->rx_dropped++;
1515                 return;
1516         }
1517
1518         if (id & RCANFD_RFID_RFIDE)
1519                 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1520         else
1521                 cf->can_id = id & CAN_SFF_MASK;
1522
1523         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1524                 if (sts & RCANFD_RFFDSTS_RFFDF)
1525                         cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1526                 else
1527                         cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1528
1529                 if (sts & RCANFD_RFFDSTS_RFESI) {
1530                         cf->flags |= CANFD_ESI;
1531                         netdev_dbg(priv->ndev, "ESI Error\n");
1532                 }
1533
1534                 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1535                         cf->can_id |= CAN_RTR_FLAG;
1536                 } else {
1537                         if (sts & RCANFD_RFFDSTS_RFBRS)
1538                                 cf->flags |= CANFD_BRS;
1539
1540                         rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
1541                 }
1542         } else {
1543                 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1544                 if (id & RCANFD_RFID_RFRTR)
1545                         cf->can_id |= CAN_RTR_FLAG;
1546                 else
1547                         rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1548         }
1549
1550         /* Write 0xff to RFPC to increment the CPU-side
1551          * pointer of the Rx FIFO
1552          */
1553         rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
1554
1555         can_led_event(priv->ndev, CAN_LED_EVENT_RX);
1556
1557         stats->rx_bytes += cf->len;
1558         stats->rx_packets++;
1559         netif_receive_skb(skb);
1560 }
1561
1562 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1563 {
1564         struct rcar_canfd_channel *priv =
1565                 container_of(napi, struct rcar_canfd_channel, napi);
1566         int num_pkts;
1567         u32 sts;
1568         u32 ch = priv->channel;
1569         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1570
1571         for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1572                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1573                 /* Check FIFO empty condition */
1574                 if (sts & RCANFD_RFSTS_RFEMP)
1575                         break;
1576
1577                 rcar_canfd_rx_pkt(priv);
1578
1579                 /* Clear interrupt bit */
1580                 if (sts & RCANFD_RFSTS_RFIF)
1581                         rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
1582                                          sts & ~RCANFD_RFSTS_RFIF);
1583         }
1584
1585         /* All packets processed */
1586         if (num_pkts < quota) {
1587                 if (napi_complete_done(napi, num_pkts)) {
1588                         /* Enable Rx FIFO interrupts */
1589                         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
1590                                            RCANFD_RFCC_RFIE);
1591                 }
1592         }
1593         return num_pkts;
1594 }
1595
1596 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1597 {
1598         int err;
1599
1600         switch (mode) {
1601         case CAN_MODE_START:
1602                 err = rcar_canfd_start(ndev);
1603                 if (err)
1604                         return err;
1605                 netif_wake_queue(ndev);
1606                 return 0;
1607         default:
1608                 return -EOPNOTSUPP;
1609         }
1610 }
1611
1612 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1613                                        struct can_berr_counter *bec)
1614 {
1615         struct rcar_canfd_channel *priv = netdev_priv(dev);
1616         u32 val, ch = priv->channel;
1617
1618         /* Peripheral clock is already enabled in probe */
1619         val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1620         bec->txerr = RCANFD_CSTS_TECCNT(val);
1621         bec->rxerr = RCANFD_CSTS_RECCNT(val);
1622         return 0;
1623 }
1624
1625 static const struct net_device_ops rcar_canfd_netdev_ops = {
1626         .ndo_open = rcar_canfd_open,
1627         .ndo_stop = rcar_canfd_close,
1628         .ndo_start_xmit = rcar_canfd_start_xmit,
1629         .ndo_change_mtu = can_change_mtu,
1630 };
1631
1632 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1633                                     u32 fcan_freq)
1634 {
1635         struct platform_device *pdev = gpriv->pdev;
1636         struct rcar_canfd_channel *priv;
1637         struct net_device *ndev;
1638         int err = -ENODEV;
1639
1640         ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1641         if (!ndev) {
1642                 dev_err(&pdev->dev, "alloc_candev() failed\n");
1643                 err = -ENOMEM;
1644                 goto fail;
1645         }
1646         priv = netdev_priv(ndev);
1647
1648         ndev->netdev_ops = &rcar_canfd_netdev_ops;
1649         ndev->flags |= IFF_ECHO;
1650         priv->ndev = ndev;
1651         priv->base = gpriv->base;
1652         priv->channel = ch;
1653         priv->can.clock.freq = fcan_freq;
1654         dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
1655
1656         if (gpriv->chip_id == RENESAS_RZG2L) {
1657                 char *irq_name;
1658                 int err_irq;
1659                 int tx_irq;
1660
1661                 err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
1662                 if (err_irq < 0) {
1663                         err = err_irq;
1664                         goto fail;
1665                 }
1666
1667                 tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
1668                 if (tx_irq < 0) {
1669                         err = tx_irq;
1670                         goto fail;
1671                 }
1672
1673                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
1674                                           "canfd.ch%d_err", ch);
1675                 if (!irq_name) {
1676                         err = -ENOMEM;
1677                         goto fail;
1678                 }
1679                 err = devm_request_irq(&pdev->dev, err_irq,
1680                                        rcar_canfd_channel_err_interrupt, 0,
1681                                        irq_name, gpriv);
1682                 if (err) {
1683                         dev_err(&pdev->dev, "devm_request_irq CH Err(%d) failed, error %d\n",
1684                                 err_irq, err);
1685                         goto fail;
1686                 }
1687                 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
1688                                           "canfd.ch%d_trx", ch);
1689                 if (!irq_name) {
1690                         err = -ENOMEM;
1691                         goto fail;
1692                 }
1693                 err = devm_request_irq(&pdev->dev, tx_irq,
1694                                        rcar_canfd_channel_tx_interrupt, 0,
1695                                        irq_name, gpriv);
1696                 if (err) {
1697                         dev_err(&pdev->dev, "devm_request_irq Tx (%d) failed, error %d\n",
1698                                 tx_irq, err);
1699                         goto fail;
1700                 }
1701         }
1702
1703         if (gpriv->fdmode) {
1704                 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1705                 priv->can.data_bittiming_const =
1706                         &rcar_canfd_data_bittiming_const;
1707
1708                 /* Controller starts in CAN FD only mode */
1709                 can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1710                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1711         } else {
1712                 /* Controller starts in Classical CAN only mode */
1713                 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1714                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1715         }
1716
1717         priv->can.do_set_mode = rcar_canfd_do_set_mode;
1718         priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1719         priv->gpriv = gpriv;
1720         SET_NETDEV_DEV(ndev, &pdev->dev);
1721
1722         netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
1723                        RCANFD_NAPI_WEIGHT);
1724         err = register_candev(ndev);
1725         if (err) {
1726                 dev_err(&pdev->dev,
1727                         "register_candev() failed, error %d\n", err);
1728                 goto fail_candev;
1729         }
1730         spin_lock_init(&priv->tx_lock);
1731         devm_can_led_init(ndev);
1732         gpriv->ch[priv->channel] = priv;
1733         dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
1734         return 0;
1735
1736 fail_candev:
1737         netif_napi_del(&priv->napi);
1738         free_candev(ndev);
1739 fail:
1740         return err;
1741 }
1742
1743 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1744 {
1745         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1746
1747         if (priv) {
1748                 unregister_candev(priv->ndev);
1749                 netif_napi_del(&priv->napi);
1750                 free_candev(priv->ndev);
1751         }
1752 }
1753
1754 static int rcar_canfd_probe(struct platform_device *pdev)
1755 {
1756         void __iomem *addr;
1757         u32 sts, ch, fcan_freq;
1758         struct rcar_canfd_global *gpriv;
1759         struct device_node *of_child;
1760         unsigned long channels_mask = 0;
1761         int err, ch_irq, g_irq;
1762         int g_err_irq, g_recc_irq;
1763         bool fdmode = true;                     /* CAN FD only mode - default */
1764         enum rcanfd_chip_id chip_id;
1765
1766         chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
1767
1768         if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
1769                 fdmode = false;                 /* Classical CAN only mode */
1770
1771         of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
1772         if (of_child && of_device_is_available(of_child))
1773                 channels_mask |= BIT(0);        /* Channel 0 */
1774
1775         of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
1776         if (of_child && of_device_is_available(of_child))
1777                 channels_mask |= BIT(1);        /* Channel 1 */
1778
1779         if (chip_id == RENESAS_RCAR_GEN3) {
1780                 ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
1781                 if (ch_irq < 0) {
1782                         /* For backward compatibility get irq by index */
1783                         ch_irq = platform_get_irq(pdev, 0);
1784                         if (ch_irq < 0)
1785                                 return ch_irq;
1786                 }
1787
1788                 g_irq = platform_get_irq_byname_optional(pdev, "g_int");
1789                 if (g_irq < 0) {
1790                         /* For backward compatibility get irq by index */
1791                         g_irq = platform_get_irq(pdev, 1);
1792                         if (g_irq < 0)
1793                                 return g_irq;
1794                 }
1795         } else {
1796                 g_err_irq = platform_get_irq_byname(pdev, "g_err");
1797                 if (g_err_irq < 0)
1798                         return g_err_irq;
1799
1800                 g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
1801                 if (g_recc_irq < 0)
1802                         return g_recc_irq;
1803         }
1804
1805         /* Global controller context */
1806         gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
1807         if (!gpriv) {
1808                 err = -ENOMEM;
1809                 goto fail_dev;
1810         }
1811         gpriv->pdev = pdev;
1812         gpriv->channels_mask = channels_mask;
1813         gpriv->fdmode = fdmode;
1814         gpriv->chip_id = chip_id;
1815
1816         if (gpriv->chip_id == RENESAS_RZG2L) {
1817                 gpriv->rstc1 = devm_reset_control_get_exclusive(&pdev->dev, "rstp_n");
1818                 if (IS_ERR(gpriv->rstc1))
1819                         return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc1),
1820                                              "failed to get rstp_n\n");
1821
1822                 gpriv->rstc2 = devm_reset_control_get_exclusive(&pdev->dev, "rstc_n");
1823                 if (IS_ERR(gpriv->rstc2))
1824                         return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc2),
1825                                              "failed to get rstc_n\n");
1826         }
1827
1828         /* Peripheral clock */
1829         gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1830         if (IS_ERR(gpriv->clkp)) {
1831                 err = PTR_ERR(gpriv->clkp);
1832                 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
1833                         err);
1834                 goto fail_dev;
1835         }
1836
1837         /* fCAN clock: Pick External clock. If not available fallback to
1838          * CANFD clock
1839          */
1840         gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1841         if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1842                 gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
1843                 if (IS_ERR(gpriv->can_clk)) {
1844                         err = PTR_ERR(gpriv->can_clk);
1845                         dev_err(&pdev->dev,
1846                                 "cannot get canfd clock, error %d\n", err);
1847                         goto fail_dev;
1848                 }
1849                 gpriv->fcan = RCANFD_CANFDCLK;
1850
1851         } else {
1852                 gpriv->fcan = RCANFD_EXTCLK;
1853         }
1854         fcan_freq = clk_get_rate(gpriv->can_clk);
1855
1856         if (gpriv->fcan == RCANFD_CANFDCLK && gpriv->chip_id == RENESAS_RCAR_GEN3)
1857                 /* CANFD clock is further divided by (1/2) within the IP */
1858                 fcan_freq /= 2;
1859
1860         addr = devm_platform_ioremap_resource(pdev, 0);
1861         if (IS_ERR(addr)) {
1862                 err = PTR_ERR(addr);
1863                 goto fail_dev;
1864         }
1865         gpriv->base = addr;
1866
1867         /* Request IRQ that's common for both channels */
1868         if (gpriv->chip_id == RENESAS_RCAR_GEN3) {
1869                 err = devm_request_irq(&pdev->dev, ch_irq,
1870                                        rcar_canfd_channel_interrupt, 0,
1871                                        "canfd.ch_int", gpriv);
1872                 if (err) {
1873                         dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1874                                 ch_irq, err);
1875                         goto fail_dev;
1876                 }
1877
1878                 err = devm_request_irq(&pdev->dev, g_irq,
1879                                        rcar_canfd_global_interrupt, 0,
1880                                        "canfd.g_int", gpriv);
1881                 if (err) {
1882                         dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1883                                 g_irq, err);
1884                         goto fail_dev;
1885                 }
1886         } else {
1887                 err = devm_request_irq(&pdev->dev, g_recc_irq,
1888                                        rcar_canfd_global_receive_fifo_interrupt, 0,
1889                                        "canfd.g_recc", gpriv);
1890
1891                 if (err) {
1892                         dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1893                                 g_recc_irq, err);
1894                         goto fail_dev;
1895                 }
1896
1897                 err = devm_request_irq(&pdev->dev, g_err_irq,
1898                                        rcar_canfd_global_err_interrupt, 0,
1899                                        "canfd.g_err", gpriv);
1900                 if (err) {
1901                         dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1902                                 g_err_irq, err);
1903                         goto fail_dev;
1904                 }
1905         }
1906
1907         err = reset_control_reset(gpriv->rstc1);
1908         if (err)
1909                 goto fail_dev;
1910         err = reset_control_reset(gpriv->rstc2);
1911         if (err) {
1912                 reset_control_assert(gpriv->rstc1);
1913                 goto fail_dev;
1914         }
1915
1916         /* Enable peripheral clock for register access */
1917         err = clk_prepare_enable(gpriv->clkp);
1918         if (err) {
1919                 dev_err(&pdev->dev,
1920                         "failed to enable peripheral clock, error %d\n", err);
1921                 goto fail_reset;
1922         }
1923
1924         err = rcar_canfd_reset_controller(gpriv);
1925         if (err) {
1926                 dev_err(&pdev->dev, "reset controller failed\n");
1927                 goto fail_clk;
1928         }
1929
1930         /* Controller in Global reset & Channel reset mode */
1931         rcar_canfd_configure_controller(gpriv);
1932
1933         /* Configure per channel attributes */
1934         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1935                 /* Configure Channel's Rx fifo */
1936                 rcar_canfd_configure_rx(gpriv, ch);
1937
1938                 /* Configure Channel's Tx (Common) fifo */
1939                 rcar_canfd_configure_tx(gpriv, ch);
1940
1941                 /* Configure receive rules */
1942                 rcar_canfd_configure_afl_rules(gpriv, ch);
1943         }
1944
1945         /* Configure common interrupts */
1946         rcar_canfd_enable_global_interrupts(gpriv);
1947
1948         /* Start Global operation mode */
1949         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
1950                               RCANFD_GCTR_GMDC_GOPM);
1951
1952         /* Verify mode change */
1953         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
1954                                  !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
1955         if (err) {
1956                 dev_err(&pdev->dev, "global operational mode failed\n");
1957                 goto fail_mode;
1958         }
1959
1960         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1961                 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
1962                 if (err)
1963                         goto fail_channel;
1964         }
1965
1966         platform_set_drvdata(pdev, gpriv);
1967         dev_info(&pdev->dev, "global operational state (clk %d, fdmode %d)\n",
1968                  gpriv->fcan, gpriv->fdmode);
1969         return 0;
1970
1971 fail_channel:
1972         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1973                 rcar_canfd_channel_remove(gpriv, ch);
1974 fail_mode:
1975         rcar_canfd_disable_global_interrupts(gpriv);
1976 fail_clk:
1977         clk_disable_unprepare(gpriv->clkp);
1978 fail_reset:
1979         reset_control_assert(gpriv->rstc1);
1980         reset_control_assert(gpriv->rstc2);
1981 fail_dev:
1982         return err;
1983 }
1984
1985 static int rcar_canfd_remove(struct platform_device *pdev)
1986 {
1987         struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
1988         u32 ch;
1989
1990         rcar_canfd_reset_controller(gpriv);
1991         rcar_canfd_disable_global_interrupts(gpriv);
1992
1993         for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1994                 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
1995                 rcar_canfd_channel_remove(gpriv, ch);
1996         }
1997
1998         /* Enter global sleep mode */
1999         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2000         clk_disable_unprepare(gpriv->clkp);
2001         reset_control_assert(gpriv->rstc1);
2002         reset_control_assert(gpriv->rstc2);
2003
2004         return 0;
2005 }
2006
2007 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
2008 {
2009         return 0;
2010 }
2011
2012 static int __maybe_unused rcar_canfd_resume(struct device *dev)
2013 {
2014         return 0;
2015 }
2016
2017 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2018                          rcar_canfd_resume);
2019
2020 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2021         { .compatible = "renesas,rcar-gen3-canfd", .data = (void *)RENESAS_RCAR_GEN3 },
2022         { .compatible = "renesas,rzg2l-canfd", .data = (void *)RENESAS_RZG2L },
2023         { }
2024 };
2025
2026 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2027
2028 static struct platform_driver rcar_canfd_driver = {
2029         .driver = {
2030                 .name = RCANFD_DRV_NAME,
2031                 .of_match_table = of_match_ptr(rcar_canfd_of_table),
2032                 .pm = &rcar_canfd_pm_ops,
2033         },
2034         .probe = rcar_canfd_probe,
2035         .remove = rcar_canfd_remove,
2036 };
2037
2038 module_platform_driver(rcar_canfd_driver);
2039
2040 MODULE_AUTHOR("Ramesh Shanmugasundaram <[email protected]>");
2041 MODULE_LICENSE("GPL");
2042 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2043 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);