drivers/net/can/rcar/rcar_canfd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Renesas R-Car CAN FD device driver
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corp.
   5  */
   6
   7 /* The R-Car CAN FD controller can operate in either one of the below two modes
   8  *  - CAN FD only mode
   9  *  - Classical CAN (CAN 2.0) only mode
  10  *
  11  * This driver puts the controller in CAN FD only mode by default. In this
  12  * mode, the controller acts as a CAN FD node that can also interoperate with
  13  * CAN 2.0 nodes.
  14  *
  15  * To switch the controller to Classical CAN (CAN 2.0) only mode, add
  16  * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
  17  * also required to switch modes.
  18  *
  19  * Note: The h/w manual register naming convention is clumsy and not acceptable
  20  * to use as it is in the driver. However, those names are added as comments
  21  * wherever it is modified to a readable name.
  22  */
  23
  24 #include <linux/bitmap.h>
  25 #include <linux/bitops.h>
  26 #include <linux/can/dev.h>
  27 #include <linux/clk.h>
  28 #include <linux/errno.h>
  29 #include <linux/ethtool.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/iopoll.h>
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/of.h>
  37 #include <linux/phy/phy.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/reset.h>
  40 #include <linux/types.h>
  41
  42 #define RCANFD_DRV_NAME                 "rcar_canfd"
  43
  44 /* Global register bits */
  45
  46 /* RSCFDnCFDGRMCFG */
  47 #define RCANFD_GRMCFG_RCMC              BIT(0)
  48
  49 /* RSCFDnCFDGCFG / RSCFDnGCFG */
  50 #define RCANFD_GCFG_EEFE                BIT(6)
  51 #define RCANFD_GCFG_CMPOC               BIT(5)  /* CAN FD only */
  52 #define RCANFD_GCFG_DCS                 BIT(4)
  53 #define RCANFD_GCFG_DCE                 BIT(1)
  54 #define RCANFD_GCFG_TPRI                BIT(0)
  55
  56 /* RSCFDnCFDGCTR / RSCFDnGCTR */
  57 #define RCANFD_GCTR_TSRST               BIT(16)
  58 #define RCANFD_GCTR_CFMPOFIE            BIT(11) /* CAN FD only */
  59 #define RCANFD_GCTR_THLEIE              BIT(10)
  60 #define RCANFD_GCTR_MEIE                BIT(9)
  61 #define RCANFD_GCTR_DEIE                BIT(8)
  62 #define RCANFD_GCTR_GSLPR               BIT(2)
  63 #define RCANFD_GCTR_GMDC_MASK           (0x3)
  64 #define RCANFD_GCTR_GMDC_GOPM           (0x0)
  65 #define RCANFD_GCTR_GMDC_GRESET         (0x1)
  66 #define RCANFD_GCTR_GMDC_GTEST          (0x2)
  67
  68 /* RSCFDnCFDGSTS / RSCFDnGSTS */
  69 #define RCANFD_GSTS_GRAMINIT            BIT(3)
  70 #define RCANFD_GSTS_GSLPSTS             BIT(2)
  71 #define RCANFD_GSTS_GHLTSTS             BIT(1)
  72 #define RCANFD_GSTS_GRSTSTS             BIT(0)
  73 /* Non-operational status */
  74 #define RCANFD_GSTS_GNOPM               (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  75
  76 /* RSCFDnCFDGERFL / RSCFDnGERFL */
  77 #define RCANFD_GERFL_EEF0_7             GENMASK(23, 16)
  78 #define RCANFD_GERFL_EEF(ch)            BIT(16 + (ch))
  79 #define RCANFD_GERFL_CMPOF              BIT(3)  /* CAN FD only */
  80 #define RCANFD_GERFL_THLES              BIT(2)
  81 #define RCANFD_GERFL_MES                BIT(1)
  82 #define RCANFD_GERFL_DEF                BIT(0)
  83
  84 #define RCANFD_GERFL_ERR(gpriv, x) \
  85         ((x) & (reg_gen4(gpriv, RCANFD_GERFL_EEF0_7, \
  86                          RCANFD_GERFL_EEF(0) | RCANFD_GERFL_EEF(1)) | \
  87                 RCANFD_GERFL_MES | \
  88                 ((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
  89
  90 /* AFL Rx rules registers */
  91
  92 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
  93 #define RCANFD_GAFLCFG_SETRNC(gpriv, n, x) \
  94         (((x) & reg_gen4(gpriv, 0x1ff, 0xff)) << \
  95          (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8)))
  96
  97 #define RCANFD_GAFLCFG_GETRNC(gpriv, n, x) \
  98         (((x) >> (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8))) & \
  99          reg_gen4(gpriv, 0x1ff, 0xff))
 100
 101 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 102 #define RCANFD_GAFLECTR_AFLDAE          BIT(8)
 103 #define RCANFD_GAFLECTR_AFLPN(gpriv, x) ((x) & reg_gen4(gpriv, 0x7f, 0x1f))
 104
 105 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 106 #define RCANFD_GAFLID_GAFLLB            BIT(29)
 107
 108 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
 109 #define RCANFD_GAFLP1_GAFLFDP(x)        (1 << (x))
 110
 111 /* Channel register bits */
 112
 113 /* RSCFDnCmCFG - Classical CAN only */
 114 #define RCANFD_CFG_SJW(x)               (((x) & 0x3) << 24)
 115 #define RCANFD_CFG_TSEG2(x)             (((x) & 0x7) << 20)
 116 #define RCANFD_CFG_TSEG1(x)             (((x) & 0xf) << 16)
 117 #define RCANFD_CFG_BRP(x)               (((x) & 0x3ff) << 0)
 118
 119 /* RSCFDnCFDCmNCFG - CAN FD only */
 120 #define RCANFD_NCFG_NTSEG2(gpriv, x) \
 121         (((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 25, 24))
 122
 123 #define RCANFD_NCFG_NTSEG1(gpriv, x) \
 124         (((x) & reg_gen4(gpriv, 0xff, 0x7f)) << reg_gen4(gpriv, 17, 16))
 125
 126 #define RCANFD_NCFG_NSJW(gpriv, x) \
 127         (((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 10, 11))
 128
 129 #define RCANFD_NCFG_NBRP(x)             (((x) & 0x3ff) << 0)
 130
 131 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 132 #define RCANFD_CCTR_CTME                BIT(24)
 133 #define RCANFD_CCTR_ERRD                BIT(23)
 134 #define RCANFD_CCTR_BOM_MASK            (0x3 << 21)
 135 #define RCANFD_CCTR_BOM_ISO             (0x0 << 21)
 136 #define RCANFD_CCTR_BOM_BENTRY          (0x1 << 21)
 137 #define RCANFD_CCTR_BOM_BEND            (0x2 << 21)
 138 #define RCANFD_CCTR_TDCVFIE             BIT(19)
 139 #define RCANFD_CCTR_SOCOIE              BIT(18)
 140 #define RCANFD_CCTR_EOCOIE              BIT(17)
 141 #define RCANFD_CCTR_TAIE                BIT(16)
 142 #define RCANFD_CCTR_ALIE                BIT(15)
 143 #define RCANFD_CCTR_BLIE                BIT(14)
 144 #define RCANFD_CCTR_OLIE                BIT(13)
 145 #define RCANFD_CCTR_BORIE               BIT(12)
 146 #define RCANFD_CCTR_BOEIE               BIT(11)
 147 #define RCANFD_CCTR_EPIE                BIT(10)
 148 #define RCANFD_CCTR_EWIE                BIT(9)
 149 #define RCANFD_CCTR_BEIE                BIT(8)
 150 #define RCANFD_CCTR_CSLPR               BIT(2)
 151 #define RCANFD_CCTR_CHMDC_MASK          (0x3)
 152 #define RCANFD_CCTR_CHDMC_COPM          (0x0)
 153 #define RCANFD_CCTR_CHDMC_CRESET        (0x1)
 154 #define RCANFD_CCTR_CHDMC_CHLT          (0x2)
 155
 156 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 157 #define RCANFD_CSTS_COMSTS              BIT(7)
 158 #define RCANFD_CSTS_RECSTS              BIT(6)
 159 #define RCANFD_CSTS_TRMSTS              BIT(5)
 160 #define RCANFD_CSTS_BOSTS               BIT(4)
 161 #define RCANFD_CSTS_EPSTS               BIT(3)
 162 #define RCANFD_CSTS_SLPSTS              BIT(2)
 163 #define RCANFD_CSTS_HLTSTS              BIT(1)
 164 #define RCANFD_CSTS_CRSTSTS             BIT(0)
 165
 166 #define RCANFD_CSTS_TECCNT(x)           (((x) >> 24) & 0xff)
 167 #define RCANFD_CSTS_RECCNT(x)           (((x) >> 16) & 0xff)
 168
 169 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 170 #define RCANFD_CERFL_ADERR              BIT(14)
 171 #define RCANFD_CERFL_B0ERR              BIT(13)
 172 #define RCANFD_CERFL_B1ERR              BIT(12)
 173 #define RCANFD_CERFL_CERR               BIT(11)
 174 #define RCANFD_CERFL_AERR               BIT(10)
 175 #define RCANFD_CERFL_FERR               BIT(9)
 176 #define RCANFD_CERFL_SERR               BIT(8)
 177 #define RCANFD_CERFL_ALF                BIT(7)
 178 #define RCANFD_CERFL_BLF                BIT(6)
 179 #define RCANFD_CERFL_OVLF               BIT(5)
 180 #define RCANFD_CERFL_BORF               BIT(4)
 181 #define RCANFD_CERFL_BOEF               BIT(3)
 182 #define RCANFD_CERFL_EPF                BIT(2)
 183 #define RCANFD_CERFL_EWF                BIT(1)
 184 #define RCANFD_CERFL_BEF                BIT(0)
 185
 186 #define RCANFD_CERFL_ERR(x)             ((x) & (0x7fff)) /* above bits 14:0 */
 187
 188 /* RSCFDnCFDCmDCFG */
 189 #define RCANFD_DCFG_DSJW(gpriv, x)      (((x) & reg_gen4(gpriv, 0xf, 0x7)) << 24)
 190
 191 #define RCANFD_DCFG_DTSEG2(gpriv, x) \
 192         (((x) & reg_gen4(gpriv, 0x0f, 0x7)) << reg_gen4(gpriv, 16, 20))
 193
 194 #define RCANFD_DCFG_DTSEG1(gpriv, x) \
 195         (((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 8, 16))
 196
 197 #define RCANFD_DCFG_DBRP(x)             (((x) & 0xff) << 0)
 198
 199 /* RSCFDnCFDCmFDCFG */
 200 #define RCANFD_GEN4_FDCFG_CLOE          BIT(30)
 201 #define RCANFD_GEN4_FDCFG_FDOE          BIT(28)
 202 #define RCANFD_FDCFG_TDCE               BIT(9)
 203 #define RCANFD_FDCFG_TDCOC              BIT(8)
 204 #define RCANFD_FDCFG_TDCO(x)            (((x) & 0x7f) >> 16)
 205
 206 /* RSCFDnCFDRFCCx */
 207 #define RCANFD_RFCC_RFIM                BIT(12)
 208 #define RCANFD_RFCC_RFDC(x)             (((x) & 0x7) << 8)
 209 #define RCANFD_RFCC_RFPLS(x)            (((x) & 0x7) << 4)
 210 #define RCANFD_RFCC_RFIE                BIT(1)
 211 #define RCANFD_RFCC_RFE                 BIT(0)
 212
 213 /* RSCFDnCFDRFSTSx */
 214 #define RCANFD_RFSTS_RFIF               BIT(3)
 215 #define RCANFD_RFSTS_RFMLT              BIT(2)
 216 #define RCANFD_RFSTS_RFFLL              BIT(1)
 217 #define RCANFD_RFSTS_RFEMP              BIT(0)
 218
 219 /* RSCFDnCFDRFIDx */
 220 #define RCANFD_RFID_RFIDE               BIT(31)
 221 #define RCANFD_RFID_RFRTR               BIT(30)
 222
 223 /* RSCFDnCFDRFPTRx */
 224 #define RCANFD_RFPTR_RFDLC(x)           (((x) >> 28) & 0xf)
 225 #define RCANFD_RFPTR_RFPTR(x)           (((x) >> 16) & 0xfff)
 226 #define RCANFD_RFPTR_RFTS(x)            (((x) >> 0) & 0xffff)
 227
 228 /* RSCFDnCFDRFFDSTSx */
 229 #define RCANFD_RFFDSTS_RFFDF            BIT(2)
 230 #define RCANFD_RFFDSTS_RFBRS            BIT(1)
 231 #define RCANFD_RFFDSTS_RFESI            BIT(0)
 232
 233 /* Common FIFO bits */
 234
 235 /* RSCFDnCFDCFCCk */
 236 #define RCANFD_CFCC_CFTML(gpriv, x)     \
 237         (((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 16, 20))
 238 #define RCANFD_CFCC_CFM(gpriv, x)       (((x) & 0x3) << reg_gen4(gpriv,  8, 16))
 239 #define RCANFD_CFCC_CFIM                BIT(12)
 240 #define RCANFD_CFCC_CFDC(gpriv, x)      (((x) & 0x7) << reg_gen4(gpriv, 21,  8))
 241 #define RCANFD_CFCC_CFPLS(x)            (((x) & 0x7) << 4)
 242 #define RCANFD_CFCC_CFTXIE              BIT(2)
 243 #define RCANFD_CFCC_CFE                 BIT(0)
 244
 245 /* RSCFDnCFDCFSTSk */
 246 #define RCANFD_CFSTS_CFMC(x)            (((x) >> 8) & 0xff)
 247 #define RCANFD_CFSTS_CFTXIF             BIT(4)
 248 #define RCANFD_CFSTS_CFMLT              BIT(2)
 249 #define RCANFD_CFSTS_CFFLL              BIT(1)
 250 #define RCANFD_CFSTS_CFEMP              BIT(0)
 251
 252 /* RSCFDnCFDCFIDk */
 253 #define RCANFD_CFID_CFIDE               BIT(31)
 254 #define RCANFD_CFID_CFRTR               BIT(30)
 255 #define RCANFD_CFID_CFID_MASK(x)        ((x) & 0x1fffffff)
 256
 257 /* RSCFDnCFDCFPTRk */
 258 #define RCANFD_CFPTR_CFDLC(x)           (((x) & 0xf) << 28)
 259 #define RCANFD_CFPTR_CFPTR(x)           (((x) & 0xfff) << 16)
 260 #define RCANFD_CFPTR_CFTS(x)            (((x) & 0xff) << 0)
 261
 262 /* RSCFDnCFDCFFDCSTSk */
 263 #define RCANFD_CFFDCSTS_CFFDF           BIT(2)
 264 #define RCANFD_CFFDCSTS_CFBRS           BIT(1)
 265 #define RCANFD_CFFDCSTS_CFESI           BIT(0)
 266
 267 /* This controller supports either Classical CAN only mode or CAN FD only mode.
 268  * These modes are supported in two separate set of register maps & names.
 269  * However, some of the register offsets are common for both modes. Those
 270  * offsets are listed below as Common registers.
 271  *
 272  * The CAN FD only mode specific registers & Classical CAN only mode specific
 273  * registers are listed separately. Their register names starts with
 274  * RCANFD_F_xxx & RCANFD_C_xxx respectively.
 275  */
 276
 277 /* Common registers */
 278
 279 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
 280 #define RCANFD_CCFG(m)                  (0x0000 + (0x10 * (m)))
 281 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 282 #define RCANFD_CCTR(m)                  (0x0004 + (0x10 * (m)))
 283 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 284 #define RCANFD_CSTS(m)                  (0x0008 + (0x10 * (m)))
 285 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 286 #define RCANFD_CERFL(m)                 (0x000C + (0x10 * (m)))
 287
 288 /* RSCFDnCFDGCFG / RSCFDnGCFG */
 289 #define RCANFD_GCFG                     (0x0084)
 290 /* RSCFDnCFDGCTR / RSCFDnGCTR */
 291 #define RCANFD_GCTR                     (0x0088)
 292 /* RSCFDnCFDGCTS / RSCFDnGCTS */
 293 #define RCANFD_GSTS                     (0x008c)
 294 /* RSCFDnCFDGERFL / RSCFDnGERFL */
 295 #define RCANFD_GERFL                    (0x0090)
 296 /* RSCFDnCFDGTSC / RSCFDnGTSC */
 297 #define RCANFD_GTSC                     (0x0094)
 298 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 299 #define RCANFD_GAFLECTR                 (0x0098)
 300 /* RSCFDnCFDGAFLCFG / RSCFDnGAFLCFG */
 301 #define RCANFD_GAFLCFG(ch)              (0x009c + (0x04 * ((ch) / 2)))
 302 /* RSCFDnCFDRMNB / RSCFDnRMNB */
 303 #define RCANFD_RMNB                     (0x00a4)
 304 /* RSCFDnCFDRMND / RSCFDnRMND */
 305 #define RCANFD_RMND(y)                  (0x00a8 + (0x04 * (y)))
 306
 307 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
 308 #define RCANFD_RFCC(gpriv, x)           (reg_gen4(gpriv, 0x00c0, 0x00b8) + (0x04 * (x)))
 309 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
 310 #define RCANFD_RFSTS(gpriv, x)          (RCANFD_RFCC(gpriv, x) + 0x20)
 311 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
 312 #define RCANFD_RFPCTR(gpriv, x)         (RCANFD_RFCC(gpriv, x) + 0x40)
 313
 314 /* Common FIFO Control registers */
 315
 316 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
 317 #define RCANFD_CFCC(gpriv, ch, idx) \
 318         (reg_gen4(gpriv, 0x0120, 0x0118) + (0x0c * (ch)) + (0x04 * (idx)))
 319 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
 320 #define RCANFD_CFSTS(gpriv, ch, idx) \
 321         (reg_gen4(gpriv, 0x01e0, 0x0178) + (0x0c * (ch)) + (0x04 * (idx)))
 322 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
 323 #define RCANFD_CFPCTR(gpriv, ch, idx) \
 324         (reg_gen4(gpriv, 0x0240, 0x01d8) + (0x0c * (ch)) + (0x04 * (idx)))
 325
 326 /* RSCFDnCFDFESTS / RSCFDnFESTS */
 327 #define RCANFD_FESTS                    (0x0238)
 328 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
 329 #define RCANFD_FFSTS                    (0x023c)
 330 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
 331 #define RCANFD_FMSTS                    (0x0240)
 332 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
 333 #define RCANFD_RFISTS                   (0x0244)
 334 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
 335 #define RCANFD_CFRISTS                  (0x0248)
 336 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
 337 #define RCANFD_CFTISTS                  (0x024c)
 338
 339 /* RSCFDnCFDTMCp / RSCFDnTMCp */
 340 #define RCANFD_TMC(p)                   (0x0250 + (0x01 * (p)))
 341 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
 342 #define RCANFD_TMSTS(p)                 (0x02d0 + (0x01 * (p)))
 343
 344 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
 345 #define RCANFD_TMTRSTS(y)               (0x0350 + (0x04 * (y)))
 346 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
 347 #define RCANFD_TMTARSTS(y)              (0x0360 + (0x04 * (y)))
 348 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
 349 #define RCANFD_TMTCSTS(y)               (0x0370 + (0x04 * (y)))
 350 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
 351 #define RCANFD_TMTASTS(y)               (0x0380 + (0x04 * (y)))
 352 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
 353 #define RCANFD_TMIEC(y)                 (0x0390 + (0x04 * (y)))
 354
 355 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
 356 #define RCANFD_TXQCC(m)                 (0x03a0 + (0x04 * (m)))
 357 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
 358 #define RCANFD_TXQSTS(m)                (0x03c0 + (0x04 * (m)))
 359 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
 360 #define RCANFD_TXQPCTR(m)               (0x03e0 + (0x04 * (m)))
 361
 362 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
 363 #define RCANFD_THLCC(m)                 (0x0400 + (0x04 * (m)))
 364 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
 365 #define RCANFD_THLSTS(m)                (0x0420 + (0x04 * (m)))
 366 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
 367 #define RCANFD_THLPCTR(m)               (0x0440 + (0x04 * (m)))
 368
 369 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
 370 #define RCANFD_GTINTSTS0                (0x0460)
 371 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
 372 #define RCANFD_GTINTSTS1                (0x0464)
 373 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
 374 #define RCANFD_GTSTCFG                  (0x0468)
 375 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
 376 #define RCANFD_GTSTCTR                  (0x046c)
 377 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
 378 #define RCANFD_GLOCKK                   (0x047c)
 379 /* RSCFDnCFDGRMCFG */
 380 #define RCANFD_GRMCFG                   (0x04fc)
 381
 382 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 383 #define RCANFD_GAFLID(offset, j)        ((offset) + (0x10 * (j)))
 384 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
 385 #define RCANFD_GAFLM(offset, j)         ((offset) + 0x04 + (0x10 * (j)))
 386 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
 387 #define RCANFD_GAFLP0(offset, j)        ((offset) + 0x08 + (0x10 * (j)))
 388 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
 389 #define RCANFD_GAFLP1(offset, j)        ((offset) + 0x0c + (0x10 * (j)))
 390
 391 /* Classical CAN only mode register map */
 392
 393 /* RSCFDnGAFLXXXj offset */
 394 #define RCANFD_C_GAFL_OFFSET            (0x0500)
 395
 396 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
 397 #define RCANFD_C_RMID(q)                (0x0600 + (0x10 * (q)))
 398 #define RCANFD_C_RMPTR(q)               (0x0604 + (0x10 * (q)))
 399 #define RCANFD_C_RMDF0(q)               (0x0608 + (0x10 * (q)))
 400 #define RCANFD_C_RMDF1(q)               (0x060c + (0x10 * (q)))
 401
 402 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
 403 #define RCANFD_C_RFOFFSET       (0x0e00)
 404 #define RCANFD_C_RFID(x)        (RCANFD_C_RFOFFSET + (0x10 * (x)))
 405 #define RCANFD_C_RFPTR(x)       (RCANFD_C_RFOFFSET + 0x04 + (0x10 * (x)))
 406 #define RCANFD_C_RFDF(x, df) \
 407                 (RCANFD_C_RFOFFSET + 0x08 + (0x10 * (x)) + (0x04 * (df)))
 408
 409 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
 410 #define RCANFD_C_CFOFFSET               (0x0e80)
 411
 412 #define RCANFD_C_CFID(ch, idx) \
 413         (RCANFD_C_CFOFFSET + (0x30 * (ch)) + (0x10 * (idx)))
 414
 415 #define RCANFD_C_CFPTR(ch, idx) \
 416         (RCANFD_C_CFOFFSET + 0x04 + (0x30 * (ch)) + (0x10 * (idx)))
 417
 418 #define RCANFD_C_CFDF(ch, idx, df) \
 419         (RCANFD_C_CFOFFSET + 0x08 + (0x30 * (ch)) + (0x10 * (idx)) + (0x04 * (df)))
 420
 421 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
 422 #define RCANFD_C_TMID(p)                (0x1000 + (0x10 * (p)))
 423 #define RCANFD_C_TMPTR(p)               (0x1004 + (0x10 * (p)))
 424 #define RCANFD_C_TMDF0(p)               (0x1008 + (0x10 * (p)))
 425 #define RCANFD_C_TMDF1(p)               (0x100c + (0x10 * (p)))
 426
 427 /* RSCFDnTHLACCm */
 428 #define RCANFD_C_THLACC(m)              (0x1800 + (0x04 * (m)))
 429 /* RSCFDnRPGACCr */
 430 #define RCANFD_C_RPGACC(r)              (0x1900 + (0x04 * (r)))
 431
 432 /* R-Car Gen4 Classical and CAN FD mode specific register map */
 433 #define RCANFD_GEN4_FDCFG(m)            (0x1404 + (0x20 * (m)))
 434
 435 #define RCANFD_GEN4_GAFL_OFFSET         (0x1800)
 436
 437 /* CAN FD mode specific register map */
 438
 439 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
 440 #define RCANFD_F_DCFG(gpriv, m)         (reg_gen4(gpriv, 0x1400, 0x0500) + (0x20 * (m)))
 441 #define RCANFD_F_CFDCFG(m)              (0x0504 + (0x20 * (m)))
 442 #define RCANFD_F_CFDCTR(m)              (0x0508 + (0x20 * (m)))
 443 #define RCANFD_F_CFDSTS(m)              (0x050c + (0x20 * (m)))
 444 #define RCANFD_F_CFDCRC(m)              (0x0510 + (0x20 * (m)))
 445
 446 /* RSCFDnCFDGAFLXXXj offset */
 447 #define RCANFD_F_GAFL_OFFSET            (0x1000)
 448
 449 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
 450 #define RCANFD_F_RMID(q)                (0x2000 + (0x20 * (q)))
 451 #define RCANFD_F_RMPTR(q)               (0x2004 + (0x20 * (q)))
 452 #define RCANFD_F_RMFDSTS(q)             (0x2008 + (0x20 * (q)))
 453 #define RCANFD_F_RMDF(q, b)             (0x200c + (0x04 * (b)) + (0x20 * (q)))
 454
 455 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
 456 #define RCANFD_F_RFOFFSET(gpriv)        reg_gen4(gpriv, 0x6000, 0x3000)
 457 #define RCANFD_F_RFID(gpriv, x)         (RCANFD_F_RFOFFSET(gpriv) + (0x80 * (x)))
 458 #define RCANFD_F_RFPTR(gpriv, x)        (RCANFD_F_RFOFFSET(gpriv) + 0x04 + (0x80 * (x)))
 459 #define RCANFD_F_RFFDSTS(gpriv, x)      (RCANFD_F_RFOFFSET(gpriv) + 0x08 + (0x80 * (x)))
 460 #define RCANFD_F_RFDF(gpriv, x, df) \
 461         (RCANFD_F_RFOFFSET(gpriv) + 0x0c + (0x80 * (x)) + (0x04 * (df)))
 462
 463 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
 464 #define RCANFD_F_CFOFFSET(gpriv)        reg_gen4(gpriv, 0x6400, 0x3400)
 465
 466 #define RCANFD_F_CFID(gpriv, ch, idx) \
 467         (RCANFD_F_CFOFFSET(gpriv) + (0x180 * (ch)) + (0x80 * (idx)))
 468
 469 #define RCANFD_F_CFPTR(gpriv, ch, idx) \
 470         (RCANFD_F_CFOFFSET(gpriv) + 0x04 + (0x180 * (ch)) + (0x80 * (idx)))
 471
 472 #define RCANFD_F_CFFDCSTS(gpriv, ch, idx) \
 473         (RCANFD_F_CFOFFSET(gpriv) + 0x08 + (0x180 * (ch)) + (0x80 * (idx)))
 474
 475 #define RCANFD_F_CFDF(gpriv, ch, idx, df) \
 476         (RCANFD_F_CFOFFSET(gpriv) + 0x0c + (0x180 * (ch)) + (0x80 * (idx)) + \
 477          (0x04 * (df)))
 478
 479 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
 480 #define RCANFD_F_TMID(p)                (0x4000 + (0x20 * (p)))
 481 #define RCANFD_F_TMPTR(p)               (0x4004 + (0x20 * (p)))
 482 #define RCANFD_F_TMFDCTR(p)             (0x4008 + (0x20 * (p)))
 483 #define RCANFD_F_TMDF(p, b)             (0x400c + (0x20 * (p)) + (0x04 * (b)))
 484
 485 /* RSCFDnCFDTHLACCm */
 486 #define RCANFD_F_THLACC(m)              (0x6000 + (0x04 * (m)))
 487 /* RSCFDnCFDRPGACCr */
 488 #define RCANFD_F_RPGACC(r)              (0x6400 + (0x04 * (r)))
 489
 490 /* Constants */
 491 #define RCANFD_FIFO_DEPTH               8       /* Tx FIFO depth */
 492 #define RCANFD_NAPI_WEIGHT              8       /* Rx poll quota */
 493
 494 #define RCANFD_NUM_CHANNELS             8       /* Eight channels max */
 495 #define RCANFD_CHANNELS_MASK            BIT((RCANFD_NUM_CHANNELS) - 1)
 496
 497 #define RCANFD_GAFL_PAGENUM(entry)      ((entry) / 16)
 498 #define RCANFD_CHANNEL_NUMRULES         1       /* only one rule per channel */
 499
 500 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
 501  * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
 502  * number is added to RFFIFO index.
 503  */
 504 #define RCANFD_RFFIFO_IDX               0
 505
 506 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
 507  * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
 508  */
 509 #define RCANFD_CFFIFO_IDX               0
 510
 511 struct rcar_canfd_global;
 512
 513 struct rcar_canfd_hw_info {
 514         u8 max_channels;
 515         u8 postdiv;
 516         /* hardware features */
 517         unsigned shared_global_irqs:1;  /* Has shared global irqs */
 518         unsigned multi_channel_irqs:1;  /* Has multiple channel irqs */
 519 };
 520
 521 /* Channel priv data */
 522 struct rcar_canfd_channel {
 523         struct can_priv can;                    /* Must be the first member */
 524         struct net_device *ndev;
 525         struct rcar_canfd_global *gpriv;        /* Controller reference */
 526         void __iomem *base;                     /* Register base address */
 527         struct phy *transceiver;                /* Optional transceiver */
 528         struct napi_struct napi;
 529         u32 tx_head;                            /* Incremented on xmit */
 530         u32 tx_tail;                            /* Incremented on xmit done */
 531         u32 channel;                            /* Channel number */
 532         spinlock_t tx_lock;                     /* To protect tx path */
 533 };
 534
 535 /* Global priv data */
 536 struct rcar_canfd_global {
 537         struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
 538         void __iomem *base;             /* Register base address */
 539         struct platform_device *pdev;   /* Respective platform device */
 540         struct clk *clkp;               /* Peripheral clock */
 541         struct clk *can_clk;            /* fCAN clock */
 542         unsigned long channels_mask;    /* Enabled channels mask */
 543         bool extclk;                    /* CANFD or Ext clock */
 544         bool fdmode;                    /* CAN FD or Classical CAN only mode */
 545         struct reset_control *rstc1;
 546         struct reset_control *rstc2;
 547         const struct rcar_canfd_hw_info *info;
 548 };
 549
 550 /* CAN FD mode nominal rate constants */
 551 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
 552         .name = RCANFD_DRV_NAME,
 553         .tseg1_min = 2,
 554         .tseg1_max = 128,
 555         .tseg2_min = 2,
 556         .tseg2_max = 32,
 557         .sjw_max = 32,
 558         .brp_min = 1,
 559         .brp_max = 1024,
 560         .brp_inc = 1,
 561 };
 562
 563 /* CAN FD mode data rate constants */
 564 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
 565         .name = RCANFD_DRV_NAME,
 566         .tseg1_min = 2,
 567         .tseg1_max = 16,
 568         .tseg2_min = 2,
 569         .tseg2_max = 8,
 570         .sjw_max = 8,
 571         .brp_min = 1,
 572         .brp_max = 256,
 573         .brp_inc = 1,
 574 };
 575
 576 /* Classical CAN mode bitrate constants */
 577 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
 578         .name = RCANFD_DRV_NAME,
 579         .tseg1_min = 4,
 580         .tseg1_max = 16,
 581         .tseg2_min = 2,
 582         .tseg2_max = 8,
 583         .sjw_max = 4,
 584         .brp_min = 1,
 585         .brp_max = 1024,
 586         .brp_inc = 1,
 587 };
 588
 589 static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
 590         .max_channels = 2,
 591         .postdiv = 2,
 592         .shared_global_irqs = 1,
 593 };
 594
 595 static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
 596         .max_channels = 8,
 597         .postdiv = 2,
 598         .shared_global_irqs = 1,
 599 };
 600
 601 static const struct rcar_canfd_hw_info rzg2l_hw_info = {
 602         .max_channels = 2,
 603         .postdiv = 1,
 604         .multi_channel_irqs = 1,
 605 };
 606
 607 /* Helper functions */
 608 static inline bool is_gen4(struct rcar_canfd_global *gpriv)
 609 {
 610         return gpriv->info == &rcar_gen4_hw_info;
 611 }
 612
 613 static inline u32 reg_gen4(struct rcar_canfd_global *gpriv,
 614                            u32 gen4, u32 not_gen4)
 615 {
 616         return is_gen4(gpriv) ? gen4 : not_gen4;
 617 }
 618
 619 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
 620 {
 621         u32 data = readl(reg);
 622
 623         data &= ~mask;
 624         data |= (val & mask);
 625         writel(data, reg);
 626 }
 627
 628 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
 629 {
 630         return readl(base + offset);
 631 }
 632
 633 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
 634 {
 635         writel(val, base + offset);
 636 }
 637
 638 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
 639 {
 640         rcar_canfd_update(val, val, base + reg);
 641 }
 642
 643 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
 644 {
 645         rcar_canfd_update(val, 0, base + reg);
 646 }
 647
 648 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
 649                                   u32 mask, u32 val)
 650 {
 651         rcar_canfd_update(mask, val, base + reg);
 652 }
 653
 654 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
 655                                 struct canfd_frame *cf, u32 off)
 656 {
 657         u32 i, lwords;
 658
 659         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 660         for (i = 0; i < lwords; i++)
 661                 *((u32 *)cf->data + i) =
 662                         rcar_canfd_read(priv->base, off + i * sizeof(u32));
 663 }
 664
 665 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
 666                                 struct canfd_frame *cf, u32 off)
 667 {
 668         u32 i, lwords;
 669
 670         lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 671         for (i = 0; i < lwords; i++)
 672                 rcar_canfd_write(priv->base, off + i * sizeof(u32),
 673                                  *((u32 *)cf->data + i));
 674 }
 675
 676 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
 677 {
 678         u32 i;
 679
 680         for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
 681                 can_free_echo_skb(ndev, i, NULL);
 682 }
 683
 684 static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv)
 685 {
 686         if (is_gen4(gpriv)) {
 687                 u32 ch, val = gpriv->fdmode ? RCANFD_GEN4_FDCFG_FDOE
 688                                             : RCANFD_GEN4_FDCFG_CLOE;
 689
 690                 for_each_set_bit(ch, &gpriv->channels_mask,
 691                                  gpriv->info->max_channels)
 692                         rcar_canfd_set_bit(gpriv->base, RCANFD_GEN4_FDCFG(ch),
 693                                            val);
 694         } else {
 695                 if (gpriv->fdmode)
 696                         rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 697                                            RCANFD_GRMCFG_RCMC);
 698                 else
 699                         rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
 700                                              RCANFD_GRMCFG_RCMC);
 701         }
 702 }
 703
 704 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 705 {
 706         u32 sts, ch;
 707         int err;
 708
 709         /* Check RAMINIT flag as CAN RAM initialization takes place
 710          * after the MCU reset
 711          */
 712         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 713                                  !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
 714         if (err) {
 715                 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
 716                 return err;
 717         }
 718
 719         /* Transition to Global Reset mode */
 720         rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
 721         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
 722                               RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
 723
 724         /* Ensure Global reset mode */
 725         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 726                                  (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
 727         if (err) {
 728                 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
 729                 return err;
 730         }
 731
 732         /* Reset Global error flags */
 733         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 734
 735         /* Set the controller into appropriate mode */
 736         rcar_canfd_set_mode(gpriv);
 737
 738         /* Transition all Channels to reset mode */
 739         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
 740                 rcar_canfd_clear_bit(gpriv->base,
 741                                      RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 742
 743                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 744                                       RCANFD_CCTR_CHMDC_MASK,
 745                                       RCANFD_CCTR_CHDMC_CRESET);
 746
 747                 /* Ensure Channel reset mode */
 748                 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
 749                                          (sts & RCANFD_CSTS_CRSTSTS),
 750                                          2, 500000);
 751                 if (err) {
 752                         dev_dbg(&gpriv->pdev->dev,
 753                                 "channel %u reset failed\n", ch);
 754                         return err;
 755                 }
 756         }
 757         return 0;
 758 }
 759
 760 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 761 {
 762         u32 cfg, ch;
 763
 764         /* Global configuration settings */
 765
 766         /* ECC Error flag Enable */
 767         cfg = RCANFD_GCFG_EEFE;
 768
 769         if (gpriv->fdmode)
 770                 /* Truncate payload to configured message size RFPLS */
 771                 cfg |= RCANFD_GCFG_CMPOC;
 772
 773         /* Set External Clock if selected */
 774         if (gpriv->extclk)
 775                 cfg |= RCANFD_GCFG_DCS;
 776
 777         rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 778
 779         /* Channel configuration settings */
 780         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
 781                 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
 782                                    RCANFD_CCTR_ERRD);
 783                 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 784                                       RCANFD_CCTR_BOM_MASK,
 785                                       RCANFD_CCTR_BOM_BENTRY);
 786         }
 787 }
 788
 789 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 790                                            u32 ch)
 791 {
 792         u32 cfg;
 793         int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 794         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 795
 796         if (ch == 0) {
 797                 start = 0; /* Channel 0 always starts from 0th rule */
 798         } else {
 799                 /* Get number of Channel 0 rules and adjust */
 800                 cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG(ch));
 801                 start = RCANFD_GAFLCFG_GETRNC(gpriv, 0, cfg);
 802         }
 803
 804         /* Enable write access to entry */
 805         page = RCANFD_GAFL_PAGENUM(start);
 806         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 807                            (RCANFD_GAFLECTR_AFLPN(gpriv, page) |
 808                             RCANFD_GAFLECTR_AFLDAE));
 809
 810         /* Write number of rules for channel */
 811         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(ch),
 812                            RCANFD_GAFLCFG_SETRNC(gpriv, ch, num_rules));
 813         if (is_gen4(gpriv))
 814                 offset = RCANFD_GEN4_GAFL_OFFSET;
 815         else if (gpriv->fdmode)
 816                 offset = RCANFD_F_GAFL_OFFSET;
 817         else
 818                 offset = RCANFD_C_GAFL_OFFSET;
 819
 820         /* Accept all IDs */
 821         rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
 822         /* IDE or RTR is not considered for matching */
 823         rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
 824         /* Any data length accepted */
 825         rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
 826         /* Place the msg in corresponding Rx FIFO entry */
 827         rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, start),
 828                            RCANFD_GAFLP1_GAFLFDP(ridx));
 829
 830         /* Disable write access to page */
 831         rcar_canfd_clear_bit(gpriv->base,
 832                              RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
 833 }
 834
 835 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 836 {
 837         /* Rx FIFO is used for reception */
 838         u32 cfg;
 839         u16 rfdc, rfpls;
 840
 841         /* Select Rx FIFO based on channel */
 842         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 843
 844         rfdc = 2;               /* b010 - 8 messages Rx FIFO depth */
 845         if (gpriv->fdmode)
 846                 rfpls = 7;      /* b111 - Max 64 bytes payload */
 847         else
 848                 rfpls = 0;      /* b000 - Max 8 bytes payload */
 849
 850         cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 851                 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 852         rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
 853 }
 854
 855 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 856 {
 857         /* Tx/Rx(Common) FIFO configured in Tx mode is
 858          * used for transmission
 859          *
 860          * Each channel has 3 Common FIFO dedicated to them.
 861          * Use the 1st (index 0) out of 3
 862          */
 863         u32 cfg;
 864         u16 cftml, cfm, cfdc, cfpls;
 865
 866         cftml = 0;              /* 0th buffer */
 867         cfm = 1;                /* b01 - Transmit mode */
 868         cfdc = 2;               /* b010 - 8 messages Tx FIFO depth */
 869         if (gpriv->fdmode)
 870                 cfpls = 7;      /* b111 - Max 64 bytes payload */
 871         else
 872                 cfpls = 0;      /* b000 - Max 8 bytes payload */
 873
 874         cfg = (RCANFD_CFCC_CFTML(gpriv, cftml) | RCANFD_CFCC_CFM(gpriv, cfm) |
 875                 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(gpriv, cfdc) |
 876                 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
 877         rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
 878
 879         if (gpriv->fdmode)
 880                 /* Clear FD mode specific control/status register */
 881                 rcar_canfd_write(gpriv->base,
 882                                  RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 0);
 883 }
 884
 885 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 886 {
 887         u32 ctr;
 888
 889         /* Clear any stray error interrupt flags */
 890         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 891
 892         /* Global interrupts setup */
 893         ctr = RCANFD_GCTR_MEIE;
 894         if (gpriv->fdmode)
 895                 ctr |= RCANFD_GCTR_CFMPOFIE;
 896
 897         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 898 }
 899
 900 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
 901                                                  *gpriv)
 902 {
 903         /* Disable all interrupts */
 904         rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
 905
 906         /* Clear any stray error interrupt flags */
 907         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 908 }
 909
 910 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
 911                                                  *priv)
 912 {
 913         u32 ctr, ch = priv->channel;
 914
 915         /* Clear any stray error flags */
 916         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 917
 918         /* Channel interrupts setup */
 919         ctr = (RCANFD_CCTR_TAIE |
 920                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 921                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 922                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 923                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 924         rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
 925 }
 926
 927 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
 928                                                   *priv)
 929 {
 930         u32 ctr, ch = priv->channel;
 931
 932         ctr = (RCANFD_CCTR_TAIE |
 933                RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 934                RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 935                RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 936                RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 937         rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
 938
 939         /* Clear any stray error flags */
 940         rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 941 }
 942
 943 static void rcar_canfd_global_error(struct net_device *ndev)
 944 {
 945         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 946         struct rcar_canfd_global *gpriv = priv->gpriv;
 947         struct net_device_stats *stats = &ndev->stats;
 948         u32 ch = priv->channel;
 949         u32 gerfl, sts;
 950         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 951
 952         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
 953         if (gerfl & RCANFD_GERFL_EEF(ch)) {
 954                 netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch);
 955                 stats->tx_dropped++;
 956         }
 957         if (gerfl & RCANFD_GERFL_MES) {
 958                 sts = rcar_canfd_read(priv->base,
 959                                       RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
 960                 if (sts & RCANFD_CFSTS_CFMLT) {
 961                         netdev_dbg(ndev, "Tx Message Lost flag\n");
 962                         stats->tx_dropped++;
 963                         rcar_canfd_write(priv->base,
 964                                          RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
 965                                          sts & ~RCANFD_CFSTS_CFMLT);
 966                 }
 967
 968                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
 969                 if (sts & RCANFD_RFSTS_RFMLT) {
 970                         netdev_dbg(ndev, "Rx Message Lost flag\n");
 971                         stats->rx_dropped++;
 972                         rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
 973                                          sts & ~RCANFD_RFSTS_RFMLT);
 974                 }
 975         }
 976         if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
 977                 /* Message Lost flag will be set for respective channel
 978                  * when this condition happens with counters and flags
 979                  * already updated.
 980                  */
 981                 netdev_dbg(ndev, "global payload overflow interrupt\n");
 982         }
 983
 984         /* Clear all global error interrupts. Only affected channels bits
 985          * get cleared
 986          */
 987         rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
 988 }
 989
 990 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
 991                              u16 txerr, u16 rxerr)
 992 {
 993         struct rcar_canfd_channel *priv = netdev_priv(ndev);
 994         struct net_device_stats *stats = &ndev->stats;
 995         struct can_frame *cf;
 996         struct sk_buff *skb;
 997         u32 ch = priv->channel;
 998
 999         netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
1000
1001         /* Propagate the error condition to the CAN stack */
1002         skb = alloc_can_err_skb(ndev, &cf);
1003         if (!skb) {
1004                 stats->rx_dropped++;
1005                 return;
1006         }
1007
1008         /* Channel error interrupts */
1009         if (cerfl & RCANFD_CERFL_BEF) {
1010                 netdev_dbg(ndev, "Bus error\n");
1011                 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1012                 cf->data[2] = CAN_ERR_PROT_UNSPEC;
1013                 priv->can.can_stats.bus_error++;
1014         }
1015         if (cerfl & RCANFD_CERFL_ADERR) {
1016                 netdev_dbg(ndev, "ACK Delimiter Error\n");
1017                 stats->tx_errors++;
1018                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1019         }
1020         if (cerfl & RCANFD_CERFL_B0ERR) {
1021                 netdev_dbg(ndev, "Bit Error (dominant)\n");
1022                 stats->tx_errors++;
1023                 cf->data[2] |= CAN_ERR_PROT_BIT0;
1024         }
1025         if (cerfl & RCANFD_CERFL_B1ERR) {
1026                 netdev_dbg(ndev, "Bit Error (recessive)\n");
1027                 stats->tx_errors++;
1028                 cf->data[2] |= CAN_ERR_PROT_BIT1;
1029         }
1030         if (cerfl & RCANFD_CERFL_CERR) {
1031                 netdev_dbg(ndev, "CRC Error\n");
1032                 stats->rx_errors++;
1033                 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1034         }
1035         if (cerfl & RCANFD_CERFL_AERR) {
1036                 netdev_dbg(ndev, "ACK Error\n");
1037                 stats->tx_errors++;
1038                 cf->can_id |= CAN_ERR_ACK;
1039                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1040         }
1041         if (cerfl & RCANFD_CERFL_FERR) {
1042                 netdev_dbg(ndev, "Form Error\n");
1043                 stats->rx_errors++;
1044                 cf->data[2] |= CAN_ERR_PROT_FORM;
1045         }
1046         if (cerfl & RCANFD_CERFL_SERR) {
1047                 netdev_dbg(ndev, "Stuff Error\n");
1048                 stats->rx_errors++;
1049                 cf->data[2] |= CAN_ERR_PROT_STUFF;
1050         }
1051         if (cerfl & RCANFD_CERFL_ALF) {
1052                 netdev_dbg(ndev, "Arbitration lost Error\n");
1053                 priv->can.can_stats.arbitration_lost++;
1054                 cf->can_id |= CAN_ERR_LOSTARB;
1055                 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1056         }
1057         if (cerfl & RCANFD_CERFL_BLF) {
1058                 netdev_dbg(ndev, "Bus Lock Error\n");
1059                 stats->rx_errors++;
1060                 cf->can_id |= CAN_ERR_BUSERROR;
1061         }
1062         if (cerfl & RCANFD_CERFL_EWF) {
1063                 netdev_dbg(ndev, "Error warning interrupt\n");
1064                 priv->can.state = CAN_STATE_ERROR_WARNING;
1065                 priv->can.can_stats.error_warning++;
1066                 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1067                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1068                         CAN_ERR_CRTL_RX_WARNING;
1069                 cf->data[6] = txerr;
1070                 cf->data[7] = rxerr;
1071         }
1072         if (cerfl & RCANFD_CERFL_EPF) {
1073                 netdev_dbg(ndev, "Error passive interrupt\n");
1074                 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1075                 priv->can.can_stats.error_passive++;
1076                 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1077                 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1078                         CAN_ERR_CRTL_RX_PASSIVE;
1079                 cf->data[6] = txerr;
1080                 cf->data[7] = rxerr;
1081         }
1082         if (cerfl & RCANFD_CERFL_BOEF) {
1083                 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1084                 rcar_canfd_tx_failure_cleanup(ndev);
1085                 priv->can.state = CAN_STATE_BUS_OFF;
1086                 priv->can.can_stats.bus_off++;
1087                 can_bus_off(ndev);
1088                 cf->can_id |= CAN_ERR_BUSOFF;
1089         }
1090         if (cerfl & RCANFD_CERFL_OVLF) {
1091                 netdev_dbg(ndev,
1092                            "Overload Frame Transmission error interrupt\n");
1093                 stats->tx_errors++;
1094                 cf->can_id |= CAN_ERR_PROT;
1095                 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1096         }
1097
1098         /* Clear channel error interrupts that are handled */
1099         rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1100                          RCANFD_CERFL_ERR(~cerfl));
1101         netif_rx(skb);
1102 }
1103
1104 static void rcar_canfd_tx_done(struct net_device *ndev)
1105 {
1106         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1107         struct rcar_canfd_global *gpriv = priv->gpriv;
1108         struct net_device_stats *stats = &ndev->stats;
1109         u32 sts;
1110         unsigned long flags;
1111         u32 ch = priv->channel;
1112
1113         do {
1114                 u8 unsent, sent;
1115
1116                 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1117                 stats->tx_packets++;
1118                 stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
1119
1120                 spin_lock_irqsave(&priv->tx_lock, flags);
1121                 priv->tx_tail++;
1122                 sts = rcar_canfd_read(priv->base,
1123                                       RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1124                 unsent = RCANFD_CFSTS_CFMC(sts);
1125
1126                 /* Wake producer only when there is room */
1127                 if (unsent != RCANFD_FIFO_DEPTH)
1128                         netif_wake_queue(ndev);
1129
1130                 if (priv->tx_head - priv->tx_tail <= unsent) {
1131                         spin_unlock_irqrestore(&priv->tx_lock, flags);
1132                         break;
1133                 }
1134                 spin_unlock_irqrestore(&priv->tx_lock, flags);
1135
1136         } while (1);
1137
1138         /* Clear interrupt */
1139         rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1140                          sts & ~RCANFD_CFSTS_CFTXIF);
1141 }
1142
1143 static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1144 {
1145         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1146         struct net_device *ndev = priv->ndev;
1147         u32 gerfl;
1148
1149         /* Handle global error interrupts */
1150         gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1151         if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1152                 rcar_canfd_global_error(ndev);
1153 }
1154
1155 static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1156 {
1157         struct rcar_canfd_global *gpriv = dev_id;
1158         u32 ch;
1159
1160         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1161                 rcar_canfd_handle_global_err(gpriv, ch);
1162
1163         return IRQ_HANDLED;
1164 }
1165
1166 static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1167 {
1168         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1169         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1170         u32 sts, cc;
1171
1172         /* Handle Rx interrupts */
1173         sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1174         cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx));
1175         if (likely(sts & RCANFD_RFSTS_RFIF &&
1176                    cc & RCANFD_RFCC_RFIE)) {
1177                 if (napi_schedule_prep(&priv->napi)) {
1178                         /* Disable Rx FIFO interrupts */
1179                         rcar_canfd_clear_bit(priv->base,
1180                                              RCANFD_RFCC(gpriv, ridx),
1181                                              RCANFD_RFCC_RFIE);
1182                         __napi_schedule(&priv->napi);
1183                 }
1184         }
1185 }
1186
1187 static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1188 {
1189         struct rcar_canfd_global *gpriv = dev_id;
1190         u32 ch;
1191
1192         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1193                 rcar_canfd_handle_global_receive(gpriv, ch);
1194
1195         return IRQ_HANDLED;
1196 }
1197
1198 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1199 {
1200         struct rcar_canfd_global *gpriv = dev_id;
1201         u32 ch;
1202
1203         /* Global error interrupts still indicate a condition specific
1204          * to a channel. RxFIFO interrupt is a global interrupt.
1205          */
1206         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1207                 rcar_canfd_handle_global_err(gpriv, ch);
1208                 rcar_canfd_handle_global_receive(gpriv, ch);
1209         }
1210         return IRQ_HANDLED;
1211 }
1212
1213 static void rcar_canfd_state_change(struct net_device *ndev,
1214                                     u16 txerr, u16 rxerr)
1215 {
1216         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1217         struct net_device_stats *stats = &ndev->stats;
1218         enum can_state rx_state, tx_state, state = priv->can.state;
1219         struct can_frame *cf;
1220         struct sk_buff *skb;
1221
1222         /* Handle transition from error to normal states */
1223         if (txerr < 96 && rxerr < 96)
1224                 state = CAN_STATE_ERROR_ACTIVE;
1225         else if (txerr < 128 && rxerr < 128)
1226                 state = CAN_STATE_ERROR_WARNING;
1227
1228         if (state != priv->can.state) {
1229                 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1230                            state, priv->can.state, txerr, rxerr);
1231                 skb = alloc_can_err_skb(ndev, &cf);
1232                 if (!skb) {
1233                         stats->rx_dropped++;
1234                         return;
1235                 }
1236                 tx_state = txerr >= rxerr ? state : 0;
1237                 rx_state = txerr <= rxerr ? state : 0;
1238
1239                 can_change_state(ndev, cf, tx_state, rx_state);
1240                 netif_rx(skb);
1241         }
1242 }
1243
1244 static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1245 {
1246         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1247         struct net_device *ndev = priv->ndev;
1248         u32 sts;
1249
1250         /* Handle Tx interrupts */
1251         sts = rcar_canfd_read(priv->base,
1252                               RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1253         if (likely(sts & RCANFD_CFSTS_CFTXIF))
1254                 rcar_canfd_tx_done(ndev);
1255 }
1256
1257 static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1258 {
1259         struct rcar_canfd_channel *priv = dev_id;
1260
1261         rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1262
1263         return IRQ_HANDLED;
1264 }
1265
1266 static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1267 {
1268         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1269         struct net_device *ndev = priv->ndev;
1270         u16 txerr, rxerr;
1271         u32 sts, cerfl;
1272
1273         /* Handle channel error interrupts */
1274         cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1275         sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1276         txerr = RCANFD_CSTS_TECCNT(sts);
1277         rxerr = RCANFD_CSTS_RECCNT(sts);
1278         if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1279                 rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1280
1281         /* Handle state change to lower states */
1282         if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1283                      priv->can.state != CAN_STATE_BUS_OFF))
1284                 rcar_canfd_state_change(ndev, txerr, rxerr);
1285 }
1286
1287 static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1288 {
1289         struct rcar_canfd_channel *priv = dev_id;
1290
1291         rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1292
1293         return IRQ_HANDLED;
1294 }
1295
1296 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1297 {
1298         struct rcar_canfd_global *gpriv = dev_id;
1299         u32 ch;
1300
1301         /* Common FIFO is a per channel resource */
1302         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1303                 rcar_canfd_handle_channel_err(gpriv, ch);
1304                 rcar_canfd_handle_channel_tx(gpriv, ch);
1305         }
1306
1307         return IRQ_HANDLED;
1308 }
1309
1310 static void rcar_canfd_set_bittiming(struct net_device *dev)
1311 {
1312         struct rcar_canfd_channel *priv = netdev_priv(dev);
1313         struct rcar_canfd_global *gpriv = priv->gpriv;
1314         const struct can_bittiming *bt = &priv->can.bittiming;
1315         const struct can_bittiming *dbt = &priv->can.data_bittiming;
1316         u16 brp, sjw, tseg1, tseg2;
1317         u32 cfg;
1318         u32 ch = priv->channel;
1319
1320         /* Nominal bit timing settings */
1321         brp = bt->brp - 1;
1322         sjw = bt->sjw - 1;
1323         tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1324         tseg2 = bt->phase_seg2 - 1;
1325
1326         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1327                 /* CAN FD only mode */
1328                 cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | RCANFD_NCFG_NBRP(brp) |
1329                        RCANFD_NCFG_NSJW(gpriv, sjw) | RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1330
1331                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1332                 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1333                            brp, sjw, tseg1, tseg2);
1334
1335                 /* Data bit timing settings */
1336                 brp = dbt->brp - 1;
1337                 sjw = dbt->sjw - 1;
1338                 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1339                 tseg2 = dbt->phase_seg2 - 1;
1340
1341                 cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
1342                        RCANFD_DCFG_DSJW(gpriv, sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
1343
1344                 rcar_canfd_write(priv->base, RCANFD_F_DCFG(gpriv, ch), cfg);
1345                 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1346                            brp, sjw, tseg1, tseg2);
1347         } else {
1348                 /* Classical CAN only mode */
1349                 if (is_gen4(gpriv)) {
1350                         cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) |
1351                                RCANFD_NCFG_NBRP(brp) |
1352                                RCANFD_NCFG_NSJW(gpriv, sjw) |
1353                                RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1354                 } else {
1355                         cfg = (RCANFD_CFG_TSEG1(tseg1) |
1356                                RCANFD_CFG_BRP(brp) |
1357                                RCANFD_CFG_SJW(sjw) |
1358                                RCANFD_CFG_TSEG2(tseg2));
1359                 }
1360
1361                 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1362                 netdev_dbg(priv->ndev,
1363                            "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1364                            brp, sjw, tseg1, tseg2);
1365         }
1366 }
1367
1368 static int rcar_canfd_start(struct net_device *ndev)
1369 {
1370         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1371         struct rcar_canfd_global *gpriv = priv->gpriv;
1372         int err = -EOPNOTSUPP;
1373         u32 sts, ch = priv->channel;
1374         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1375
1376         rcar_canfd_set_bittiming(ndev);
1377
1378         rcar_canfd_enable_channel_interrupts(priv);
1379
1380         /* Set channel to Operational mode */
1381         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1382                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1383
1384         /* Verify channel mode change */
1385         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1386                                  (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1387         if (err) {
1388                 netdev_err(ndev, "channel %u communication state failed\n", ch);
1389                 goto fail_mode_change;
1390         }
1391
1392         /* Enable Common & Rx FIFO */
1393         rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1394                            RCANFD_CFCC_CFE);
1395         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1396
1397         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1398         return 0;
1399
1400 fail_mode_change:
1401         rcar_canfd_disable_channel_interrupts(priv);
1402         return err;
1403 }
1404
1405 static int rcar_canfd_open(struct net_device *ndev)
1406 {
1407         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1408         struct rcar_canfd_global *gpriv = priv->gpriv;
1409         int err;
1410
1411         err = phy_power_on(priv->transceiver);
1412         if (err) {
1413                 netdev_err(ndev, "failed to power on PHY: %pe\n", ERR_PTR(err));
1414                 return err;
1415         }
1416
1417         /* Peripheral clock is already enabled in probe */
1418         err = clk_prepare_enable(gpriv->can_clk);
1419         if (err) {
1420                 netdev_err(ndev, "failed to enable CAN clock: %pe\n", ERR_PTR(err));
1421                 goto out_phy;
1422         }
1423
1424         err = open_candev(ndev);
1425         if (err) {
1426                 netdev_err(ndev, "open_candev() failed: %pe\n", ERR_PTR(err));
1427                 goto out_can_clock;
1428         }
1429
1430         napi_enable(&priv->napi);
1431         err = rcar_canfd_start(ndev);
1432         if (err)
1433                 goto out_close;
1434         netif_start_queue(ndev);
1435         return 0;
1436 out_close:
1437         napi_disable(&priv->napi);
1438         close_candev(ndev);
1439 out_can_clock:
1440         clk_disable_unprepare(gpriv->can_clk);
1441 out_phy:
1442         phy_power_off(priv->transceiver);
1443         return err;
1444 }
1445
1446 static void rcar_canfd_stop(struct net_device *ndev)
1447 {
1448         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1449         struct rcar_canfd_global *gpriv = priv->gpriv;
1450         int err;
1451         u32 sts, ch = priv->channel;
1452         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1453
1454         /* Transition to channel reset mode  */
1455         rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1456                               RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1457
1458         /* Check Channel reset mode */
1459         err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1460                                  (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1461         if (err)
1462                 netdev_err(ndev, "channel %u reset failed\n", ch);
1463
1464         rcar_canfd_disable_channel_interrupts(priv);
1465
1466         /* Disable Common & Rx FIFO */
1467         rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1468                              RCANFD_CFCC_CFE);
1469         rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1470
1471         /* Set the state as STOPPED */
1472         priv->can.state = CAN_STATE_STOPPED;
1473 }
1474
1475 static int rcar_canfd_close(struct net_device *ndev)
1476 {
1477         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1478         struct rcar_canfd_global *gpriv = priv->gpriv;
1479
1480         netif_stop_queue(ndev);
1481         rcar_canfd_stop(ndev);
1482         napi_disable(&priv->napi);
1483         clk_disable_unprepare(gpriv->can_clk);
1484         close_candev(ndev);
1485         phy_power_off(priv->transceiver);
1486         return 0;
1487 }
1488
1489 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1490                                          struct net_device *ndev)
1491 {
1492         struct rcar_canfd_channel *priv = netdev_priv(ndev);
1493         struct rcar_canfd_global *gpriv = priv->gpriv;
1494         struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1495         u32 sts = 0, id, dlc;
1496         unsigned long flags;
1497         u32 ch = priv->channel;
1498
1499         if (can_dev_dropped_skb(ndev, skb))
1500                 return NETDEV_TX_OK;
1501
1502         if (cf->can_id & CAN_EFF_FLAG) {
1503                 id = cf->can_id & CAN_EFF_MASK;
1504                 id |= RCANFD_CFID_CFIDE;
1505         } else {
1506                 id = cf->can_id & CAN_SFF_MASK;
1507         }
1508
1509         if (cf->can_id & CAN_RTR_FLAG)
1510                 id |= RCANFD_CFID_CFRTR;
1511
1512         dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1513
1514         if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1515                 rcar_canfd_write(priv->base,
1516                                  RCANFD_F_CFID(gpriv, ch, RCANFD_CFFIFO_IDX), id);
1517                 rcar_canfd_write(priv->base,
1518                                  RCANFD_F_CFPTR(gpriv, ch, RCANFD_CFFIFO_IDX), dlc);
1519
1520                 if (can_is_canfd_skb(skb)) {
1521                         /* CAN FD frame format */
1522                         sts |= RCANFD_CFFDCSTS_CFFDF;
1523                         if (cf->flags & CANFD_BRS)
1524                                 sts |= RCANFD_CFFDCSTS_CFBRS;
1525
1526                         if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1527                                 sts |= RCANFD_CFFDCSTS_CFESI;
1528                 }
1529
1530                 rcar_canfd_write(priv->base,
1531                                  RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), sts);
1532
1533                 rcar_canfd_put_data(priv, cf,
1534                                     RCANFD_F_CFDF(gpriv, ch, RCANFD_CFFIFO_IDX, 0));
1535         } else {
1536                 rcar_canfd_write(priv->base,
1537                                  RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1538                 rcar_canfd_write(priv->base,
1539                                  RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1540                 rcar_canfd_put_data(priv, cf,
1541                                     RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1542         }
1543
1544         can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1545
1546         spin_lock_irqsave(&priv->tx_lock, flags);
1547         priv->tx_head++;
1548
1549         /* Stop the queue if we've filled all FIFO entries */
1550         if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1551                 netif_stop_queue(ndev);
1552
1553         /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1554          * pointer for the Common FIFO
1555          */
1556         rcar_canfd_write(priv->base,
1557                          RCANFD_CFPCTR(gpriv, ch, RCANFD_CFFIFO_IDX), 0xff);
1558
1559         spin_unlock_irqrestore(&priv->tx_lock, flags);
1560         return NETDEV_TX_OK;
1561 }
1562
1563 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1564 {
1565         struct net_device_stats *stats = &priv->ndev->stats;
1566         struct rcar_canfd_global *gpriv = priv->gpriv;
1567         struct canfd_frame *cf;
1568         struct sk_buff *skb;
1569         u32 sts = 0, id, dlc;
1570         u32 ch = priv->channel;
1571         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1572
1573         if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1574                 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1575                 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1576
1577                 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1578
1579                 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1580                     sts & RCANFD_RFFDSTS_RFFDF)
1581                         skb = alloc_canfd_skb(priv->ndev, &cf);
1582                 else
1583                         skb = alloc_can_skb(priv->ndev,
1584                                             (struct can_frame **)&cf);
1585         } else {
1586                 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1587                 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1588                 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1589         }
1590
1591         if (!skb) {
1592                 stats->rx_dropped++;
1593                 return;
1594         }
1595
1596         if (id & RCANFD_RFID_RFIDE)
1597                 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1598         else
1599                 cf->can_id = id & CAN_SFF_MASK;
1600
1601         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1602                 if (sts & RCANFD_RFFDSTS_RFFDF)
1603                         cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1604                 else
1605                         cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1606
1607                 if (sts & RCANFD_RFFDSTS_RFESI) {
1608                         cf->flags |= CANFD_ESI;
1609                         netdev_dbg(priv->ndev, "ESI Error\n");
1610                 }
1611
1612                 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1613                         cf->can_id |= CAN_RTR_FLAG;
1614                 } else {
1615                         if (sts & RCANFD_RFFDSTS_RFBRS)
1616                                 cf->flags |= CANFD_BRS;
1617
1618                         rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1619                 }
1620         } else {
1621                 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1622                 if (id & RCANFD_RFID_RFRTR)
1623                         cf->can_id |= CAN_RTR_FLAG;
1624                 else if (is_gen4(gpriv))
1625                         rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1626                 else
1627                         rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1628         }
1629
1630         /* Write 0xff to RFPC to increment the CPU-side
1631          * pointer of the Rx FIFO
1632          */
1633         rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
1634
1635         if (!(cf->can_id & CAN_RTR_FLAG))
1636                 stats->rx_bytes += cf->len;
1637         stats->rx_packets++;
1638         netif_receive_skb(skb);
1639 }
1640
1641 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1642 {
1643         struct rcar_canfd_channel *priv =
1644                 container_of(napi, struct rcar_canfd_channel, napi);
1645         struct rcar_canfd_global *gpriv = priv->gpriv;
1646         int num_pkts;
1647         u32 sts;
1648         u32 ch = priv->channel;
1649         u32 ridx = ch + RCANFD_RFFIFO_IDX;
1650
1651         for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1652                 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1653                 /* Check FIFO empty condition */
1654                 if (sts & RCANFD_RFSTS_RFEMP)
1655                         break;
1656
1657                 rcar_canfd_rx_pkt(priv);
1658
1659                 /* Clear interrupt bit */
1660                 if (sts & RCANFD_RFSTS_RFIF)
1661                         rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1662                                          sts & ~RCANFD_RFSTS_RFIF);
1663         }
1664
1665         /* All packets processed */
1666         if (num_pkts < quota) {
1667                 if (napi_complete_done(napi, num_pkts)) {
1668                         /* Enable Rx FIFO interrupts */
1669                         rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1670                                            RCANFD_RFCC_RFIE);
1671                 }
1672         }
1673         return num_pkts;
1674 }
1675
1676 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1677 {
1678         int err;
1679
1680         switch (mode) {
1681         case CAN_MODE_START:
1682                 err = rcar_canfd_start(ndev);
1683                 if (err)
1684                         return err;
1685                 netif_wake_queue(ndev);
1686                 return 0;
1687         default:
1688                 return -EOPNOTSUPP;
1689         }
1690 }
1691
1692 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1693                                        struct can_berr_counter *bec)
1694 {
1695         struct rcar_canfd_channel *priv = netdev_priv(dev);
1696         u32 val, ch = priv->channel;
1697
1698         /* Peripheral clock is already enabled in probe */
1699         val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1700         bec->txerr = RCANFD_CSTS_TECCNT(val);
1701         bec->rxerr = RCANFD_CSTS_RECCNT(val);
1702         return 0;
1703 }
1704
1705 static const struct net_device_ops rcar_canfd_netdev_ops = {
1706         .ndo_open = rcar_canfd_open,
1707         .ndo_stop = rcar_canfd_close,
1708         .ndo_start_xmit = rcar_canfd_start_xmit,
1709         .ndo_change_mtu = can_change_mtu,
1710 };
1711
1712 static const struct ethtool_ops rcar_canfd_ethtool_ops = {
1713         .get_ts_info = ethtool_op_get_ts_info,
1714 };
1715
1716 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1717                                     u32 fcan_freq, struct phy *transceiver)
1718 {
1719         const struct rcar_canfd_hw_info *info = gpriv->info;
1720         struct platform_device *pdev = gpriv->pdev;
1721         struct device *dev = &pdev->dev;
1722         struct rcar_canfd_channel *priv;
1723         struct net_device *ndev;
1724         int err = -ENODEV;
1725
1726         ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1727         if (!ndev)
1728                 return -ENOMEM;
1729
1730         priv = netdev_priv(ndev);
1731
1732         ndev->netdev_ops = &rcar_canfd_netdev_ops;
1733         ndev->ethtool_ops = &rcar_canfd_ethtool_ops;
1734         ndev->flags |= IFF_ECHO;
1735         priv->ndev = ndev;
1736         priv->base = gpriv->base;
1737         priv->transceiver = transceiver;
1738         priv->channel = ch;
1739         priv->gpriv = gpriv;
1740         if (transceiver)
1741                 priv->can.bitrate_max = transceiver->attrs.max_link_rate;
1742         priv->can.clock.freq = fcan_freq;
1743         dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
1744
1745         if (info->multi_channel_irqs) {
1746                 char *irq_name;
1747                 int err_irq;
1748                 int tx_irq;
1749
1750                 err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
1751                 if (err_irq < 0) {
1752                         err = err_irq;
1753                         goto fail;
1754                 }
1755
1756                 tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
1757                 if (tx_irq < 0) {
1758                         err = tx_irq;
1759                         goto fail;
1760                 }
1761
1762                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_err",
1763                                           ch);
1764                 if (!irq_name) {
1765                         err = -ENOMEM;
1766                         goto fail;
1767                 }
1768                 err = devm_request_irq(dev, err_irq,
1769                                        rcar_canfd_channel_err_interrupt, 0,
1770                                        irq_name, priv);
1771                 if (err) {
1772                         dev_err(dev, "devm_request_irq CH Err %d failed: %pe\n",
1773                                 err_irq, ERR_PTR(err));
1774                         goto fail;
1775                 }
1776                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_trx",
1777                                           ch);
1778                 if (!irq_name) {
1779                         err = -ENOMEM;
1780                         goto fail;
1781                 }
1782                 err = devm_request_irq(dev, tx_irq,
1783                                        rcar_canfd_channel_tx_interrupt, 0,
1784                                        irq_name, priv);
1785                 if (err) {
1786                         dev_err(dev, "devm_request_irq Tx %d failed: %pe\n",
1787                                 tx_irq, ERR_PTR(err));
1788                         goto fail;
1789                 }
1790         }
1791
1792         if (gpriv->fdmode) {
1793                 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1794                 priv->can.data_bittiming_const =
1795                         &rcar_canfd_data_bittiming_const;
1796
1797                 /* Controller starts in CAN FD only mode */
1798                 err = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1799                 if (err)
1800                         goto fail;
1801                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1802         } else {
1803                 /* Controller starts in Classical CAN only mode */
1804                 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1805                 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1806         }
1807
1808         priv->can.do_set_mode = rcar_canfd_do_set_mode;
1809         priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1810         SET_NETDEV_DEV(ndev, dev);
1811
1812         netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1813                               RCANFD_NAPI_WEIGHT);
1814         spin_lock_init(&priv->tx_lock);
1815         gpriv->ch[priv->channel] = priv;
1816         err = register_candev(ndev);
1817         if (err) {
1818                 dev_err(dev, "register_candev() failed: %pe\n", ERR_PTR(err));
1819                 goto fail_candev;
1820         }
1821         dev_info(dev, "device registered (channel %u)\n", priv->channel);
1822         return 0;
1823
1824 fail_candev:
1825         netif_napi_del(&priv->napi);
1826 fail:
1827         free_candev(ndev);
1828         return err;
1829 }
1830
1831 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1832 {
1833         struct rcar_canfd_channel *priv = gpriv->ch[ch];
1834
1835         if (priv) {
1836                 unregister_candev(priv->ndev);
1837                 netif_napi_del(&priv->napi);
1838                 free_candev(priv->ndev);
1839         }
1840 }
1841
1842 static int rcar_canfd_probe(struct platform_device *pdev)
1843 {
1844         struct phy *transceivers[RCANFD_NUM_CHANNELS] = { NULL, };
1845         const struct rcar_canfd_hw_info *info;
1846         struct device *dev = &pdev->dev;
1847         void __iomem *addr;
1848         u32 sts, ch, fcan_freq;
1849         struct rcar_canfd_global *gpriv;
1850         struct device_node *of_child;
1851         unsigned long channels_mask = 0;
1852         int err, ch_irq, g_irq;
1853         int g_err_irq, g_recc_irq;
1854         bool fdmode = true;                     /* CAN FD only mode - default */
1855         char name[9] = "channelX";
1856         int i;
1857
1858         info = of_device_get_match_data(dev);
1859
1860         if (of_property_read_bool(dev->of_node, "renesas,no-can-fd"))
1861                 fdmode = false;                 /* Classical CAN only mode */
1862
1863         for (i = 0; i < info->max_channels; ++i) {
1864                 name[7] = '0' + i;
1865                 of_child = of_get_child_by_name(dev->of_node, name);
1866                 if (of_child && of_device_is_available(of_child)) {
1867                         channels_mask |= BIT(i);
1868                         transceivers[i] = devm_of_phy_optional_get(dev,
1869                                                         of_child, NULL);
1870                 }
1871                 of_node_put(of_child);
1872                 if (IS_ERR(transceivers[i]))
1873                         return PTR_ERR(transceivers[i]);
1874         }
1875
1876         if (info->shared_global_irqs) {
1877                 ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
1878                 if (ch_irq < 0) {
1879                         /* For backward compatibility get irq by index */
1880                         ch_irq = platform_get_irq(pdev, 0);
1881                         if (ch_irq < 0)
1882                                 return ch_irq;
1883                 }
1884
1885                 g_irq = platform_get_irq_byname_optional(pdev, "g_int");
1886                 if (g_irq < 0) {
1887                         /* For backward compatibility get irq by index */
1888                         g_irq = platform_get_irq(pdev, 1);
1889                         if (g_irq < 0)
1890                                 return g_irq;
1891                 }
1892         } else {
1893                 g_err_irq = platform_get_irq_byname(pdev, "g_err");
1894                 if (g_err_irq < 0)
1895                         return g_err_irq;
1896
1897                 g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
1898                 if (g_recc_irq < 0)
1899                         return g_recc_irq;
1900         }
1901
1902         /* Global controller context */
1903         gpriv = devm_kzalloc(dev, sizeof(*gpriv), GFP_KERNEL);
1904         if (!gpriv)
1905                 return -ENOMEM;
1906
1907         gpriv->pdev = pdev;
1908         gpriv->channels_mask = channels_mask;
1909         gpriv->fdmode = fdmode;
1910         gpriv->info = info;
1911
1912         gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
1913         if (IS_ERR(gpriv->rstc1))
1914                 return dev_err_probe(dev, PTR_ERR(gpriv->rstc1),
1915                                      "failed to get rstp_n\n");
1916
1917         gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
1918         if (IS_ERR(gpriv->rstc2))
1919                 return dev_err_probe(dev, PTR_ERR(gpriv->rstc2),
1920                                      "failed to get rstc_n\n");
1921
1922         /* Peripheral clock */
1923         gpriv->clkp = devm_clk_get(dev, "fck");
1924         if (IS_ERR(gpriv->clkp))
1925                 return dev_err_probe(dev, PTR_ERR(gpriv->clkp),
1926                                      "cannot get peripheral clock\n");
1927
1928         /* fCAN clock: Pick External clock. If not available fallback to
1929          * CANFD clock
1930          */
1931         gpriv->can_clk = devm_clk_get(dev, "can_clk");
1932         if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1933                 gpriv->can_clk = devm_clk_get(dev, "canfd");
1934                 if (IS_ERR(gpriv->can_clk))
1935                         return dev_err_probe(dev, PTR_ERR(gpriv->can_clk),
1936                                              "cannot get canfd clock\n");
1937
1938                 /* CANFD clock may be further divided within the IP */
1939                 fcan_freq = clk_get_rate(gpriv->can_clk) / info->postdiv;
1940         } else {
1941                 fcan_freq = clk_get_rate(gpriv->can_clk);
1942                 gpriv->extclk = true;
1943         }
1944
1945         addr = devm_platform_ioremap_resource(pdev, 0);
1946         if (IS_ERR(addr)) {
1947                 err = PTR_ERR(addr);
1948                 goto fail_dev;
1949         }
1950         gpriv->base = addr;
1951
1952         /* Request IRQ that's common for both channels */
1953         if (info->shared_global_irqs) {
1954                 err = devm_request_irq(dev, ch_irq,
1955                                        rcar_canfd_channel_interrupt, 0,
1956                                        "canfd.ch_int", gpriv);
1957                 if (err) {
1958                         dev_err(dev, "devm_request_irq %d failed: %pe\n",
1959                                 ch_irq, ERR_PTR(err));
1960                         goto fail_dev;
1961                 }
1962
1963                 err = devm_request_irq(dev, g_irq, rcar_canfd_global_interrupt,
1964                                        0, "canfd.g_int", gpriv);
1965                 if (err) {
1966                         dev_err(dev, "devm_request_irq %d failed: %pe\n",
1967                                 g_irq, ERR_PTR(err));
1968                         goto fail_dev;
1969                 }
1970         } else {
1971                 err = devm_request_irq(dev, g_recc_irq,
1972                                        rcar_canfd_global_receive_fifo_interrupt, 0,
1973                                        "canfd.g_recc", gpriv);
1974
1975                 if (err) {
1976                         dev_err(dev, "devm_request_irq %d failed: %pe\n",
1977                                 g_recc_irq, ERR_PTR(err));
1978                         goto fail_dev;
1979                 }
1980
1981                 err = devm_request_irq(dev, g_err_irq,
1982                                        rcar_canfd_global_err_interrupt, 0,
1983                                        "canfd.g_err", gpriv);
1984                 if (err) {
1985                         dev_err(dev, "devm_request_irq %d failed: %pe\n",
1986                                 g_err_irq, ERR_PTR(err));
1987                         goto fail_dev;
1988                 }
1989         }
1990
1991         err = reset_control_reset(gpriv->rstc1);
1992         if (err)
1993                 goto fail_dev;
1994         err = reset_control_reset(gpriv->rstc2);
1995         if (err) {
1996                 reset_control_assert(gpriv->rstc1);
1997                 goto fail_dev;
1998         }
1999
2000         /* Enable peripheral clock for register access */
2001         err = clk_prepare_enable(gpriv->clkp);
2002         if (err) {
2003                 dev_err(dev, "failed to enable peripheral clock: %pe\n",
2004                         ERR_PTR(err));
2005                 goto fail_reset;
2006         }
2007
2008         err = rcar_canfd_reset_controller(gpriv);
2009         if (err) {
2010                 dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err));
2011                 goto fail_clk;
2012         }
2013
2014         /* Controller in Global reset & Channel reset mode */
2015         rcar_canfd_configure_controller(gpriv);
2016
2017         /* Configure per channel attributes */
2018         for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2019                 /* Configure Channel's Rx fifo */
2020                 rcar_canfd_configure_rx(gpriv, ch);
2021
2022                 /* Configure Channel's Tx (Common) fifo */
2023                 rcar_canfd_configure_tx(gpriv, ch);
2024
2025                 /* Configure receive rules */
2026                 rcar_canfd_configure_afl_rules(gpriv, ch);
2027         }
2028
2029         /* Configure common interrupts */
2030         rcar_canfd_enable_global_interrupts(gpriv);
2031
2032         /* Start Global operation mode */
2033         rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2034                               RCANFD_GCTR_GMDC_GOPM);
2035
2036         /* Verify mode change */
2037         err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2038                                  !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
2039         if (err) {
2040                 dev_err(dev, "global operational mode failed\n");
2041                 goto fail_mode;
2042         }
2043
2044         for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2045                 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq,
2046                                                transceivers[ch]);
2047                 if (err)
2048                         goto fail_channel;
2049         }
2050
2051         platform_set_drvdata(pdev, gpriv);
2052         dev_info(dev, "global operational state (%s clk, %s mode)\n",
2053                  gpriv->extclk ? "ext" : "canfd",
2054                  gpriv->fdmode ? "fd" : "classical");
2055         return 0;
2056
2057 fail_channel:
2058         for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
2059                 rcar_canfd_channel_remove(gpriv, ch);
2060 fail_mode:
2061         rcar_canfd_disable_global_interrupts(gpriv);
2062 fail_clk:
2063         clk_disable_unprepare(gpriv->clkp);
2064 fail_reset:
2065         reset_control_assert(gpriv->rstc1);
2066         reset_control_assert(gpriv->rstc2);
2067 fail_dev:
2068         return err;
2069 }
2070
2071 static void rcar_canfd_remove(struct platform_device *pdev)
2072 {
2073         struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
2074         u32 ch;
2075
2076         rcar_canfd_reset_controller(gpriv);
2077         rcar_canfd_disable_global_interrupts(gpriv);
2078
2079         for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2080                 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2081                 rcar_canfd_channel_remove(gpriv, ch);
2082         }
2083
2084         /* Enter global sleep mode */
2085         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2086         clk_disable_unprepare(gpriv->clkp);
2087         reset_control_assert(gpriv->rstc1);
2088         reset_control_assert(gpriv->rstc2);
2089 }
2090
2091 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
2092 {
2093         return 0;
2094 }
2095
2096 static int __maybe_unused rcar_canfd_resume(struct device *dev)
2097 {
2098         return 0;
2099 }
2100
2101 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2102                          rcar_canfd_resume);
2103
2104 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2105         { .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info },
2106         { .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info },
2107         { .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info },
2108         { .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },
2109         { }
2110 };
2111
2112 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2113
2114 static struct platform_driver rcar_canfd_driver = {
2115         .driver = {
2116                 .name = RCANFD_DRV_NAME,
2117                 .of_match_table = of_match_ptr(rcar_canfd_of_table),
2118                 .pm = &rcar_canfd_pm_ops,
2119         },
2120         .probe = rcar_canfd_probe,
2121         .remove = rcar_canfd_remove,
2122 };
2123
2124 module_platform_driver(rcar_canfd_driver);
2125
2126 MODULE_AUTHOR("Ramesh Shanmugasundaram <[email protected]>");
2127 MODULE_LICENSE("GPL");
2128 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2129 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);