drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <[email protected]>
   7  *          Mika Westerberg <[email protected]>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/cleanup.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/log2.h>
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/property.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/string_helpers.h>
  20 #include <linux/time.h>
  21
  22 #include <linux/pinctrl/consumer.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinmux.h>
  27
  28 #include <linux/platform_data/x86/pwm-lpss.h>
  29
  30 #include "../core.h"
  31 #include "pinctrl-intel.h"
  32
  33 /* Offset from regs */
  34 #define REVID                           0x000
  35 #define REVID_SHIFT                     16
  36 #define REVID_MASK                      GENMASK(31, 16)
  37
  38 #define CAPLIST                         0x004
  39 #define CAPLIST_ID_SHIFT                16
  40 #define CAPLIST_ID_MASK                 GENMASK(23, 16)
  41 #define CAPLIST_ID_GPIO_HW_INFO         1
  42 #define CAPLIST_ID_PWM                  2
  43 #define CAPLIST_ID_BLINK                3
  44 #define CAPLIST_ID_EXP                  4
  45 #define CAPLIST_NEXT_SHIFT              0
  46 #define CAPLIST_NEXT_MASK               GENMASK(15, 0)
  47
  48 #define PADBAR                          0x00c
  49
  50 #define PADOWN_BITS                     4
  51 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  52 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  53 #define PADOWN_GPP(p)                   ((p) / 8)
  54
  55 #define PWMC                            0x204
  56
  57 /* Offset from pad_regs */
  58 #define PADCFG0                         0x000
  59 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  60 #define PADCFG0_RXEVCFG_LEVEL           (0 << 25)
  61 #define PADCFG0_RXEVCFG_EDGE            (1 << 25)
  62 #define PADCFG0_RXEVCFG_DISABLED        (2 << 25)
  63 #define PADCFG0_RXEVCFG_EDGE_BOTH       (3 << 25)
  64 #define PADCFG0_PREGFRXSEL              BIT(24)
  65 #define PADCFG0_RXINV                   BIT(23)
  66 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  67 #define PADCFG0_GPIROUTSCI              BIT(19)
  68 #define PADCFG0_GPIROUTSMI              BIT(18)
  69 #define PADCFG0_GPIROUTNMI              BIT(17)
  70 #define PADCFG0_PMODE_SHIFT             10
  71 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  72 #define PADCFG0_PMODE_GPIO              0
  73 #define PADCFG0_GPIORXDIS               BIT(9)
  74 #define PADCFG0_GPIOTXDIS               BIT(8)
  75 #define PADCFG0_GPIORXSTATE             BIT(1)
  76 #define PADCFG0_GPIOTXSTATE             BIT(0)
  77
  78 #define PADCFG1                         0x004
  79 #define PADCFG1_TERM_UP                 BIT(13)
  80 #define PADCFG1_TERM_SHIFT              10
  81 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  82 #define PADCFG1_TERM_20K                BIT(2)
  83 #define PADCFG1_TERM_5K                 BIT(1)
  84 #define PADCFG1_TERM_4K                 (BIT(2) | BIT(1))
  85 #define PADCFG1_TERM_1K                 BIT(0)
  86 #define PADCFG1_TERM_952                (BIT(2) | BIT(0))
  87 #define PADCFG1_TERM_833                (BIT(1) | BIT(0))
  88 #define PADCFG1_TERM_800                (BIT(2) | BIT(1) | BIT(0))
  89
  90 #define PADCFG2                         0x008
  91 #define PADCFG2_DEBOUNCE_SHIFT          1
  92 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  93 #define PADCFG2_DEBEN                   BIT(0)
  94
  95 #define DEBOUNCE_PERIOD_NSEC            31250
  96
  97 struct intel_pad_context {
  98         u32 padcfg0;
  99         u32 padcfg1;
 100         u32 padcfg2;
 101 };
 102
 103 struct intel_community_context {
 104         u32 *intmask;
 105         u32 *hostown;
 106 };
 107
 108 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 109 #define padgroup_offset(g, p)   ((p) - (g)->base)
 110
 111 struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin)
 112 {
 113         struct intel_community *community;
 114         int i;
 115
 116         for (i = 0; i < pctrl->ncommunities; i++) {
 117                 community = &pctrl->communities[i];
 118                 if (pin >= community->pin_base &&
 119                     pin < community->pin_base + community->npins)
 120                         return community;
 121         }
 122
 123         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 124         return NULL;
 125 }
 126 EXPORT_SYMBOL_NS_GPL(intel_get_community, PINCTRL_INTEL);
 127
 128 static const struct intel_padgroup *
 129 intel_community_get_padgroup(const struct intel_community *community,
 130                              unsigned int pin)
 131 {
 132         int i;
 133
 134         for (i = 0; i < community->ngpps; i++) {
 135                 const struct intel_padgroup *padgrp = &community->gpps[i];
 136
 137                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 138                         return padgrp;
 139         }
 140
 141         return NULL;
 142 }
 143
 144 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 145                                       unsigned int pin, unsigned int reg)
 146 {
 147         const struct intel_community *community;
 148         unsigned int padno;
 149         size_t nregs;
 150
 151         community = intel_get_community(pctrl, pin);
 152         if (!community)
 153                 return NULL;
 154
 155         padno = pin_to_padno(community, pin);
 156         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 157
 158         if (reg >= nregs * 4)
 159                 return NULL;
 160
 161         return community->pad_regs + reg + padno * nregs * 4;
 162 }
 163
 164 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 165 {
 166         const struct intel_community *community;
 167         const struct intel_padgroup *padgrp;
 168         unsigned int gpp, offset, gpp_offset;
 169         void __iomem *padown;
 170
 171         community = intel_get_community(pctrl, pin);
 172         if (!community)
 173                 return false;
 174         if (!community->padown_offset)
 175                 return true;
 176
 177         padgrp = intel_community_get_padgroup(community, pin);
 178         if (!padgrp)
 179                 return false;
 180
 181         gpp_offset = padgroup_offset(padgrp, pin);
 182         gpp = PADOWN_GPP(gpp_offset);
 183         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 184         padown = community->regs + offset;
 185
 186         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 187 }
 188
 189 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 190 {
 191         const struct intel_community *community;
 192         const struct intel_padgroup *padgrp;
 193         unsigned int offset, gpp_offset;
 194         void __iomem *hostown;
 195
 196         community = intel_get_community(pctrl, pin);
 197         if (!community)
 198                 return true;
 199         if (!community->hostown_offset)
 200                 return false;
 201
 202         padgrp = intel_community_get_padgroup(community, pin);
 203         if (!padgrp)
 204                 return true;
 205
 206         gpp_offset = padgroup_offset(padgrp, pin);
 207         offset = community->hostown_offset + padgrp->reg_num * 4;
 208         hostown = community->regs + offset;
 209
 210         return !(readl(hostown) & BIT(gpp_offset));
 211 }
 212
 213 /**
 214  * enum - Locking variants of the pad configuration
 215  *
 216  * @PAD_UNLOCKED:       pad is fully controlled by the configuration registers
 217  * @PAD_LOCKED:         pad configuration registers, except TX state, are locked
 218  * @PAD_LOCKED_TX:      pad configuration TX state is locked
 219  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
 220  *
 221  * Locking is considered as read-only mode for corresponding registers and
 222  * their respective fields. That said, TX state bit is locked separately from
 223  * the main locking scheme.
 224  */
 225 enum {
 226         PAD_UNLOCKED    = 0,
 227         PAD_LOCKED      = 1,
 228         PAD_LOCKED_TX   = 2,
 229         PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
 230 };
 231
 232 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 233 {
 234         struct intel_community *community;
 235         const struct intel_padgroup *padgrp;
 236         unsigned int offset, gpp_offset;
 237         u32 value;
 238         int ret = PAD_UNLOCKED;
 239
 240         community = intel_get_community(pctrl, pin);
 241         if (!community)
 242                 return PAD_LOCKED_FULL;
 243         if (!community->padcfglock_offset)
 244                 return PAD_UNLOCKED;
 245
 246         padgrp = intel_community_get_padgroup(community, pin);
 247         if (!padgrp)
 248                 return PAD_LOCKED_FULL;
 249
 250         gpp_offset = padgroup_offset(padgrp, pin);
 251
 252         /*
 253          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 254          * the pad is considered unlocked. Any other case means that it is
 255          * either fully or partially locked.
 256          */
 257         offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
 258         value = readl(community->regs + offset);
 259         if (value & BIT(gpp_offset))
 260                 ret |= PAD_LOCKED;
 261
 262         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 263         value = readl(community->regs + offset);
 264         if (value & BIT(gpp_offset))
 265                 ret |= PAD_LOCKED_TX;
 266
 267         return ret;
 268 }
 269
 270 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
 271 {
 272         return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
 273 }
 274
 275 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 276 {
 277         return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
 278 }
 279
 280 int intel_get_groups_count(struct pinctrl_dev *pctldev)
 281 {
 282         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 283
 284         return pctrl->soc->ngroups;
 285 }
 286 EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, PINCTRL_INTEL);
 287
 288 const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
 289 {
 290         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 291
 292         return pctrl->soc->groups[group].grp.name;
 293 }
 294 EXPORT_SYMBOL_NS_GPL(intel_get_group_name, PINCTRL_INTEL);
 295
 296 int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 297                          const unsigned int **pins, unsigned int *npins)
 298 {
 299         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 300
 301         *pins = pctrl->soc->groups[group].grp.pins;
 302         *npins = pctrl->soc->groups[group].grp.npins;
 303         return 0;
 304 }
 305 EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, PINCTRL_INTEL);
 306
 307 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 308                                unsigned int pin)
 309 {
 310         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 311         void __iomem *padcfg;
 312         u32 cfg0, cfg1, mode;
 313         int locked;
 314         bool acpi;
 315
 316         if (!intel_pad_owned_by_host(pctrl, pin)) {
 317                 seq_puts(s, "not available");
 318                 return;
 319         }
 320
 321         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 322         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 323
 324         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 325         if (mode == PADCFG0_PMODE_GPIO)
 326                 seq_puts(s, "GPIO ");
 327         else
 328                 seq_printf(s, "mode %d ", mode);
 329
 330         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 331
 332         /* Dump the additional PADCFG registers if available */
 333         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 334         if (padcfg)
 335                 seq_printf(s, " 0x%08x", readl(padcfg));
 336
 337         locked = intel_pad_locked(pctrl, pin);
 338         acpi = intel_pad_acpi_mode(pctrl, pin);
 339
 340         if (locked || acpi) {
 341                 seq_puts(s, " [");
 342                 if (locked)
 343                         seq_puts(s, "LOCKED");
 344                 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
 345                         seq_puts(s, " tx");
 346                 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
 347                         seq_puts(s, " full");
 348
 349                 if (locked && acpi)
 350                         seq_puts(s, ", ");
 351
 352                 if (acpi)
 353                         seq_puts(s, "ACPI");
 354                 seq_puts(s, "]");
 355         }
 356 }
 357
 358 static const struct pinctrl_ops intel_pinctrl_ops = {
 359         .get_groups_count = intel_get_groups_count,
 360         .get_group_name = intel_get_group_name,
 361         .get_group_pins = intel_get_group_pins,
 362         .pin_dbg_show = intel_pin_dbg_show,
 363 };
 364
 365 int intel_get_functions_count(struct pinctrl_dev *pctldev)
 366 {
 367         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 368
 369         return pctrl->soc->nfunctions;
 370 }
 371 EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, PINCTRL_INTEL);
 372
 373 const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
 374 {
 375         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 376
 377         return pctrl->soc->functions[function].func.name;
 378 }
 379 EXPORT_SYMBOL_NS_GPL(intel_get_function_name, PINCTRL_INTEL);
 380
 381 int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
 382                               const char * const **groups, unsigned int * const ngroups)
 383 {
 384         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 385
 386         *groups = pctrl->soc->functions[function].func.groups;
 387         *ngroups = pctrl->soc->functions[function].func.ngroups;
 388         return 0;
 389 }
 390 EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, PINCTRL_INTEL);
 391
 392 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 393                                 unsigned int function, unsigned int group)
 394 {
 395         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 396         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 397         int i;
 398
 399         guard(raw_spinlock_irqsave)(&pctrl->lock);
 400
 401         /*
 402          * All pins in the groups needs to be accessible and writable
 403          * before we can enable the mux for this group.
 404          */
 405         for (i = 0; i < grp->grp.npins; i++) {
 406                 if (!intel_pad_usable(pctrl, grp->grp.pins[i]))
 407                         return -EBUSY;
 408         }
 409
 410         /* Now enable the mux setting for each pin in the group */
 411         for (i = 0; i < grp->grp.npins; i++) {
 412                 void __iomem *padcfg0;
 413                 u32 value, pmode;
 414
 415                 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
 416
 417                 value = readl(padcfg0);
 418                 value &= ~PADCFG0_PMODE_MASK;
 419
 420                 if (grp->modes)
 421                         pmode = grp->modes[i];
 422                 else
 423                         pmode = grp->mode;
 424
 425                 value |= pmode << PADCFG0_PMODE_SHIFT;
 426                 writel(value, padcfg0);
 427         }
 428
 429         return 0;
 430 }
 431
 432 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 433 {
 434         u32 value;
 435
 436         value = readl(padcfg0);
 437         if (input) {
 438                 value &= ~PADCFG0_GPIORXDIS;
 439                 value |= PADCFG0_GPIOTXDIS;
 440         } else {
 441                 value &= ~PADCFG0_GPIOTXDIS;
 442                 value |= PADCFG0_GPIORXDIS;
 443         }
 444         writel(value, padcfg0);
 445 }
 446
 447 static int __intel_gpio_get_gpio_mode(u32 value)
 448 {
 449         return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 450 }
 451
 452 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 453 {
 454         return __intel_gpio_get_gpio_mode(readl(padcfg0));
 455 }
 456
 457 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 458 {
 459         u32 value;
 460
 461         value = readl(padcfg0);
 462
 463         /* Put the pad into GPIO mode */
 464         value &= ~PADCFG0_PMODE_MASK;
 465         value |= PADCFG0_PMODE_GPIO;
 466
 467         /* Disable TX buffer and enable RX (this will be input) */
 468         value &= ~PADCFG0_GPIORXDIS;
 469         value |= PADCFG0_GPIOTXDIS;
 470
 471         /* Disable SCI/SMI/NMI generation */
 472         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 473         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 474
 475         writel(value, padcfg0);
 476 }
 477
 478 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 479                                      struct pinctrl_gpio_range *range,
 480                                      unsigned int pin)
 481 {
 482         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 483         void __iomem *padcfg0;
 484
 485         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 486
 487         guard(raw_spinlock_irqsave)(&pctrl->lock);
 488
 489         if (!intel_pad_owned_by_host(pctrl, pin))
 490                 return -EBUSY;
 491
 492         if (!intel_pad_is_unlocked(pctrl, pin))
 493                 return 0;
 494
 495         /*
 496          * If pin is already configured in GPIO mode, we assume that
 497          * firmware provides correct settings. In such case we avoid
 498          * potential glitches on the pin. Otherwise, for the pin in
 499          * alternative mode, consumer has to supply respective flags.
 500          */
 501         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO)
 502                 return 0;
 503
 504         intel_gpio_set_gpio_mode(padcfg0);
 505
 506         return 0;
 507 }
 508
 509 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 510                                     struct pinctrl_gpio_range *range,
 511                                     unsigned int pin, bool input)
 512 {
 513         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 514         void __iomem *padcfg0;
 515
 516         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 517
 518         guard(raw_spinlock_irqsave)(&pctrl->lock);
 519
 520         __intel_gpio_set_direction(padcfg0, input);
 521
 522         return 0;
 523 }
 524
 525 static const struct pinmux_ops intel_pinmux_ops = {
 526         .get_functions_count = intel_get_functions_count,
 527         .get_function_name = intel_get_function_name,
 528         .get_function_groups = intel_get_function_groups,
 529         .set_mux = intel_pinmux_set_mux,
 530         .gpio_request_enable = intel_gpio_request_enable,
 531         .gpio_set_direction = intel_gpio_set_direction,
 532 };
 533
 534 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 535                                  enum pin_config_param param, u32 *arg)
 536 {
 537         void __iomem *padcfg1;
 538         u32 value, term;
 539
 540         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 541
 542         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 543                 value = readl(padcfg1);
 544
 545         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 546
 547         switch (param) {
 548         case PIN_CONFIG_BIAS_DISABLE:
 549                 if (term)
 550                         return -EINVAL;
 551                 break;
 552
 553         case PIN_CONFIG_BIAS_PULL_UP:
 554                 if (!term || !(value & PADCFG1_TERM_UP))
 555                         return -EINVAL;
 556
 557                 switch (term) {
 558                 case PADCFG1_TERM_833:
 559                         *arg = 833;
 560                         break;
 561                 case PADCFG1_TERM_1K:
 562                         *arg = 1000;
 563                         break;
 564                 case PADCFG1_TERM_4K:
 565                         *arg = 4000;
 566                         break;
 567                 case PADCFG1_TERM_5K:
 568                         *arg = 5000;
 569                         break;
 570                 case PADCFG1_TERM_20K:
 571                         *arg = 20000;
 572                         break;
 573                 }
 574
 575                 break;
 576
 577         case PIN_CONFIG_BIAS_PULL_DOWN: {
 578                 const struct intel_community *community = intel_get_community(pctrl, pin);
 579
 580                 if (!term || value & PADCFG1_TERM_UP)
 581                         return -EINVAL;
 582
 583                 switch (term) {
 584                 case PADCFG1_TERM_833:
 585                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 586                                 return -EINVAL;
 587                         *arg = 833;
 588                         break;
 589                 case PADCFG1_TERM_1K:
 590                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 591                                 return -EINVAL;
 592                         *arg = 1000;
 593                         break;
 594                 case PADCFG1_TERM_4K:
 595                         *arg = 4000;
 596                         break;
 597                 case PADCFG1_TERM_5K:
 598                         *arg = 5000;
 599                         break;
 600                 case PADCFG1_TERM_20K:
 601                         *arg = 20000;
 602                         break;
 603                 }
 604
 605                 break;
 606         }
 607
 608         default:
 609                 return -EINVAL;
 610         }
 611
 612         return 0;
 613 }
 614
 615 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
 616                                      enum pin_config_param param, u32 *arg)
 617 {
 618         void __iomem *padcfg2;
 619         unsigned long v;
 620         u32 value2;
 621
 622         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 623         if (!padcfg2)
 624                 return -ENOTSUPP;
 625
 626         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 627                 value2 = readl(padcfg2);
 628
 629         if (!(value2 & PADCFG2_DEBEN))
 630                 return -EINVAL;
 631
 632         v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 633         *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 634
 635         return 0;
 636 }
 637
 638 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 639                             unsigned long *config)
 640 {
 641         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 642         enum pin_config_param param = pinconf_to_config_param(*config);
 643         u32 arg = 0;
 644         int ret;
 645
 646         if (!intel_pad_owned_by_host(pctrl, pin))
 647                 return -ENOTSUPP;
 648
 649         switch (param) {
 650         case PIN_CONFIG_BIAS_DISABLE:
 651         case PIN_CONFIG_BIAS_PULL_UP:
 652         case PIN_CONFIG_BIAS_PULL_DOWN:
 653                 ret = intel_config_get_pull(pctrl, pin, param, &arg);
 654                 if (ret)
 655                         return ret;
 656                 break;
 657
 658         case PIN_CONFIG_INPUT_DEBOUNCE:
 659                 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
 660                 if (ret)
 661                         return ret;
 662                 break;
 663
 664         default:
 665                 return -ENOTSUPP;
 666         }
 667
 668         *config = pinconf_to_config_packed(param, arg);
 669         return 0;
 670 }
 671
 672 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 673                                  unsigned long config)
 674 {
 675         unsigned int param = pinconf_to_config_param(config);
 676         unsigned int arg = pinconf_to_config_argument(config);
 677         u32 term = 0, up = 0, value;
 678         void __iomem *padcfg1;
 679
 680         /* Set default strength value in case none is given */
 681         if (arg == 1)
 682                 arg = 5000;
 683
 684         switch (param) {
 685         case PIN_CONFIG_BIAS_DISABLE:
 686                 break;
 687
 688         case PIN_CONFIG_BIAS_PULL_UP:
 689                 switch (arg) {
 690                 case 20000:
 691                         term = PADCFG1_TERM_20K;
 692                         break;
 693                 case 5000:
 694                         term = PADCFG1_TERM_5K;
 695                         break;
 696                 case 4000:
 697                         term = PADCFG1_TERM_4K;
 698                         break;
 699                 case 1000:
 700                         term = PADCFG1_TERM_1K;
 701                         break;
 702                 case 833:
 703                         term = PADCFG1_TERM_833;
 704                         break;
 705                 default:
 706                         return -EINVAL;
 707                 }
 708
 709                 up = PADCFG1_TERM_UP;
 710                 break;
 711
 712         case PIN_CONFIG_BIAS_PULL_DOWN: {
 713                 const struct intel_community *community = intel_get_community(pctrl, pin);
 714
 715                 switch (arg) {
 716                 case 20000:
 717                         term = PADCFG1_TERM_20K;
 718                         break;
 719                 case 5000:
 720                         term = PADCFG1_TERM_5K;
 721                         break;
 722                 case 4000:
 723                         term = PADCFG1_TERM_4K;
 724                         break;
 725                 case 1000:
 726                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 727                                 return -EINVAL;
 728                         term = PADCFG1_TERM_1K;
 729                         break;
 730                 case 833:
 731                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 732                                 return -EINVAL;
 733                         term = PADCFG1_TERM_833;
 734                         break;
 735                 default:
 736                         return -EINVAL;
 737                 }
 738
 739                 break;
 740         }
 741
 742         default:
 743                 return -EINVAL;
 744         }
 745
 746         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 747
 748         guard(raw_spinlock_irqsave)(&pctrl->lock);
 749
 750         value = readl(padcfg1);
 751         value = (value & ~PADCFG1_TERM_MASK) | (term << PADCFG1_TERM_SHIFT);
 752         value = (value & ~PADCFG1_TERM_UP) | up;
 753         writel(value, padcfg1);
 754
 755         return 0;
 756 }
 757
 758 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 759                                      unsigned int pin, unsigned int debounce)
 760 {
 761         void __iomem *padcfg0, *padcfg2;
 762         u32 value0, value2;
 763
 764         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 765         if (!padcfg2)
 766                 return -ENOTSUPP;
 767
 768         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 769
 770         guard(raw_spinlock_irqsave)(&pctrl->lock);
 771
 772         value0 = readl(padcfg0);
 773         value2 = readl(padcfg2);
 774
 775         /* Disable glitch filter and debouncer */
 776         value0 &= ~PADCFG0_PREGFRXSEL;
 777         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 778
 779         if (debounce) {
 780                 unsigned long v;
 781
 782                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 783                 if (v < 3 || v > 15)
 784                         return -EINVAL;
 785
 786                 /* Enable glitch filter and debouncer */
 787                 value0 |= PADCFG0_PREGFRXSEL;
 788                 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 789                 value2 |= PADCFG2_DEBEN;
 790         }
 791
 792         writel(value0, padcfg0);
 793         writel(value2, padcfg2);
 794
 795         return 0;
 796 }
 797
 798 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 799                           unsigned long *configs, unsigned int nconfigs)
 800 {
 801         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 802         int i, ret;
 803
 804         if (!intel_pad_usable(pctrl, pin))
 805                 return -ENOTSUPP;
 806
 807         for (i = 0; i < nconfigs; i++) {
 808                 switch (pinconf_to_config_param(configs[i])) {
 809                 case PIN_CONFIG_BIAS_DISABLE:
 810                 case PIN_CONFIG_BIAS_PULL_UP:
 811                 case PIN_CONFIG_BIAS_PULL_DOWN:
 812                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 813                         if (ret)
 814                                 return ret;
 815                         break;
 816
 817                 case PIN_CONFIG_INPUT_DEBOUNCE:
 818                         ret = intel_config_set_debounce(pctrl, pin,
 819                                 pinconf_to_config_argument(configs[i]));
 820                         if (ret)
 821                                 return ret;
 822                         break;
 823
 824                 default:
 825                         return -ENOTSUPP;
 826                 }
 827         }
 828
 829         return 0;
 830 }
 831
 832 static const struct pinconf_ops intel_pinconf_ops = {
 833         .is_generic = true,
 834         .pin_config_get = intel_config_get,
 835         .pin_config_set = intel_config_set,
 836 };
 837
 838 static const struct pinctrl_desc intel_pinctrl_desc = {
 839         .pctlops = &intel_pinctrl_ops,
 840         .pmxops = &intel_pinmux_ops,
 841         .confops = &intel_pinconf_ops,
 842         .owner = THIS_MODULE,
 843 };
 844
 845 /**
 846  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 847  * @pctrl: Pinctrl structure
 848  * @offset: GPIO offset from gpiolib
 849  * @community: Community is filled here if not %NULL
 850  * @padgrp: Pad group is filled here if not %NULL
 851  *
 852  * When coming through gpiolib irqchip, the GPIO offset is not
 853  * automatically translated to pinctrl pin number. This function can be
 854  * used to find out the corresponding pinctrl pin.
 855  *
 856  * Return: a pin number and pointers to the community and pad group, which
 857  * the pin belongs to, or negative error code if translation can't be done.
 858  */
 859 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
 860                              const struct intel_community **community,
 861                              const struct intel_padgroup **padgrp)
 862 {
 863         int i;
 864
 865         for (i = 0; i < pctrl->ncommunities; i++) {
 866                 const struct intel_community *comm = &pctrl->communities[i];
 867                 int j;
 868
 869                 for (j = 0; j < comm->ngpps; j++) {
 870                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 871
 872                         if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
 873                                 continue;
 874
 875                         if (offset >= pgrp->gpio_base &&
 876                             offset < pgrp->gpio_base + pgrp->size) {
 877                                 int pin;
 878
 879                                 pin = pgrp->base + offset - pgrp->gpio_base;
 880                                 if (community)
 881                                         *community = comm;
 882                                 if (padgrp)
 883                                         *padgrp = pgrp;
 884
 885                                 return pin;
 886                         }
 887                 }
 888         }
 889
 890         return -EINVAL;
 891 }
 892
 893 /**
 894  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
 895  * @pctrl: Pinctrl structure
 896  * @pin: pin number
 897  *
 898  * Translate the pin number of pinctrl to GPIO offset
 899  *
 900  * Return: a GPIO offset, or negative error code if translation can't be done.
 901  */
 902 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
 903 {
 904         const struct intel_community *community;
 905         const struct intel_padgroup *padgrp;
 906
 907         community = intel_get_community(pctrl, pin);
 908         if (!community)
 909                 return -EINVAL;
 910
 911         padgrp = intel_community_get_padgroup(community, pin);
 912         if (!padgrp)
 913                 return -EINVAL;
 914
 915         return pin - padgrp->base + padgrp->gpio_base;
 916 }
 917
 918 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 919 {
 920         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 921         void __iomem *reg;
 922         u32 padcfg0;
 923         int pin;
 924
 925         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 926         if (pin < 0)
 927                 return -EINVAL;
 928
 929         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 930         if (!reg)
 931                 return -EINVAL;
 932
 933         padcfg0 = readl(reg);
 934         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 935                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 936
 937         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 938 }
 939
 940 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
 941                            int value)
 942 {
 943         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 944         void __iomem *reg;
 945         u32 padcfg0;
 946         int pin;
 947
 948         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 949         if (pin < 0)
 950                 return;
 951
 952         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 953         if (!reg)
 954                 return;
 955
 956         guard(raw_spinlock_irqsave)(&pctrl->lock);
 957
 958         padcfg0 = readl(reg);
 959         if (value)
 960                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 961         else
 962                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 963         writel(padcfg0, reg);
 964 }
 965
 966 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 967 {
 968         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 969         void __iomem *reg;
 970         u32 padcfg0;
 971         int pin;
 972
 973         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 974         if (pin < 0)
 975                 return -EINVAL;
 976
 977         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 978         if (!reg)
 979                 return -EINVAL;
 980
 981         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 982                 padcfg0 = readl(reg);
 983
 984         if (padcfg0 & PADCFG0_PMODE_MASK)
 985                 return -EINVAL;
 986
 987         if (padcfg0 & PADCFG0_GPIOTXDIS)
 988                 return GPIO_LINE_DIRECTION_IN;
 989
 990         return GPIO_LINE_DIRECTION_OUT;
 991 }
 992
 993 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 994 {
 995         return pinctrl_gpio_direction_input(chip, offset);
 996 }
 997
 998 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
 999                                        int value)
1000 {
1001         intel_gpio_set(chip, offset, value);
1002         return pinctrl_gpio_direction_output(chip, offset);
1003 }
1004
1005 static const struct gpio_chip intel_gpio_chip = {
1006         .owner = THIS_MODULE,
1007         .request = gpiochip_generic_request,
1008         .free = gpiochip_generic_free,
1009         .get_direction = intel_gpio_get_direction,
1010         .direction_input = intel_gpio_direction_input,
1011         .direction_output = intel_gpio_direction_output,
1012         .get = intel_gpio_get,
1013         .set = intel_gpio_set,
1014         .set_config = gpiochip_generic_config,
1015 };
1016
1017 static void intel_gpio_irq_ack(struct irq_data *d)
1018 {
1019         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1020         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1021         const struct intel_community *community;
1022         const struct intel_padgroup *padgrp;
1023         int pin;
1024
1025         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1026         if (pin >= 0) {
1027                 unsigned int gpp, gpp_offset;
1028                 void __iomem *is;
1029
1030                 gpp = padgrp->reg_num;
1031                 gpp_offset = padgroup_offset(padgrp, pin);
1032
1033                 is = community->regs + community->is_offset + gpp * 4;
1034
1035                 guard(raw_spinlock)(&pctrl->lock);
1036
1037                 writel(BIT(gpp_offset), is);
1038         }
1039 }
1040
1041 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1042 {
1043         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1044         const struct intel_community *community;
1045         const struct intel_padgroup *padgrp;
1046         int pin;
1047
1048         pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
1049         if (pin >= 0) {
1050                 unsigned int gpp, gpp_offset;
1051                 void __iomem *reg, *is;
1052                 u32 value;
1053
1054                 gpp = padgrp->reg_num;
1055                 gpp_offset = padgroup_offset(padgrp, pin);
1056
1057                 reg = community->regs + community->ie_offset + gpp * 4;
1058                 is = community->regs + community->is_offset + gpp * 4;
1059
1060                 guard(raw_spinlock_irqsave)(&pctrl->lock);
1061
1062                 /* Clear interrupt status first to avoid unexpected interrupt */
1063                 writel(BIT(gpp_offset), is);
1064
1065                 value = readl(reg);
1066                 if (mask)
1067                         value &= ~BIT(gpp_offset);
1068                 else
1069                         value |= BIT(gpp_offset);
1070                 writel(value, reg);
1071         }
1072 }
1073
1074 static void intel_gpio_irq_mask(struct irq_data *d)
1075 {
1076         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1077         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1078
1079         intel_gpio_irq_mask_unmask(gc, hwirq, true);
1080         gpiochip_disable_irq(gc, hwirq);
1081 }
1082
1083 static void intel_gpio_irq_unmask(struct irq_data *d)
1084 {
1085         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1086         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1087
1088         gpiochip_enable_irq(gc, hwirq);
1089         intel_gpio_irq_mask_unmask(gc, hwirq, false);
1090 }
1091
1092 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1093 {
1094         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1095         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1096         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1097         u32 rxevcfg, rxinv, value;
1098         void __iomem *reg;
1099
1100         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1101         if (!reg)
1102                 return -EINVAL;
1103
1104         /*
1105          * If the pin is in ACPI mode it is still usable as a GPIO but it
1106          * cannot be used as IRQ because GPI_IS status bit will not be
1107          * updated by the host controller hardware.
1108          */
1109         if (intel_pad_acpi_mode(pctrl, pin)) {
1110                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1111                 return -EPERM;
1112         }
1113
1114         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1115                 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
1116         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1117                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1118         } else if (type & IRQ_TYPE_EDGE_RISING) {
1119                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1120         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1121                 rxevcfg = PADCFG0_RXEVCFG_LEVEL;
1122         } else {
1123                 rxevcfg = PADCFG0_RXEVCFG_DISABLED;
1124         }
1125
1126         if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW)
1127                 rxinv = PADCFG0_RXINV;
1128         else
1129                 rxinv = 0;
1130
1131         guard(raw_spinlock_irqsave)(&pctrl->lock);
1132
1133         intel_gpio_set_gpio_mode(reg);
1134
1135         value = readl(reg);
1136
1137         value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;
1138         value = (value & ~PADCFG0_RXINV) | rxinv;
1139
1140         writel(value, reg);
1141
1142         if (type & IRQ_TYPE_EDGE_BOTH)
1143                 irq_set_handler_locked(d, handle_edge_irq);
1144         else if (type & IRQ_TYPE_LEVEL_MASK)
1145                 irq_set_handler_locked(d, handle_level_irq);
1146
1147         return 0;
1148 }
1149
1150 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1151 {
1152         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1153         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1154         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1155
1156         if (on)
1157                 enable_irq_wake(pctrl->irq);
1158         else
1159                 disable_irq_wake(pctrl->irq);
1160
1161         dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin);
1162         return 0;
1163 }
1164
1165 static const struct irq_chip intel_gpio_irq_chip = {
1166         .name = "intel-gpio",
1167         .irq_ack = intel_gpio_irq_ack,
1168         .irq_mask = intel_gpio_irq_mask,
1169         .irq_unmask = intel_gpio_irq_unmask,
1170         .irq_set_type = intel_gpio_irq_type,
1171         .irq_set_wake = intel_gpio_irq_wake,
1172         .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1173         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1174 };
1175
1176 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1177                                             const struct intel_community *community)
1178 {
1179         struct gpio_chip *gc = &pctrl->chip;
1180         unsigned int gpp;
1181         int ret = 0;
1182
1183         for (gpp = 0; gpp < community->ngpps; gpp++) {
1184                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1185                 unsigned long pending, enabled;
1186                 unsigned int gpp, gpp_offset;
1187                 void __iomem *reg, *is;
1188
1189                 gpp = padgrp->reg_num;
1190
1191                 reg = community->regs + community->ie_offset + gpp * 4;
1192                 is = community->regs + community->is_offset + gpp * 4;
1193
1194                 scoped_guard(raw_spinlock, &pctrl->lock) {
1195                         pending = readl(is);
1196                         enabled = readl(reg);
1197                 }
1198
1199                 /* Only interrupts that are enabled */
1200                 pending &= enabled;
1201
1202                 for_each_set_bit(gpp_offset, &pending, padgrp->size)
1203                         generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset);
1204
1205                 ret += pending ? 1 : 0;
1206         }
1207
1208         return ret;
1209 }
1210
1211 static irqreturn_t intel_gpio_irq(int irq, void *data)
1212 {
1213         const struct intel_community *community;
1214         struct intel_pinctrl *pctrl = data;
1215         unsigned int i;
1216         int ret = 0;
1217
1218         /* Need to check all communities for pending interrupts */
1219         for (i = 0; i < pctrl->ncommunities; i++) {
1220                 community = &pctrl->communities[i];
1221                 ret += intel_gpio_community_irq_handler(pctrl, community);
1222         }
1223
1224         return IRQ_RETVAL(ret);
1225 }
1226
1227 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1228 {
1229         int i;
1230
1231         for (i = 0; i < pctrl->ncommunities; i++) {
1232                 const struct intel_community *community;
1233                 void __iomem *reg, *is;
1234                 unsigned int gpp;
1235
1236                 community = &pctrl->communities[i];
1237
1238                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1239                         reg = community->regs + community->ie_offset + gpp * 4;
1240                         is = community->regs + community->is_offset + gpp * 4;
1241
1242                         /* Mask and clear all interrupts */
1243                         writel(0, reg);
1244                         writel(0xffff, is);
1245                 }
1246         }
1247 }
1248
1249 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1250 {
1251         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1252
1253         /*
1254          * Make sure the interrupt lines are in a proper state before
1255          * further configuration.
1256          */
1257         intel_gpio_irq_init(pctrl);
1258
1259         return 0;
1260 }
1261
1262 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1263                                 const struct intel_community *community)
1264 {
1265         int ret = 0, i;
1266
1267         for (i = 0; i < community->ngpps; i++) {
1268                 const struct intel_padgroup *gpp = &community->gpps[i];
1269
1270                 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1271                         continue;
1272
1273                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1274                                              gpp->gpio_base, gpp->base,
1275                                              gpp->size);
1276                 if (ret)
1277                         return ret;
1278         }
1279
1280         return ret;
1281 }
1282
1283 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1284 {
1285         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1286         int ret, i;
1287
1288         for (i = 0; i < pctrl->ncommunities; i++) {
1289                 struct intel_community *community = &pctrl->communities[i];
1290
1291                 ret = intel_gpio_add_community_ranges(pctrl, community);
1292                 if (ret) {
1293                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1294                         return ret;
1295                 }
1296         }
1297
1298         return 0;
1299 }
1300
1301 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1302 {
1303         const struct intel_community *community;
1304         unsigned int ngpio = 0;
1305         int i, j;
1306
1307         for (i = 0; i < pctrl->ncommunities; i++) {
1308                 community = &pctrl->communities[i];
1309                 for (j = 0; j < community->ngpps; j++) {
1310                         const struct intel_padgroup *gpp = &community->gpps[j];
1311
1312                         if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1313                                 continue;
1314
1315                         if (gpp->gpio_base + gpp->size > ngpio)
1316                                 ngpio = gpp->gpio_base + gpp->size;
1317                 }
1318         }
1319
1320         return ngpio;
1321 }
1322
1323 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1324 {
1325         int ret;
1326         struct gpio_irq_chip *girq;
1327
1328         pctrl->chip = intel_gpio_chip;
1329
1330         /* Setup GPIO chip */
1331         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1332         pctrl->chip.label = dev_name(pctrl->dev);
1333         pctrl->chip.parent = pctrl->dev;
1334         pctrl->chip.base = -1;
1335         pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1336         pctrl->irq = irq;
1337
1338         /*
1339          * On some platforms several GPIO controllers share the same interrupt
1340          * line.
1341          */
1342         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1343                                IRQF_SHARED | IRQF_NO_THREAD,
1344                                dev_name(pctrl->dev), pctrl);
1345         if (ret) {
1346                 dev_err(pctrl->dev, "failed to request interrupt\n");
1347                 return ret;
1348         }
1349
1350         /* Setup IRQ chip */
1351         girq = &pctrl->chip.irq;
1352         gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
1353         /* This will let us handle the IRQ in the driver */
1354         girq->parent_handler = NULL;
1355         girq->num_parents = 0;
1356         girq->default_type = IRQ_TYPE_NONE;
1357         girq->handler = handle_bad_irq;
1358         girq->init_hw = intel_gpio_irq_init_hw;
1359
1360         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1361         if (ret) {
1362                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1363                 return ret;
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1370                                                struct intel_community *community)
1371 {
1372         struct intel_padgroup *gpps;
1373         unsigned int padown_num = 0;
1374         size_t i, ngpps = community->ngpps;
1375
1376         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1377         if (!gpps)
1378                 return -ENOMEM;
1379
1380         for (i = 0; i < ngpps; i++) {
1381                 gpps[i] = community->gpps[i];
1382
1383                 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE)
1384                         return -EINVAL;
1385
1386                 /* Special treatment for GPIO base */
1387                 switch (gpps[i].gpio_base) {
1388                         case INTEL_GPIO_BASE_MATCH:
1389                                 gpps[i].gpio_base = gpps[i].base;
1390                                 break;
1391                         case INTEL_GPIO_BASE_ZERO:
1392                                 gpps[i].gpio_base = 0;
1393                                 break;
1394                         case INTEL_GPIO_BASE_NOMAP:
1395                                 break;
1396                         default:
1397                                 break;
1398                 }
1399
1400                 gpps[i].padown_num = padown_num;
1401                 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE);
1402         }
1403
1404         community->gpps = gpps;
1405
1406         return 0;
1407 }
1408
1409 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1410                                                struct intel_community *community)
1411 {
1412         struct intel_padgroup *gpps;
1413         unsigned int npins = community->npins;
1414         unsigned int padown_num = 0;
1415         size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1416
1417         if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE)
1418                 return -EINVAL;
1419
1420         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1421         if (!gpps)
1422                 return -ENOMEM;
1423
1424         for (i = 0; i < ngpps; i++) {
1425                 unsigned int gpp_size = community->gpp_size;
1426
1427                 gpps[i].reg_num = i;
1428                 gpps[i].base = community->pin_base + i * gpp_size;
1429                 gpps[i].size = min(gpp_size, npins);
1430                 npins -= gpps[i].size;
1431
1432                 gpps[i].gpio_base = gpps[i].base;
1433                 gpps[i].padown_num = padown_num;
1434
1435                 padown_num += community->gpp_num_padown_regs;
1436         }
1437
1438         community->ngpps = ngpps;
1439         community->gpps = gpps;
1440
1441         return 0;
1442 }
1443
1444 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1445 {
1446 #ifdef CONFIG_PM_SLEEP
1447         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1448         struct intel_community_context *communities;
1449         struct intel_pad_context *pads;
1450         int i;
1451
1452         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1453         if (!pads)
1454                 return -ENOMEM;
1455
1456         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1457                                    sizeof(*communities), GFP_KERNEL);
1458         if (!communities)
1459                 return -ENOMEM;
1460
1461
1462         for (i = 0; i < pctrl->ncommunities; i++) {
1463                 struct intel_community *community = &pctrl->communities[i];
1464                 u32 *intmask, *hostown;
1465
1466                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1467                                        sizeof(*intmask), GFP_KERNEL);
1468                 if (!intmask)
1469                         return -ENOMEM;
1470
1471                 communities[i].intmask = intmask;
1472
1473                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1474                                        sizeof(*hostown), GFP_KERNEL);
1475                 if (!hostown)
1476                         return -ENOMEM;
1477
1478                 communities[i].hostown = hostown;
1479         }
1480
1481         pctrl->context.pads = pads;
1482         pctrl->context.communities = communities;
1483 #endif
1484
1485         return 0;
1486 }
1487
1488 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
1489                                    struct intel_community *community)
1490 {
1491         static const struct pwm_lpss_boardinfo info = {
1492                 .clk_rate = 19200000,
1493                 .npwm = 1,
1494                 .base_unit_bits = 22,
1495                 .bypass = true,
1496         };
1497         struct pwm_lpss_chip *pwm;
1498
1499         if (!(community->features & PINCTRL_FEATURE_PWM))
1500                 return 0;
1501
1502         if (!IS_REACHABLE(CONFIG_PWM_LPSS))
1503                 return 0;
1504
1505         pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
1506         return PTR_ERR_OR_ZERO(pwm);
1507 }
1508
1509 static int intel_pinctrl_probe(struct platform_device *pdev,
1510                                const struct intel_pinctrl_soc_data *soc_data)
1511 {
1512         struct device *dev = &pdev->dev;
1513         struct intel_pinctrl *pctrl;
1514         int i, ret, irq;
1515
1516         pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1517         if (!pctrl)
1518                 return -ENOMEM;
1519
1520         pctrl->dev = dev;
1521         pctrl->soc = soc_data;
1522         raw_spin_lock_init(&pctrl->lock);
1523
1524         /*
1525          * Make a copy of the communities which we can use to hold pointers
1526          * to the registers.
1527          */
1528         pctrl->ncommunities = pctrl->soc->ncommunities;
1529         pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities,
1530                                           sizeof(*pctrl->communities), GFP_KERNEL);
1531         if (!pctrl->communities)
1532                 return -ENOMEM;
1533
1534         for (i = 0; i < pctrl->ncommunities; i++) {
1535                 struct intel_community *community = &pctrl->communities[i];
1536                 void __iomem *regs;
1537                 u32 offset;
1538                 u32 value;
1539
1540                 *community = pctrl->soc->communities[i];
1541
1542                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1543                 if (IS_ERR(regs))
1544                         return PTR_ERR(regs);
1545
1546                 /*
1547                  * Determine community features based on the revision.
1548                  * A value of all ones means the device is not present.
1549                  */
1550                 value = readl(regs + REVID);
1551                 if (value == ~0u)
1552                         return -ENODEV;
1553                 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1554                         community->features |= PINCTRL_FEATURE_DEBOUNCE;
1555                         community->features |= PINCTRL_FEATURE_1K_PD;
1556                 }
1557
1558                 /* Determine community features based on the capabilities */
1559                 offset = CAPLIST;
1560                 do {
1561                         value = readl(regs + offset);
1562                         switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1563                         case CAPLIST_ID_GPIO_HW_INFO:
1564                                 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1565                                 break;
1566                         case CAPLIST_ID_PWM:
1567                                 community->features |= PINCTRL_FEATURE_PWM;
1568                                 break;
1569                         case CAPLIST_ID_BLINK:
1570                                 community->features |= PINCTRL_FEATURE_BLINK;
1571                                 break;
1572                         case CAPLIST_ID_EXP:
1573                                 community->features |= PINCTRL_FEATURE_EXP;
1574                                 break;
1575                         default:
1576                                 break;
1577                         }
1578                         offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1579                 } while (offset);
1580
1581                 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features);
1582
1583                 /* Read offset of the pad configuration registers */
1584                 offset = readl(regs + PADBAR);
1585
1586                 community->regs = regs;
1587                 community->pad_regs = regs + offset;
1588
1589                 if (community->gpps)
1590                         ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1591                 else
1592                         ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1593                 if (ret)
1594                         return ret;
1595
1596                 ret = intel_pinctrl_probe_pwm(pctrl, community);
1597                 if (ret)
1598                         return ret;
1599         }
1600
1601         irq = platform_get_irq(pdev, 0);
1602         if (irq < 0)
1603                 return irq;
1604
1605         ret = intel_pinctrl_pm_init(pctrl);
1606         if (ret)
1607                 return ret;
1608
1609         pctrl->pctldesc = intel_pinctrl_desc;
1610         pctrl->pctldesc.name = dev_name(dev);
1611         pctrl->pctldesc.pins = pctrl->soc->pins;
1612         pctrl->pctldesc.npins = pctrl->soc->npins;
1613
1614         pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1615         if (IS_ERR(pctrl->pctldev)) {
1616                 dev_err(dev, "failed to register pinctrl driver\n");
1617                 return PTR_ERR(pctrl->pctldev);
1618         }
1619
1620         ret = intel_gpio_probe(pctrl, irq);
1621         if (ret)
1622                 return ret;
1623
1624         platform_set_drvdata(pdev, pctrl);
1625
1626         return 0;
1627 }
1628
1629 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1630 {
1631         const struct intel_pinctrl_soc_data *data;
1632
1633         data = device_get_match_data(&pdev->dev);
1634         if (!data)
1635                 return -ENODATA;
1636
1637         return intel_pinctrl_probe(pdev, data);
1638 }
1639 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, PINCTRL_INTEL);
1640
1641 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1642 {
1643         const struct intel_pinctrl_soc_data *data;
1644
1645         data = intel_pinctrl_get_soc_data(pdev);
1646         if (IS_ERR(data))
1647                 return PTR_ERR(data);
1648
1649         return intel_pinctrl_probe(pdev, data);
1650 }
1651 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, PINCTRL_INTEL);
1652
1653 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1654 {
1655         const struct intel_pinctrl_soc_data * const *table;
1656         const struct intel_pinctrl_soc_data *data = NULL;
1657         struct device *dev = &pdev->dev;
1658
1659         table = device_get_match_data(dev);
1660         if (table) {
1661                 struct acpi_device *adev = ACPI_COMPANION(dev);
1662                 unsigned int i;
1663
1664                 for (i = 0; table[i]; i++) {
1665                         if (acpi_dev_uid_match(adev, table[i]->uid)) {
1666                                 data = table[i];
1667                                 break;
1668                         }
1669                 }
1670         } else {
1671                 const struct platform_device_id *id;
1672
1673                 id = platform_get_device_id(pdev);
1674                 if (!id)
1675                         return ERR_PTR(-ENODEV);
1676
1677                 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1678                 data = table[pdev->id];
1679         }
1680
1681         return data ?: ERR_PTR(-ENODATA);
1682 }
1683 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL);
1684
1685 #ifdef CONFIG_PM_SLEEP
1686 static bool __intel_gpio_is_direct_irq(u32 value)
1687 {
1688         return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
1689                (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1690 }
1691
1692 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1693 {
1694         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1695         u32 value;
1696
1697         if (!pd || !intel_pad_usable(pctrl, pin))
1698                 return false;
1699
1700         /*
1701          * Only restore the pin if it is actually in use by the kernel (or
1702          * by userspace). It is possible that some pins are used by the
1703          * BIOS during resume and those are not always locked down so leave
1704          * them alone.
1705          */
1706         if (pd->mux_owner || pd->gpio_owner ||
1707             gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1708                 return true;
1709
1710         /*
1711          * The firmware on some systems may configure GPIO pins to be
1712          * an interrupt source in so called "direct IRQ" mode. In such
1713          * cases the GPIO controller driver has no idea if those pins
1714          * are being used or not. At the same time, there is a known bug
1715          * in the firmwares that don't restore the pin settings correctly
1716          * after suspend, i.e. by an unknown reason the Rx value becomes
1717          * inverted.
1718          *
1719          * Hence, let's save and restore the pins that are configured
1720          * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
1721          *
1722          * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
1723          */
1724         value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1725         if (__intel_gpio_is_direct_irq(value))
1726                 return true;
1727
1728         return false;
1729 }
1730
1731 int intel_pinctrl_suspend_noirq(struct device *dev)
1732 {
1733         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1734         struct intel_community_context *communities;
1735         struct intel_pad_context *pads;
1736         int i;
1737
1738         pads = pctrl->context.pads;
1739         for (i = 0; i < pctrl->soc->npins; i++) {
1740                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1741                 void __iomem *padcfg;
1742                 u32 val;
1743
1744                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1745                         continue;
1746
1747                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1748                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1749                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1750                 pads[i].padcfg1 = val;
1751
1752                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1753                 if (padcfg)
1754                         pads[i].padcfg2 = readl(padcfg);
1755         }
1756
1757         communities = pctrl->context.communities;
1758         for (i = 0; i < pctrl->ncommunities; i++) {
1759                 struct intel_community *community = &pctrl->communities[i];
1760                 void __iomem *base;
1761                 unsigned int gpp;
1762
1763                 base = community->regs + community->ie_offset;
1764                 for (gpp = 0; gpp < community->ngpps; gpp++)
1765                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1766
1767                 base = community->regs + community->hostown_offset;
1768                 for (gpp = 0; gpp < community->ngpps; gpp++)
1769                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1770         }
1771
1772         return 0;
1773 }
1774 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1775
1776 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1777 {
1778         u32 curr, updated;
1779
1780         curr = readl(reg);
1781
1782         updated = (curr & ~mask) | (value & mask);
1783         if (curr == updated)
1784                 return false;
1785
1786         writel(updated, reg);
1787         return true;
1788 }
1789
1790 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1791                                   void __iomem *base, unsigned int gpp, u32 saved)
1792 {
1793         const struct intel_community *community = &pctrl->communities[c];
1794         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1795         struct device *dev = pctrl->dev;
1796         const char *dummy;
1797         u32 requested = 0;
1798         unsigned int i;
1799
1800         if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1801                 return;
1802
1803         for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1804                 requested |= BIT(i);
1805
1806         if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1807                 return;
1808
1809         dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1810 }
1811
1812 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1813                                   void __iomem *base, unsigned int gpp, u32 saved)
1814 {
1815         struct device *dev = pctrl->dev;
1816
1817         if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1818                 return;
1819
1820         dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1821 }
1822
1823 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1824                                  unsigned int reg, u32 saved)
1825 {
1826         u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1827         unsigned int n = reg / sizeof(u32);
1828         struct device *dev = pctrl->dev;
1829         void __iomem *padcfg;
1830
1831         padcfg = intel_get_padcfg(pctrl, pin, reg);
1832         if (!padcfg)
1833                 return;
1834
1835         if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1836                 return;
1837
1838         dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1839 }
1840
1841 int intel_pinctrl_resume_noirq(struct device *dev)
1842 {
1843         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1844         const struct intel_community_context *communities;
1845         const struct intel_pad_context *pads;
1846         int i;
1847
1848         /* Mask all interrupts */
1849         intel_gpio_irq_init(pctrl);
1850
1851         pads = pctrl->context.pads;
1852         for (i = 0; i < pctrl->soc->npins; i++) {
1853                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1854
1855                 if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
1856                       /*
1857                        * If the firmware mangled the register contents too much,
1858                        * check the saved value for the Direct IRQ mode.
1859                        */
1860                       __intel_gpio_is_direct_irq(pads[i].padcfg0)))
1861                         continue;
1862
1863                 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1864                 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1865                 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1866         }
1867
1868         communities = pctrl->context.communities;
1869         for (i = 0; i < pctrl->ncommunities; i++) {
1870                 struct intel_community *community = &pctrl->communities[i];
1871                 void __iomem *base;
1872                 unsigned int gpp;
1873
1874                 base = community->regs + community->ie_offset;
1875                 for (gpp = 0; gpp < community->ngpps; gpp++)
1876                         intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1877
1878                 base = community->regs + community->hostown_offset;
1879                 for (gpp = 0; gpp < community->ngpps; gpp++)
1880                         intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1881         }
1882
1883         return 0;
1884 }
1885 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1886 #endif
1887
1888 MODULE_AUTHOR("Mathias Nyman <[email protected]>");
1889 MODULE_AUTHOR("Mika Westerberg <[email protected]>");
1890 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1891 MODULE_LICENSE("GPL v2");