drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <[email protected]>
   7  *          Mika Westerberg <[email protected]>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/cleanup.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/log2.h>
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/property.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/string_helpers.h>
  20 #include <linux/time.h>
  21
  22 #include <linux/pinctrl/consumer.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinmux.h>
  27
  28 #include <linux/platform_data/x86/pwm-lpss.h>
  29
  30 #include "../core.h"
  31 #include "pinctrl-intel.h"
  32
  33 /* Offset from regs */
  34 #define REVID                           0x000
  35 #define REVID_SHIFT                     16
  36 #define REVID_MASK                      GENMASK(31, 16)
  37
  38 #define CAPLIST                         0x004
  39 #define CAPLIST_ID_SHIFT                16
  40 #define CAPLIST_ID_MASK                 GENMASK(23, 16)
  41 #define CAPLIST_ID_GPIO_HW_INFO         1
  42 #define CAPLIST_ID_PWM                  2
  43 #define CAPLIST_ID_BLINK                3
  44 #define CAPLIST_ID_EXP                  4
  45 #define CAPLIST_NEXT_SHIFT              0
  46 #define CAPLIST_NEXT_MASK               GENMASK(15, 0)
  47
  48 #define PADBAR                          0x00c
  49
  50 #define PADOWN_BITS                     4
  51 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  52 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  53 #define PADOWN_GPP(p)                   ((p) / 8)
  54
  55 #define PWMC                            0x204
  56
  57 /* Offset from pad_regs */
  58 #define PADCFG0                         0x000
  59 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  60 #define PADCFG0_RXEVCFG_LEVEL           (0 << 25)
  61 #define PADCFG0_RXEVCFG_EDGE            (1 << 25)
  62 #define PADCFG0_RXEVCFG_DISABLED        (2 << 25)
  63 #define PADCFG0_RXEVCFG_EDGE_BOTH       (3 << 25)
  64 #define PADCFG0_PREGFRXSEL              BIT(24)
  65 #define PADCFG0_RXINV                   BIT(23)
  66 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  67 #define PADCFG0_GPIROUTSCI              BIT(19)
  68 #define PADCFG0_GPIROUTSMI              BIT(18)
  69 #define PADCFG0_GPIROUTNMI              BIT(17)
  70 #define PADCFG0_PMODE_SHIFT             10
  71 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  72 #define PADCFG0_PMODE_GPIO              0
  73 #define PADCFG0_GPIODIS_SHIFT           8
  74 #define PADCFG0_GPIODIS_MASK            GENMASK(9, 8)
  75 #define PADCFG0_GPIODIS_NONE            0
  76 #define PADCFG0_GPIODIS_OUTPUT          1
  77 #define PADCFG0_GPIODIS_INPUT           2
  78 #define PADCFG0_GPIODIS_FULL            3
  79 #define PADCFG0_GPIORXDIS               BIT(9)
  80 #define PADCFG0_GPIOTXDIS               BIT(8)
  81 #define PADCFG0_GPIORXSTATE             BIT(1)
  82 #define PADCFG0_GPIOTXSTATE             BIT(0)
  83
  84 #define PADCFG1                         0x004
  85 #define PADCFG1_TERM_UP                 BIT(13)
  86 #define PADCFG1_TERM_SHIFT              10
  87 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  88 /*
  89  * Bit 0  Bit 1  Bit 2                  Value, Ohms
  90  *
  91  *   0      0      0                    -
  92  *   0      0      1                    20000
  93  *   0      1      0                    5000
  94  *   0      1      1                    ~4000
  95  *   1      0      0                    1000 (if supported)
  96  *   1      0      1                    ~952 (if supported)
  97  *   1      1      0                    ~833 (if supported)
  98  *   1      1      1                    ~800 (if supported)
  99  */
 100 #define PADCFG1_TERM_20K                BIT(2)
 101 #define PADCFG1_TERM_5K                 BIT(1)
 102 #define PADCFG1_TERM_4K                 (BIT(2) | BIT(1))
 103 #define PADCFG1_TERM_1K                 BIT(0)
 104 #define PADCFG1_TERM_952                (BIT(2) | BIT(0))
 105 #define PADCFG1_TERM_833                (BIT(1) | BIT(0))
 106 #define PADCFG1_TERM_800                (BIT(2) | BIT(1) | BIT(0))
 107
 108 #define PADCFG2                         0x008
 109 #define PADCFG2_DEBOUNCE_SHIFT          1
 110 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
 111 #define PADCFG2_DEBEN                   BIT(0)
 112
 113 #define DEBOUNCE_PERIOD_NSEC            31250
 114
 115 struct intel_pad_context {
 116         u32 padcfg0;
 117         u32 padcfg1;
 118         u32 padcfg2;
 119 };
 120
 121 struct intel_community_context {
 122         u32 *intmask;
 123         u32 *hostown;
 124 };
 125
 126 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 127 #define padgroup_offset(g, p)   ((p) - (g)->base)
 128
 129 #define for_each_intel_pin_community(pctrl, community)                                  \
 130         for (unsigned int __ci = 0;                                                     \
 131              __ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]);     \
 132              __ci++)                                                                    \
 133
 134 #define for_each_intel_community_pad_group(community, grp)                      \
 135         for (unsigned int __gi = 0;                                             \
 136              __gi < community->ngpps && (grp = &community->gpps[__gi]);         \
 137              __gi++)                                                            \
 138
 139 #define for_each_intel_pad_group(pctrl, community, grp)                 \
 140         for_each_intel_pin_community(pctrl, community)                  \
 141                 for_each_intel_community_pad_group(community, grp)
 142
 143 #define for_each_intel_gpio_group(pctrl, community, grp)                \
 144         for_each_intel_pad_group(pctrl, community, grp)                 \
 145                 if (grp->gpio_base == INTEL_GPIO_BASE_NOMAP) {} else
 146
 147 const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
 148                                                   unsigned int pin)
 149 {
 150         const struct intel_community *community;
 151
 152         for_each_intel_pin_community(pctrl, community) {
 153                 if (pin >= community->pin_base &&
 154                     pin < community->pin_base + community->npins)
 155                         return community;
 156         }
 157
 158         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 159         return NULL;
 160 }
 161 EXPORT_SYMBOL_NS_GPL(intel_get_community, "PINCTRL_INTEL");
 162
 163 static const struct intel_padgroup *
 164 intel_community_get_padgroup(const struct intel_community *community,
 165                              unsigned int pin)
 166 {
 167         const struct intel_padgroup *padgrp;
 168
 169         for_each_intel_community_pad_group(community, padgrp) {
 170                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 171                         return padgrp;
 172         }
 173
 174         return NULL;
 175 }
 176
 177 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 178                                       unsigned int pin, unsigned int reg)
 179 {
 180         const struct intel_community *community;
 181         unsigned int padno;
 182         size_t nregs;
 183
 184         community = intel_get_community(pctrl, pin);
 185         if (!community)
 186                 return NULL;
 187
 188         padno = pin_to_padno(community, pin);
 189         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 190
 191         if (reg >= nregs * 4)
 192                 return NULL;
 193
 194         return community->pad_regs + reg + padno * nregs * 4;
 195 }
 196
 197 static bool intel_pad_owned_by_host(const struct intel_pinctrl *pctrl, unsigned int pin)
 198 {
 199         const struct intel_community *community;
 200         const struct intel_padgroup *padgrp;
 201         unsigned int gpp, offset, gpp_offset;
 202         void __iomem *padown;
 203
 204         community = intel_get_community(pctrl, pin);
 205         if (!community)
 206                 return false;
 207         if (!community->padown_offset)
 208                 return true;
 209
 210         padgrp = intel_community_get_padgroup(community, pin);
 211         if (!padgrp)
 212                 return false;
 213
 214         gpp_offset = padgroup_offset(padgrp, pin);
 215         gpp = PADOWN_GPP(gpp_offset);
 216         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 217         padown = community->regs + offset;
 218
 219         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 220 }
 221
 222 static bool intel_pad_acpi_mode(const struct intel_pinctrl *pctrl, unsigned int pin)
 223 {
 224         const struct intel_community *community;
 225         const struct intel_padgroup *padgrp;
 226         unsigned int offset, gpp_offset;
 227         void __iomem *hostown;
 228
 229         community = intel_get_community(pctrl, pin);
 230         if (!community)
 231                 return true;
 232         if (!community->hostown_offset)
 233                 return false;
 234
 235         padgrp = intel_community_get_padgroup(community, pin);
 236         if (!padgrp)
 237                 return true;
 238
 239         gpp_offset = padgroup_offset(padgrp, pin);
 240         offset = community->hostown_offset + padgrp->reg_num * 4;
 241         hostown = community->regs + offset;
 242
 243         return !(readl(hostown) & BIT(gpp_offset));
 244 }
 245
 246 /**
 247  * enum - Locking variants of the pad configuration
 248  * @PAD_UNLOCKED:       pad is fully controlled by the configuration registers
 249  * @PAD_LOCKED:         pad configuration registers, except TX state, are locked
 250  * @PAD_LOCKED_TX:      pad configuration TX state is locked
 251  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
 252  *
 253  * Locking is considered as read-only mode for corresponding registers and
 254  * their respective fields. That said, TX state bit is locked separately from
 255  * the main locking scheme.
 256  */
 257 enum {
 258         PAD_UNLOCKED    = 0,
 259         PAD_LOCKED      = 1,
 260         PAD_LOCKED_TX   = 2,
 261         PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
 262 };
 263
 264 static int intel_pad_locked(const struct intel_pinctrl *pctrl, unsigned int pin)
 265 {
 266         const struct intel_community *community;
 267         const struct intel_padgroup *padgrp;
 268         unsigned int offset, gpp_offset;
 269         u32 value;
 270         int ret = PAD_UNLOCKED;
 271
 272         community = intel_get_community(pctrl, pin);
 273         if (!community)
 274                 return PAD_LOCKED_FULL;
 275         if (!community->padcfglock_offset)
 276                 return PAD_UNLOCKED;
 277
 278         padgrp = intel_community_get_padgroup(community, pin);
 279         if (!padgrp)
 280                 return PAD_LOCKED_FULL;
 281
 282         gpp_offset = padgroup_offset(padgrp, pin);
 283
 284         /*
 285          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 286          * the pad is considered unlocked. Any other case means that it is
 287          * either fully or partially locked.
 288          */
 289         offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
 290         value = readl(community->regs + offset);
 291         if (value & BIT(gpp_offset))
 292                 ret |= PAD_LOCKED;
 293
 294         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 295         value = readl(community->regs + offset);
 296         if (value & BIT(gpp_offset))
 297                 ret |= PAD_LOCKED_TX;
 298
 299         return ret;
 300 }
 301
 302 static bool intel_pad_is_unlocked(const struct intel_pinctrl *pctrl, unsigned int pin)
 303 {
 304         return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
 305 }
 306
 307 static bool intel_pad_usable(const struct intel_pinctrl *pctrl, unsigned int pin)
 308 {
 309         return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
 310 }
 311
 312 int intel_get_groups_count(struct pinctrl_dev *pctldev)
 313 {
 314         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 315
 316         return pctrl->soc->ngroups;
 317 }
 318 EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, "PINCTRL_INTEL");
 319
 320 const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
 321 {
 322         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 323
 324         return pctrl->soc->groups[group].grp.name;
 325 }
 326 EXPORT_SYMBOL_NS_GPL(intel_get_group_name, "PINCTRL_INTEL");
 327
 328 int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 329                          const unsigned int **pins, unsigned int *npins)
 330 {
 331         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 332
 333         *pins = pctrl->soc->groups[group].grp.pins;
 334         *npins = pctrl->soc->groups[group].grp.npins;
 335         return 0;
 336 }
 337 EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, "PINCTRL_INTEL");
 338
 339 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 340                                unsigned int pin)
 341 {
 342         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 343         void __iomem *padcfg;
 344         u32 cfg0, cfg1, mode;
 345         int locked;
 346         bool acpi;
 347
 348         if (!intel_pad_owned_by_host(pctrl, pin)) {
 349                 seq_puts(s, "not available");
 350                 return;
 351         }
 352
 353         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 354         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 355
 356         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 357         if (mode == PADCFG0_PMODE_GPIO)
 358                 seq_puts(s, "GPIO ");
 359         else
 360                 seq_printf(s, "mode %d ", mode);
 361
 362         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 363
 364         /* Dump the additional PADCFG registers if available */
 365         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 366         if (padcfg)
 367                 seq_printf(s, " 0x%08x", readl(padcfg));
 368
 369         locked = intel_pad_locked(pctrl, pin);
 370         acpi = intel_pad_acpi_mode(pctrl, pin);
 371
 372         if (locked || acpi) {
 373                 seq_puts(s, " [");
 374                 if (locked)
 375                         seq_puts(s, "LOCKED");
 376                 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
 377                         seq_puts(s, " tx");
 378                 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
 379                         seq_puts(s, " full");
 380
 381                 if (locked && acpi)
 382                         seq_puts(s, ", ");
 383
 384                 if (acpi)
 385                         seq_puts(s, "ACPI");
 386                 seq_puts(s, "]");
 387         }
 388 }
 389
 390 static const struct pinctrl_ops intel_pinctrl_ops = {
 391         .get_groups_count = intel_get_groups_count,
 392         .get_group_name = intel_get_group_name,
 393         .get_group_pins = intel_get_group_pins,
 394         .pin_dbg_show = intel_pin_dbg_show,
 395 };
 396
 397 int intel_get_functions_count(struct pinctrl_dev *pctldev)
 398 {
 399         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 400
 401         return pctrl->soc->nfunctions;
 402 }
 403 EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, "PINCTRL_INTEL");
 404
 405 const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
 406 {
 407         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 408
 409         return pctrl->soc->functions[function].func.name;
 410 }
 411 EXPORT_SYMBOL_NS_GPL(intel_get_function_name, "PINCTRL_INTEL");
 412
 413 int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
 414                               const char * const **groups, unsigned int * const ngroups)
 415 {
 416         const struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 417
 418         *groups = pctrl->soc->functions[function].func.groups;
 419         *ngroups = pctrl->soc->functions[function].func.ngroups;
 420         return 0;
 421 }
 422 EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, "PINCTRL_INTEL");
 423
 424 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 425                                 unsigned int function, unsigned int group)
 426 {
 427         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 428         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 429         int i;
 430
 431         guard(raw_spinlock_irqsave)(&pctrl->lock);
 432
 433         /*
 434          * All pins in the groups needs to be accessible and writable
 435          * before we can enable the mux for this group.
 436          */
 437         for (i = 0; i < grp->grp.npins; i++) {
 438                 if (!intel_pad_usable(pctrl, grp->grp.pins[i]))
 439                         return -EBUSY;
 440         }
 441
 442         /* Now enable the mux setting for each pin in the group */
 443         for (i = 0; i < grp->grp.npins; i++) {
 444                 void __iomem *padcfg0;
 445                 u32 value, pmode;
 446
 447                 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
 448
 449                 value = readl(padcfg0);
 450                 value &= ~PADCFG0_PMODE_MASK;
 451
 452                 if (grp->modes)
 453                         pmode = grp->modes[i];
 454                 else
 455                         pmode = grp->mode;
 456
 457                 value |= pmode << PADCFG0_PMODE_SHIFT;
 458                 writel(value, padcfg0);
 459         }
 460
 461         return 0;
 462 }
 463
 464 /**
 465  * enum - Possible pad physical connections
 466  * @PAD_CONNECT_NONE:   pad is fully disconnected
 467  * @PAD_CONNECT_INPUT:  pad is in input only mode
 468  * @PAD_CONNECT_OUTPUT: pad is in output only mode
 469  * @PAD_CONNECT_FULL:   pad is fully connected
 470  */
 471 enum {
 472         PAD_CONNECT_NONE        = 0,
 473         PAD_CONNECT_INPUT       = 1,
 474         PAD_CONNECT_OUTPUT      = 2,
 475         PAD_CONNECT_FULL        = PAD_CONNECT_INPUT | PAD_CONNECT_OUTPUT,
 476 };
 477
 478 static int __intel_gpio_get_direction(u32 value)
 479 {
 480         switch ((value & PADCFG0_GPIODIS_MASK) >> PADCFG0_GPIODIS_SHIFT) {
 481         case PADCFG0_GPIODIS_FULL:
 482                 return PAD_CONNECT_NONE;
 483         case PADCFG0_GPIODIS_OUTPUT:
 484                 return PAD_CONNECT_INPUT;
 485         case PADCFG0_GPIODIS_INPUT:
 486                 return PAD_CONNECT_OUTPUT;
 487         case PADCFG0_GPIODIS_NONE:
 488                 return PAD_CONNECT_FULL;
 489         default:
 490                 return -ENOTSUPP;
 491         };
 492 }
 493
 494 static u32 __intel_gpio_set_direction(u32 value, bool input, bool output)
 495 {
 496         if (input)
 497                 value &= ~PADCFG0_GPIORXDIS;
 498         else
 499                 value |= PADCFG0_GPIORXDIS;
 500
 501         if (output)
 502                 value &= ~PADCFG0_GPIOTXDIS;
 503         else
 504                 value |= PADCFG0_GPIOTXDIS;
 505
 506         return value;
 507 }
 508
 509 static int __intel_gpio_get_gpio_mode(u32 value)
 510 {
 511         return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 512 }
 513
 514 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 515 {
 516         return __intel_gpio_get_gpio_mode(readl(padcfg0));
 517 }
 518
 519 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 520 {
 521         u32 value;
 522
 523         value = readl(padcfg0);
 524
 525         /* Put the pad into GPIO mode */
 526         value &= ~PADCFG0_PMODE_MASK;
 527         value |= PADCFG0_PMODE_GPIO;
 528
 529         /* Disable TX buffer and enable RX (this will be input) */
 530         value = __intel_gpio_set_direction(value, true, false);
 531
 532         /* Disable SCI/SMI/NMI generation */
 533         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 534         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 535
 536         writel(value, padcfg0);
 537 }
 538
 539 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 540                                      struct pinctrl_gpio_range *range,
 541                                      unsigned int pin)
 542 {
 543         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 544         void __iomem *padcfg0;
 545
 546         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 547
 548         guard(raw_spinlock_irqsave)(&pctrl->lock);
 549
 550         if (!intel_pad_owned_by_host(pctrl, pin))
 551                 return -EBUSY;
 552
 553         if (!intel_pad_is_unlocked(pctrl, pin))
 554                 return 0;
 555
 556         /*
 557          * If pin is already configured in GPIO mode, we assume that
 558          * firmware provides correct settings. In such case we avoid
 559          * potential glitches on the pin. Otherwise, for the pin in
 560          * alternative mode, consumer has to supply respective flags.
 561          */
 562         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO)
 563                 return 0;
 564
 565         intel_gpio_set_gpio_mode(padcfg0);
 566
 567         return 0;
 568 }
 569
 570 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 571                                     struct pinctrl_gpio_range *range,
 572                                     unsigned int pin, bool input)
 573 {
 574         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 575         void __iomem *padcfg0;
 576         u32 value;
 577
 578         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 579
 580         guard(raw_spinlock_irqsave)(&pctrl->lock);
 581
 582         value = readl(padcfg0);
 583         if (input)
 584                 value = __intel_gpio_set_direction(value, true, false);
 585         else
 586                 value = __intel_gpio_set_direction(value, false, true);
 587         writel(value, padcfg0);
 588
 589         return 0;
 590 }
 591
 592 static const struct pinmux_ops intel_pinmux_ops = {
 593         .get_functions_count = intel_get_functions_count,
 594         .get_function_name = intel_get_function_name,
 595         .get_function_groups = intel_get_function_groups,
 596         .set_mux = intel_pinmux_set_mux,
 597         .gpio_request_enable = intel_gpio_request_enable,
 598         .gpio_set_direction = intel_gpio_set_direction,
 599 };
 600
 601 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 602                                  enum pin_config_param param, u32 *arg)
 603 {
 604         void __iomem *padcfg1;
 605         u32 value, term;
 606
 607         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 608
 609         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 610                 value = readl(padcfg1);
 611
 612         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 613
 614         switch (param) {
 615         case PIN_CONFIG_BIAS_DISABLE:
 616                 if (term)
 617                         return -EINVAL;
 618                 break;
 619
 620         case PIN_CONFIG_BIAS_PULL_UP:
 621                 if (!term || !(value & PADCFG1_TERM_UP))
 622                         return -EINVAL;
 623
 624                 switch (term) {
 625                 case PADCFG1_TERM_833:
 626                         *arg = 833;
 627                         break;
 628                 case PADCFG1_TERM_1K:
 629                         *arg = 1000;
 630                         break;
 631                 case PADCFG1_TERM_4K:
 632                         *arg = 4000;
 633                         break;
 634                 case PADCFG1_TERM_5K:
 635                         *arg = 5000;
 636                         break;
 637                 case PADCFG1_TERM_20K:
 638                         *arg = 20000;
 639                         break;
 640                 }
 641
 642                 break;
 643
 644         case PIN_CONFIG_BIAS_PULL_DOWN: {
 645                 const struct intel_community *community = intel_get_community(pctrl, pin);
 646
 647                 if (!term || value & PADCFG1_TERM_UP)
 648                         return -EINVAL;
 649
 650                 switch (term) {
 651                 case PADCFG1_TERM_833:
 652                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 653                                 return -EINVAL;
 654                         *arg = 833;
 655                         break;
 656                 case PADCFG1_TERM_1K:
 657                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 658                                 return -EINVAL;
 659                         *arg = 1000;
 660                         break;
 661                 case PADCFG1_TERM_4K:
 662                         *arg = 4000;
 663                         break;
 664                 case PADCFG1_TERM_5K:
 665                         *arg = 5000;
 666                         break;
 667                 case PADCFG1_TERM_20K:
 668                         *arg = 20000;
 669                         break;
 670                 }
 671
 672                 break;
 673         }
 674
 675         default:
 676                 return -EINVAL;
 677         }
 678
 679         return 0;
 680 }
 681
 682 static int intel_config_get_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin,
 683                                            enum pin_config_param param, u32 *arg)
 684 {
 685         void __iomem *padcfg0;
 686         u32 value;
 687
 688         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 689
 690         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 691                 value = readl(padcfg0);
 692
 693         if (__intel_gpio_get_direction(value) != PAD_CONNECT_NONE)
 694                 return -EINVAL;
 695
 696         return 0;
 697 }
 698
 699 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
 700                                      enum pin_config_param param, u32 *arg)
 701 {
 702         void __iomem *padcfg2;
 703         unsigned long v;
 704         u32 value2;
 705
 706         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 707         if (!padcfg2)
 708                 return -ENOTSUPP;
 709
 710         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
 711                 value2 = readl(padcfg2);
 712
 713         if (!(value2 & PADCFG2_DEBEN))
 714                 return -EINVAL;
 715
 716         v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 717         *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 718
 719         return 0;
 720 }
 721
 722 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 723                             unsigned long *config)
 724 {
 725         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 726         enum pin_config_param param = pinconf_to_config_param(*config);
 727         u32 arg = 0;
 728         int ret;
 729
 730         if (!intel_pad_owned_by_host(pctrl, pin))
 731                 return -ENOTSUPP;
 732
 733         switch (param) {
 734         case PIN_CONFIG_BIAS_DISABLE:
 735         case PIN_CONFIG_BIAS_PULL_UP:
 736         case PIN_CONFIG_BIAS_PULL_DOWN:
 737                 ret = intel_config_get_pull(pctrl, pin, param, &arg);
 738                 if (ret)
 739                         return ret;
 740                 break;
 741
 742         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 743                 ret = intel_config_get_high_impedance(pctrl, pin, param, &arg);
 744                 if (ret)
 745                         return ret;
 746                 break;
 747
 748         case PIN_CONFIG_INPUT_DEBOUNCE:
 749                 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
 750                 if (ret)
 751                         return ret;
 752                 break;
 753
 754         default:
 755                 return -ENOTSUPP;
 756         }
 757
 758         *config = pinconf_to_config_packed(param, arg);
 759         return 0;
 760 }
 761
 762 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 763                                  unsigned long config)
 764 {
 765         unsigned int param = pinconf_to_config_param(config);
 766         unsigned int arg = pinconf_to_config_argument(config);
 767         u32 term = 0, up = 0, value;
 768         void __iomem *padcfg1;
 769
 770         switch (param) {
 771         case PIN_CONFIG_BIAS_DISABLE:
 772                 break;
 773
 774         case PIN_CONFIG_BIAS_PULL_UP:
 775                 switch (arg) {
 776                 case 20000:
 777                         term = PADCFG1_TERM_20K;
 778                         break;
 779                 case 1: /* Set default strength value in case none is given */
 780                 case 5000:
 781                         term = PADCFG1_TERM_5K;
 782                         break;
 783                 case 4000:
 784                         term = PADCFG1_TERM_4K;
 785                         break;
 786                 case 1000:
 787                         term = PADCFG1_TERM_1K;
 788                         break;
 789                 case 833:
 790                         term = PADCFG1_TERM_833;
 791                         break;
 792                 default:
 793                         return -EINVAL;
 794                 }
 795
 796                 up = PADCFG1_TERM_UP;
 797                 break;
 798
 799         case PIN_CONFIG_BIAS_PULL_DOWN: {
 800                 const struct intel_community *community = intel_get_community(pctrl, pin);
 801
 802                 switch (arg) {
 803                 case 20000:
 804                         term = PADCFG1_TERM_20K;
 805                         break;
 806                 case 1: /* Set default strength value in case none is given */
 807                 case 5000:
 808                         term = PADCFG1_TERM_5K;
 809                         break;
 810                 case 4000:
 811                         term = PADCFG1_TERM_4K;
 812                         break;
 813                 case 1000:
 814                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 815                                 return -EINVAL;
 816                         term = PADCFG1_TERM_1K;
 817                         break;
 818                 case 833:
 819                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 820                                 return -EINVAL;
 821                         term = PADCFG1_TERM_833;
 822                         break;
 823                 default:
 824                         return -EINVAL;
 825                 }
 826
 827                 break;
 828         }
 829
 830         default:
 831                 return -EINVAL;
 832         }
 833
 834         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 835
 836         guard(raw_spinlock_irqsave)(&pctrl->lock);
 837
 838         value = readl(padcfg1);
 839         value = (value & ~PADCFG1_TERM_MASK) | (term << PADCFG1_TERM_SHIFT);
 840         value = (value & ~PADCFG1_TERM_UP) | up;
 841         writel(value, padcfg1);
 842
 843         return 0;
 844 }
 845
 846 static void intel_gpio_set_high_impedance(struct intel_pinctrl *pctrl, unsigned int pin)
 847 {
 848         void __iomem *padcfg0;
 849         u32 value;
 850
 851         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 852
 853         guard(raw_spinlock_irqsave)(&pctrl->lock);
 854
 855         value = readl(padcfg0);
 856         value = __intel_gpio_set_direction(value, false, false);
 857         writel(value, padcfg0);
 858 }
 859
 860 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 861                                      unsigned int pin, unsigned int debounce)
 862 {
 863         void __iomem *padcfg0, *padcfg2;
 864         u32 value0, value2;
 865         unsigned long v;
 866
 867         if (debounce) {
 868                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 869                 if (v < 3 || v > 15)
 870                         return -EINVAL;
 871         } else {
 872                 v = 0;
 873         }
 874
 875         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 876         if (!padcfg2)
 877                 return -ENOTSUPP;
 878
 879         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 880
 881         guard(raw_spinlock_irqsave)(&pctrl->lock);
 882
 883         value0 = readl(padcfg0);
 884         value2 = readl(padcfg2);
 885
 886         value2 = (value2 & ~PADCFG2_DEBOUNCE_MASK) | (v << PADCFG2_DEBOUNCE_SHIFT);
 887         if (v) {
 888                 /* Enable glitch filter and debouncer */
 889                 value0 |= PADCFG0_PREGFRXSEL;
 890                 value2 |= PADCFG2_DEBEN;
 891         } else {
 892                 /* Disable glitch filter and debouncer */
 893                 value0 &= ~PADCFG0_PREGFRXSEL;
 894                 value2 &= ~PADCFG2_DEBEN;
 895         }
 896
 897         writel(value0, padcfg0);
 898         writel(value2, padcfg2);
 899
 900         return 0;
 901 }
 902
 903 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 904                           unsigned long *configs, unsigned int nconfigs)
 905 {
 906         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 907         int i, ret;
 908
 909         if (!intel_pad_usable(pctrl, pin))
 910                 return -ENOTSUPP;
 911
 912         for (i = 0; i < nconfigs; i++) {
 913                 switch (pinconf_to_config_param(configs[i])) {
 914                 case PIN_CONFIG_BIAS_DISABLE:
 915                 case PIN_CONFIG_BIAS_PULL_UP:
 916                 case PIN_CONFIG_BIAS_PULL_DOWN:
 917                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 918                         if (ret)
 919                                 return ret;
 920                         break;
 921
 922                 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 923                         intel_gpio_set_high_impedance(pctrl, pin);
 924                         break;
 925
 926                 case PIN_CONFIG_INPUT_DEBOUNCE:
 927                         ret = intel_config_set_debounce(pctrl, pin,
 928                                 pinconf_to_config_argument(configs[i]));
 929                         if (ret)
 930                                 return ret;
 931                         break;
 932
 933                 default:
 934                         return -ENOTSUPP;
 935                 }
 936         }
 937
 938         return 0;
 939 }
 940
 941 static const struct pinconf_ops intel_pinconf_ops = {
 942         .is_generic = true,
 943         .pin_config_get = intel_config_get,
 944         .pin_config_set = intel_config_set,
 945 };
 946
 947 static const struct pinctrl_desc intel_pinctrl_desc = {
 948         .pctlops = &intel_pinctrl_ops,
 949         .pmxops = &intel_pinmux_ops,
 950         .confops = &intel_pinconf_ops,
 951         .owner = THIS_MODULE,
 952 };
 953
 954 /**
 955  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 956  * @pctrl: Pinctrl structure
 957  * @offset: GPIO offset from gpiolib
 958  * @community: Community is filled here if not %NULL
 959  * @padgrp: Pad group is filled here if not %NULL
 960  *
 961  * When coming through gpiolib irqchip, the GPIO offset is not
 962  * automatically translated to pinctrl pin number. This function can be
 963  * used to find out the corresponding pinctrl pin.
 964  *
 965  * Return: a pin number and pointers to the community and pad group, which
 966  * the pin belongs to, or negative error code if translation can't be done.
 967  */
 968 static int intel_gpio_to_pin(const struct intel_pinctrl *pctrl, unsigned int offset,
 969                              const struct intel_community **community,
 970                              const struct intel_padgroup **padgrp)
 971 {
 972         const struct intel_community *comm;
 973         const struct intel_padgroup *grp;
 974
 975         for_each_intel_gpio_group(pctrl, comm, grp) {
 976                 if (offset >= grp->gpio_base && offset < grp->gpio_base + grp->size) {
 977                         if (community)
 978                                 *community = comm;
 979                         if (padgrp)
 980                                 *padgrp = grp;
 981
 982                         return grp->base + offset - grp->gpio_base;
 983                 }
 984         }
 985
 986         return -EINVAL;
 987 }
 988
 989 /**
 990  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
 991  * @pctrl: Pinctrl structure
 992  * @pin: pin number
 993  *
 994  * Translate the pin number of pinctrl to GPIO offset
 995  *
 996  * Return: a GPIO offset, or negative error code if translation can't be done.
 997  */
 998 static int intel_pin_to_gpio(const struct intel_pinctrl *pctrl, int pin)
 999 {
1000         const struct intel_community *community;
1001         const struct intel_padgroup *padgrp;
1002
1003         community = intel_get_community(pctrl, pin);
1004         if (!community)
1005                 return -EINVAL;
1006
1007         padgrp = intel_community_get_padgroup(community, pin);
1008         if (!padgrp)
1009                 return -EINVAL;
1010
1011         return pin - padgrp->base + padgrp->gpio_base;
1012 }
1013
1014 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
1015 {
1016         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1017         void __iomem *reg;
1018         u32 padcfg0;
1019         int pin;
1020
1021         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
1022         if (pin < 0)
1023                 return -EINVAL;
1024
1025         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1026         if (!reg)
1027                 return -EINVAL;
1028
1029         padcfg0 = readl(reg);
1030         if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
1031                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
1032
1033         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
1034 }
1035
1036 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
1037                            int value)
1038 {
1039         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1040         void __iomem *reg;
1041         u32 padcfg0;
1042         int pin;
1043
1044         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
1045         if (pin < 0)
1046                 return;
1047
1048         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1049         if (!reg)
1050                 return;
1051
1052         guard(raw_spinlock_irqsave)(&pctrl->lock);
1053
1054         padcfg0 = readl(reg);
1055         if (value)
1056                 padcfg0 |= PADCFG0_GPIOTXSTATE;
1057         else
1058                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
1059         writel(padcfg0, reg);
1060 }
1061
1062 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1063 {
1064         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1065         void __iomem *reg;
1066         u32 padcfg0;
1067         int pin;
1068
1069         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
1070         if (pin < 0)
1071                 return -EINVAL;
1072
1073         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1074         if (!reg)
1075                 return -EINVAL;
1076
1077         scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
1078                 padcfg0 = readl(reg);
1079
1080         if (padcfg0 & PADCFG0_PMODE_MASK)
1081                 return -EINVAL;
1082
1083         if (__intel_gpio_get_direction(padcfg0) & PAD_CONNECT_OUTPUT)
1084                 return GPIO_LINE_DIRECTION_OUT;
1085
1086         return GPIO_LINE_DIRECTION_IN;
1087 }
1088
1089 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1090 {
1091         return pinctrl_gpio_direction_input(chip, offset);
1092 }
1093
1094 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1095                                        int value)
1096 {
1097         intel_gpio_set(chip, offset, value);
1098         return pinctrl_gpio_direction_output(chip, offset);
1099 }
1100
1101 static const struct gpio_chip intel_gpio_chip = {
1102         .owner = THIS_MODULE,
1103         .request = gpiochip_generic_request,
1104         .free = gpiochip_generic_free,
1105         .get_direction = intel_gpio_get_direction,
1106         .direction_input = intel_gpio_direction_input,
1107         .direction_output = intel_gpio_direction_output,
1108         .get = intel_gpio_get,
1109         .set = intel_gpio_set,
1110         .set_config = gpiochip_generic_config,
1111 };
1112
1113 static void intel_gpio_irq_ack(struct irq_data *d)
1114 {
1115         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1116         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1117         const struct intel_community *community;
1118         const struct intel_padgroup *padgrp;
1119         int pin;
1120
1121         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1122         if (pin >= 0) {
1123                 unsigned int gpp, gpp_offset;
1124                 void __iomem *is;
1125
1126                 gpp = padgrp->reg_num;
1127                 gpp_offset = padgroup_offset(padgrp, pin);
1128
1129                 is = community->regs + community->is_offset + gpp * 4;
1130
1131                 guard(raw_spinlock)(&pctrl->lock);
1132
1133                 writel(BIT(gpp_offset), is);
1134         }
1135 }
1136
1137 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1138 {
1139         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1140         const struct intel_community *community;
1141         const struct intel_padgroup *padgrp;
1142         int pin;
1143
1144         pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
1145         if (pin >= 0) {
1146                 unsigned int gpp, gpp_offset;
1147                 void __iomem *reg, *is;
1148                 u32 value;
1149
1150                 gpp = padgrp->reg_num;
1151                 gpp_offset = padgroup_offset(padgrp, pin);
1152
1153                 reg = community->regs + community->ie_offset + gpp * 4;
1154                 is = community->regs + community->is_offset + gpp * 4;
1155
1156                 guard(raw_spinlock_irqsave)(&pctrl->lock);
1157
1158                 /* Clear interrupt status first to avoid unexpected interrupt */
1159                 writel(BIT(gpp_offset), is);
1160
1161                 value = readl(reg);
1162                 if (mask)
1163                         value &= ~BIT(gpp_offset);
1164                 else
1165                         value |= BIT(gpp_offset);
1166                 writel(value, reg);
1167         }
1168 }
1169
1170 static void intel_gpio_irq_mask(struct irq_data *d)
1171 {
1172         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1173         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1174
1175         intel_gpio_irq_mask_unmask(gc, hwirq, true);
1176         gpiochip_disable_irq(gc, hwirq);
1177 }
1178
1179 static void intel_gpio_irq_unmask(struct irq_data *d)
1180 {
1181         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1182         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1183
1184         gpiochip_enable_irq(gc, hwirq);
1185         intel_gpio_irq_mask_unmask(gc, hwirq, false);
1186 }
1187
1188 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1189 {
1190         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1191         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1192         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1193         u32 rxevcfg, rxinv, value;
1194         void __iomem *reg;
1195
1196         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1197         if (!reg)
1198                 return -EINVAL;
1199
1200         /*
1201          * If the pin is in ACPI mode it is still usable as a GPIO but it
1202          * cannot be used as IRQ because GPI_IS status bit will not be
1203          * updated by the host controller hardware.
1204          */
1205         if (intel_pad_acpi_mode(pctrl, pin)) {
1206                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1207                 return -EPERM;
1208         }
1209
1210         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1211                 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
1212         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1213                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1214         } else if (type & IRQ_TYPE_EDGE_RISING) {
1215                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1216         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1217                 rxevcfg = PADCFG0_RXEVCFG_LEVEL;
1218         } else {
1219                 rxevcfg = PADCFG0_RXEVCFG_DISABLED;
1220         }
1221
1222         if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW)
1223                 rxinv = PADCFG0_RXINV;
1224         else
1225                 rxinv = 0;
1226
1227         guard(raw_spinlock_irqsave)(&pctrl->lock);
1228
1229         intel_gpio_set_gpio_mode(reg);
1230
1231         value = readl(reg);
1232
1233         value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;
1234         value = (value & ~PADCFG0_RXINV) | rxinv;
1235
1236         writel(value, reg);
1237
1238         if (type & IRQ_TYPE_EDGE_BOTH)
1239                 irq_set_handler_locked(d, handle_edge_irq);
1240         else if (type & IRQ_TYPE_LEVEL_MASK)
1241                 irq_set_handler_locked(d, handle_level_irq);
1242
1243         return 0;
1244 }
1245
1246 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1247 {
1248         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1249         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1250         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1251
1252         if (on)
1253                 enable_irq_wake(pctrl->irq);
1254         else
1255                 disable_irq_wake(pctrl->irq);
1256
1257         dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin);
1258         return 0;
1259 }
1260
1261 static const struct irq_chip intel_gpio_irq_chip = {
1262         .name = "intel-gpio",
1263         .irq_ack = intel_gpio_irq_ack,
1264         .irq_mask = intel_gpio_irq_mask,
1265         .irq_unmask = intel_gpio_irq_unmask,
1266         .irq_set_type = intel_gpio_irq_type,
1267         .irq_set_wake = intel_gpio_irq_wake,
1268         .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1269         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1270 };
1271
1272 static irqreturn_t intel_gpio_irq(int irq, void *data)
1273 {
1274         const struct intel_community *community;
1275         const struct intel_padgroup *padgrp;
1276         struct intel_pinctrl *pctrl = data;
1277         int ret = 0;
1278
1279         /* Need to check all communities for pending interrupts */
1280         for_each_intel_pad_group(pctrl, community, padgrp) {
1281                 struct gpio_chip *gc = &pctrl->chip;
1282                 unsigned long pending, enabled;
1283                 unsigned int gpp, gpp_offset;
1284                 void __iomem *reg, *is;
1285
1286                 gpp = padgrp->reg_num;
1287
1288                 reg = community->regs + community->ie_offset + gpp * 4;
1289                 is = community->regs + community->is_offset + gpp * 4;
1290
1291                 scoped_guard(raw_spinlock, &pctrl->lock) {
1292                         pending = readl(is);
1293                         enabled = readl(reg);
1294                 }
1295
1296                 /* Only interrupts that are enabled */
1297                 pending &= enabled;
1298
1299                 for_each_set_bit(gpp_offset, &pending, padgrp->size)
1300                         generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset);
1301
1302                 ret += pending ? 1 : 0;
1303         }
1304
1305         return IRQ_RETVAL(ret);
1306 }
1307
1308 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1309 {
1310         const struct intel_community *community;
1311
1312         for_each_intel_pin_community(pctrl, community) {
1313                 void __iomem *reg, *is;
1314                 unsigned int gpp;
1315
1316                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1317                         reg = community->regs + community->ie_offset + gpp * 4;
1318                         is = community->regs + community->is_offset + gpp * 4;
1319
1320                         /* Mask and clear all interrupts */
1321                         writel(0, reg);
1322                         writel(0xffff, is);
1323                 }
1324         }
1325 }
1326
1327 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1328 {
1329         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1330
1331         /*
1332          * Make sure the interrupt lines are in a proper state before
1333          * further configuration.
1334          */
1335         intel_gpio_irq_init(pctrl);
1336
1337         return 0;
1338 }
1339
1340 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1341 {
1342         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1343         const struct intel_community *community;
1344         const struct intel_padgroup *grp;
1345         int ret;
1346
1347         for_each_intel_gpio_group(pctrl, community, grp) {
1348                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1349                                              grp->gpio_base, grp->base,
1350                                              grp->size);
1351                 if (ret) {
1352                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1353                         return ret;
1354                 }
1355         }
1356
1357         return 0;
1358 }
1359
1360 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1361 {
1362         const struct intel_community *community;
1363         const struct intel_padgroup *grp;
1364         unsigned int ngpio = 0;
1365
1366         for_each_intel_gpio_group(pctrl, community, grp) {
1367                 if (grp->gpio_base + grp->size > ngpio)
1368                         ngpio = grp->gpio_base + grp->size;
1369         }
1370
1371         return ngpio;
1372 }
1373
1374 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1375 {
1376         int ret;
1377         struct gpio_irq_chip *girq;
1378
1379         pctrl->chip = intel_gpio_chip;
1380
1381         /* Setup GPIO chip */
1382         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1383         pctrl->chip.label = dev_name(pctrl->dev);
1384         pctrl->chip.parent = pctrl->dev;
1385         pctrl->chip.base = -1;
1386         pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1387         pctrl->irq = irq;
1388
1389         /*
1390          * On some platforms several GPIO controllers share the same interrupt
1391          * line.
1392          */
1393         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1394                                IRQF_SHARED | IRQF_NO_THREAD,
1395                                dev_name(pctrl->dev), pctrl);
1396         if (ret) {
1397                 dev_err(pctrl->dev, "failed to request interrupt\n");
1398                 return ret;
1399         }
1400
1401         /* Setup IRQ chip */
1402         girq = &pctrl->chip.irq;
1403         gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
1404         /* This will let us handle the IRQ in the driver */
1405         girq->parent_handler = NULL;
1406         girq->num_parents = 0;
1407         girq->default_type = IRQ_TYPE_NONE;
1408         girq->handler = handle_bad_irq;
1409         girq->init_hw = intel_gpio_irq_init_hw;
1410
1411         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1412         if (ret) {
1413                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1414                 return ret;
1415         }
1416
1417         return 0;
1418 }
1419
1420 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1421                                                struct intel_community *community)
1422 {
1423         struct intel_padgroup *gpps;
1424         unsigned int padown_num = 0;
1425         size_t i, ngpps = community->ngpps;
1426
1427         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1428         if (!gpps)
1429                 return -ENOMEM;
1430
1431         for (i = 0; i < ngpps; i++) {
1432                 gpps[i] = community->gpps[i];
1433
1434                 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE)
1435                         return -EINVAL;
1436
1437                 /* Special treatment for GPIO base */
1438                 switch (gpps[i].gpio_base) {
1439                         case INTEL_GPIO_BASE_MATCH:
1440                                 gpps[i].gpio_base = gpps[i].base;
1441                                 break;
1442                         case INTEL_GPIO_BASE_ZERO:
1443                                 gpps[i].gpio_base = 0;
1444                                 break;
1445                         case INTEL_GPIO_BASE_NOMAP:
1446                                 break;
1447                         default:
1448                                 break;
1449                 }
1450
1451                 gpps[i].padown_num = padown_num;
1452                 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE);
1453         }
1454
1455         community->gpps = gpps;
1456
1457         return 0;
1458 }
1459
1460 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1461                                                struct intel_community *community)
1462 {
1463         struct intel_padgroup *gpps;
1464         unsigned int npins = community->npins;
1465         unsigned int padown_num = 0;
1466         size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1467
1468         if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE)
1469                 return -EINVAL;
1470
1471         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1472         if (!gpps)
1473                 return -ENOMEM;
1474
1475         for (i = 0; i < ngpps; i++) {
1476                 unsigned int gpp_size = community->gpp_size;
1477
1478                 gpps[i].reg_num = i;
1479                 gpps[i].base = community->pin_base + i * gpp_size;
1480                 gpps[i].size = min(gpp_size, npins);
1481                 npins -= gpps[i].size;
1482
1483                 gpps[i].gpio_base = gpps[i].base;
1484                 gpps[i].padown_num = padown_num;
1485
1486                 padown_num += community->gpp_num_padown_regs;
1487         }
1488
1489         community->ngpps = ngpps;
1490         community->gpps = gpps;
1491
1492         return 0;
1493 }
1494
1495 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1496 {
1497 #ifdef CONFIG_PM_SLEEP
1498         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1499         struct intel_community_context *communities;
1500         struct intel_pad_context *pads;
1501         int i;
1502
1503         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1504         if (!pads)
1505                 return -ENOMEM;
1506
1507         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1508                                    sizeof(*communities), GFP_KERNEL);
1509         if (!communities)
1510                 return -ENOMEM;
1511
1512
1513         for (i = 0; i < pctrl->ncommunities; i++) {
1514                 struct intel_community *community = &pctrl->communities[i];
1515                 u32 *intmask, *hostown;
1516
1517                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1518                                        sizeof(*intmask), GFP_KERNEL);
1519                 if (!intmask)
1520                         return -ENOMEM;
1521
1522                 communities[i].intmask = intmask;
1523
1524                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1525                                        sizeof(*hostown), GFP_KERNEL);
1526                 if (!hostown)
1527                         return -ENOMEM;
1528
1529                 communities[i].hostown = hostown;
1530         }
1531
1532         pctrl->context.pads = pads;
1533         pctrl->context.communities = communities;
1534 #endif
1535
1536         return 0;
1537 }
1538
1539 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
1540                                    struct intel_community *community)
1541 {
1542         static const struct pwm_lpss_boardinfo info = {
1543                 .clk_rate = 19200000,
1544                 .npwm = 1,
1545                 .base_unit_bits = 22,
1546                 .bypass = true,
1547         };
1548         struct pwm_chip *chip;
1549
1550         if (!(community->features & PINCTRL_FEATURE_PWM))
1551                 return 0;
1552
1553         if (!IS_REACHABLE(CONFIG_PWM_LPSS))
1554                 return 0;
1555
1556         chip = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
1557         return PTR_ERR_OR_ZERO(chip);
1558 }
1559
1560 int intel_pinctrl_probe(struct platform_device *pdev,
1561                         const struct intel_pinctrl_soc_data *soc_data)
1562 {
1563         struct device *dev = &pdev->dev;
1564         struct intel_pinctrl *pctrl;
1565         int i, ret, irq;
1566
1567         pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1568         if (!pctrl)
1569                 return -ENOMEM;
1570
1571         pctrl->dev = dev;
1572         pctrl->soc = soc_data;
1573         raw_spin_lock_init(&pctrl->lock);
1574
1575         /*
1576          * Make a copy of the communities which we can use to hold pointers
1577          * to the registers.
1578          */
1579         pctrl->ncommunities = pctrl->soc->ncommunities;
1580         pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities,
1581                                           sizeof(*pctrl->communities), GFP_KERNEL);
1582         if (!pctrl->communities)
1583                 return -ENOMEM;
1584
1585         for (i = 0; i < pctrl->ncommunities; i++) {
1586                 struct intel_community *community = &pctrl->communities[i];
1587                 void __iomem *regs;
1588                 u32 offset;
1589                 u32 value;
1590
1591                 *community = pctrl->soc->communities[i];
1592
1593                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1594                 if (IS_ERR(regs))
1595                         return PTR_ERR(regs);
1596
1597                 /*
1598                  * Determine community features based on the revision.
1599                  * A value of all ones means the device is not present.
1600                  */
1601                 value = readl(regs + REVID);
1602                 if (value == ~0u)
1603                         return -ENODEV;
1604                 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1605                         community->features |= PINCTRL_FEATURE_DEBOUNCE;
1606                         community->features |= PINCTRL_FEATURE_1K_PD;
1607                 }
1608
1609                 /* Determine community features based on the capabilities */
1610                 offset = CAPLIST;
1611                 do {
1612                         value = readl(regs + offset);
1613                         switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1614                         case CAPLIST_ID_GPIO_HW_INFO:
1615                                 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1616                                 break;
1617                         case CAPLIST_ID_PWM:
1618                                 community->features |= PINCTRL_FEATURE_PWM;
1619                                 break;
1620                         case CAPLIST_ID_BLINK:
1621                                 community->features |= PINCTRL_FEATURE_BLINK;
1622                                 break;
1623                         case CAPLIST_ID_EXP:
1624                                 community->features |= PINCTRL_FEATURE_EXP;
1625                                 break;
1626                         default:
1627                                 break;
1628                         }
1629                         offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1630                 } while (offset);
1631
1632                 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features);
1633
1634                 /* Read offset of the pad configuration registers */
1635                 offset = readl(regs + PADBAR);
1636
1637                 community->regs = regs;
1638                 community->pad_regs = regs + offset;
1639
1640                 if (community->gpps)
1641                         ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1642                 else
1643                         ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1644                 if (ret)
1645                         return ret;
1646
1647                 ret = intel_pinctrl_probe_pwm(pctrl, community);
1648                 if (ret)
1649                         return ret;
1650         }
1651
1652         irq = platform_get_irq(pdev, 0);
1653         if (irq < 0)
1654                 return irq;
1655
1656         ret = intel_pinctrl_pm_init(pctrl);
1657         if (ret)
1658                 return ret;
1659
1660         pctrl->pctldesc = intel_pinctrl_desc;
1661         pctrl->pctldesc.name = dev_name(dev);
1662         pctrl->pctldesc.pins = pctrl->soc->pins;
1663         pctrl->pctldesc.npins = pctrl->soc->npins;
1664
1665         pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1666         if (IS_ERR(pctrl->pctldev)) {
1667                 dev_err(dev, "failed to register pinctrl driver\n");
1668                 return PTR_ERR(pctrl->pctldev);
1669         }
1670
1671         ret = intel_gpio_probe(pctrl, irq);
1672         if (ret)
1673                 return ret;
1674
1675         platform_set_drvdata(pdev, pctrl);
1676
1677         return 0;
1678 }
1679 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, "PINCTRL_INTEL");
1680
1681 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1682 {
1683         const struct intel_pinctrl_soc_data *data;
1684
1685         data = device_get_match_data(&pdev->dev);
1686         if (!data)
1687                 return -ENODATA;
1688
1689         return intel_pinctrl_probe(pdev, data);
1690 }
1691 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, "PINCTRL_INTEL");
1692
1693 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1694 {
1695         const struct intel_pinctrl_soc_data *data;
1696
1697         data = intel_pinctrl_get_soc_data(pdev);
1698         if (IS_ERR(data))
1699                 return PTR_ERR(data);
1700
1701         return intel_pinctrl_probe(pdev, data);
1702 }
1703 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, "PINCTRL_INTEL");
1704
1705 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1706 {
1707         const struct intel_pinctrl_soc_data * const *table;
1708         const struct intel_pinctrl_soc_data *data;
1709         struct device *dev = &pdev->dev;
1710
1711         table = device_get_match_data(dev);
1712         if (table) {
1713                 struct acpi_device *adev = ACPI_COMPANION(dev);
1714                 unsigned int i;
1715
1716                 for (i = 0; table[i]; i++) {
1717                         if (acpi_dev_uid_match(adev, table[i]->uid))
1718                                 break;
1719                 }
1720                 data = table[i];
1721         } else {
1722                 const struct platform_device_id *id;
1723
1724                 id = platform_get_device_id(pdev);
1725                 if (!id)
1726                         return ERR_PTR(-ENODEV);
1727
1728                 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1729                 data = table[pdev->id];
1730         }
1731
1732         return data ?: ERR_PTR(-ENODATA);
1733 }
1734 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, "PINCTRL_INTEL");
1735
1736 static bool __intel_gpio_is_direct_irq(u32 value)
1737 {
1738         return (value & PADCFG0_GPIROUTIOXAPIC) &&
1739                (__intel_gpio_get_direction(value) == PAD_CONNECT_INPUT) &&
1740                (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1741 }
1742
1743 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1744 {
1745         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1746         u32 value;
1747
1748         if (!pd || !intel_pad_usable(pctrl, pin))
1749                 return false;
1750
1751         /*
1752          * Only restore the pin if it is actually in use by the kernel (or
1753          * by userspace). It is possible that some pins are used by the
1754          * BIOS during resume and those are not always locked down so leave
1755          * them alone.
1756          */
1757         if (pd->mux_owner || pd->gpio_owner ||
1758             gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1759                 return true;
1760
1761         /*
1762          * The firmware on some systems may configure GPIO pins to be
1763          * an interrupt source in so called "direct IRQ" mode. In such
1764          * cases the GPIO controller driver has no idea if those pins
1765          * are being used or not. At the same time, there is a known bug
1766          * in the firmwares that don't restore the pin settings correctly
1767          * after suspend, i.e. by an unknown reason the Rx value becomes
1768          * inverted.
1769          *
1770          * Hence, let's save and restore the pins that are configured
1771          * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
1772          *
1773          * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
1774          */
1775         value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1776         if (__intel_gpio_is_direct_irq(value))
1777                 return true;
1778
1779         return false;
1780 }
1781
1782 static int intel_pinctrl_suspend_noirq(struct device *dev)
1783 {
1784         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1785         struct intel_community_context *communities;
1786         struct intel_pad_context *pads;
1787         int i;
1788
1789         pads = pctrl->context.pads;
1790         for (i = 0; i < pctrl->soc->npins; i++) {
1791                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1792                 void __iomem *padcfg;
1793                 u32 val;
1794
1795                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1796                         continue;
1797
1798                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1799                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1800                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1801                 pads[i].padcfg1 = val;
1802
1803                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1804                 if (padcfg)
1805                         pads[i].padcfg2 = readl(padcfg);
1806         }
1807
1808         communities = pctrl->context.communities;
1809         for (i = 0; i < pctrl->ncommunities; i++) {
1810                 struct intel_community *community = &pctrl->communities[i];
1811                 void __iomem *base;
1812                 unsigned int gpp;
1813
1814                 base = community->regs + community->ie_offset;
1815                 for (gpp = 0; gpp < community->ngpps; gpp++)
1816                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1817
1818                 base = community->regs + community->hostown_offset;
1819                 for (gpp = 0; gpp < community->ngpps; gpp++)
1820                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1821         }
1822
1823         return 0;
1824 }
1825
1826 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1827 {
1828         u32 curr, updated;
1829
1830         curr = readl(reg);
1831
1832         updated = (curr & ~mask) | (value & mask);
1833         if (curr == updated)
1834                 return false;
1835
1836         writel(updated, reg);
1837         return true;
1838 }
1839
1840 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1841                                   void __iomem *base, unsigned int gpp, u32 saved)
1842 {
1843         const struct intel_community *community = &pctrl->communities[c];
1844         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1845         struct device *dev = pctrl->dev;
1846         const char *dummy;
1847         u32 requested = 0;
1848         unsigned int i;
1849
1850         if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1851                 return;
1852
1853         for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1854                 requested |= BIT(i);
1855
1856         if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1857                 return;
1858
1859         dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1860 }
1861
1862 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1863                                   void __iomem *base, unsigned int gpp, u32 saved)
1864 {
1865         struct device *dev = pctrl->dev;
1866
1867         if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1868                 return;
1869
1870         dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1871 }
1872
1873 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1874                                  unsigned int reg, u32 saved)
1875 {
1876         u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1877         unsigned int n = reg / sizeof(u32);
1878         struct device *dev = pctrl->dev;
1879         void __iomem *padcfg;
1880
1881         padcfg = intel_get_padcfg(pctrl, pin, reg);
1882         if (!padcfg)
1883                 return;
1884
1885         if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1886                 return;
1887
1888         dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1889 }
1890
1891 static int intel_pinctrl_resume_noirq(struct device *dev)
1892 {
1893         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1894         const struct intel_community_context *communities;
1895         const struct intel_pad_context *pads;
1896         int i;
1897
1898         /* Mask all interrupts */
1899         intel_gpio_irq_init(pctrl);
1900
1901         pads = pctrl->context.pads;
1902         for (i = 0; i < pctrl->soc->npins; i++) {
1903                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1904
1905                 if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
1906                       /*
1907                        * If the firmware mangled the register contents too much,
1908                        * check the saved value for the Direct IRQ mode.
1909                        */
1910                       __intel_gpio_is_direct_irq(pads[i].padcfg0)))
1911                         continue;
1912
1913                 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1914                 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1915                 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1916         }
1917
1918         communities = pctrl->context.communities;
1919         for (i = 0; i < pctrl->ncommunities; i++) {
1920                 struct intel_community *community = &pctrl->communities[i];
1921                 void __iomem *base;
1922                 unsigned int gpp;
1923
1924                 base = community->regs + community->ie_offset;
1925                 for (gpp = 0; gpp < community->ngpps; gpp++)
1926                         intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1927
1928                 base = community->regs + community->hostown_offset;
1929                 for (gpp = 0; gpp < community->ngpps; gpp++)
1930                         intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1931         }
1932
1933         return 0;
1934 }
1935
1936 EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(intel_pinctrl_pm_ops, PINCTRL_INTEL) = {
1937         NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, intel_pinctrl_resume_noirq)
1938 };
1939
1940 MODULE_AUTHOR("Mathias Nyman <[email protected]>");
1941 MODULE_AUTHOR("Mika Westerberg <[email protected]>");
1942 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1943 MODULE_LICENSE("GPL v2");