drivers/gpu/drm/arm/malidp_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   4  * Author: Liviu Dudau <[email protected]>
   5  *
   6  * ARM Mali DP500/DP550/DP650 KMS/DRM driver
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/clk.h>
  11 #include <linux/component.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_graph.h>
  14 #include <linux/of_reserved_mem.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/debugfs.h>
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_drv.h>
  22 #include <drm/drm_fbdev_dma.h>
  23 #include <drm/drm_fourcc.h>
  24 #include <drm/drm_gem_dma_helper.h>
  25 #include <drm/drm_gem_framebuffer_helper.h>
  26 #include <drm/drm_managed.h>
  27 #include <drm/drm_modeset_helper.h>
  28 #include <drm/drm_module.h>
  29 #include <drm/drm_of.h>
  30 #include <drm/drm_probe_helper.h>
  31 #include <drm/drm_vblank.h>
  32
  33 #include "malidp_drv.h"
  34 #include "malidp_mw.h"
  35 #include "malidp_regs.h"
  36 #include "malidp_hw.h"
  37
  38 #define MALIDP_CONF_VALID_TIMEOUT       250
  39 #define AFBC_HEADER_SIZE                16
  40 #define AFBC_SUPERBLK_ALIGNMENT         128
  41
  42 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
  43                                      u32 data[MALIDP_COEFFTAB_NUM_COEFFS])
  44 {
  45         int i;
  46         /* Update all channels with a single gamma curve. */
  47         const u32 gamma_write_mask = GENMASK(18, 16);
  48         /*
  49          * Always write an entire table, so the address field in
  50          * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask
  51          * directly.
  52          */
  53         malidp_hw_write(hwdev, gamma_write_mask,
  54                         hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
  55         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i)
  56                 malidp_hw_write(hwdev, data[i],
  57                                 hwdev->hw->map.coeffs_base +
  58                                 MALIDP_COEF_TABLE_DATA);
  59 }
  60
  61 static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc,
  62                                               struct drm_crtc_state *old_state)
  63 {
  64         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  65         struct malidp_hw_device *hwdev = malidp->dev;
  66
  67         if (!crtc->state->color_mgmt_changed)
  68                 return;
  69
  70         if (!crtc->state->gamma_lut) {
  71                 malidp_hw_clearbits(hwdev,
  72                                     MALIDP_DISP_FUNC_GAMMA,
  73                                     MALIDP_DE_DISPLAY_FUNC);
  74         } else {
  75                 struct malidp_crtc_state *mc =
  76                         to_malidp_crtc_state(crtc->state);
  77
  78                 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id !=
  79                                               old_state->gamma_lut->base.id))
  80                         malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
  81
  82                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
  83                                   MALIDP_DE_DISPLAY_FUNC);
  84         }
  85 }
  86
  87 static
  88 void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc,
  89                                           struct drm_crtc_state *old_state)
  90 {
  91         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  92         struct malidp_hw_device *hwdev = malidp->dev;
  93         int i;
  94
  95         if (!crtc->state->color_mgmt_changed)
  96                 return;
  97
  98         if (!crtc->state->ctm) {
  99                 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
 100                                     MALIDP_DE_DISPLAY_FUNC);
 101         } else {
 102                 struct malidp_crtc_state *mc =
 103                         to_malidp_crtc_state(crtc->state);
 104
 105                 if (!old_state->ctm || (crtc->state->ctm->base.id !=
 106                                         old_state->ctm->base.id))
 107                         for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i)
 108                                 malidp_hw_write(hwdev,
 109                                                 mc->coloradj_coeffs[i],
 110                                                 hwdev->hw->map.coeffs_base +
 111                                                 MALIDP_COLOR_ADJ_COEF + 4 * i);
 112
 113                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
 114                                   MALIDP_DE_DISPLAY_FUNC);
 115         }
 116 }
 117
 118 static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
 119                                            struct drm_crtc_state *old_state)
 120 {
 121         struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state);
 122         struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state);
 123         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 124         struct malidp_hw_device *hwdev = malidp->dev;
 125         struct malidp_se_config *s = &cs->scaler_config;
 126         struct malidp_se_config *old_s = &old_cs->scaler_config;
 127         u32 se_control = hwdev->hw->map.se_base +
 128                          ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
 129                          0x10 : 0xC);
 130         u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL;
 131         u32 scr = se_control + MALIDP_SE_SCALING_CONTROL;
 132         u32 val;
 133
 134         /* Set SE_CONTROL */
 135         if (!s->scale_enable) {
 136                 val = malidp_hw_read(hwdev, se_control);
 137                 val &= ~MALIDP_SE_SCALING_EN;
 138                 malidp_hw_write(hwdev, val, se_control);
 139                 return;
 140         }
 141
 142         hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
 143         val = malidp_hw_read(hwdev, se_control);
 144         val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
 145
 146         val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK);
 147         val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0;
 148
 149         val |= MALIDP_SE_RGBO_IF_EN;
 150         malidp_hw_write(hwdev, val, se_control);
 151
 152         /* Set IN_SIZE & OUT_SIZE. */
 153         val = MALIDP_SE_SET_V_SIZE(s->input_h) |
 154               MALIDP_SE_SET_H_SIZE(s->input_w);
 155         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
 156         val = MALIDP_SE_SET_V_SIZE(s->output_h) |
 157               MALIDP_SE_SET_H_SIZE(s->output_w);
 158         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
 159
 160         /* Set phase regs. */
 161         malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
 162         malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
 163         malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
 164         malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
 165 }
 166
 167 /*
 168  * set the "config valid" bit and wait until the hardware acts on it
 169  */
 170 static int malidp_set_and_wait_config_valid(struct drm_device *drm)
 171 {
 172         struct malidp_drm *malidp = drm_to_malidp(drm);
 173         struct malidp_hw_device *hwdev = malidp->dev;
 174         int ret;
 175
 176         hwdev->hw->set_config_valid(hwdev, 1);
 177         /* don't wait for config_valid flag if we are in config mode */
 178         if (hwdev->hw->in_config_mode(hwdev)) {
 179                 atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE);
 180                 return 0;
 181         }
 182
 183         ret = wait_event_interruptible_timeout(malidp->wq,
 184                         atomic_read(&malidp->config_valid) == MALIDP_CONFIG_VALID_DONE,
 185                         msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
 186
 187         return (ret > 0) ? 0 : -ETIMEDOUT;
 188 }
 189
 190 static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
 191 {
 192         struct drm_device *drm = state->dev;
 193         struct malidp_drm *malidp = drm_to_malidp(drm);
 194         int loop = 5;
 195
 196         malidp->event = malidp->crtc.state->event;
 197         malidp->crtc.state->event = NULL;
 198
 199         if (malidp->crtc.state->active) {
 200                 /*
 201                  * if we have an event to deliver to userspace, make sure
 202                  * the vblank is enabled as we are sending it from the IRQ
 203                  * handler.
 204                  */
 205                 if (malidp->event)
 206                         drm_crtc_vblank_get(&malidp->crtc);
 207
 208                 /* only set config_valid if the CRTC is enabled */
 209                 if (malidp_set_and_wait_config_valid(drm) < 0) {
 210                         /*
 211                          * make a loop around the second CVAL setting and
 212                          * try 5 times before giving up.
 213                          */
 214                         while (loop--) {
 215                                 if (!malidp_set_and_wait_config_valid(drm))
 216                                         break;
 217                         }
 218                         DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
 219                 }
 220
 221         } else if (malidp->event) {
 222                 /* CRTC inactive means vblank IRQ is disabled, send event directly */
 223                 spin_lock_irq(&drm->event_lock);
 224                 drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
 225                 malidp->event = NULL;
 226                 spin_unlock_irq(&drm->event_lock);
 227         }
 228         drm_atomic_helper_commit_hw_done(state);
 229 }
 230
 231 static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
 232 {
 233         struct drm_device *drm = state->dev;
 234         struct malidp_drm *malidp = drm_to_malidp(drm);
 235         struct drm_crtc *crtc;
 236         struct drm_crtc_state *old_crtc_state;
 237         int i;
 238         bool fence_cookie = dma_fence_begin_signalling();
 239
 240         pm_runtime_get_sync(drm->dev);
 241
 242         /*
 243          * set config_valid to a special value to let IRQ handlers
 244          * know that we are updating registers
 245          */
 246         atomic_set(&malidp->config_valid, MALIDP_CONFIG_START);
 247         malidp->dev->hw->set_config_valid(malidp->dev, 0);
 248
 249         drm_atomic_helper_commit_modeset_disables(drm, state);
 250
 251         for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
 252                 malidp_atomic_commit_update_gamma(crtc, old_crtc_state);
 253                 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state);
 254                 malidp_atomic_commit_se_config(crtc, old_crtc_state);
 255         }
 256
 257         drm_atomic_helper_commit_planes(drm, state, DRM_PLANE_COMMIT_ACTIVE_ONLY);
 258
 259         malidp_mw_atomic_commit(drm, state);
 260
 261         drm_atomic_helper_commit_modeset_enables(drm, state);
 262
 263         malidp_atomic_commit_hw_done(state);
 264
 265         dma_fence_end_signalling(fence_cookie);
 266
 267         pm_runtime_put(drm->dev);
 268
 269         drm_atomic_helper_cleanup_planes(drm, state);
 270 }
 271
 272 static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
 273         .atomic_commit_tail = malidp_atomic_commit_tail,
 274 };
 275
 276 static bool
 277 malidp_verify_afbc_framebuffer_caps(struct drm_device *dev,
 278                                     const struct drm_mode_fb_cmd2 *mode_cmd)
 279 {
 280         if (malidp_format_mod_supported(dev, mode_cmd->pixel_format,
 281                                         mode_cmd->modifier[0]) == false)
 282                 return false;
 283
 284         if (mode_cmd->offsets[0] != 0) {
 285                 DRM_DEBUG_KMS("AFBC buffers' plane offset should be 0\n");
 286                 return false;
 287         }
 288
 289         switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
 290         case AFBC_SIZE_16X16:
 291                 if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) {
 292                         DRM_DEBUG_KMS("AFBC buffers must be aligned to 16 pixels\n");
 293                         return false;
 294                 }
 295                 break;
 296         default:
 297                 DRM_DEBUG_KMS("Unsupported AFBC block size\n");
 298                 return false;
 299         }
 300
 301         return true;
 302 }
 303
 304 static bool
 305 malidp_verify_afbc_framebuffer_size(struct drm_device *dev,
 306                                     struct drm_file *file,
 307                                     const struct drm_mode_fb_cmd2 *mode_cmd)
 308 {
 309         int n_superblocks = 0;
 310         const struct drm_format_info *info;
 311         struct drm_gem_object *objs = NULL;
 312         u32 afbc_superblock_size = 0, afbc_superblock_height = 0;
 313         u32 afbc_superblock_width = 0, afbc_size = 0;
 314         int bpp = 0;
 315
 316         switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
 317         case AFBC_SIZE_16X16:
 318                 afbc_superblock_height = 16;
 319                 afbc_superblock_width = 16;
 320                 break;
 321         default:
 322                 DRM_DEBUG_KMS("AFBC superblock size is not supported\n");
 323                 return false;
 324         }
 325
 326         info = drm_get_format_info(dev, mode_cmd);
 327
 328         n_superblocks = (mode_cmd->width / afbc_superblock_width) *
 329                 (mode_cmd->height / afbc_superblock_height);
 330
 331         bpp = malidp_format_get_bpp(info->format);
 332
 333         afbc_superblock_size = (bpp * afbc_superblock_width * afbc_superblock_height)
 334                                 / BITS_PER_BYTE;
 335
 336         afbc_size = ALIGN(n_superblocks * AFBC_HEADER_SIZE, AFBC_SUPERBLK_ALIGNMENT);
 337         afbc_size += n_superblocks * ALIGN(afbc_superblock_size, AFBC_SUPERBLK_ALIGNMENT);
 338
 339         if ((mode_cmd->width * bpp) != (mode_cmd->pitches[0] * BITS_PER_BYTE)) {
 340                 DRM_DEBUG_KMS("Invalid value of (pitch * BITS_PER_BYTE) (=%u) "
 341                               "should be same as width (=%u) * bpp (=%u)\n",
 342                               (mode_cmd->pitches[0] * BITS_PER_BYTE),
 343                               mode_cmd->width, bpp);
 344                 return false;
 345         }
 346
 347         objs = drm_gem_object_lookup(file, mode_cmd->handles[0]);
 348         if (!objs) {
 349                 DRM_DEBUG_KMS("Failed to lookup GEM object\n");
 350                 return false;
 351         }
 352
 353         if (objs->size < afbc_size) {
 354                 DRM_DEBUG_KMS("buffer size (%zu) too small for AFBC buffer size = %u\n",
 355                               objs->size, afbc_size);
 356                 drm_gem_object_put(objs);
 357                 return false;
 358         }
 359
 360         drm_gem_object_put(objs);
 361
 362         return true;
 363 }
 364
 365 static bool
 366 malidp_verify_afbc_framebuffer(struct drm_device *dev, struct drm_file *file,
 367                                const struct drm_mode_fb_cmd2 *mode_cmd)
 368 {
 369         if (malidp_verify_afbc_framebuffer_caps(dev, mode_cmd))
 370                 return malidp_verify_afbc_framebuffer_size(dev, file, mode_cmd);
 371
 372         return false;
 373 }
 374
 375 static struct drm_framebuffer *
 376 malidp_fb_create(struct drm_device *dev, struct drm_file *file,
 377                  const struct drm_mode_fb_cmd2 *mode_cmd)
 378 {
 379         if (mode_cmd->modifier[0]) {
 380                 if (!malidp_verify_afbc_framebuffer(dev, file, mode_cmd))
 381                         return ERR_PTR(-EINVAL);
 382         }
 383
 384         return drm_gem_fb_create(dev, file, mode_cmd);
 385 }
 386
 387 static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
 388         .fb_create = malidp_fb_create,
 389         .atomic_check = drm_atomic_helper_check,
 390         .atomic_commit = drm_atomic_helper_commit,
 391 };
 392
 393 static int malidp_init(struct drm_device *drm)
 394 {
 395         int ret;
 396         struct malidp_drm *malidp = drm_to_malidp(drm);
 397         struct malidp_hw_device *hwdev = malidp->dev;
 398
 399         ret = drmm_mode_config_init(drm);
 400         if (ret)
 401                 goto out;
 402
 403         drm->mode_config.min_width = hwdev->min_line_size;
 404         drm->mode_config.min_height = hwdev->min_line_size;
 405         drm->mode_config.max_width = hwdev->max_line_size;
 406         drm->mode_config.max_height = hwdev->max_line_size;
 407         drm->mode_config.funcs = &malidp_mode_config_funcs;
 408         drm->mode_config.helper_private = &malidp_mode_config_helpers;
 409
 410         ret = malidp_crtc_init(drm);
 411         if (ret)
 412                 goto out;
 413
 414         ret = malidp_mw_connector_init(drm);
 415         if (ret)
 416                 goto out;
 417
 418 out:
 419         return ret;
 420 }
 421
 422 static int malidp_irq_init(struct platform_device *pdev)
 423 {
 424         int irq_de, irq_se, ret = 0;
 425         struct drm_device *drm = dev_get_drvdata(&pdev->dev);
 426         struct malidp_drm *malidp = drm_to_malidp(drm);
 427         struct malidp_hw_device *hwdev = malidp->dev;
 428
 429         /* fetch the interrupts from DT */
 430         irq_de = platform_get_irq_byname(pdev, "DE");
 431         if (irq_de < 0) {
 432                 DRM_ERROR("no 'DE' IRQ specified!\n");
 433                 return irq_de;
 434         }
 435         irq_se = platform_get_irq_byname(pdev, "SE");
 436         if (irq_se < 0) {
 437                 DRM_ERROR("no 'SE' IRQ specified!\n");
 438                 return irq_se;
 439         }
 440
 441         ret = malidp_de_irq_init(drm, irq_de);
 442         if (ret)
 443                 return ret;
 444
 445         ret = malidp_se_irq_init(drm, irq_se);
 446         if (ret) {
 447                 malidp_de_irq_fini(hwdev);
 448                 return ret;
 449         }
 450
 451         return 0;
 452 }
 453
 454 DEFINE_DRM_GEM_DMA_FOPS(fops);
 455
 456 static int malidp_dumb_create(struct drm_file *file_priv,
 457                               struct drm_device *drm,
 458                               struct drm_mode_create_dumb *args)
 459 {
 460         struct malidp_drm *malidp = drm_to_malidp(drm);
 461         /* allocate for the worst case scenario, i.e. rotated buffers */
 462         u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 1);
 463
 464         args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), alignment);
 465
 466         return drm_gem_dma_dumb_create_internal(file_priv, drm, args);
 467 }
 468
 469 #ifdef CONFIG_DEBUG_FS
 470
 471 static void malidp_error_stats_init(struct malidp_error_stats *error_stats)
 472 {
 473         error_stats->num_errors = 0;
 474         error_stats->last_error_status = 0;
 475         error_stats->last_error_vblank = -1;
 476 }
 477
 478 void malidp_error(struct malidp_drm *malidp,
 479                   struct malidp_error_stats *error_stats, u32 status,
 480                   u64 vblank)
 481 {
 482         unsigned long irqflags;
 483
 484         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 485         error_stats->last_error_status = status;
 486         error_stats->last_error_vblank = vblank;
 487         error_stats->num_errors++;
 488         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 489 }
 490
 491 static void malidp_error_stats_dump(const char *prefix,
 492                                     struct malidp_error_stats error_stats,
 493                                     struct seq_file *m)
 494 {
 495         seq_printf(m, "[%s] num_errors : %d\n", prefix,
 496                    error_stats.num_errors);
 497         seq_printf(m, "[%s] last_error_status  : 0x%08x\n", prefix,
 498                    error_stats.last_error_status);
 499         seq_printf(m, "[%s] last_error_vblank : %lld\n", prefix,
 500                    error_stats.last_error_vblank);
 501 }
 502
 503 static int malidp_show_stats(struct seq_file *m, void *arg)
 504 {
 505         struct drm_device *drm = m->private;
 506         struct malidp_drm *malidp = drm_to_malidp(drm);
 507         unsigned long irqflags;
 508         struct malidp_error_stats de_errors, se_errors;
 509
 510         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 511         de_errors = malidp->de_errors;
 512         se_errors = malidp->se_errors;
 513         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 514         malidp_error_stats_dump("DE", de_errors, m);
 515         malidp_error_stats_dump("SE", se_errors, m);
 516         return 0;
 517 }
 518
 519 static int malidp_debugfs_open(struct inode *inode, struct file *file)
 520 {
 521         return single_open(file, malidp_show_stats, inode->i_private);
 522 }
 523
 524 static ssize_t malidp_debugfs_write(struct file *file, const char __user *ubuf,
 525                                     size_t len, loff_t *offp)
 526 {
 527         struct seq_file *m = file->private_data;
 528         struct drm_device *drm = m->private;
 529         struct malidp_drm *malidp = drm_to_malidp(drm);
 530         unsigned long irqflags;
 531
 532         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 533         malidp_error_stats_init(&malidp->de_errors);
 534         malidp_error_stats_init(&malidp->se_errors);
 535         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 536         return len;
 537 }
 538
 539 static const struct file_operations malidp_debugfs_fops = {
 540         .owner = THIS_MODULE,
 541         .open = malidp_debugfs_open,
 542         .read = seq_read,
 543         .write = malidp_debugfs_write,
 544         .llseek = seq_lseek,
 545         .release = single_release,
 546 };
 547
 548 static void malidp_debugfs_init(struct drm_minor *minor)
 549 {
 550         struct malidp_drm *malidp = drm_to_malidp(minor->dev);
 551
 552         malidp_error_stats_init(&malidp->de_errors);
 553         malidp_error_stats_init(&malidp->se_errors);
 554         spin_lock_init(&malidp->errors_lock);
 555         debugfs_create_file("debug", S_IRUGO | S_IWUSR, minor->debugfs_root,
 556                             minor->dev, &malidp_debugfs_fops);
 557 }
 558
 559 #endif //CONFIG_DEBUG_FS
 560
 561 static const struct drm_driver malidp_driver = {
 562         .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
 563         DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(malidp_dumb_create),
 564 #ifdef CONFIG_DEBUG_FS
 565         .debugfs_init = malidp_debugfs_init,
 566 #endif
 567         .fops = &fops,
 568         .name = "mali-dp",
 569         .desc = "ARM Mali Display Processor driver",
 570         .date = "20160106",
 571         .major = 1,
 572         .minor = 0,
 573 };
 574
 575 static const struct of_device_id  malidp_drm_of_match[] = {
 576         {
 577                 .compatible = "arm,mali-dp500",
 578                 .data = &malidp_device[MALIDP_500]
 579         },
 580         {
 581                 .compatible = "arm,mali-dp550",
 582                 .data = &malidp_device[MALIDP_550]
 583         },
 584         {
 585                 .compatible = "arm,mali-dp650",
 586                 .data = &malidp_device[MALIDP_650]
 587         },
 588         {},
 589 };
 590 MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
 591
 592 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
 593                                        const struct of_device_id *dev_id)
 594 {
 595         u32 core_id;
 596         const char *compatstr_dp500 = "arm,mali-dp500";
 597         bool is_dp500;
 598         bool dt_is_dp500;
 599
 600         /*
 601          * The DP500 CORE_ID register is in a different location, so check it
 602          * first. If the product id field matches, then this is DP500, otherwise
 603          * check the DP550/650 CORE_ID register.
 604          */
 605         core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
 606         /* Offset 0x18 will never read 0x500 on products other than DP500. */
 607         is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);
 608         dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,
 609                               sizeof(dev_id->compatible)) != NULL;
 610         if (is_dp500 != dt_is_dp500) {
 611                 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",
 612                           dev_id->compatible, is_dp500 ? "is" : "is not");
 613                 return false;
 614         } else if (!dt_is_dp500) {
 615                 u16 product_id;
 616                 char buf[32];
 617
 618                 core_id = malidp_hw_read(hwdev,
 619                                          MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);
 620                 product_id = MALIDP_PRODUCT_ID(core_id);
 621                 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);
 622                 if (!strnstr(dev_id->compatible, buf,
 623                              sizeof(dev_id->compatible))) {
 624                         DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",
 625                                   dev_id->compatible, product_id);
 626                         return false;
 627                 }
 628         }
 629         return true;
 630 }
 631
 632 static bool malidp_has_sufficient_address_space(const struct resource *res,
 633                                                 const struct of_device_id *dev_id)
 634 {
 635         resource_size_t res_size = resource_size(res);
 636         const char *compatstr_dp500 = "arm,mali-dp500";
 637
 638         if (!strnstr(dev_id->compatible, compatstr_dp500,
 639                      sizeof(dev_id->compatible)))
 640                 return res_size >= MALIDP550_ADDR_SPACE_SIZE;
 641         else if (res_size < MALIDP500_ADDR_SPACE_SIZE)
 642                 return false;
 643         return true;
 644 }
 645
 646 static ssize_t core_id_show(struct device *dev, struct device_attribute *attr,
 647                             char *buf)
 648 {
 649         struct drm_device *drm = dev_get_drvdata(dev);
 650         struct malidp_drm *malidp = drm_to_malidp(drm);
 651
 652         return sysfs_emit(buf, "%08x\n", malidp->core_id);
 653 }
 654
 655 static DEVICE_ATTR_RO(core_id);
 656
 657 static struct attribute *mali_dp_attrs[] = {
 658         &dev_attr_core_id.attr,
 659         NULL,
 660 };
 661 ATTRIBUTE_GROUPS(mali_dp);
 662
 663 #define MAX_OUTPUT_CHANNELS     3
 664
 665 static int malidp_runtime_pm_suspend(struct device *dev)
 666 {
 667         struct drm_device *drm = dev_get_drvdata(dev);
 668         struct malidp_drm *malidp = drm_to_malidp(drm);
 669         struct malidp_hw_device *hwdev = malidp->dev;
 670
 671         /* we can only suspend if the hardware is in config mode */
 672         WARN_ON(!hwdev->hw->in_config_mode(hwdev));
 673
 674         malidp_se_irq_fini(hwdev);
 675         malidp_de_irq_fini(hwdev);
 676         hwdev->pm_suspended = true;
 677         clk_disable_unprepare(hwdev->mclk);
 678         clk_disable_unprepare(hwdev->aclk);
 679         clk_disable_unprepare(hwdev->pclk);
 680
 681         return 0;
 682 }
 683
 684 static int malidp_runtime_pm_resume(struct device *dev)
 685 {
 686         struct drm_device *drm = dev_get_drvdata(dev);
 687         struct malidp_drm *malidp = drm_to_malidp(drm);
 688         struct malidp_hw_device *hwdev = malidp->dev;
 689
 690         clk_prepare_enable(hwdev->pclk);
 691         clk_prepare_enable(hwdev->aclk);
 692         clk_prepare_enable(hwdev->mclk);
 693         hwdev->pm_suspended = false;
 694         malidp_de_irq_hw_init(hwdev);
 695         malidp_se_irq_hw_init(hwdev);
 696
 697         return 0;
 698 }
 699
 700 static int malidp_bind(struct device *dev)
 701 {
 702         struct resource *res;
 703         struct drm_device *drm;
 704         struct malidp_drm *malidp;
 705         struct malidp_hw_device *hwdev;
 706         struct platform_device *pdev = to_platform_device(dev);
 707         struct of_device_id const *dev_id;
 708         struct drm_encoder *encoder;
 709         /* number of lines for the R, G and B output */
 710         u8 output_width[MAX_OUTPUT_CHANNELS];
 711         int ret = 0, i;
 712         u32 version, out_depth = 0;
 713
 714         malidp = devm_drm_dev_alloc(dev, &malidp_driver, typeof(*malidp), base);
 715         if (IS_ERR(malidp))
 716                 return PTR_ERR(malidp);
 717
 718         drm = &malidp->base;
 719
 720         hwdev = drmm_kzalloc(drm, sizeof(*hwdev), GFP_KERNEL);
 721         if (!hwdev)
 722                 return -ENOMEM;
 723
 724         hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
 725         malidp->dev = hwdev;
 726
 727         hwdev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 728         if (IS_ERR(hwdev->regs))
 729                 return PTR_ERR(hwdev->regs);
 730
 731         hwdev->pclk = devm_clk_get(dev, "pclk");
 732         if (IS_ERR(hwdev->pclk))
 733                 return PTR_ERR(hwdev->pclk);
 734
 735         hwdev->aclk = devm_clk_get(dev, "aclk");
 736         if (IS_ERR(hwdev->aclk))
 737                 return PTR_ERR(hwdev->aclk);
 738
 739         hwdev->mclk = devm_clk_get(dev, "mclk");
 740         if (IS_ERR(hwdev->mclk))
 741                 return PTR_ERR(hwdev->mclk);
 742
 743         hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
 744         if (IS_ERR(hwdev->pxlclk))
 745                 return PTR_ERR(hwdev->pxlclk);
 746
 747         /* Get the optional framebuffer memory resource */
 748         ret = of_reserved_mem_device_init(dev);
 749         if (ret && ret != -ENODEV)
 750                 return ret;
 751
 752         dev_set_drvdata(dev, drm);
 753
 754         /* Enable power management */
 755         pm_runtime_enable(dev);
 756
 757         /* Resume device to enable the clocks */
 758         if (pm_runtime_enabled(dev))
 759                 pm_runtime_get_sync(dev);
 760         else
 761                 malidp_runtime_pm_resume(dev);
 762
 763         dev_id = of_match_device(malidp_drm_of_match, dev);
 764         if (!dev_id) {
 765                 ret = -EINVAL;
 766                 goto query_hw_fail;
 767         }
 768
 769         if (!malidp_has_sufficient_address_space(res, dev_id)) {
 770                 DRM_ERROR("Insufficient address space in device-tree.\n");
 771                 ret = -EINVAL;
 772                 goto query_hw_fail;
 773         }
 774
 775         if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
 776                 ret = -EINVAL;
 777                 goto query_hw_fail;
 778         }
 779
 780         ret = hwdev->hw->query_hw(hwdev);
 781         if (ret) {
 782                 DRM_ERROR("Invalid HW configuration\n");
 783                 goto query_hw_fail;
 784         }
 785
 786         version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
 787         DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
 788                  (version >> 12) & 0xf, (version >> 8) & 0xf);
 789
 790         malidp->core_id = version;
 791
 792         ret = of_property_read_u32(dev->of_node,
 793                                         "arm,malidp-arqos-value",
 794                                         &hwdev->arqos_value);
 795         if (ret)
 796                 hwdev->arqos_value = 0x0;
 797
 798         /* set the number of lines used for output of RGB data */
 799         ret = of_property_read_u8_array(dev->of_node,
 800                                         "arm,malidp-output-port-lines",
 801                                         output_width, MAX_OUTPUT_CHANNELS);
 802         if (ret)
 803                 goto query_hw_fail;
 804
 805         for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
 806                 out_depth = (out_depth << 8) | (output_width[i] & 0xf);
 807         malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
 808         hwdev->output_color_depth = out_depth;
 809
 810         atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_INIT);
 811         init_waitqueue_head(&malidp->wq);
 812
 813         ret = malidp_init(drm);
 814         if (ret < 0)
 815                 goto query_hw_fail;
 816
 817         /* Set the CRTC's port so that the encoder component can find it */
 818         malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
 819
 820         ret = component_bind_all(dev, drm);
 821         if (ret) {
 822                 DRM_ERROR("Failed to bind all components\n");
 823                 goto bind_fail;
 824         }
 825
 826         /* We expect to have a maximum of two encoders one for the actual
 827          * display and a virtual one for the writeback connector
 828          */
 829         WARN_ON(drm->mode_config.num_encoder > 2);
 830         list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) {
 831                 encoder->possible_clones =
 832                                 (1 << drm->mode_config.num_encoder) -  1;
 833         }
 834
 835         ret = malidp_irq_init(pdev);
 836         if (ret < 0)
 837                 goto irq_init_fail;
 838
 839         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
 840         if (ret < 0) {
 841                 DRM_ERROR("failed to initialise vblank\n");
 842                 goto vblank_fail;
 843         }
 844         pm_runtime_put(dev);
 845
 846         drm_mode_config_reset(drm);
 847
 848         drm_kms_helper_poll_init(drm);
 849
 850         ret = drm_dev_register(drm, 0);
 851         if (ret)
 852                 goto register_fail;
 853
 854         drm_fbdev_dma_setup(drm, 32);
 855
 856         return 0;
 857
 858 register_fail:
 859         drm_kms_helper_poll_fini(drm);
 860         pm_runtime_get_sync(dev);
 861 vblank_fail:
 862         malidp_se_irq_fini(hwdev);
 863         malidp_de_irq_fini(hwdev);
 864 irq_init_fail:
 865         drm_atomic_helper_shutdown(drm);
 866         component_unbind_all(dev, drm);
 867 bind_fail:
 868         of_node_put(malidp->crtc.port);
 869         malidp->crtc.port = NULL;
 870 query_hw_fail:
 871         pm_runtime_put(dev);
 872         if (pm_runtime_enabled(dev))
 873                 pm_runtime_disable(dev);
 874         else
 875                 malidp_runtime_pm_suspend(dev);
 876         dev_set_drvdata(dev, NULL);
 877         of_reserved_mem_device_release(dev);
 878
 879         return ret;
 880 }
 881
 882 static void malidp_unbind(struct device *dev)
 883 {
 884         struct drm_device *drm = dev_get_drvdata(dev);
 885         struct malidp_drm *malidp = drm_to_malidp(drm);
 886         struct malidp_hw_device *hwdev = malidp->dev;
 887
 888         drm_dev_unregister(drm);
 889         drm_kms_helper_poll_fini(drm);
 890         pm_runtime_get_sync(dev);
 891         drm_atomic_helper_shutdown(drm);
 892         malidp_se_irq_fini(hwdev);
 893         malidp_de_irq_fini(hwdev);
 894         component_unbind_all(dev, drm);
 895         of_node_put(malidp->crtc.port);
 896         malidp->crtc.port = NULL;
 897         pm_runtime_put(dev);
 898         if (pm_runtime_enabled(dev))
 899                 pm_runtime_disable(dev);
 900         else
 901                 malidp_runtime_pm_suspend(dev);
 902         dev_set_drvdata(dev, NULL);
 903         of_reserved_mem_device_release(dev);
 904 }
 905
 906 static const struct component_master_ops malidp_master_ops = {
 907         .bind = malidp_bind,
 908         .unbind = malidp_unbind,
 909 };
 910
 911 static int malidp_compare_dev(struct device *dev, void *data)
 912 {
 913         struct device_node *np = data;
 914
 915         return dev->of_node == np;
 916 }
 917
 918 static int malidp_platform_probe(struct platform_device *pdev)
 919 {
 920         struct device_node *port;
 921         struct component_match *match = NULL;
 922
 923         if (!pdev->dev.of_node)
 924                 return -ENODEV;
 925
 926         /* there is only one output port inside each device, find it */
 927         port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
 928         if (!port)
 929                 return -ENODEV;
 930
 931         drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
 932                                    port);
 933         of_node_put(port);
 934         return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
 935                                                match);
 936 }
 937
 938 static int malidp_platform_remove(struct platform_device *pdev)
 939 {
 940         component_master_del(&pdev->dev, &malidp_master_ops);
 941         return 0;
 942 }
 943
 944 static int __maybe_unused malidp_pm_suspend(struct device *dev)
 945 {
 946         struct drm_device *drm = dev_get_drvdata(dev);
 947
 948         return drm_mode_config_helper_suspend(drm);
 949 }
 950
 951 static int __maybe_unused malidp_pm_resume(struct device *dev)
 952 {
 953         struct drm_device *drm = dev_get_drvdata(dev);
 954
 955         drm_mode_config_helper_resume(drm);
 956
 957         return 0;
 958 }
 959
 960 static int __maybe_unused malidp_pm_suspend_late(struct device *dev)
 961 {
 962         if (!pm_runtime_status_suspended(dev)) {
 963                 malidp_runtime_pm_suspend(dev);
 964                 pm_runtime_set_suspended(dev);
 965         }
 966         return 0;
 967 }
 968
 969 static int __maybe_unused malidp_pm_resume_early(struct device *dev)
 970 {
 971         malidp_runtime_pm_resume(dev);
 972         pm_runtime_set_active(dev);
 973         return 0;
 974 }
 975
 976 static const struct dev_pm_ops malidp_pm_ops = {
 977         SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \
 978         SET_LATE_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend_late, malidp_pm_resume_early) \
 979         SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL)
 980 };
 981
 982 static struct platform_driver malidp_platform_driver = {
 983         .probe          = malidp_platform_probe,
 984         .remove         = malidp_platform_remove,
 985         .driver = {
 986                 .name = "mali-dp",
 987                 .pm = &malidp_pm_ops,
 988                 .of_match_table = malidp_drm_of_match,
 989                 .dev_groups = mali_dp_groups,
 990         },
 991 };
 992
 993 drm_module_platform_driver(malidp_platform_driver);
 994
 995 MODULE_AUTHOR("Liviu Dudau <[email protected]>");
 996 MODULE_DESCRIPTION("ARM Mali DP DRM driver");
 997 MODULE_LICENSE("GPL v2");