drivers/gpu/drm/arm/malidp_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   4  * Author: Liviu Dudau <[email protected]>
   5  *
   6  * ARM Mali DP500/DP550/DP650 KMS/DRM driver
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/clk.h>
  11 #include <linux/component.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_graph.h>
  14 #include <linux/of_reserved_mem.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/debugfs.h>
  18
  19 #include <drm/clients/drm_client_setup.h>
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_crtc.h>
  23 #include <drm/drm_drv.h>
  24 #include <drm/drm_fbdev_dma.h>
  25 #include <drm/drm_fourcc.h>
  26 #include <drm/drm_gem_dma_helper.h>
  27 #include <drm/drm_gem_framebuffer_helper.h>
  28 #include <drm/drm_managed.h>
  29 #include <drm/drm_modeset_helper.h>
  30 #include <drm/drm_module.h>
  31 #include <drm/drm_of.h>
  32 #include <drm/drm_probe_helper.h>
  33 #include <drm/drm_vblank.h>
  34
  35 #include "malidp_drv.h"
  36 #include "malidp_mw.h"
  37 #include "malidp_regs.h"
  38 #include "malidp_hw.h"
  39
  40 #define MALIDP_CONF_VALID_TIMEOUT       250
  41 #define AFBC_HEADER_SIZE                16
  42 #define AFBC_SUPERBLK_ALIGNMENT         128
  43
  44 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
  45                                      u32 data[MALIDP_COEFFTAB_NUM_COEFFS])
  46 {
  47         int i;
  48         /* Update all channels with a single gamma curve. */
  49         const u32 gamma_write_mask = GENMASK(18, 16);
  50         /*
  51          * Always write an entire table, so the address field in
  52          * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask
  53          * directly.
  54          */
  55         malidp_hw_write(hwdev, gamma_write_mask,
  56                         hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
  57         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i)
  58                 malidp_hw_write(hwdev, data[i],
  59                                 hwdev->hw->map.coeffs_base +
  60                                 MALIDP_COEF_TABLE_DATA);
  61 }
  62
  63 static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc,
  64                                               struct drm_crtc_state *old_state)
  65 {
  66         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  67         struct malidp_hw_device *hwdev = malidp->dev;
  68
  69         if (!crtc->state->color_mgmt_changed)
  70                 return;
  71
  72         if (!crtc->state->gamma_lut) {
  73                 malidp_hw_clearbits(hwdev,
  74                                     MALIDP_DISP_FUNC_GAMMA,
  75                                     MALIDP_DE_DISPLAY_FUNC);
  76         } else {
  77                 struct malidp_crtc_state *mc =
  78                         to_malidp_crtc_state(crtc->state);
  79
  80                 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id !=
  81                                               old_state->gamma_lut->base.id))
  82                         malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
  83
  84                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
  85                                   MALIDP_DE_DISPLAY_FUNC);
  86         }
  87 }
  88
  89 static
  90 void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc,
  91                                           struct drm_crtc_state *old_state)
  92 {
  93         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  94         struct malidp_hw_device *hwdev = malidp->dev;
  95         int i;
  96
  97         if (!crtc->state->color_mgmt_changed)
  98                 return;
  99
 100         if (!crtc->state->ctm) {
 101                 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
 102                                     MALIDP_DE_DISPLAY_FUNC);
 103         } else {
 104                 struct malidp_crtc_state *mc =
 105                         to_malidp_crtc_state(crtc->state);
 106
 107                 if (!old_state->ctm || (crtc->state->ctm->base.id !=
 108                                         old_state->ctm->base.id))
 109                         for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i)
 110                                 malidp_hw_write(hwdev,
 111                                                 mc->coloradj_coeffs[i],
 112                                                 hwdev->hw->map.coeffs_base +
 113                                                 MALIDP_COLOR_ADJ_COEF + 4 * i);
 114
 115                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
 116                                   MALIDP_DE_DISPLAY_FUNC);
 117         }
 118 }
 119
 120 static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
 121                                            struct drm_crtc_state *old_state)
 122 {
 123         struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state);
 124         struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state);
 125         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 126         struct malidp_hw_device *hwdev = malidp->dev;
 127         struct malidp_se_config *s = &cs->scaler_config;
 128         struct malidp_se_config *old_s = &old_cs->scaler_config;
 129         u32 se_control = hwdev->hw->map.se_base +
 130                          ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
 131                          0x10 : 0xC);
 132         u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL;
 133         u32 scr = se_control + MALIDP_SE_SCALING_CONTROL;
 134         u32 val;
 135
 136         /* Set SE_CONTROL */
 137         if (!s->scale_enable) {
 138                 val = malidp_hw_read(hwdev, se_control);
 139                 val &= ~MALIDP_SE_SCALING_EN;
 140                 malidp_hw_write(hwdev, val, se_control);
 141                 return;
 142         }
 143
 144         hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
 145         val = malidp_hw_read(hwdev, se_control);
 146         val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
 147
 148         val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK);
 149         val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0;
 150
 151         val |= MALIDP_SE_RGBO_IF_EN;
 152         malidp_hw_write(hwdev, val, se_control);
 153
 154         /* Set IN_SIZE & OUT_SIZE. */
 155         val = MALIDP_SE_SET_V_SIZE(s->input_h) |
 156               MALIDP_SE_SET_H_SIZE(s->input_w);
 157         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
 158         val = MALIDP_SE_SET_V_SIZE(s->output_h) |
 159               MALIDP_SE_SET_H_SIZE(s->output_w);
 160         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
 161
 162         /* Set phase regs. */
 163         malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
 164         malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
 165         malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
 166         malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
 167 }
 168
 169 /*
 170  * set the "config valid" bit and wait until the hardware acts on it
 171  */
 172 static int malidp_set_and_wait_config_valid(struct drm_device *drm)
 173 {
 174         struct malidp_drm *malidp = drm_to_malidp(drm);
 175         struct malidp_hw_device *hwdev = malidp->dev;
 176         int ret;
 177
 178         hwdev->hw->set_config_valid(hwdev, 1);
 179         /* don't wait for config_valid flag if we are in config mode */
 180         if (hwdev->hw->in_config_mode(hwdev)) {
 181                 atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE);
 182                 return 0;
 183         }
 184
 185         ret = wait_event_interruptible_timeout(malidp->wq,
 186                         atomic_read(&malidp->config_valid) == MALIDP_CONFIG_VALID_DONE,
 187                         msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
 188
 189         return (ret > 0) ? 0 : -ETIMEDOUT;
 190 }
 191
 192 static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
 193 {
 194         struct drm_device *drm = state->dev;
 195         struct malidp_drm *malidp = drm_to_malidp(drm);
 196         int loop = 5;
 197
 198         malidp->event = malidp->crtc.state->event;
 199         malidp->crtc.state->event = NULL;
 200
 201         if (malidp->crtc.state->active) {
 202                 /*
 203                  * if we have an event to deliver to userspace, make sure
 204                  * the vblank is enabled as we are sending it from the IRQ
 205                  * handler.
 206                  */
 207                 if (malidp->event)
 208                         drm_crtc_vblank_get(&malidp->crtc);
 209
 210                 /* only set config_valid if the CRTC is enabled */
 211                 if (malidp_set_and_wait_config_valid(drm) < 0) {
 212                         /*
 213                          * make a loop around the second CVAL setting and
 214                          * try 5 times before giving up.
 215                          */
 216                         while (loop--) {
 217                                 if (!malidp_set_and_wait_config_valid(drm))
 218                                         break;
 219                         }
 220                         DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
 221                 }
 222
 223         } else if (malidp->event) {
 224                 /* CRTC inactive means vblank IRQ is disabled, send event directly */
 225                 spin_lock_irq(&drm->event_lock);
 226                 drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
 227                 malidp->event = NULL;
 228                 spin_unlock_irq(&drm->event_lock);
 229         }
 230         drm_atomic_helper_commit_hw_done(state);
 231 }
 232
 233 static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
 234 {
 235         struct drm_device *drm = state->dev;
 236         struct malidp_drm *malidp = drm_to_malidp(drm);
 237         struct drm_crtc *crtc;
 238         struct drm_crtc_state *old_crtc_state;
 239         int i;
 240         bool fence_cookie = dma_fence_begin_signalling();
 241
 242         pm_runtime_get_sync(drm->dev);
 243
 244         /*
 245          * set config_valid to a special value to let IRQ handlers
 246          * know that we are updating registers
 247          */
 248         atomic_set(&malidp->config_valid, MALIDP_CONFIG_START);
 249         malidp->dev->hw->set_config_valid(malidp->dev, 0);
 250
 251         drm_atomic_helper_commit_modeset_disables(drm, state);
 252
 253         for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
 254                 malidp_atomic_commit_update_gamma(crtc, old_crtc_state);
 255                 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state);
 256                 malidp_atomic_commit_se_config(crtc, old_crtc_state);
 257         }
 258
 259         drm_atomic_helper_commit_planes(drm, state, DRM_PLANE_COMMIT_ACTIVE_ONLY);
 260
 261         malidp_mw_atomic_commit(drm, state);
 262
 263         drm_atomic_helper_commit_modeset_enables(drm, state);
 264
 265         malidp_atomic_commit_hw_done(state);
 266
 267         dma_fence_end_signalling(fence_cookie);
 268
 269         pm_runtime_put(drm->dev);
 270
 271         drm_atomic_helper_cleanup_planes(drm, state);
 272 }
 273
 274 static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
 275         .atomic_commit_tail = malidp_atomic_commit_tail,
 276 };
 277
 278 static bool
 279 malidp_verify_afbc_framebuffer_caps(struct drm_device *dev,
 280                                     const struct drm_mode_fb_cmd2 *mode_cmd)
 281 {
 282         if (malidp_format_mod_supported(dev, mode_cmd->pixel_format,
 283                                         mode_cmd->modifier[0]) == false)
 284                 return false;
 285
 286         if (mode_cmd->offsets[0] != 0) {
 287                 DRM_DEBUG_KMS("AFBC buffers' plane offset should be 0\n");
 288                 return false;
 289         }
 290
 291         switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
 292         case AFBC_SIZE_16X16:
 293                 if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) {
 294                         DRM_DEBUG_KMS("AFBC buffers must be aligned to 16 pixels\n");
 295                         return false;
 296                 }
 297                 break;
 298         default:
 299                 DRM_DEBUG_KMS("Unsupported AFBC block size\n");
 300                 return false;
 301         }
 302
 303         return true;
 304 }
 305
 306 static bool
 307 malidp_verify_afbc_framebuffer_size(struct drm_device *dev,
 308                                     struct drm_file *file,
 309                                     const struct drm_mode_fb_cmd2 *mode_cmd)
 310 {
 311         int n_superblocks = 0;
 312         const struct drm_format_info *info;
 313         struct drm_gem_object *objs = NULL;
 314         u32 afbc_superblock_size = 0, afbc_superblock_height = 0;
 315         u32 afbc_superblock_width = 0, afbc_size = 0;
 316         int bpp = 0;
 317
 318         switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
 319         case AFBC_SIZE_16X16:
 320                 afbc_superblock_height = 16;
 321                 afbc_superblock_width = 16;
 322                 break;
 323         default:
 324                 DRM_DEBUG_KMS("AFBC superblock size is not supported\n");
 325                 return false;
 326         }
 327
 328         info = drm_get_format_info(dev, mode_cmd);
 329
 330         n_superblocks = (mode_cmd->width / afbc_superblock_width) *
 331                 (mode_cmd->height / afbc_superblock_height);
 332
 333         bpp = malidp_format_get_bpp(info->format);
 334
 335         afbc_superblock_size = (bpp * afbc_superblock_width * afbc_superblock_height)
 336                                 / BITS_PER_BYTE;
 337
 338         afbc_size = ALIGN(n_superblocks * AFBC_HEADER_SIZE, AFBC_SUPERBLK_ALIGNMENT);
 339         afbc_size += n_superblocks * ALIGN(afbc_superblock_size, AFBC_SUPERBLK_ALIGNMENT);
 340
 341         if ((mode_cmd->width * bpp) != (mode_cmd->pitches[0] * BITS_PER_BYTE)) {
 342                 DRM_DEBUG_KMS("Invalid value of (pitch * BITS_PER_BYTE) (=%u) "
 343                               "should be same as width (=%u) * bpp (=%u)\n",
 344                               (mode_cmd->pitches[0] * BITS_PER_BYTE),
 345                               mode_cmd->width, bpp);
 346                 return false;
 347         }
 348
 349         objs = drm_gem_object_lookup(file, mode_cmd->handles[0]);
 350         if (!objs) {
 351                 DRM_DEBUG_KMS("Failed to lookup GEM object\n");
 352                 return false;
 353         }
 354
 355         if (objs->size < afbc_size) {
 356                 DRM_DEBUG_KMS("buffer size (%zu) too small for AFBC buffer size = %u\n",
 357                               objs->size, afbc_size);
 358                 drm_gem_object_put(objs);
 359                 return false;
 360         }
 361
 362         drm_gem_object_put(objs);
 363
 364         return true;
 365 }
 366
 367 static bool
 368 malidp_verify_afbc_framebuffer(struct drm_device *dev, struct drm_file *file,
 369                                const struct drm_mode_fb_cmd2 *mode_cmd)
 370 {
 371         if (malidp_verify_afbc_framebuffer_caps(dev, mode_cmd))
 372                 return malidp_verify_afbc_framebuffer_size(dev, file, mode_cmd);
 373
 374         return false;
 375 }
 376
 377 static struct drm_framebuffer *
 378 malidp_fb_create(struct drm_device *dev, struct drm_file *file,
 379                  const struct drm_mode_fb_cmd2 *mode_cmd)
 380 {
 381         if (mode_cmd->modifier[0]) {
 382                 if (!malidp_verify_afbc_framebuffer(dev, file, mode_cmd))
 383                         return ERR_PTR(-EINVAL);
 384         }
 385
 386         return drm_gem_fb_create(dev, file, mode_cmd);
 387 }
 388
 389 static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
 390         .fb_create = malidp_fb_create,
 391         .atomic_check = drm_atomic_helper_check,
 392         .atomic_commit = drm_atomic_helper_commit,
 393 };
 394
 395 static int malidp_init(struct drm_device *drm)
 396 {
 397         int ret;
 398         struct malidp_drm *malidp = drm_to_malidp(drm);
 399         struct malidp_hw_device *hwdev = malidp->dev;
 400
 401         ret = drmm_mode_config_init(drm);
 402         if (ret)
 403                 goto out;
 404
 405         drm->mode_config.min_width = hwdev->min_line_size;
 406         drm->mode_config.min_height = hwdev->min_line_size;
 407         drm->mode_config.max_width = hwdev->max_line_size;
 408         drm->mode_config.max_height = hwdev->max_line_size;
 409         drm->mode_config.funcs = &malidp_mode_config_funcs;
 410         drm->mode_config.helper_private = &malidp_mode_config_helpers;
 411
 412         ret = malidp_crtc_init(drm);
 413         if (ret)
 414                 goto out;
 415
 416         ret = malidp_mw_connector_init(drm);
 417         if (ret)
 418                 goto out;
 419
 420 out:
 421         return ret;
 422 }
 423
 424 static int malidp_irq_init(struct platform_device *pdev)
 425 {
 426         int irq_de, irq_se, ret = 0;
 427         struct drm_device *drm = dev_get_drvdata(&pdev->dev);
 428         struct malidp_drm *malidp = drm_to_malidp(drm);
 429         struct malidp_hw_device *hwdev = malidp->dev;
 430
 431         /* fetch the interrupts from DT */
 432         irq_de = platform_get_irq_byname(pdev, "DE");
 433         if (irq_de < 0) {
 434                 DRM_ERROR("no 'DE' IRQ specified!\n");
 435                 return irq_de;
 436         }
 437         irq_se = platform_get_irq_byname(pdev, "SE");
 438         if (irq_se < 0) {
 439                 DRM_ERROR("no 'SE' IRQ specified!\n");
 440                 return irq_se;
 441         }
 442
 443         ret = malidp_de_irq_init(drm, irq_de);
 444         if (ret)
 445                 return ret;
 446
 447         ret = malidp_se_irq_init(drm, irq_se);
 448         if (ret) {
 449                 malidp_de_irq_fini(hwdev);
 450                 return ret;
 451         }
 452
 453         return 0;
 454 }
 455
 456 DEFINE_DRM_GEM_DMA_FOPS(fops);
 457
 458 static int malidp_dumb_create(struct drm_file *file_priv,
 459                               struct drm_device *drm,
 460                               struct drm_mode_create_dumb *args)
 461 {
 462         struct malidp_drm *malidp = drm_to_malidp(drm);
 463         /* allocate for the worst case scenario, i.e. rotated buffers */
 464         u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 1);
 465
 466         args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), alignment);
 467
 468         return drm_gem_dma_dumb_create_internal(file_priv, drm, args);
 469 }
 470
 471 #ifdef CONFIG_DEBUG_FS
 472
 473 static void malidp_error_stats_init(struct malidp_error_stats *error_stats)
 474 {
 475         error_stats->num_errors = 0;
 476         error_stats->last_error_status = 0;
 477         error_stats->last_error_vblank = -1;
 478 }
 479
 480 void malidp_error(struct malidp_drm *malidp,
 481                   struct malidp_error_stats *error_stats, u32 status,
 482                   u64 vblank)
 483 {
 484         unsigned long irqflags;
 485
 486         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 487         error_stats->last_error_status = status;
 488         error_stats->last_error_vblank = vblank;
 489         error_stats->num_errors++;
 490         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 491 }
 492
 493 static void malidp_error_stats_dump(const char *prefix,
 494                                     struct malidp_error_stats error_stats,
 495                                     struct seq_file *m)
 496 {
 497         seq_printf(m, "[%s] num_errors : %d\n", prefix,
 498                    error_stats.num_errors);
 499         seq_printf(m, "[%s] last_error_status  : 0x%08x\n", prefix,
 500                    error_stats.last_error_status);
 501         seq_printf(m, "[%s] last_error_vblank : %lld\n", prefix,
 502                    error_stats.last_error_vblank);
 503 }
 504
 505 static int malidp_show_stats(struct seq_file *m, void *arg)
 506 {
 507         struct drm_device *drm = m->private;
 508         struct malidp_drm *malidp = drm_to_malidp(drm);
 509         unsigned long irqflags;
 510         struct malidp_error_stats de_errors, se_errors;
 511
 512         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 513         de_errors = malidp->de_errors;
 514         se_errors = malidp->se_errors;
 515         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 516         malidp_error_stats_dump("DE", de_errors, m);
 517         malidp_error_stats_dump("SE", se_errors, m);
 518         return 0;
 519 }
 520
 521 static int malidp_debugfs_open(struct inode *inode, struct file *file)
 522 {
 523         return single_open(file, malidp_show_stats, inode->i_private);
 524 }
 525
 526 static ssize_t malidp_debugfs_write(struct file *file, const char __user *ubuf,
 527                                     size_t len, loff_t *offp)
 528 {
 529         struct seq_file *m = file->private_data;
 530         struct drm_device *drm = m->private;
 531         struct malidp_drm *malidp = drm_to_malidp(drm);
 532         unsigned long irqflags;
 533
 534         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 535         malidp_error_stats_init(&malidp->de_errors);
 536         malidp_error_stats_init(&malidp->se_errors);
 537         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 538         return len;
 539 }
 540
 541 static const struct file_operations malidp_debugfs_fops = {
 542         .owner = THIS_MODULE,
 543         .open = malidp_debugfs_open,
 544         .read = seq_read,
 545         .write = malidp_debugfs_write,
 546         .llseek = seq_lseek,
 547         .release = single_release,
 548 };
 549
 550 static void malidp_debugfs_init(struct drm_minor *minor)
 551 {
 552         struct malidp_drm *malidp = drm_to_malidp(minor->dev);
 553
 554         malidp_error_stats_init(&malidp->de_errors);
 555         malidp_error_stats_init(&malidp->se_errors);
 556         spin_lock_init(&malidp->errors_lock);
 557         debugfs_create_file("debug", S_IRUGO | S_IWUSR, minor->debugfs_root,
 558                             minor->dev, &malidp_debugfs_fops);
 559 }
 560
 561 #endif //CONFIG_DEBUG_FS
 562
 563 static const struct drm_driver malidp_driver = {
 564         .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
 565         DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(malidp_dumb_create),
 566         DRM_FBDEV_DMA_DRIVER_OPS,
 567 #ifdef CONFIG_DEBUG_FS
 568         .debugfs_init = malidp_debugfs_init,
 569 #endif
 570         .fops = &fops,
 571         .name = "mali-dp",
 572         .desc = "ARM Mali Display Processor driver",
 573         .major = 1,
 574         .minor = 0,
 575 };
 576
 577 static const struct of_device_id  malidp_drm_of_match[] = {
 578         {
 579                 .compatible = "arm,mali-dp500",
 580                 .data = &malidp_device[MALIDP_500]
 581         },
 582         {
 583                 .compatible = "arm,mali-dp550",
 584                 .data = &malidp_device[MALIDP_550]
 585         },
 586         {
 587                 .compatible = "arm,mali-dp650",
 588                 .data = &malidp_device[MALIDP_650]
 589         },
 590         {},
 591 };
 592 MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
 593
 594 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
 595                                        const struct of_device_id *dev_id)
 596 {
 597         u32 core_id;
 598         const char *compatstr_dp500 = "arm,mali-dp500";
 599         bool is_dp500;
 600         bool dt_is_dp500;
 601
 602         /*
 603          * The DP500 CORE_ID register is in a different location, so check it
 604          * first. If the product id field matches, then this is DP500, otherwise
 605          * check the DP550/650 CORE_ID register.
 606          */
 607         core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
 608         /* Offset 0x18 will never read 0x500 on products other than DP500. */
 609         is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);
 610         dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,
 611                               sizeof(dev_id->compatible)) != NULL;
 612         if (is_dp500 != dt_is_dp500) {
 613                 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",
 614                           dev_id->compatible, is_dp500 ? "is" : "is not");
 615                 return false;
 616         } else if (!dt_is_dp500) {
 617                 u16 product_id;
 618                 char buf[32];
 619
 620                 core_id = malidp_hw_read(hwdev,
 621                                          MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);
 622                 product_id = MALIDP_PRODUCT_ID(core_id);
 623                 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);
 624                 if (!strnstr(dev_id->compatible, buf,
 625                              sizeof(dev_id->compatible))) {
 626                         DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",
 627                                   dev_id->compatible, product_id);
 628                         return false;
 629                 }
 630         }
 631         return true;
 632 }
 633
 634 static bool malidp_has_sufficient_address_space(const struct resource *res,
 635                                                 const struct of_device_id *dev_id)
 636 {
 637         resource_size_t res_size = resource_size(res);
 638         const char *compatstr_dp500 = "arm,mali-dp500";
 639
 640         if (!strnstr(dev_id->compatible, compatstr_dp500,
 641                      sizeof(dev_id->compatible)))
 642                 return res_size >= MALIDP550_ADDR_SPACE_SIZE;
 643         else if (res_size < MALIDP500_ADDR_SPACE_SIZE)
 644                 return false;
 645         return true;
 646 }
 647
 648 static ssize_t core_id_show(struct device *dev, struct device_attribute *attr,
 649                             char *buf)
 650 {
 651         struct drm_device *drm = dev_get_drvdata(dev);
 652         struct malidp_drm *malidp = drm_to_malidp(drm);
 653
 654         return sysfs_emit(buf, "%08x\n", malidp->core_id);
 655 }
 656
 657 static DEVICE_ATTR_RO(core_id);
 658
 659 static struct attribute *mali_dp_attrs[] = {
 660         &dev_attr_core_id.attr,
 661         NULL,
 662 };
 663 ATTRIBUTE_GROUPS(mali_dp);
 664
 665 #define MAX_OUTPUT_CHANNELS     3
 666
 667 static int malidp_runtime_pm_suspend(struct device *dev)
 668 {
 669         struct drm_device *drm = dev_get_drvdata(dev);
 670         struct malidp_drm *malidp = drm_to_malidp(drm);
 671         struct malidp_hw_device *hwdev = malidp->dev;
 672
 673         /* we can only suspend if the hardware is in config mode */
 674         WARN_ON(!hwdev->hw->in_config_mode(hwdev));
 675
 676         malidp_se_irq_fini(hwdev);
 677         malidp_de_irq_fini(hwdev);
 678         hwdev->pm_suspended = true;
 679         clk_disable_unprepare(hwdev->mclk);
 680         clk_disable_unprepare(hwdev->aclk);
 681         clk_disable_unprepare(hwdev->pclk);
 682
 683         return 0;
 684 }
 685
 686 static int malidp_runtime_pm_resume(struct device *dev)
 687 {
 688         struct drm_device *drm = dev_get_drvdata(dev);
 689         struct malidp_drm *malidp = drm_to_malidp(drm);
 690         struct malidp_hw_device *hwdev = malidp->dev;
 691
 692         clk_prepare_enable(hwdev->pclk);
 693         clk_prepare_enable(hwdev->aclk);
 694         clk_prepare_enable(hwdev->mclk);
 695         hwdev->pm_suspended = false;
 696         malidp_de_irq_hw_init(hwdev);
 697         malidp_se_irq_hw_init(hwdev);
 698
 699         return 0;
 700 }
 701
 702 static int malidp_bind(struct device *dev)
 703 {
 704         struct resource *res;
 705         struct drm_device *drm;
 706         struct malidp_drm *malidp;
 707         struct malidp_hw_device *hwdev;
 708         struct platform_device *pdev = to_platform_device(dev);
 709         struct of_device_id const *dev_id;
 710         struct drm_encoder *encoder;
 711         /* number of lines for the R, G and B output */
 712         u8 output_width[MAX_OUTPUT_CHANNELS];
 713         int ret = 0, i;
 714         u32 version, out_depth = 0;
 715
 716         malidp = devm_drm_dev_alloc(dev, &malidp_driver, typeof(*malidp), base);
 717         if (IS_ERR(malidp))
 718                 return PTR_ERR(malidp);
 719
 720         drm = &malidp->base;
 721
 722         hwdev = drmm_kzalloc(drm, sizeof(*hwdev), GFP_KERNEL);
 723         if (!hwdev)
 724                 return -ENOMEM;
 725
 726         hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
 727         malidp->dev = hwdev;
 728
 729         hwdev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 730         if (IS_ERR(hwdev->regs))
 731                 return PTR_ERR(hwdev->regs);
 732
 733         hwdev->pclk = devm_clk_get(dev, "pclk");
 734         if (IS_ERR(hwdev->pclk))
 735                 return PTR_ERR(hwdev->pclk);
 736
 737         hwdev->aclk = devm_clk_get(dev, "aclk");
 738         if (IS_ERR(hwdev->aclk))
 739                 return PTR_ERR(hwdev->aclk);
 740
 741         hwdev->mclk = devm_clk_get(dev, "mclk");
 742         if (IS_ERR(hwdev->mclk))
 743                 return PTR_ERR(hwdev->mclk);
 744
 745         hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
 746         if (IS_ERR(hwdev->pxlclk))
 747                 return PTR_ERR(hwdev->pxlclk);
 748
 749         /* Get the optional framebuffer memory resource */
 750         ret = of_reserved_mem_device_init(dev);
 751         if (ret && ret != -ENODEV)
 752                 return ret;
 753
 754         dev_set_drvdata(dev, drm);
 755
 756         /* Enable power management */
 757         pm_runtime_enable(dev);
 758
 759         /* Resume device to enable the clocks */
 760         if (pm_runtime_enabled(dev))
 761                 pm_runtime_get_sync(dev);
 762         else
 763                 malidp_runtime_pm_resume(dev);
 764
 765         dev_id = of_match_device(malidp_drm_of_match, dev);
 766         if (!dev_id) {
 767                 ret = -EINVAL;
 768                 goto query_hw_fail;
 769         }
 770
 771         if (!malidp_has_sufficient_address_space(res, dev_id)) {
 772                 DRM_ERROR("Insufficient address space in device-tree.\n");
 773                 ret = -EINVAL;
 774                 goto query_hw_fail;
 775         }
 776
 777         if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
 778                 ret = -EINVAL;
 779                 goto query_hw_fail;
 780         }
 781
 782         ret = hwdev->hw->query_hw(hwdev);
 783         if (ret) {
 784                 DRM_ERROR("Invalid HW configuration\n");
 785                 goto query_hw_fail;
 786         }
 787
 788         version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
 789         DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
 790                  (version >> 12) & 0xf, (version >> 8) & 0xf);
 791
 792         malidp->core_id = version;
 793
 794         ret = of_property_read_u32(dev->of_node,
 795                                         "arm,malidp-arqos-value",
 796                                         &hwdev->arqos_value);
 797         if (ret)
 798                 hwdev->arqos_value = 0x0;
 799
 800         /* set the number of lines used for output of RGB data */
 801         ret = of_property_read_u8_array(dev->of_node,
 802                                         "arm,malidp-output-port-lines",
 803                                         output_width, MAX_OUTPUT_CHANNELS);
 804         if (ret)
 805                 goto query_hw_fail;
 806
 807         for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
 808                 out_depth = (out_depth << 8) | (output_width[i] & 0xf);
 809         malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
 810         hwdev->output_color_depth = out_depth;
 811
 812         atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_INIT);
 813         init_waitqueue_head(&malidp->wq);
 814
 815         ret = malidp_init(drm);
 816         if (ret < 0)
 817                 goto query_hw_fail;
 818
 819         /* Set the CRTC's port so that the encoder component can find it */
 820         malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
 821
 822         ret = component_bind_all(dev, drm);
 823         if (ret) {
 824                 DRM_ERROR("Failed to bind all components\n");
 825                 goto bind_fail;
 826         }
 827
 828         /* We expect to have a maximum of two encoders one for the actual
 829          * display and a virtual one for the writeback connector
 830          */
 831         WARN_ON(drm->mode_config.num_encoder > 2);
 832         list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) {
 833                 encoder->possible_clones =
 834                                 (1 << drm->mode_config.num_encoder) -  1;
 835         }
 836
 837         ret = malidp_irq_init(pdev);
 838         if (ret < 0)
 839                 goto irq_init_fail;
 840
 841         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
 842         if (ret < 0) {
 843                 DRM_ERROR("failed to initialise vblank\n");
 844                 goto vblank_fail;
 845         }
 846         pm_runtime_put(dev);
 847
 848         drm_mode_config_reset(drm);
 849
 850         drm_kms_helper_poll_init(drm);
 851
 852         ret = drm_dev_register(drm, 0);
 853         if (ret)
 854                 goto register_fail;
 855
 856         drm_client_setup(drm, NULL);
 857
 858         return 0;
 859
 860 register_fail:
 861         drm_kms_helper_poll_fini(drm);
 862         pm_runtime_get_sync(dev);
 863 vblank_fail:
 864         malidp_se_irq_fini(hwdev);
 865         malidp_de_irq_fini(hwdev);
 866 irq_init_fail:
 867         drm_atomic_helper_shutdown(drm);
 868         component_unbind_all(dev, drm);
 869 bind_fail:
 870         of_node_put(malidp->crtc.port);
 871         malidp->crtc.port = NULL;
 872 query_hw_fail:
 873         pm_runtime_put(dev);
 874         if (pm_runtime_enabled(dev))
 875                 pm_runtime_disable(dev);
 876         else
 877                 malidp_runtime_pm_suspend(dev);
 878         dev_set_drvdata(dev, NULL);
 879         of_reserved_mem_device_release(dev);
 880
 881         return ret;
 882 }
 883
 884 static void malidp_unbind(struct device *dev)
 885 {
 886         struct drm_device *drm = dev_get_drvdata(dev);
 887         struct malidp_drm *malidp = drm_to_malidp(drm);
 888         struct malidp_hw_device *hwdev = malidp->dev;
 889
 890         drm_dev_unregister(drm);
 891         drm_kms_helper_poll_fini(drm);
 892         pm_runtime_get_sync(dev);
 893         drm_atomic_helper_shutdown(drm);
 894         malidp_se_irq_fini(hwdev);
 895         malidp_de_irq_fini(hwdev);
 896         component_unbind_all(dev, drm);
 897         of_node_put(malidp->crtc.port);
 898         malidp->crtc.port = NULL;
 899         pm_runtime_put(dev);
 900         if (pm_runtime_enabled(dev))
 901                 pm_runtime_disable(dev);
 902         else
 903                 malidp_runtime_pm_suspend(dev);
 904         dev_set_drvdata(dev, NULL);
 905         of_reserved_mem_device_release(dev);
 906 }
 907
 908 static const struct component_master_ops malidp_master_ops = {
 909         .bind = malidp_bind,
 910         .unbind = malidp_unbind,
 911 };
 912
 913 static int malidp_compare_dev(struct device *dev, void *data)
 914 {
 915         struct device_node *np = data;
 916
 917         return dev->of_node == np;
 918 }
 919
 920 static int malidp_platform_probe(struct platform_device *pdev)
 921 {
 922         struct device_node *port;
 923         struct component_match *match = NULL;
 924
 925         if (!pdev->dev.of_node)
 926                 return -ENODEV;
 927
 928         /* there is only one output port inside each device, find it */
 929         port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
 930         if (!port)
 931                 return -ENODEV;
 932
 933         drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
 934                                    port);
 935         of_node_put(port);
 936         return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
 937                                                match);
 938 }
 939
 940 static void malidp_platform_remove(struct platform_device *pdev)
 941 {
 942         component_master_del(&pdev->dev, &malidp_master_ops);
 943 }
 944
 945 static void malidp_platform_shutdown(struct platform_device *pdev)
 946 {
 947         drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
 948 }
 949
 950 static int __maybe_unused malidp_pm_suspend(struct device *dev)
 951 {
 952         struct drm_device *drm = dev_get_drvdata(dev);
 953
 954         return drm_mode_config_helper_suspend(drm);
 955 }
 956
 957 static int __maybe_unused malidp_pm_resume(struct device *dev)
 958 {
 959         struct drm_device *drm = dev_get_drvdata(dev);
 960
 961         drm_mode_config_helper_resume(drm);
 962
 963         return 0;
 964 }
 965
 966 static int __maybe_unused malidp_pm_suspend_late(struct device *dev)
 967 {
 968         if (!pm_runtime_status_suspended(dev)) {
 969                 malidp_runtime_pm_suspend(dev);
 970                 pm_runtime_set_suspended(dev);
 971         }
 972         return 0;
 973 }
 974
 975 static int __maybe_unused malidp_pm_resume_early(struct device *dev)
 976 {
 977         malidp_runtime_pm_resume(dev);
 978         pm_runtime_set_active(dev);
 979         return 0;
 980 }
 981
 982 static const struct dev_pm_ops malidp_pm_ops = {
 983         SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \
 984         SET_LATE_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend_late, malidp_pm_resume_early) \
 985         SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL)
 986 };
 987
 988 static struct platform_driver malidp_platform_driver = {
 989         .probe          = malidp_platform_probe,
 990         .remove         = malidp_platform_remove,
 991         .shutdown       = malidp_platform_shutdown,
 992         .driver = {
 993                 .name = "mali-dp",
 994                 .pm = &malidp_pm_ops,
 995                 .of_match_table = malidp_drm_of_match,
 996                 .dev_groups = mali_dp_groups,
 997         },
 998 };
 999
1000 drm_module_platform_driver(malidp_platform_driver);
1001
1002 MODULE_AUTHOR("Liviu Dudau <[email protected]>");
1003 MODULE_DESCRIPTION("ARM Mali DP DRM driver");
1004 MODULE_LICENSE("GPL v2");