drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <[email protected]>
   7  *          Mika Westerberg <[email protected]>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/log2.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/property.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/string_helpers.h>
  19 #include <linux/time.h>
  20
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/pinctrl/pinconf.h>
  23 #include <linux/pinctrl/pinconf-generic.h>
  24 #include <linux/pinctrl/pinctrl.h>
  25 #include <linux/pinctrl/pinmux.h>
  26
  27 #include <linux/platform_data/x86/pwm-lpss.h>
  28
  29 #include "../core.h"
  30 #include "pinctrl-intel.h"
  31
  32 /* Offset from regs */
  33 #define REVID                           0x000
  34 #define REVID_SHIFT                     16
  35 #define REVID_MASK                      GENMASK(31, 16)
  36
  37 #define CAPLIST                         0x004
  38 #define CAPLIST_ID_SHIFT                16
  39 #define CAPLIST_ID_MASK                 GENMASK(23, 16)
  40 #define CAPLIST_ID_GPIO_HW_INFO         1
  41 #define CAPLIST_ID_PWM                  2
  42 #define CAPLIST_ID_BLINK                3
  43 #define CAPLIST_ID_EXP                  4
  44 #define CAPLIST_NEXT_SHIFT              0
  45 #define CAPLIST_NEXT_MASK               GENMASK(15, 0)
  46
  47 #define PADBAR                          0x00c
  48
  49 #define PADOWN_BITS                     4
  50 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  51 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  52 #define PADOWN_GPP(p)                   ((p) / 8)
  53
  54 #define PWMC                            0x204
  55
  56 /* Offset from pad_regs */
  57 #define PADCFG0                         0x000
  58 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  59 #define PADCFG0_RXEVCFG_LEVEL           (0 << 25)
  60 #define PADCFG0_RXEVCFG_EDGE            (1 << 25)
  61 #define PADCFG0_RXEVCFG_DISABLED        (2 << 25)
  62 #define PADCFG0_RXEVCFG_EDGE_BOTH       (3 << 25)
  63 #define PADCFG0_PREGFRXSEL              BIT(24)
  64 #define PADCFG0_RXINV                   BIT(23)
  65 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  66 #define PADCFG0_GPIROUTSCI              BIT(19)
  67 #define PADCFG0_GPIROUTSMI              BIT(18)
  68 #define PADCFG0_GPIROUTNMI              BIT(17)
  69 #define PADCFG0_PMODE_SHIFT             10
  70 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  71 #define PADCFG0_PMODE_GPIO              0
  72 #define PADCFG0_GPIORXDIS               BIT(9)
  73 #define PADCFG0_GPIOTXDIS               BIT(8)
  74 #define PADCFG0_GPIORXSTATE             BIT(1)
  75 #define PADCFG0_GPIOTXSTATE             BIT(0)
  76
  77 #define PADCFG1                         0x004
  78 #define PADCFG1_TERM_UP                 BIT(13)
  79 #define PADCFG1_TERM_SHIFT              10
  80 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  81 #define PADCFG1_TERM_20K                BIT(2)
  82 #define PADCFG1_TERM_5K                 BIT(1)
  83 #define PADCFG1_TERM_4K                 (BIT(2) | BIT(1))
  84 #define PADCFG1_TERM_1K                 BIT(0)
  85 #define PADCFG1_TERM_952                (BIT(2) | BIT(0))
  86 #define PADCFG1_TERM_833                (BIT(1) | BIT(0))
  87 #define PADCFG1_TERM_800                (BIT(2) | BIT(1) | BIT(0))
  88
  89 #define PADCFG2                         0x008
  90 #define PADCFG2_DEBOUNCE_SHIFT          1
  91 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  92 #define PADCFG2_DEBEN                   BIT(0)
  93
  94 #define DEBOUNCE_PERIOD_NSEC            31250
  95
  96 struct intel_pad_context {
  97         u32 padcfg0;
  98         u32 padcfg1;
  99         u32 padcfg2;
 100 };
 101
 102 struct intel_community_context {
 103         u32 *intmask;
 104         u32 *hostown;
 105 };
 106
 107 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 108 #define padgroup_offset(g, p)   ((p) - (g)->base)
 109
 110 struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin)
 111 {
 112         struct intel_community *community;
 113         int i;
 114
 115         for (i = 0; i < pctrl->ncommunities; i++) {
 116                 community = &pctrl->communities[i];
 117                 if (pin >= community->pin_base &&
 118                     pin < community->pin_base + community->npins)
 119                         return community;
 120         }
 121
 122         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 123         return NULL;
 124 }
 125 EXPORT_SYMBOL_NS_GPL(intel_get_community, PINCTRL_INTEL);
 126
 127 static const struct intel_padgroup *
 128 intel_community_get_padgroup(const struct intel_community *community,
 129                              unsigned int pin)
 130 {
 131         int i;
 132
 133         for (i = 0; i < community->ngpps; i++) {
 134                 const struct intel_padgroup *padgrp = &community->gpps[i];
 135
 136                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 137                         return padgrp;
 138         }
 139
 140         return NULL;
 141 }
 142
 143 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 144                                       unsigned int pin, unsigned int reg)
 145 {
 146         const struct intel_community *community;
 147         unsigned int padno;
 148         size_t nregs;
 149
 150         community = intel_get_community(pctrl, pin);
 151         if (!community)
 152                 return NULL;
 153
 154         padno = pin_to_padno(community, pin);
 155         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 156
 157         if (reg >= nregs * 4)
 158                 return NULL;
 159
 160         return community->pad_regs + reg + padno * nregs * 4;
 161 }
 162
 163 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 164 {
 165         const struct intel_community *community;
 166         const struct intel_padgroup *padgrp;
 167         unsigned int gpp, offset, gpp_offset;
 168         void __iomem *padown;
 169
 170         community = intel_get_community(pctrl, pin);
 171         if (!community)
 172                 return false;
 173         if (!community->padown_offset)
 174                 return true;
 175
 176         padgrp = intel_community_get_padgroup(community, pin);
 177         if (!padgrp)
 178                 return false;
 179
 180         gpp_offset = padgroup_offset(padgrp, pin);
 181         gpp = PADOWN_GPP(gpp_offset);
 182         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 183         padown = community->regs + offset;
 184
 185         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 186 }
 187
 188 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 189 {
 190         const struct intel_community *community;
 191         const struct intel_padgroup *padgrp;
 192         unsigned int offset, gpp_offset;
 193         void __iomem *hostown;
 194
 195         community = intel_get_community(pctrl, pin);
 196         if (!community)
 197                 return true;
 198         if (!community->hostown_offset)
 199                 return false;
 200
 201         padgrp = intel_community_get_padgroup(community, pin);
 202         if (!padgrp)
 203                 return true;
 204
 205         gpp_offset = padgroup_offset(padgrp, pin);
 206         offset = community->hostown_offset + padgrp->reg_num * 4;
 207         hostown = community->regs + offset;
 208
 209         return !(readl(hostown) & BIT(gpp_offset));
 210 }
 211
 212 /**
 213  * enum - Locking variants of the pad configuration
 214  *
 215  * @PAD_UNLOCKED:       pad is fully controlled by the configuration registers
 216  * @PAD_LOCKED:         pad configuration registers, except TX state, are locked
 217  * @PAD_LOCKED_TX:      pad configuration TX state is locked
 218  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
 219  *
 220  * Locking is considered as read-only mode for corresponding registers and
 221  * their respective fields. That said, TX state bit is locked separately from
 222  * the main locking scheme.
 223  */
 224 enum {
 225         PAD_UNLOCKED    = 0,
 226         PAD_LOCKED      = 1,
 227         PAD_LOCKED_TX   = 2,
 228         PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
 229 };
 230
 231 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 232 {
 233         struct intel_community *community;
 234         const struct intel_padgroup *padgrp;
 235         unsigned int offset, gpp_offset;
 236         u32 value;
 237         int ret = PAD_UNLOCKED;
 238
 239         community = intel_get_community(pctrl, pin);
 240         if (!community)
 241                 return PAD_LOCKED_FULL;
 242         if (!community->padcfglock_offset)
 243                 return PAD_UNLOCKED;
 244
 245         padgrp = intel_community_get_padgroup(community, pin);
 246         if (!padgrp)
 247                 return PAD_LOCKED_FULL;
 248
 249         gpp_offset = padgroup_offset(padgrp, pin);
 250
 251         /*
 252          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 253          * the pad is considered unlocked. Any other case means that it is
 254          * either fully or partially locked.
 255          */
 256         offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
 257         value = readl(community->regs + offset);
 258         if (value & BIT(gpp_offset))
 259                 ret |= PAD_LOCKED;
 260
 261         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 262         value = readl(community->regs + offset);
 263         if (value & BIT(gpp_offset))
 264                 ret |= PAD_LOCKED_TX;
 265
 266         return ret;
 267 }
 268
 269 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
 270 {
 271         return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
 272 }
 273
 274 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 275 {
 276         return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
 277 }
 278
 279 int intel_get_groups_count(struct pinctrl_dev *pctldev)
 280 {
 281         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 282
 283         return pctrl->soc->ngroups;
 284 }
 285 EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, PINCTRL_INTEL);
 286
 287 const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
 288 {
 289         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 290
 291         return pctrl->soc->groups[group].grp.name;
 292 }
 293 EXPORT_SYMBOL_NS_GPL(intel_get_group_name, PINCTRL_INTEL);
 294
 295 int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 296                          const unsigned int **pins, unsigned int *npins)
 297 {
 298         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 299
 300         *pins = pctrl->soc->groups[group].grp.pins;
 301         *npins = pctrl->soc->groups[group].grp.npins;
 302         return 0;
 303 }
 304 EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, PINCTRL_INTEL);
 305
 306 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 307                                unsigned int pin)
 308 {
 309         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 310         void __iomem *padcfg;
 311         u32 cfg0, cfg1, mode;
 312         int locked;
 313         bool acpi;
 314
 315         if (!intel_pad_owned_by_host(pctrl, pin)) {
 316                 seq_puts(s, "not available");
 317                 return;
 318         }
 319
 320         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 321         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 322
 323         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 324         if (mode == PADCFG0_PMODE_GPIO)
 325                 seq_puts(s, "GPIO ");
 326         else
 327                 seq_printf(s, "mode %d ", mode);
 328
 329         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 330
 331         /* Dump the additional PADCFG registers if available */
 332         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 333         if (padcfg)
 334                 seq_printf(s, " 0x%08x", readl(padcfg));
 335
 336         locked = intel_pad_locked(pctrl, pin);
 337         acpi = intel_pad_acpi_mode(pctrl, pin);
 338
 339         if (locked || acpi) {
 340                 seq_puts(s, " [");
 341                 if (locked)
 342                         seq_puts(s, "LOCKED");
 343                 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
 344                         seq_puts(s, " tx");
 345                 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
 346                         seq_puts(s, " full");
 347
 348                 if (locked && acpi)
 349                         seq_puts(s, ", ");
 350
 351                 if (acpi)
 352                         seq_puts(s, "ACPI");
 353                 seq_puts(s, "]");
 354         }
 355 }
 356
 357 static const struct pinctrl_ops intel_pinctrl_ops = {
 358         .get_groups_count = intel_get_groups_count,
 359         .get_group_name = intel_get_group_name,
 360         .get_group_pins = intel_get_group_pins,
 361         .pin_dbg_show = intel_pin_dbg_show,
 362 };
 363
 364 int intel_get_functions_count(struct pinctrl_dev *pctldev)
 365 {
 366         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 367
 368         return pctrl->soc->nfunctions;
 369 }
 370 EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, PINCTRL_INTEL);
 371
 372 const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
 373 {
 374         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 375
 376         return pctrl->soc->functions[function].func.name;
 377 }
 378 EXPORT_SYMBOL_NS_GPL(intel_get_function_name, PINCTRL_INTEL);
 379
 380 int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
 381                               const char * const **groups, unsigned int * const ngroups)
 382 {
 383         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 384
 385         *groups = pctrl->soc->functions[function].func.groups;
 386         *ngroups = pctrl->soc->functions[function].func.ngroups;
 387         return 0;
 388 }
 389 EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, PINCTRL_INTEL);
 390
 391 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 392                                 unsigned int function, unsigned int group)
 393 {
 394         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 395         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 396         unsigned long flags;
 397         int i;
 398
 399         raw_spin_lock_irqsave(&pctrl->lock, flags);
 400
 401         /*
 402          * All pins in the groups needs to be accessible and writable
 403          * before we can enable the mux for this group.
 404          */
 405         for (i = 0; i < grp->grp.npins; i++) {
 406                 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) {
 407                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 408                         return -EBUSY;
 409                 }
 410         }
 411
 412         /* Now enable the mux setting for each pin in the group */
 413         for (i = 0; i < grp->grp.npins; i++) {
 414                 void __iomem *padcfg0;
 415                 u32 value, pmode;
 416
 417                 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
 418
 419                 value = readl(padcfg0);
 420                 value &= ~PADCFG0_PMODE_MASK;
 421
 422                 if (grp->modes)
 423                         pmode = grp->modes[i];
 424                 else
 425                         pmode = grp->mode;
 426
 427                 value |= pmode << PADCFG0_PMODE_SHIFT;
 428                 writel(value, padcfg0);
 429         }
 430
 431         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 432
 433         return 0;
 434 }
 435
 436 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 437 {
 438         u32 value;
 439
 440         value = readl(padcfg0);
 441         if (input) {
 442                 value &= ~PADCFG0_GPIORXDIS;
 443                 value |= PADCFG0_GPIOTXDIS;
 444         } else {
 445                 value &= ~PADCFG0_GPIOTXDIS;
 446                 value |= PADCFG0_GPIORXDIS;
 447         }
 448         writel(value, padcfg0);
 449 }
 450
 451 static int __intel_gpio_get_gpio_mode(u32 value)
 452 {
 453         return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 454 }
 455
 456 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 457 {
 458         return __intel_gpio_get_gpio_mode(readl(padcfg0));
 459 }
 460
 461 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 462 {
 463         u32 value;
 464
 465         value = readl(padcfg0);
 466
 467         /* Put the pad into GPIO mode */
 468         value &= ~PADCFG0_PMODE_MASK;
 469         value |= PADCFG0_PMODE_GPIO;
 470
 471         /* Disable TX buffer and enable RX (this will be input) */
 472         value &= ~PADCFG0_GPIORXDIS;
 473         value |= PADCFG0_GPIOTXDIS;
 474
 475         /* Disable SCI/SMI/NMI generation */
 476         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 477         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 478
 479         writel(value, padcfg0);
 480 }
 481
 482 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 483                                      struct pinctrl_gpio_range *range,
 484                                      unsigned int pin)
 485 {
 486         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 487         void __iomem *padcfg0;
 488         unsigned long flags;
 489
 490         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 491
 492         raw_spin_lock_irqsave(&pctrl->lock, flags);
 493
 494         if (!intel_pad_owned_by_host(pctrl, pin)) {
 495                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 496                 return -EBUSY;
 497         }
 498
 499         if (!intel_pad_is_unlocked(pctrl, pin)) {
 500                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 501                 return 0;
 502         }
 503
 504         /*
 505          * If pin is already configured in GPIO mode, we assume that
 506          * firmware provides correct settings. In such case we avoid
 507          * potential glitches on the pin. Otherwise, for the pin in
 508          * alternative mode, consumer has to supply respective flags.
 509          */
 510         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
 511                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 512                 return 0;
 513         }
 514
 515         intel_gpio_set_gpio_mode(padcfg0);
 516
 517         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 518
 519         return 0;
 520 }
 521
 522 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 523                                     struct pinctrl_gpio_range *range,
 524                                     unsigned int pin, bool input)
 525 {
 526         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 527         void __iomem *padcfg0;
 528         unsigned long flags;
 529
 530         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 531
 532         raw_spin_lock_irqsave(&pctrl->lock, flags);
 533         __intel_gpio_set_direction(padcfg0, input);
 534         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 535
 536         return 0;
 537 }
 538
 539 static const struct pinmux_ops intel_pinmux_ops = {
 540         .get_functions_count = intel_get_functions_count,
 541         .get_function_name = intel_get_function_name,
 542         .get_function_groups = intel_get_function_groups,
 543         .set_mux = intel_pinmux_set_mux,
 544         .gpio_request_enable = intel_gpio_request_enable,
 545         .gpio_set_direction = intel_gpio_set_direction,
 546 };
 547
 548 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 549                                  enum pin_config_param param, u32 *arg)
 550 {
 551         const struct intel_community *community;
 552         void __iomem *padcfg1;
 553         unsigned long flags;
 554         u32 value, term;
 555
 556         community = intel_get_community(pctrl, pin);
 557         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 558
 559         raw_spin_lock_irqsave(&pctrl->lock, flags);
 560         value = readl(padcfg1);
 561         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 562
 563         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 564
 565         switch (param) {
 566         case PIN_CONFIG_BIAS_DISABLE:
 567                 if (term)
 568                         return -EINVAL;
 569                 break;
 570
 571         case PIN_CONFIG_BIAS_PULL_UP:
 572                 if (!term || !(value & PADCFG1_TERM_UP))
 573                         return -EINVAL;
 574
 575                 switch (term) {
 576                 case PADCFG1_TERM_833:
 577                         *arg = 833;
 578                         break;
 579                 case PADCFG1_TERM_1K:
 580                         *arg = 1000;
 581                         break;
 582                 case PADCFG1_TERM_4K:
 583                         *arg = 4000;
 584                         break;
 585                 case PADCFG1_TERM_5K:
 586                         *arg = 5000;
 587                         break;
 588                 case PADCFG1_TERM_20K:
 589                         *arg = 20000;
 590                         break;
 591                 }
 592
 593                 break;
 594
 595         case PIN_CONFIG_BIAS_PULL_DOWN:
 596                 if (!term || value & PADCFG1_TERM_UP)
 597                         return -EINVAL;
 598
 599                 switch (term) {
 600                 case PADCFG1_TERM_833:
 601                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 602                                 return -EINVAL;
 603                         *arg = 833;
 604                         break;
 605                 case PADCFG1_TERM_1K:
 606                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 607                                 return -EINVAL;
 608                         *arg = 1000;
 609                         break;
 610                 case PADCFG1_TERM_4K:
 611                         *arg = 4000;
 612                         break;
 613                 case PADCFG1_TERM_5K:
 614                         *arg = 5000;
 615                         break;
 616                 case PADCFG1_TERM_20K:
 617                         *arg = 20000;
 618                         break;
 619                 }
 620
 621                 break;
 622
 623         default:
 624                 return -EINVAL;
 625         }
 626
 627         return 0;
 628 }
 629
 630 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
 631                                      enum pin_config_param param, u32 *arg)
 632 {
 633         void __iomem *padcfg2;
 634         unsigned long flags;
 635         unsigned long v;
 636         u32 value2;
 637
 638         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 639         if (!padcfg2)
 640                 return -ENOTSUPP;
 641
 642         raw_spin_lock_irqsave(&pctrl->lock, flags);
 643         value2 = readl(padcfg2);
 644         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 645         if (!(value2 & PADCFG2_DEBEN))
 646                 return -EINVAL;
 647
 648         v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 649         *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 650
 651         return 0;
 652 }
 653
 654 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 655                             unsigned long *config)
 656 {
 657         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 658         enum pin_config_param param = pinconf_to_config_param(*config);
 659         u32 arg = 0;
 660         int ret;
 661
 662         if (!intel_pad_owned_by_host(pctrl, pin))
 663                 return -ENOTSUPP;
 664
 665         switch (param) {
 666         case PIN_CONFIG_BIAS_DISABLE:
 667         case PIN_CONFIG_BIAS_PULL_UP:
 668         case PIN_CONFIG_BIAS_PULL_DOWN:
 669                 ret = intel_config_get_pull(pctrl, pin, param, &arg);
 670                 if (ret)
 671                         return ret;
 672                 break;
 673
 674         case PIN_CONFIG_INPUT_DEBOUNCE:
 675                 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
 676                 if (ret)
 677                         return ret;
 678                 break;
 679
 680         default:
 681                 return -ENOTSUPP;
 682         }
 683
 684         *config = pinconf_to_config_packed(param, arg);
 685         return 0;
 686 }
 687
 688 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 689                                  unsigned long config)
 690 {
 691         unsigned int param = pinconf_to_config_param(config);
 692         unsigned int arg = pinconf_to_config_argument(config);
 693         const struct intel_community *community;
 694         void __iomem *padcfg1;
 695         unsigned long flags;
 696         int ret = 0;
 697         u32 value;
 698
 699         community = intel_get_community(pctrl, pin);
 700         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 701
 702         raw_spin_lock_irqsave(&pctrl->lock, flags);
 703
 704         value = readl(padcfg1);
 705         value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 706
 707         /* Set default strength value in case none is given */
 708         if (arg == 1)
 709                 arg = 5000;
 710
 711         switch (param) {
 712         case PIN_CONFIG_BIAS_DISABLE:
 713                 break;
 714
 715         case PIN_CONFIG_BIAS_PULL_UP:
 716                 switch (arg) {
 717                 case 20000:
 718                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 719                         break;
 720                 case 5000:
 721                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 722                         break;
 723                 case 4000:
 724                         value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT;
 725                         break;
 726                 case 1000:
 727                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 728                         break;
 729                 case 833:
 730                         value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
 731                         break;
 732                 default:
 733                         ret = -EINVAL;
 734                         break;
 735                 }
 736
 737                 value |= PADCFG1_TERM_UP;
 738                 break;
 739
 740         case PIN_CONFIG_BIAS_PULL_DOWN:
 741                 switch (arg) {
 742                 case 20000:
 743                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 744                         break;
 745                 case 5000:
 746                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 747                         break;
 748                 case 4000:
 749                         value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT;
 750                         break;
 751                 case 1000:
 752                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 753                                 ret = -EINVAL;
 754                                 break;
 755                         }
 756                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 757                         break;
 758                 case 833:
 759                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 760                                 ret = -EINVAL;
 761                                 break;
 762                         }
 763                         value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
 764                         break;
 765                 default:
 766                         ret = -EINVAL;
 767                         break;
 768                 }
 769
 770                 break;
 771
 772         default:
 773                 ret = -EINVAL;
 774                 break;
 775         }
 776
 777         if (!ret)
 778                 writel(value, padcfg1);
 779
 780         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 781
 782         return ret;
 783 }
 784
 785 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 786                                      unsigned int pin, unsigned int debounce)
 787 {
 788         void __iomem *padcfg0, *padcfg2;
 789         unsigned long flags;
 790         u32 value0, value2;
 791
 792         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 793         if (!padcfg2)
 794                 return -ENOTSUPP;
 795
 796         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 797
 798         raw_spin_lock_irqsave(&pctrl->lock, flags);
 799
 800         value0 = readl(padcfg0);
 801         value2 = readl(padcfg2);
 802
 803         /* Disable glitch filter and debouncer */
 804         value0 &= ~PADCFG0_PREGFRXSEL;
 805         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 806
 807         if (debounce) {
 808                 unsigned long v;
 809
 810                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 811                 if (v < 3 || v > 15) {
 812                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 813                         return -EINVAL;
 814                 }
 815
 816                 /* Enable glitch filter and debouncer */
 817                 value0 |= PADCFG0_PREGFRXSEL;
 818                 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 819                 value2 |= PADCFG2_DEBEN;
 820         }
 821
 822         writel(value0, padcfg0);
 823         writel(value2, padcfg2);
 824
 825         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 826
 827         return 0;
 828 }
 829
 830 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 831                           unsigned long *configs, unsigned int nconfigs)
 832 {
 833         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 834         int i, ret;
 835
 836         if (!intel_pad_usable(pctrl, pin))
 837                 return -ENOTSUPP;
 838
 839         for (i = 0; i < nconfigs; i++) {
 840                 switch (pinconf_to_config_param(configs[i])) {
 841                 case PIN_CONFIG_BIAS_DISABLE:
 842                 case PIN_CONFIG_BIAS_PULL_UP:
 843                 case PIN_CONFIG_BIAS_PULL_DOWN:
 844                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 845                         if (ret)
 846                                 return ret;
 847                         break;
 848
 849                 case PIN_CONFIG_INPUT_DEBOUNCE:
 850                         ret = intel_config_set_debounce(pctrl, pin,
 851                                 pinconf_to_config_argument(configs[i]));
 852                         if (ret)
 853                                 return ret;
 854                         break;
 855
 856                 default:
 857                         return -ENOTSUPP;
 858                 }
 859         }
 860
 861         return 0;
 862 }
 863
 864 static const struct pinconf_ops intel_pinconf_ops = {
 865         .is_generic = true,
 866         .pin_config_get = intel_config_get,
 867         .pin_config_set = intel_config_set,
 868 };
 869
 870 static const struct pinctrl_desc intel_pinctrl_desc = {
 871         .pctlops = &intel_pinctrl_ops,
 872         .pmxops = &intel_pinmux_ops,
 873         .confops = &intel_pinconf_ops,
 874         .owner = THIS_MODULE,
 875 };
 876
 877 /**
 878  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 879  * @pctrl: Pinctrl structure
 880  * @offset: GPIO offset from gpiolib
 881  * @community: Community is filled here if not %NULL
 882  * @padgrp: Pad group is filled here if not %NULL
 883  *
 884  * When coming through gpiolib irqchip, the GPIO offset is not
 885  * automatically translated to pinctrl pin number. This function can be
 886  * used to find out the corresponding pinctrl pin.
 887  *
 888  * Return: a pin number and pointers to the community and pad group, which
 889  * the pin belongs to, or negative error code if translation can't be done.
 890  */
 891 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
 892                              const struct intel_community **community,
 893                              const struct intel_padgroup **padgrp)
 894 {
 895         int i;
 896
 897         for (i = 0; i < pctrl->ncommunities; i++) {
 898                 const struct intel_community *comm = &pctrl->communities[i];
 899                 int j;
 900
 901                 for (j = 0; j < comm->ngpps; j++) {
 902                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 903
 904                         if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
 905                                 continue;
 906
 907                         if (offset >= pgrp->gpio_base &&
 908                             offset < pgrp->gpio_base + pgrp->size) {
 909                                 int pin;
 910
 911                                 pin = pgrp->base + offset - pgrp->gpio_base;
 912                                 if (community)
 913                                         *community = comm;
 914                                 if (padgrp)
 915                                         *padgrp = pgrp;
 916
 917                                 return pin;
 918                         }
 919                 }
 920         }
 921
 922         return -EINVAL;
 923 }
 924
 925 /**
 926  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
 927  * @pctrl: Pinctrl structure
 928  * @pin: pin number
 929  *
 930  * Translate the pin number of pinctrl to GPIO offset
 931  *
 932  * Return: a GPIO offset, or negative error code if translation can't be done.
 933  */
 934 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
 935 {
 936         const struct intel_community *community;
 937         const struct intel_padgroup *padgrp;
 938
 939         community = intel_get_community(pctrl, pin);
 940         if (!community)
 941                 return -EINVAL;
 942
 943         padgrp = intel_community_get_padgroup(community, pin);
 944         if (!padgrp)
 945                 return -EINVAL;
 946
 947         return pin - padgrp->base + padgrp->gpio_base;
 948 }
 949
 950 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 951 {
 952         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 953         void __iomem *reg;
 954         u32 padcfg0;
 955         int pin;
 956
 957         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 958         if (pin < 0)
 959                 return -EINVAL;
 960
 961         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 962         if (!reg)
 963                 return -EINVAL;
 964
 965         padcfg0 = readl(reg);
 966         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 967                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 968
 969         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 970 }
 971
 972 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
 973                            int value)
 974 {
 975         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 976         unsigned long flags;
 977         void __iomem *reg;
 978         u32 padcfg0;
 979         int pin;
 980
 981         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 982         if (pin < 0)
 983                 return;
 984
 985         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 986         if (!reg)
 987                 return;
 988
 989         raw_spin_lock_irqsave(&pctrl->lock, flags);
 990         padcfg0 = readl(reg);
 991         if (value)
 992                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 993         else
 994                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 995         writel(padcfg0, reg);
 996         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 997 }
 998
 999 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1000 {
1001         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1002         unsigned long flags;
1003         void __iomem *reg;
1004         u32 padcfg0;
1005         int pin;
1006
1007         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
1008         if (pin < 0)
1009                 return -EINVAL;
1010
1011         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1012         if (!reg)
1013                 return -EINVAL;
1014
1015         raw_spin_lock_irqsave(&pctrl->lock, flags);
1016         padcfg0 = readl(reg);
1017         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1018         if (padcfg0 & PADCFG0_PMODE_MASK)
1019                 return -EINVAL;
1020
1021         if (padcfg0 & PADCFG0_GPIOTXDIS)
1022                 return GPIO_LINE_DIRECTION_IN;
1023
1024         return GPIO_LINE_DIRECTION_OUT;
1025 }
1026
1027 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1028 {
1029         return pinctrl_gpio_direction_input(chip->base + offset);
1030 }
1031
1032 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1033                                        int value)
1034 {
1035         intel_gpio_set(chip, offset, value);
1036         return pinctrl_gpio_direction_output(chip->base + offset);
1037 }
1038
1039 static const struct gpio_chip intel_gpio_chip = {
1040         .owner = THIS_MODULE,
1041         .request = gpiochip_generic_request,
1042         .free = gpiochip_generic_free,
1043         .get_direction = intel_gpio_get_direction,
1044         .direction_input = intel_gpio_direction_input,
1045         .direction_output = intel_gpio_direction_output,
1046         .get = intel_gpio_get,
1047         .set = intel_gpio_set,
1048         .set_config = gpiochip_generic_config,
1049 };
1050
1051 static void intel_gpio_irq_ack(struct irq_data *d)
1052 {
1053         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1054         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1055         const struct intel_community *community;
1056         const struct intel_padgroup *padgrp;
1057         int pin;
1058
1059         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1060         if (pin >= 0) {
1061                 unsigned int gpp, gpp_offset, is_offset;
1062
1063                 gpp = padgrp->reg_num;
1064                 gpp_offset = padgroup_offset(padgrp, pin);
1065                 is_offset = community->is_offset + gpp * 4;
1066
1067                 raw_spin_lock(&pctrl->lock);
1068                 writel(BIT(gpp_offset), community->regs + is_offset);
1069                 raw_spin_unlock(&pctrl->lock);
1070         }
1071 }
1072
1073 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1074 {
1075         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1076         const struct intel_community *community;
1077         const struct intel_padgroup *padgrp;
1078         int pin;
1079
1080         pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
1081         if (pin >= 0) {
1082                 unsigned int gpp, gpp_offset;
1083                 unsigned long flags;
1084                 void __iomem *reg, *is;
1085                 u32 value;
1086
1087                 gpp = padgrp->reg_num;
1088                 gpp_offset = padgroup_offset(padgrp, pin);
1089
1090                 reg = community->regs + community->ie_offset + gpp * 4;
1091                 is = community->regs + community->is_offset + gpp * 4;
1092
1093                 raw_spin_lock_irqsave(&pctrl->lock, flags);
1094
1095                 /* Clear interrupt status first to avoid unexpected interrupt */
1096                 writel(BIT(gpp_offset), is);
1097
1098                 value = readl(reg);
1099                 if (mask)
1100                         value &= ~BIT(gpp_offset);
1101                 else
1102                         value |= BIT(gpp_offset);
1103                 writel(value, reg);
1104                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1105         }
1106 }
1107
1108 static void intel_gpio_irq_mask(struct irq_data *d)
1109 {
1110         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1111         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1112
1113         intel_gpio_irq_mask_unmask(gc, hwirq, true);
1114         gpiochip_disable_irq(gc, hwirq);
1115 }
1116
1117 static void intel_gpio_irq_unmask(struct irq_data *d)
1118 {
1119         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1120         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1121
1122         gpiochip_enable_irq(gc, hwirq);
1123         intel_gpio_irq_mask_unmask(gc, hwirq, false);
1124 }
1125
1126 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1127 {
1128         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1129         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1130         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1131         u32 rxevcfg, rxinv, value;
1132         unsigned long flags;
1133         void __iomem *reg;
1134
1135         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1136         if (!reg)
1137                 return -EINVAL;
1138
1139         /*
1140          * If the pin is in ACPI mode it is still usable as a GPIO but it
1141          * cannot be used as IRQ because GPI_IS status bit will not be
1142          * updated by the host controller hardware.
1143          */
1144         if (intel_pad_acpi_mode(pctrl, pin)) {
1145                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1146                 return -EPERM;
1147         }
1148
1149         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1150                 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
1151         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1152                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1153         } else if (type & IRQ_TYPE_EDGE_RISING) {
1154                 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1155         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1156                 rxevcfg = PADCFG0_RXEVCFG_LEVEL;
1157         } else {
1158                 rxevcfg = PADCFG0_RXEVCFG_DISABLED;
1159         }
1160
1161         if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW)
1162                 rxinv = PADCFG0_RXINV;
1163         else
1164                 rxinv = 0;
1165
1166         raw_spin_lock_irqsave(&pctrl->lock, flags);
1167
1168         intel_gpio_set_gpio_mode(reg);
1169
1170         value = readl(reg);
1171
1172         value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;
1173         value = (value & ~PADCFG0_RXINV) | rxinv;
1174
1175         writel(value, reg);
1176
1177         if (type & IRQ_TYPE_EDGE_BOTH)
1178                 irq_set_handler_locked(d, handle_edge_irq);
1179         else if (type & IRQ_TYPE_LEVEL_MASK)
1180                 irq_set_handler_locked(d, handle_level_irq);
1181
1182         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1183
1184         return 0;
1185 }
1186
1187 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1188 {
1189         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1190         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1191         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1192
1193         if (on)
1194                 enable_irq_wake(pctrl->irq);
1195         else
1196                 disable_irq_wake(pctrl->irq);
1197
1198         dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin);
1199         return 0;
1200 }
1201
1202 static const struct irq_chip intel_gpio_irq_chip = {
1203         .name = "intel-gpio",
1204         .irq_ack = intel_gpio_irq_ack,
1205         .irq_mask = intel_gpio_irq_mask,
1206         .irq_unmask = intel_gpio_irq_unmask,
1207         .irq_set_type = intel_gpio_irq_type,
1208         .irq_set_wake = intel_gpio_irq_wake,
1209         .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1210         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1211 };
1212
1213 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1214                                             const struct intel_community *community)
1215 {
1216         struct gpio_chip *gc = &pctrl->chip;
1217         unsigned int gpp;
1218         int ret = 0;
1219
1220         for (gpp = 0; gpp < community->ngpps; gpp++) {
1221                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1222                 unsigned long pending, enabled, gpp_offset;
1223
1224                 raw_spin_lock(&pctrl->lock);
1225
1226                 pending = readl(community->regs + community->is_offset +
1227                                 padgrp->reg_num * 4);
1228                 enabled = readl(community->regs + community->ie_offset +
1229                                 padgrp->reg_num * 4);
1230
1231                 raw_spin_unlock(&pctrl->lock);
1232
1233                 /* Only interrupts that are enabled */
1234                 pending &= enabled;
1235
1236                 for_each_set_bit(gpp_offset, &pending, padgrp->size)
1237                         generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset);
1238
1239                 ret += pending ? 1 : 0;
1240         }
1241
1242         return ret;
1243 }
1244
1245 static irqreturn_t intel_gpio_irq(int irq, void *data)
1246 {
1247         const struct intel_community *community;
1248         struct intel_pinctrl *pctrl = data;
1249         unsigned int i;
1250         int ret = 0;
1251
1252         /* Need to check all communities for pending interrupts */
1253         for (i = 0; i < pctrl->ncommunities; i++) {
1254                 community = &pctrl->communities[i];
1255                 ret += intel_gpio_community_irq_handler(pctrl, community);
1256         }
1257
1258         return IRQ_RETVAL(ret);
1259 }
1260
1261 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1262 {
1263         int i;
1264
1265         for (i = 0; i < pctrl->ncommunities; i++) {
1266                 const struct intel_community *community;
1267                 void __iomem *base;
1268                 unsigned int gpp;
1269
1270                 community = &pctrl->communities[i];
1271                 base = community->regs;
1272
1273                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1274                         /* Mask and clear all interrupts */
1275                         writel(0, base + community->ie_offset + gpp * 4);
1276                         writel(0xffff, base + community->is_offset + gpp * 4);
1277                 }
1278         }
1279 }
1280
1281 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1282 {
1283         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1284
1285         /*
1286          * Make sure the interrupt lines are in a proper state before
1287          * further configuration.
1288          */
1289         intel_gpio_irq_init(pctrl);
1290
1291         return 0;
1292 }
1293
1294 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1295                                 const struct intel_community *community)
1296 {
1297         int ret = 0, i;
1298
1299         for (i = 0; i < community->ngpps; i++) {
1300                 const struct intel_padgroup *gpp = &community->gpps[i];
1301
1302                 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1303                         continue;
1304
1305                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1306                                              gpp->gpio_base, gpp->base,
1307                                              gpp->size);
1308                 if (ret)
1309                         return ret;
1310         }
1311
1312         return ret;
1313 }
1314
1315 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1316 {
1317         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1318         int ret, i;
1319
1320         for (i = 0; i < pctrl->ncommunities; i++) {
1321                 struct intel_community *community = &pctrl->communities[i];
1322
1323                 ret = intel_gpio_add_community_ranges(pctrl, community);
1324                 if (ret) {
1325                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1326                         return ret;
1327                 }
1328         }
1329
1330         return 0;
1331 }
1332
1333 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1334 {
1335         const struct intel_community *community;
1336         unsigned int ngpio = 0;
1337         int i, j;
1338
1339         for (i = 0; i < pctrl->ncommunities; i++) {
1340                 community = &pctrl->communities[i];
1341                 for (j = 0; j < community->ngpps; j++) {
1342                         const struct intel_padgroup *gpp = &community->gpps[j];
1343
1344                         if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1345                                 continue;
1346
1347                         if (gpp->gpio_base + gpp->size > ngpio)
1348                                 ngpio = gpp->gpio_base + gpp->size;
1349                 }
1350         }
1351
1352         return ngpio;
1353 }
1354
1355 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1356 {
1357         int ret;
1358         struct gpio_irq_chip *girq;
1359
1360         pctrl->chip = intel_gpio_chip;
1361
1362         /* Setup GPIO chip */
1363         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1364         pctrl->chip.label = dev_name(pctrl->dev);
1365         pctrl->chip.parent = pctrl->dev;
1366         pctrl->chip.base = -1;
1367         pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1368         pctrl->irq = irq;
1369
1370         /*
1371          * On some platforms several GPIO controllers share the same interrupt
1372          * line.
1373          */
1374         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1375                                IRQF_SHARED | IRQF_NO_THREAD,
1376                                dev_name(pctrl->dev), pctrl);
1377         if (ret) {
1378                 dev_err(pctrl->dev, "failed to request interrupt\n");
1379                 return ret;
1380         }
1381
1382         /* Setup IRQ chip */
1383         girq = &pctrl->chip.irq;
1384         gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
1385         /* This will let us handle the IRQ in the driver */
1386         girq->parent_handler = NULL;
1387         girq->num_parents = 0;
1388         girq->default_type = IRQ_TYPE_NONE;
1389         girq->handler = handle_bad_irq;
1390         girq->init_hw = intel_gpio_irq_init_hw;
1391
1392         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1393         if (ret) {
1394                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1395                 return ret;
1396         }
1397
1398         return 0;
1399 }
1400
1401 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1402                                                struct intel_community *community)
1403 {
1404         struct intel_padgroup *gpps;
1405         unsigned int padown_num = 0;
1406         size_t i, ngpps = community->ngpps;
1407
1408         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1409         if (!gpps)
1410                 return -ENOMEM;
1411
1412         for (i = 0; i < ngpps; i++) {
1413                 gpps[i] = community->gpps[i];
1414
1415                 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE)
1416                         return -EINVAL;
1417
1418                 /* Special treatment for GPIO base */
1419                 switch (gpps[i].gpio_base) {
1420                         case INTEL_GPIO_BASE_MATCH:
1421                                 gpps[i].gpio_base = gpps[i].base;
1422                                 break;
1423                         case INTEL_GPIO_BASE_ZERO:
1424                                 gpps[i].gpio_base = 0;
1425                                 break;
1426                         case INTEL_GPIO_BASE_NOMAP:
1427                                 break;
1428                         default:
1429                                 break;
1430                 }
1431
1432                 gpps[i].padown_num = padown_num;
1433                 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE);
1434         }
1435
1436         community->gpps = gpps;
1437
1438         return 0;
1439 }
1440
1441 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1442                                                struct intel_community *community)
1443 {
1444         struct intel_padgroup *gpps;
1445         unsigned int npins = community->npins;
1446         unsigned int padown_num = 0;
1447         size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1448
1449         if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE)
1450                 return -EINVAL;
1451
1452         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1453         if (!gpps)
1454                 return -ENOMEM;
1455
1456         for (i = 0; i < ngpps; i++) {
1457                 unsigned int gpp_size = community->gpp_size;
1458
1459                 gpps[i].reg_num = i;
1460                 gpps[i].base = community->pin_base + i * gpp_size;
1461                 gpps[i].size = min(gpp_size, npins);
1462                 npins -= gpps[i].size;
1463
1464                 gpps[i].gpio_base = gpps[i].base;
1465                 gpps[i].padown_num = padown_num;
1466
1467                 padown_num += community->gpp_num_padown_regs;
1468         }
1469
1470         community->ngpps = ngpps;
1471         community->gpps = gpps;
1472
1473         return 0;
1474 }
1475
1476 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1477 {
1478 #ifdef CONFIG_PM_SLEEP
1479         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1480         struct intel_community_context *communities;
1481         struct intel_pad_context *pads;
1482         int i;
1483
1484         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1485         if (!pads)
1486                 return -ENOMEM;
1487
1488         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1489                                    sizeof(*communities), GFP_KERNEL);
1490         if (!communities)
1491                 return -ENOMEM;
1492
1493
1494         for (i = 0; i < pctrl->ncommunities; i++) {
1495                 struct intel_community *community = &pctrl->communities[i];
1496                 u32 *intmask, *hostown;
1497
1498                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1499                                        sizeof(*intmask), GFP_KERNEL);
1500                 if (!intmask)
1501                         return -ENOMEM;
1502
1503                 communities[i].intmask = intmask;
1504
1505                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1506                                        sizeof(*hostown), GFP_KERNEL);
1507                 if (!hostown)
1508                         return -ENOMEM;
1509
1510                 communities[i].hostown = hostown;
1511         }
1512
1513         pctrl->context.pads = pads;
1514         pctrl->context.communities = communities;
1515 #endif
1516
1517         return 0;
1518 }
1519
1520 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
1521                                    struct intel_community *community)
1522 {
1523         static const struct pwm_lpss_boardinfo info = {
1524                 .clk_rate = 19200000,
1525                 .npwm = 1,
1526                 .base_unit_bits = 22,
1527                 .bypass = true,
1528         };
1529         struct pwm_lpss_chip *pwm;
1530
1531         if (!(community->features & PINCTRL_FEATURE_PWM))
1532                 return 0;
1533
1534         if (!IS_REACHABLE(CONFIG_PWM_LPSS))
1535                 return 0;
1536
1537         pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
1538         return PTR_ERR_OR_ZERO(pwm);
1539 }
1540
1541 static int intel_pinctrl_probe(struct platform_device *pdev,
1542                                const struct intel_pinctrl_soc_data *soc_data)
1543 {
1544         struct device *dev = &pdev->dev;
1545         struct intel_pinctrl *pctrl;
1546         int i, ret, irq;
1547
1548         pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1549         if (!pctrl)
1550                 return -ENOMEM;
1551
1552         pctrl->dev = dev;
1553         pctrl->soc = soc_data;
1554         raw_spin_lock_init(&pctrl->lock);
1555
1556         /*
1557          * Make a copy of the communities which we can use to hold pointers
1558          * to the registers.
1559          */
1560         pctrl->ncommunities = pctrl->soc->ncommunities;
1561         pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities,
1562                                           sizeof(*pctrl->communities), GFP_KERNEL);
1563         if (!pctrl->communities)
1564                 return -ENOMEM;
1565
1566         for (i = 0; i < pctrl->ncommunities; i++) {
1567                 struct intel_community *community = &pctrl->communities[i];
1568                 void __iomem *regs;
1569                 u32 offset;
1570                 u32 value;
1571
1572                 *community = pctrl->soc->communities[i];
1573
1574                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1575                 if (IS_ERR(regs))
1576                         return PTR_ERR(regs);
1577
1578                 /*
1579                  * Determine community features based on the revision.
1580                  * A value of all ones means the device is not present.
1581                  */
1582                 value = readl(regs + REVID);
1583                 if (value == ~0u)
1584                         return -ENODEV;
1585                 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1586                         community->features |= PINCTRL_FEATURE_DEBOUNCE;
1587                         community->features |= PINCTRL_FEATURE_1K_PD;
1588                 }
1589
1590                 /* Determine community features based on the capabilities */
1591                 offset = CAPLIST;
1592                 do {
1593                         value = readl(regs + offset);
1594                         switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1595                         case CAPLIST_ID_GPIO_HW_INFO:
1596                                 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1597                                 break;
1598                         case CAPLIST_ID_PWM:
1599                                 community->features |= PINCTRL_FEATURE_PWM;
1600                                 break;
1601                         case CAPLIST_ID_BLINK:
1602                                 community->features |= PINCTRL_FEATURE_BLINK;
1603                                 break;
1604                         case CAPLIST_ID_EXP:
1605                                 community->features |= PINCTRL_FEATURE_EXP;
1606                                 break;
1607                         default:
1608                                 break;
1609                         }
1610                         offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1611                 } while (offset);
1612
1613                 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features);
1614
1615                 /* Read offset of the pad configuration registers */
1616                 offset = readl(regs + PADBAR);
1617
1618                 community->regs = regs;
1619                 community->pad_regs = regs + offset;
1620
1621                 if (community->gpps)
1622                         ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1623                 else
1624                         ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1625                 if (ret)
1626                         return ret;
1627
1628                 ret = intel_pinctrl_probe_pwm(pctrl, community);
1629                 if (ret)
1630                         return ret;
1631         }
1632
1633         irq = platform_get_irq(pdev, 0);
1634         if (irq < 0)
1635                 return irq;
1636
1637         ret = intel_pinctrl_pm_init(pctrl);
1638         if (ret)
1639                 return ret;
1640
1641         pctrl->pctldesc = intel_pinctrl_desc;
1642         pctrl->pctldesc.name = dev_name(dev);
1643         pctrl->pctldesc.pins = pctrl->soc->pins;
1644         pctrl->pctldesc.npins = pctrl->soc->npins;
1645
1646         pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1647         if (IS_ERR(pctrl->pctldev)) {
1648                 dev_err(dev, "failed to register pinctrl driver\n");
1649                 return PTR_ERR(pctrl->pctldev);
1650         }
1651
1652         ret = intel_gpio_probe(pctrl, irq);
1653         if (ret)
1654                 return ret;
1655
1656         platform_set_drvdata(pdev, pctrl);
1657
1658         return 0;
1659 }
1660
1661 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1662 {
1663         const struct intel_pinctrl_soc_data *data;
1664
1665         data = device_get_match_data(&pdev->dev);
1666         if (!data)
1667                 return -ENODATA;
1668
1669         return intel_pinctrl_probe(pdev, data);
1670 }
1671 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, PINCTRL_INTEL);
1672
1673 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1674 {
1675         const struct intel_pinctrl_soc_data *data;
1676
1677         data = intel_pinctrl_get_soc_data(pdev);
1678         if (IS_ERR(data))
1679                 return PTR_ERR(data);
1680
1681         return intel_pinctrl_probe(pdev, data);
1682 }
1683 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, PINCTRL_INTEL);
1684
1685 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1686 {
1687         const struct intel_pinctrl_soc_data * const *table;
1688         const struct intel_pinctrl_soc_data *data = NULL;
1689         struct device *dev = &pdev->dev;
1690
1691         table = device_get_match_data(dev);
1692         if (table) {
1693                 struct acpi_device *adev = ACPI_COMPANION(dev);
1694                 unsigned int i;
1695
1696                 for (i = 0; table[i]; i++) {
1697                         if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1698                                 data = table[i];
1699                                 break;
1700                         }
1701                 }
1702         } else {
1703                 const struct platform_device_id *id;
1704
1705                 id = platform_get_device_id(pdev);
1706                 if (!id)
1707                         return ERR_PTR(-ENODEV);
1708
1709                 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1710                 data = table[pdev->id];
1711         }
1712
1713         return data ?: ERR_PTR(-ENODATA);
1714 }
1715 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL);
1716
1717 #ifdef CONFIG_PM_SLEEP
1718 static bool __intel_gpio_is_direct_irq(u32 value)
1719 {
1720         return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
1721                (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1722 }
1723
1724 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1725 {
1726         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1727         u32 value;
1728
1729         if (!pd || !intel_pad_usable(pctrl, pin))
1730                 return false;
1731
1732         /*
1733          * Only restore the pin if it is actually in use by the kernel (or
1734          * by userspace). It is possible that some pins are used by the
1735          * BIOS during resume and those are not always locked down so leave
1736          * them alone.
1737          */
1738         if (pd->mux_owner || pd->gpio_owner ||
1739             gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1740                 return true;
1741
1742         /*
1743          * The firmware on some systems may configure GPIO pins to be
1744          * an interrupt source in so called "direct IRQ" mode. In such
1745          * cases the GPIO controller driver has no idea if those pins
1746          * are being used or not. At the same time, there is a known bug
1747          * in the firmwares that don't restore the pin settings correctly
1748          * after suspend, i.e. by an unknown reason the Rx value becomes
1749          * inverted.
1750          *
1751          * Hence, let's save and restore the pins that are configured
1752          * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
1753          *
1754          * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
1755          */
1756         value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1757         if (__intel_gpio_is_direct_irq(value))
1758                 return true;
1759
1760         return false;
1761 }
1762
1763 int intel_pinctrl_suspend_noirq(struct device *dev)
1764 {
1765         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1766         struct intel_community_context *communities;
1767         struct intel_pad_context *pads;
1768         int i;
1769
1770         pads = pctrl->context.pads;
1771         for (i = 0; i < pctrl->soc->npins; i++) {
1772                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1773                 void __iomem *padcfg;
1774                 u32 val;
1775
1776                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1777                         continue;
1778
1779                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1780                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1781                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1782                 pads[i].padcfg1 = val;
1783
1784                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1785                 if (padcfg)
1786                         pads[i].padcfg2 = readl(padcfg);
1787         }
1788
1789         communities = pctrl->context.communities;
1790         for (i = 0; i < pctrl->ncommunities; i++) {
1791                 struct intel_community *community = &pctrl->communities[i];
1792                 void __iomem *base;
1793                 unsigned int gpp;
1794
1795                 base = community->regs + community->ie_offset;
1796                 for (gpp = 0; gpp < community->ngpps; gpp++)
1797                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1798
1799                 base = community->regs + community->hostown_offset;
1800                 for (gpp = 0; gpp < community->ngpps; gpp++)
1801                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1802         }
1803
1804         return 0;
1805 }
1806 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1807
1808 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1809 {
1810         u32 curr, updated;
1811
1812         curr = readl(reg);
1813
1814         updated = (curr & ~mask) | (value & mask);
1815         if (curr == updated)
1816                 return false;
1817
1818         writel(updated, reg);
1819         return true;
1820 }
1821
1822 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1823                                   void __iomem *base, unsigned int gpp, u32 saved)
1824 {
1825         const struct intel_community *community = &pctrl->communities[c];
1826         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1827         struct device *dev = pctrl->dev;
1828         const char *dummy;
1829         u32 requested = 0;
1830         unsigned int i;
1831
1832         if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1833                 return;
1834
1835         for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1836                 requested |= BIT(i);
1837
1838         if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1839                 return;
1840
1841         dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1842 }
1843
1844 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1845                                   void __iomem *base, unsigned int gpp, u32 saved)
1846 {
1847         struct device *dev = pctrl->dev;
1848
1849         if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1850                 return;
1851
1852         dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1853 }
1854
1855 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1856                                  unsigned int reg, u32 saved)
1857 {
1858         u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1859         unsigned int n = reg / sizeof(u32);
1860         struct device *dev = pctrl->dev;
1861         void __iomem *padcfg;
1862
1863         padcfg = intel_get_padcfg(pctrl, pin, reg);
1864         if (!padcfg)
1865                 return;
1866
1867         if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1868                 return;
1869
1870         dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1871 }
1872
1873 int intel_pinctrl_resume_noirq(struct device *dev)
1874 {
1875         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1876         const struct intel_community_context *communities;
1877         const struct intel_pad_context *pads;
1878         int i;
1879
1880         /* Mask all interrupts */
1881         intel_gpio_irq_init(pctrl);
1882
1883         pads = pctrl->context.pads;
1884         for (i = 0; i < pctrl->soc->npins; i++) {
1885                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1886
1887                 if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
1888                       /*
1889                        * If the firmware mangled the register contents too much,
1890                        * check the saved value for the Direct IRQ mode.
1891                        */
1892                       __intel_gpio_is_direct_irq(pads[i].padcfg0)))
1893                         continue;
1894
1895                 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1896                 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1897                 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1898         }
1899
1900         communities = pctrl->context.communities;
1901         for (i = 0; i < pctrl->ncommunities; i++) {
1902                 struct intel_community *community = &pctrl->communities[i];
1903                 void __iomem *base;
1904                 unsigned int gpp;
1905
1906                 base = community->regs + community->ie_offset;
1907                 for (gpp = 0; gpp < community->ngpps; gpp++)
1908                         intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1909
1910                 base = community->regs + community->hostown_offset;
1911                 for (gpp = 0; gpp < community->ngpps; gpp++)
1912                         intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1913         }
1914
1915         return 0;
1916 }
1917 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1918 #endif
1919
1920 MODULE_AUTHOR("Mathias Nyman <[email protected]>");
1921 MODULE_AUTHOR("Mika Westerberg <[email protected]>");
1922 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1923 MODULE_LICENSE("GPL v2");