drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_sched.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46
  47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  48 {
  49         struct amdgpu_gpu_instance *gpu_instance;
  50         int i;
  51
  52         mutex_lock(&mgpu_info.mutex);
  53
  54         for (i = 0; i < mgpu_info.num_gpu; i++) {
  55                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  56                 if (gpu_instance->adev == adev) {
  57                         mgpu_info.gpu_ins[i] =
  58                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  59                         mgpu_info.num_gpu--;
  60                         if (adev->flags & AMD_IS_APU)
  61                                 mgpu_info.num_apu--;
  62                         else
  63                                 mgpu_info.num_dgpu--;
  64                         break;
  65                 }
  66         }
  67
  68         mutex_unlock(&mgpu_info.mutex);
  69 }
  70
  71 /**
  72  * amdgpu_driver_unload_kms - Main unload function for KMS.
  73  *
  74  * @dev: drm dev pointer
  75  *
  76  * This is the main unload function for KMS (all asics).
  77  * Returns 0 on success.
  78  */
  79 void amdgpu_driver_unload_kms(struct drm_device *dev)
  80 {
  81         struct amdgpu_device *adev = dev->dev_private;
  82
  83         if (adev == NULL)
  84                 return;
  85
  86         amdgpu_unregister_gpu_instance(adev);
  87
  88         if (adev->rmmio == NULL)
  89                 goto done_free;
  90
  91         if (amdgpu_sriov_vf(adev))
  92                 amdgpu_virt_request_full_gpu(adev, false);
  93
  94         if (amdgpu_device_is_px(dev)) {
  95                 pm_runtime_get_sync(dev->dev);
  96                 pm_runtime_forbid(dev->dev);
  97         }
  98
  99         amdgpu_acpi_fini(adev);
 100
 101         amdgpu_device_fini(adev);
 102
 103 done_free:
 104         kfree(adev);
 105         dev->dev_private = NULL;
 106 }
 107
 108 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 109 {
 110         struct amdgpu_gpu_instance *gpu_instance;
 111
 112         mutex_lock(&mgpu_info.mutex);
 113
 114         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 115                 DRM_ERROR("Cannot register more gpu instance\n");
 116                 mutex_unlock(&mgpu_info.mutex);
 117                 return;
 118         }
 119
 120         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 121         gpu_instance->adev = adev;
 122         gpu_instance->mgpu_fan_enabled = 0;
 123
 124         mgpu_info.num_gpu++;
 125         if (adev->flags & AMD_IS_APU)
 126                 mgpu_info.num_apu++;
 127         else
 128                 mgpu_info.num_dgpu++;
 129
 130         mutex_unlock(&mgpu_info.mutex);
 131 }
 132
 133 /**
 134  * amdgpu_driver_load_kms - Main load function for KMS.
 135  *
 136  * @dev: drm dev pointer
 137  * @flags: device flags
 138  *
 139  * This is the main load function for KMS (all asics).
 140  * Returns 0 on success, error on failure.
 141  */
 142 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 143 {
 144         struct amdgpu_device *adev;
 145         int r, acpi_status;
 146
 147         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 148         if (adev == NULL) {
 149                 return -ENOMEM;
 150         }
 151         dev->dev_private = (void *)adev;
 152
 153         if ((amdgpu_runtime_pm != 0) &&
 154             amdgpu_has_atpx() &&
 155             (amdgpu_is_atpx_hybrid() ||
 156              amdgpu_has_atpx_dgpu_power_cntl()) &&
 157             ((flags & AMD_IS_APU) == 0) &&
 158             !pci_is_thunderbolt_attached(dev->pdev))
 159                 flags |= AMD_IS_PX;
 160
 161         /* amdgpu_device_init should report only fatal error
 162          * like memory allocation failure or iomapping failure,
 163          * or memory manager initialization failure, it must
 164          * properly initialize the GPU MC controller and permit
 165          * VRAM allocation
 166          */
 167         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 168         if (r) {
 169                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 170                 goto out;
 171         }
 172
 173         /* Call ACPI methods: require modeset init
 174          * but failure is not fatal
 175          */
 176         if (!r) {
 177                 acpi_status = amdgpu_acpi_init(adev);
 178                 if (acpi_status)
 179                         dev_dbg(&dev->pdev->dev,
 180                                 "Error during ACPI methods call\n");
 181         }
 182
 183         if (amdgpu_device_is_px(dev)) {
 184                 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
 185                 pm_runtime_use_autosuspend(dev->dev);
 186                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 187                 pm_runtime_set_active(dev->dev);
 188                 pm_runtime_allow(dev->dev);
 189                 pm_runtime_mark_last_busy(dev->dev);
 190                 pm_runtime_put_autosuspend(dev->dev);
 191         }
 192
 193 out:
 194         if (r) {
 195                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 196                 if (adev->rmmio && amdgpu_device_is_px(dev))
 197                         pm_runtime_put_noidle(dev->dev);
 198                 amdgpu_driver_unload_kms(dev);
 199         }
 200
 201         return r;
 202 }
 203
 204 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 205                                 struct drm_amdgpu_query_fw *query_fw,
 206                                 struct amdgpu_device *adev)
 207 {
 208         switch (query_fw->fw_type) {
 209         case AMDGPU_INFO_FW_VCE:
 210                 fw_info->ver = adev->vce.fw_version;
 211                 fw_info->feature = adev->vce.fb_version;
 212                 break;
 213         case AMDGPU_INFO_FW_UVD:
 214                 fw_info->ver = adev->uvd.fw_version;
 215                 fw_info->feature = 0;
 216                 break;
 217         case AMDGPU_INFO_FW_VCN:
 218                 fw_info->ver = adev->vcn.fw_version;
 219                 fw_info->feature = 0;
 220                 break;
 221         case AMDGPU_INFO_FW_GMC:
 222                 fw_info->ver = adev->gmc.fw_version;
 223                 fw_info->feature = 0;
 224                 break;
 225         case AMDGPU_INFO_FW_GFX_ME:
 226                 fw_info->ver = adev->gfx.me_fw_version;
 227                 fw_info->feature = adev->gfx.me_feature_version;
 228                 break;
 229         case AMDGPU_INFO_FW_GFX_PFP:
 230                 fw_info->ver = adev->gfx.pfp_fw_version;
 231                 fw_info->feature = adev->gfx.pfp_feature_version;
 232                 break;
 233         case AMDGPU_INFO_FW_GFX_CE:
 234                 fw_info->ver = adev->gfx.ce_fw_version;
 235                 fw_info->feature = adev->gfx.ce_feature_version;
 236                 break;
 237         case AMDGPU_INFO_FW_GFX_RLC:
 238                 fw_info->ver = adev->gfx.rlc_fw_version;
 239                 fw_info->feature = adev->gfx.rlc_feature_version;
 240                 break;
 241         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 242                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 243                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 244                 break;
 245         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 246                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 247                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 248                 break;
 249         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 250                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 251                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 252                 break;
 253         case AMDGPU_INFO_FW_GFX_MEC:
 254                 if (query_fw->index == 0) {
 255                         fw_info->ver = adev->gfx.mec_fw_version;
 256                         fw_info->feature = adev->gfx.mec_feature_version;
 257                 } else if (query_fw->index == 1) {
 258                         fw_info->ver = adev->gfx.mec2_fw_version;
 259                         fw_info->feature = adev->gfx.mec2_feature_version;
 260                 } else
 261                         return -EINVAL;
 262                 break;
 263         case AMDGPU_INFO_FW_SMC:
 264                 fw_info->ver = adev->pm.fw_version;
 265                 fw_info->feature = 0;
 266                 break;
 267         case AMDGPU_INFO_FW_TA:
 268                 if (query_fw->index > 1)
 269                         return -EINVAL;
 270                 if (query_fw->index == 0) {
 271                         fw_info->ver = adev->psp.ta_fw_version;
 272                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 273                 } else {
 274                         fw_info->ver = adev->psp.ta_fw_version;
 275                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 276                 }
 277                 break;
 278         case AMDGPU_INFO_FW_SDMA:
 279                 if (query_fw->index >= adev->sdma.num_instances)
 280                         return -EINVAL;
 281                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 282                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 283                 break;
 284         case AMDGPU_INFO_FW_SOS:
 285                 fw_info->ver = adev->psp.sos_fw_version;
 286                 fw_info->feature = adev->psp.sos_feature_version;
 287                 break;
 288         case AMDGPU_INFO_FW_ASD:
 289                 fw_info->ver = adev->psp.asd_fw_version;
 290                 fw_info->feature = adev->psp.asd_feature_version;
 291                 break;
 292         case AMDGPU_INFO_FW_DMCU:
 293                 fw_info->ver = adev->dm.dmcu_fw_version;
 294                 fw_info->feature = 0;
 295                 break;
 296         default:
 297                 return -EINVAL;
 298         }
 299         return 0;
 300 }
 301
 302 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 303                              struct drm_amdgpu_info *info,
 304                              struct drm_amdgpu_info_hw_ip *result)
 305 {
 306         uint32_t ib_start_alignment = 0;
 307         uint32_t ib_size_alignment = 0;
 308         enum amd_ip_block_type type;
 309         unsigned int num_rings = 0;
 310         unsigned int i, j;
 311
 312         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 313                 return -EINVAL;
 314
 315         switch (info->query_hw_ip.type) {
 316         case AMDGPU_HW_IP_GFX:
 317                 type = AMD_IP_BLOCK_TYPE_GFX;
 318                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 319                         if (adev->gfx.gfx_ring[i].sched.ready)
 320                                 ++num_rings;
 321                 ib_start_alignment = 32;
 322                 ib_size_alignment = 32;
 323                 break;
 324         case AMDGPU_HW_IP_COMPUTE:
 325                 type = AMD_IP_BLOCK_TYPE_GFX;
 326                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 327                         if (adev->gfx.compute_ring[i].sched.ready)
 328                                 ++num_rings;
 329                 ib_start_alignment = 32;
 330                 ib_size_alignment = 32;
 331                 break;
 332         case AMDGPU_HW_IP_DMA:
 333                 type = AMD_IP_BLOCK_TYPE_SDMA;
 334                 for (i = 0; i < adev->sdma.num_instances; i++)
 335                         if (adev->sdma.instance[i].ring.sched.ready)
 336                                 ++num_rings;
 337                 ib_start_alignment = 256;
 338                 ib_size_alignment = 4;
 339                 break;
 340         case AMDGPU_HW_IP_UVD:
 341                 type = AMD_IP_BLOCK_TYPE_UVD;
 342                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 343                         if (adev->uvd.harvest_config & (1 << i))
 344                                 continue;
 345
 346                         if (adev->uvd.inst[i].ring.sched.ready)
 347                                 ++num_rings;
 348                 }
 349                 ib_start_alignment = 64;
 350                 ib_size_alignment = 64;
 351                 break;
 352         case AMDGPU_HW_IP_VCE:
 353                 type = AMD_IP_BLOCK_TYPE_VCE;
 354                 for (i = 0; i < adev->vce.num_rings; i++)
 355                         if (adev->vce.ring[i].sched.ready)
 356                                 ++num_rings;
 357                 ib_start_alignment = 4;
 358                 ib_size_alignment = 1;
 359                 break;
 360         case AMDGPU_HW_IP_UVD_ENC:
 361                 type = AMD_IP_BLOCK_TYPE_UVD;
 362                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 363                         if (adev->uvd.harvest_config & (1 << i))
 364                                 continue;
 365
 366                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 367                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 368                                         ++num_rings;
 369                 }
 370                 ib_start_alignment = 64;
 371                 ib_size_alignment = 64;
 372                 break;
 373         case AMDGPU_HW_IP_VCN_DEC:
 374                 type = AMD_IP_BLOCK_TYPE_VCN;
 375                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 376                         if (adev->uvd.harvest_config & (1 << i))
 377                                 continue;
 378
 379                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 380                                 ++num_rings;
 381                 }
 382                 ib_start_alignment = 16;
 383                 ib_size_alignment = 16;
 384                 break;
 385         case AMDGPU_HW_IP_VCN_ENC:
 386                 type = AMD_IP_BLOCK_TYPE_VCN;
 387                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 388                         if (adev->uvd.harvest_config & (1 << i))
 389                                 continue;
 390
 391                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 392                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 393                                         ++num_rings;
 394                 }
 395                 ib_start_alignment = 64;
 396                 ib_size_alignment = 1;
 397                 break;
 398         case AMDGPU_HW_IP_VCN_JPEG:
 399                 type = AMD_IP_BLOCK_TYPE_VCN;
 400                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 401                         if (adev->uvd.harvest_config & (1 << i))
 402                                 continue;
 403
 404                         if (adev->vcn.inst[i].ring_jpeg.sched.ready)
 405                                 ++num_rings;
 406                 }
 407                 ib_start_alignment = 16;
 408                 ib_size_alignment = 16;
 409                 break;
 410         default:
 411                 return -EINVAL;
 412         }
 413
 414         for (i = 0; i < adev->num_ip_blocks; i++)
 415                 if (adev->ip_blocks[i].version->type == type &&
 416                     adev->ip_blocks[i].status.valid)
 417                         break;
 418
 419         if (i == adev->num_ip_blocks)
 420                 return 0;
 421
 422         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 423                         num_rings);
 424
 425         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 426         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 427         result->capabilities_flags = 0;
 428         result->available_rings = (1 << num_rings) - 1;
 429         result->ib_start_alignment = ib_start_alignment;
 430         result->ib_size_alignment = ib_size_alignment;
 431         return 0;
 432 }
 433
 434 /*
 435  * Userspace get information ioctl
 436  */
 437 /**
 438  * amdgpu_info_ioctl - answer a device specific request.
 439  *
 440  * @adev: amdgpu device pointer
 441  * @data: request object
 442  * @filp: drm filp
 443  *
 444  * This function is used to pass device specific parameters to the userspace
 445  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 446  * etc. (all asics).
 447  * Returns 0 on success, -EINVAL on failure.
 448  */
 449 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 450 {
 451         struct amdgpu_device *adev = dev->dev_private;
 452         struct drm_amdgpu_info *info = data;
 453         struct amdgpu_mode_info *minfo = &adev->mode_info;
 454         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 455         uint32_t size = info->return_size;
 456         struct drm_crtc *crtc;
 457         uint32_t ui32 = 0;
 458         uint64_t ui64 = 0;
 459         int i, found;
 460         int ui32_size = sizeof(ui32);
 461
 462         if (!info->return_size || !info->return_pointer)
 463                 return -EINVAL;
 464
 465         switch (info->query) {
 466         case AMDGPU_INFO_ACCEL_WORKING:
 467                 ui32 = adev->accel_working;
 468                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 469         case AMDGPU_INFO_CRTC_FROM_ID:
 470                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 471                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 472                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 473                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 474                                 ui32 = amdgpu_crtc->crtc_id;
 475                                 found = 1;
 476                                 break;
 477                         }
 478                 }
 479                 if (!found) {
 480                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 481                         return -EINVAL;
 482                 }
 483                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 484         case AMDGPU_INFO_HW_IP_INFO: {
 485                 struct drm_amdgpu_info_hw_ip ip = {};
 486                 int ret;
 487
 488                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 489                 if (ret)
 490                         return ret;
 491
 492                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 493                 return ret ? -EFAULT : 0;
 494         }
 495         case AMDGPU_INFO_HW_IP_COUNT: {
 496                 enum amd_ip_block_type type;
 497                 uint32_t count = 0;
 498
 499                 switch (info->query_hw_ip.type) {
 500                 case AMDGPU_HW_IP_GFX:
 501                         type = AMD_IP_BLOCK_TYPE_GFX;
 502                         break;
 503                 case AMDGPU_HW_IP_COMPUTE:
 504                         type = AMD_IP_BLOCK_TYPE_GFX;
 505                         break;
 506                 case AMDGPU_HW_IP_DMA:
 507                         type = AMD_IP_BLOCK_TYPE_SDMA;
 508                         break;
 509                 case AMDGPU_HW_IP_UVD:
 510                         type = AMD_IP_BLOCK_TYPE_UVD;
 511                         break;
 512                 case AMDGPU_HW_IP_VCE:
 513                         type = AMD_IP_BLOCK_TYPE_VCE;
 514                         break;
 515                 case AMDGPU_HW_IP_UVD_ENC:
 516                         type = AMD_IP_BLOCK_TYPE_UVD;
 517                         break;
 518                 case AMDGPU_HW_IP_VCN_DEC:
 519                 case AMDGPU_HW_IP_VCN_ENC:
 520                 case AMDGPU_HW_IP_VCN_JPEG:
 521                         type = AMD_IP_BLOCK_TYPE_VCN;
 522                         break;
 523                 default:
 524                         return -EINVAL;
 525                 }
 526
 527                 for (i = 0; i < adev->num_ip_blocks; i++)
 528                         if (adev->ip_blocks[i].version->type == type &&
 529                             adev->ip_blocks[i].status.valid &&
 530                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 531                                 count++;
 532
 533                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 534         }
 535         case AMDGPU_INFO_TIMESTAMP:
 536                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 537                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 538         case AMDGPU_INFO_FW_VERSION: {
 539                 struct drm_amdgpu_info_firmware fw_info;
 540                 int ret;
 541
 542                 /* We only support one instance of each IP block right now. */
 543                 if (info->query_fw.ip_instance != 0)
 544                         return -EINVAL;
 545
 546                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 547                 if (ret)
 548                         return ret;
 549
 550                 return copy_to_user(out, &fw_info,
 551                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 552         }
 553         case AMDGPU_INFO_NUM_BYTES_MOVED:
 554                 ui64 = atomic64_read(&adev->num_bytes_moved);
 555                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 556         case AMDGPU_INFO_NUM_EVICTIONS:
 557                 ui64 = atomic64_read(&adev->num_evictions);
 558                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 559         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 560                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 561                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 562         case AMDGPU_INFO_VRAM_USAGE:
 563                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 564                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 565         case AMDGPU_INFO_VIS_VRAM_USAGE:
 566                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 567                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 568         case AMDGPU_INFO_GTT_USAGE:
 569                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 570                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 571         case AMDGPU_INFO_GDS_CONFIG: {
 572                 struct drm_amdgpu_info_gds gds_info;
 573
 574                 memset(&gds_info, 0, sizeof(gds_info));
 575                 gds_info.compute_partition_size = adev->gds.gds_size;
 576                 gds_info.gds_total_size = adev->gds.gds_size;
 577                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 578                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 579                 return copy_to_user(out, &gds_info,
 580                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 581         }
 582         case AMDGPU_INFO_VRAM_GTT: {
 583                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 584
 585                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 586                         atomic64_read(&adev->vram_pin_size);
 587                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 588                         atomic64_read(&adev->visible_pin_size);
 589                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 590                 vram_gtt.gtt_size *= PAGE_SIZE;
 591                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 592                 return copy_to_user(out, &vram_gtt,
 593                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 594         }
 595         case AMDGPU_INFO_MEMORY: {
 596                 struct drm_amdgpu_memory_info mem;
 597
 598                 memset(&mem, 0, sizeof(mem));
 599                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 600                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 601                         atomic64_read(&adev->vram_pin_size);
 602                 mem.vram.heap_usage =
 603                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 604                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 605
 606                 mem.cpu_accessible_vram.total_heap_size =
 607                         adev->gmc.visible_vram_size;
 608                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 609                         atomic64_read(&adev->visible_pin_size);
 610                 mem.cpu_accessible_vram.heap_usage =
 611                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 612                 mem.cpu_accessible_vram.max_allocation =
 613                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 614
 615                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 616                 mem.gtt.total_heap_size *= PAGE_SIZE;
 617                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 618                         atomic64_read(&adev->gart_pin_size);
 619                 mem.gtt.heap_usage =
 620                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 621                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 622
 623                 return copy_to_user(out, &mem,
 624                                     min((size_t)size, sizeof(mem)))
 625                                     ? -EFAULT : 0;
 626         }
 627         case AMDGPU_INFO_READ_MMR_REG: {
 628                 unsigned n, alloc_size;
 629                 uint32_t *regs;
 630                 unsigned se_num = (info->read_mmr_reg.instance >>
 631                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 632                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 633                 unsigned sh_num = (info->read_mmr_reg.instance >>
 634                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 635                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 636
 637                 /* set full masks if the userspace set all bits
 638                  * in the bitfields */
 639                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 640                         se_num = 0xffffffff;
 641                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 642                         sh_num = 0xffffffff;
 643
 644                 if (info->read_mmr_reg.count > 128)
 645                         return -EINVAL;
 646
 647                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 648                 if (!regs)
 649                         return -ENOMEM;
 650                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 651
 652                 for (i = 0; i < info->read_mmr_reg.count; i++)
 653                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 654                                                       info->read_mmr_reg.dword_offset + i,
 655                                                       &regs[i])) {
 656                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 657                                               info->read_mmr_reg.dword_offset + i);
 658                                 kfree(regs);
 659                                 return -EFAULT;
 660                         }
 661                 n = copy_to_user(out, regs, min(size, alloc_size));
 662                 kfree(regs);
 663                 return n ? -EFAULT : 0;
 664         }
 665         case AMDGPU_INFO_DEV_INFO: {
 666                 struct drm_amdgpu_info_device dev_info = {};
 667                 uint64_t vm_size;
 668
 669                 dev_info.device_id = dev->pdev->device;
 670                 dev_info.chip_rev = adev->rev_id;
 671                 dev_info.external_rev = adev->external_rev_id;
 672                 dev_info.pci_rev = dev->pdev->revision;
 673                 dev_info.family = adev->family;
 674                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 675                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 676                 /* return all clocks in KHz */
 677                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 678                 if (adev->pm.dpm_enabled) {
 679                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 680                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 681                 } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
 682                            adev->virt.ops->get_pp_clk) {
 683                         dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev, false) * 10;
 684                         dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev, false) * 10;
 685                 } else {
 686                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 687                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 688                 }
 689                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 690                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 691                         adev->gfx.config.max_shader_engines;
 692                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 693                 dev_info._pad = 0;
 694                 dev_info.ids_flags = 0;
 695                 if (adev->flags & AMD_IS_APU)
 696                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 697                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 698                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 699
 700                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 701                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 702
 703                 /* Older VCE FW versions are buggy and can handle only 40bits */
 704                 if (adev->vce.fw_version &&
 705                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 706                         vm_size = min(vm_size, 1ULL << 40);
 707
 708                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 709                 dev_info.virtual_address_max =
 710                         min(vm_size, AMDGPU_GMC_HOLE_START);
 711
 712                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 713                         dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
 714                         dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 715                 }
 716                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 717                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 718                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 719                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 720                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 721                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 722                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 723                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 724                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 725                        sizeof(adev->gfx.cu_info.bitmap));
 726                 dev_info.vram_type = adev->gmc.vram_type;
 727                 dev_info.vram_bit_width = adev->gmc.vram_width;
 728                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 729                 dev_info.gc_double_offchip_lds_buf =
 730                         adev->gfx.config.double_offchip_lds_buf;
 731
 732                 if (amdgpu_ngg) {
 733                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 734                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 735                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 736                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 737                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 738                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 739                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 740                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 741                 }
 742                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 743                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 744                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 745                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 746                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 747                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 748                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 749
 750                 if (adev->family >= AMDGPU_FAMILY_NV)
 751                         dev_info.pa_sc_tile_steering_override =
 752                                 adev->gfx.config.pa_sc_tile_steering_override;
 753
 754                 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 755
 756                 return copy_to_user(out, &dev_info,
 757                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 758         }
 759         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 760                 unsigned i;
 761                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 762                 struct amd_vce_state *vce_state;
 763
 764                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 765                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 766                         if (vce_state) {
 767                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 768                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 769                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 770                                 vce_clk_table.num_valid_entries++;
 771                         }
 772                 }
 773
 774                 return copy_to_user(out, &vce_clk_table,
 775                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 776         }
 777         case AMDGPU_INFO_VBIOS: {
 778                 uint32_t bios_size = adev->bios_size;
 779
 780                 switch (info->vbios_info.type) {
 781                 case AMDGPU_INFO_VBIOS_SIZE:
 782                         return copy_to_user(out, &bios_size,
 783                                         min((size_t)size, sizeof(bios_size)))
 784                                         ? -EFAULT : 0;
 785                 case AMDGPU_INFO_VBIOS_IMAGE: {
 786                         uint8_t *bios;
 787                         uint32_t bios_offset = info->vbios_info.offset;
 788
 789                         if (bios_offset >= bios_size)
 790                                 return -EINVAL;
 791
 792                         bios = adev->bios + bios_offset;
 793                         return copy_to_user(out, bios,
 794                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 795                                         ? -EFAULT : 0;
 796                 }
 797                 default:
 798                         DRM_DEBUG_KMS("Invalid request %d\n",
 799                                         info->vbios_info.type);
 800                         return -EINVAL;
 801                 }
 802         }
 803         case AMDGPU_INFO_NUM_HANDLES: {
 804                 struct drm_amdgpu_info_num_handles handle;
 805
 806                 switch (info->query_hw_ip.type) {
 807                 case AMDGPU_HW_IP_UVD:
 808                         /* Starting Polaris, we support unlimited UVD handles */
 809                         if (adev->asic_type < CHIP_POLARIS10) {
 810                                 handle.uvd_max_handles = adev->uvd.max_handles;
 811                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 812
 813                                 return copy_to_user(out, &handle,
 814                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 815                         } else {
 816                                 return -ENODATA;
 817                         }
 818
 819                         break;
 820                 default:
 821                         return -EINVAL;
 822                 }
 823         }
 824         case AMDGPU_INFO_SENSOR: {
 825                 if (!adev->pm.dpm_enabled)
 826                         return -ENOENT;
 827
 828                 switch (info->sensor_info.type) {
 829                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 830                         /* get sclk in Mhz */
 831                         if (amdgpu_dpm_read_sensor(adev,
 832                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 833                                                    (void *)&ui32, &ui32_size)) {
 834                                 return -EINVAL;
 835                         }
 836                         ui32 /= 100;
 837                         break;
 838                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 839                         /* get mclk in Mhz */
 840                         if (amdgpu_dpm_read_sensor(adev,
 841                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 842                                                    (void *)&ui32, &ui32_size)) {
 843                                 return -EINVAL;
 844                         }
 845                         ui32 /= 100;
 846                         break;
 847                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 848                         /* get temperature in millidegrees C */
 849                         if (amdgpu_dpm_read_sensor(adev,
 850                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 851                                                    (void *)&ui32, &ui32_size)) {
 852                                 return -EINVAL;
 853                         }
 854                         break;
 855                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 856                         /* get GPU load */
 857                         if (amdgpu_dpm_read_sensor(adev,
 858                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 859                                                    (void *)&ui32, &ui32_size)) {
 860                                 return -EINVAL;
 861                         }
 862                         break;
 863                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 864                         /* get average GPU power */
 865                         if (amdgpu_dpm_read_sensor(adev,
 866                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 867                                                    (void *)&ui32, &ui32_size)) {
 868                                 return -EINVAL;
 869                         }
 870                         ui32 >>= 8;
 871                         break;
 872                 case AMDGPU_INFO_SENSOR_VDDNB:
 873                         /* get VDDNB in millivolts */
 874                         if (amdgpu_dpm_read_sensor(adev,
 875                                                    AMDGPU_PP_SENSOR_VDDNB,
 876                                                    (void *)&ui32, &ui32_size)) {
 877                                 return -EINVAL;
 878                         }
 879                         break;
 880                 case AMDGPU_INFO_SENSOR_VDDGFX:
 881                         /* get VDDGFX in millivolts */
 882                         if (amdgpu_dpm_read_sensor(adev,
 883                                                    AMDGPU_PP_SENSOR_VDDGFX,
 884                                                    (void *)&ui32, &ui32_size)) {
 885                                 return -EINVAL;
 886                         }
 887                         break;
 888                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 889                         /* get stable pstate sclk in Mhz */
 890                         if (amdgpu_dpm_read_sensor(adev,
 891                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 892                                                    (void *)&ui32, &ui32_size)) {
 893                                 return -EINVAL;
 894                         }
 895                         ui32 /= 100;
 896                         break;
 897                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 898                         /* get stable pstate mclk in Mhz */
 899                         if (amdgpu_dpm_read_sensor(adev,
 900                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 901                                                    (void *)&ui32, &ui32_size)) {
 902                                 return -EINVAL;
 903                         }
 904                         ui32 /= 100;
 905                         break;
 906                 default:
 907                         DRM_DEBUG_KMS("Invalid request %d\n",
 908                                       info->sensor_info.type);
 909                         return -EINVAL;
 910                 }
 911                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 912         }
 913         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 914                 ui32 = atomic_read(&adev->vram_lost_counter);
 915                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 916         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 917                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 918                 uint64_t ras_mask;
 919
 920                 if (!ras)
 921                         return -EINVAL;
 922                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 923
 924                 return copy_to_user(out, &ras_mask,
 925                                 min_t(u64, size, sizeof(ras_mask))) ?
 926                         -EFAULT : 0;
 927         }
 928         default:
 929                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 930                 return -EINVAL;
 931         }
 932         return 0;
 933 }
 934
 935
 936 /*
 937  * Outdated mess for old drm with Xorg being in charge (void function now).
 938  */
 939 /**
 940  * amdgpu_driver_lastclose_kms - drm callback for last close
 941  *
 942  * @dev: drm dev pointer
 943  *
 944  * Switch vga_switcheroo state after last close (all asics).
 945  */
 946 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 947 {
 948         drm_fb_helper_lastclose(dev);
 949         vga_switcheroo_process_delayed_switch();
 950 }
 951
 952 /**
 953  * amdgpu_driver_open_kms - drm callback for open
 954  *
 955  * @dev: drm dev pointer
 956  * @file_priv: drm file
 957  *
 958  * On device open, init vm on cayman+ (all asics).
 959  * Returns 0 on success, error on failure.
 960  */
 961 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 962 {
 963         struct amdgpu_device *adev = dev->dev_private;
 964         struct amdgpu_fpriv *fpriv;
 965         int r, pasid;
 966
 967         /* Ensure IB tests are run on ring */
 968         flush_delayed_work(&adev->delayed_init_work);
 969
 970         file_priv->driver_priv = NULL;
 971
 972         r = pm_runtime_get_sync(dev->dev);
 973         if (r < 0)
 974                 return r;
 975
 976         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 977         if (unlikely(!fpriv)) {
 978                 r = -ENOMEM;
 979                 goto out_suspend;
 980         }
 981
 982         pasid = amdgpu_pasid_alloc(16);
 983         if (pasid < 0) {
 984                 dev_warn(adev->dev, "No more PASIDs available!");
 985                 pasid = 0;
 986         }
 987         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
 988         if (r)
 989                 goto error_pasid;
 990
 991         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 992         if (!fpriv->prt_va) {
 993                 r = -ENOMEM;
 994                 goto error_vm;
 995         }
 996
 997         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 998                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
 999
1000                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1001                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1002                 if (r)
1003                         goto error_vm;
1004         }
1005
1006         mutex_init(&fpriv->bo_list_lock);
1007         idr_init(&fpriv->bo_list_handles);
1008
1009         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1010
1011         file_priv->driver_priv = fpriv;
1012         goto out_suspend;
1013
1014 error_vm:
1015         amdgpu_vm_fini(adev, &fpriv->vm);
1016
1017 error_pasid:
1018         if (pasid)
1019                 amdgpu_pasid_free(pasid);
1020
1021         kfree(fpriv);
1022
1023 out_suspend:
1024         pm_runtime_mark_last_busy(dev->dev);
1025         pm_runtime_put_autosuspend(dev->dev);
1026
1027         return r;
1028 }
1029
1030 /**
1031  * amdgpu_driver_postclose_kms - drm callback for post close
1032  *
1033  * @dev: drm dev pointer
1034  * @file_priv: drm file
1035  *
1036  * On device post close, tear down vm on cayman+ (all asics).
1037  */
1038 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1039                                  struct drm_file *file_priv)
1040 {
1041         struct amdgpu_device *adev = dev->dev_private;
1042         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1043         struct amdgpu_bo_list *list;
1044         struct amdgpu_bo *pd;
1045         unsigned int pasid;
1046         int handle;
1047
1048         if (!fpriv)
1049                 return;
1050
1051         pm_runtime_get_sync(dev->dev);
1052
1053         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1054                 amdgpu_uvd_free_handles(adev, file_priv);
1055         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1056                 amdgpu_vce_free_handles(adev, file_priv);
1057
1058         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1059
1060         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1061                 /* TODO: how to handle reserve failure */
1062                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1063                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1064                 fpriv->csa_va = NULL;
1065                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1066         }
1067
1068         pasid = fpriv->vm.pasid;
1069         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1070
1071         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1072         amdgpu_vm_fini(adev, &fpriv->vm);
1073
1074         if (pasid)
1075                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1076         amdgpu_bo_unref(&pd);
1077
1078         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1079                 amdgpu_bo_list_put(list);
1080
1081         idr_destroy(&fpriv->bo_list_handles);
1082         mutex_destroy(&fpriv->bo_list_lock);
1083
1084         kfree(fpriv);
1085         file_priv->driver_priv = NULL;
1086
1087         pm_runtime_mark_last_busy(dev->dev);
1088         pm_runtime_put_autosuspend(dev->dev);
1089 }
1090
1091 /*
1092  * VBlank related functions.
1093  */
1094 /**
1095  * amdgpu_get_vblank_counter_kms - get frame count
1096  *
1097  * @dev: drm dev pointer
1098  * @pipe: crtc to get the frame count from
1099  *
1100  * Gets the frame count on the requested crtc (all asics).
1101  * Returns frame count on success, -EINVAL on failure.
1102  */
1103 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
1104 {
1105         struct amdgpu_device *adev = dev->dev_private;
1106         int vpos, hpos, stat;
1107         u32 count;
1108
1109         if (pipe >= adev->mode_info.num_crtc) {
1110                 DRM_ERROR("Invalid crtc %u\n", pipe);
1111                 return -EINVAL;
1112         }
1113
1114         /* The hw increments its frame counter at start of vsync, not at start
1115          * of vblank, as is required by DRM core vblank counter handling.
1116          * Cook the hw count here to make it appear to the caller as if it
1117          * incremented at start of vblank. We measure distance to start of
1118          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1119          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1120          * result by 1 to give the proper appearance to caller.
1121          */
1122         if (adev->mode_info.crtcs[pipe]) {
1123                 /* Repeat readout if needed to provide stable result if
1124                  * we cross start of vsync during the queries.
1125                  */
1126                 do {
1127                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1128                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1129                          * vpos as distance to start of vblank, instead of
1130                          * regular vertical scanout pos.
1131                          */
1132                         stat = amdgpu_display_get_crtc_scanoutpos(
1133                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1134                                 &vpos, &hpos, NULL, NULL,
1135                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1136                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1137
1138                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1139                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1140                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1141                 } else {
1142                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1143                                       pipe, vpos);
1144
1145                         /* Bump counter if we are at >= leading edge of vblank,
1146                          * but before vsync where vpos would turn negative and
1147                          * the hw counter really increments.
1148                          */
1149                         if (vpos >= 0)
1150                                 count++;
1151                 }
1152         } else {
1153                 /* Fallback to use value as is. */
1154                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1155                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1156         }
1157
1158         return count;
1159 }
1160
1161 /**
1162  * amdgpu_enable_vblank_kms - enable vblank interrupt
1163  *
1164  * @dev: drm dev pointer
1165  * @pipe: crtc to enable vblank interrupt for
1166  *
1167  * Enable the interrupt on the requested crtc (all asics).
1168  * Returns 0 on success, -EINVAL on failure.
1169  */
1170 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1171 {
1172         struct amdgpu_device *adev = dev->dev_private;
1173         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1174
1175         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1176 }
1177
1178 /**
1179  * amdgpu_disable_vblank_kms - disable vblank interrupt
1180  *
1181  * @dev: drm dev pointer
1182  * @pipe: crtc to disable vblank interrupt for
1183  *
1184  * Disable the interrupt on the requested crtc (all asics).
1185  */
1186 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1187 {
1188         struct amdgpu_device *adev = dev->dev_private;
1189         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1190
1191         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1192 }
1193
1194 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1195         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1196         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1197         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1198         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1199         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1200         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1201         /* KMS */
1202         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1203         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1204         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1205         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1206         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1207         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1208         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1209         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1210         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1211         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1212 };
1213 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1214
1215 /*
1216  * Debugfs info
1217  */
1218 #if defined(CONFIG_DEBUG_FS)
1219
1220 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1221 {
1222         struct drm_info_node *node = (struct drm_info_node *) m->private;
1223         struct drm_device *dev = node->minor->dev;
1224         struct amdgpu_device *adev = dev->dev_private;
1225         struct drm_amdgpu_info_firmware fw_info;
1226         struct drm_amdgpu_query_fw query_fw;
1227         struct atom_context *ctx = adev->mode_info.atom_context;
1228         int ret, i;
1229
1230         /* VCE */
1231         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1232         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1233         if (ret)
1234                 return ret;
1235         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1236                    fw_info.feature, fw_info.ver);
1237
1238         /* UVD */
1239         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1240         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1241         if (ret)
1242                 return ret;
1243         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1244                    fw_info.feature, fw_info.ver);
1245
1246         /* GMC */
1247         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1248         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1249         if (ret)
1250                 return ret;
1251         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1252                    fw_info.feature, fw_info.ver);
1253
1254         /* ME */
1255         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1256         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1257         if (ret)
1258                 return ret;
1259         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1260                    fw_info.feature, fw_info.ver);
1261
1262         /* PFP */
1263         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1264         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1265         if (ret)
1266                 return ret;
1267         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1268                    fw_info.feature, fw_info.ver);
1269
1270         /* CE */
1271         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1272         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1273         if (ret)
1274                 return ret;
1275         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1276                    fw_info.feature, fw_info.ver);
1277
1278         /* RLC */
1279         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1280         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1281         if (ret)
1282                 return ret;
1283         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1284                    fw_info.feature, fw_info.ver);
1285
1286         /* RLC SAVE RESTORE LIST CNTL */
1287         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1288         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1289         if (ret)
1290                 return ret;
1291         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1292                    fw_info.feature, fw_info.ver);
1293
1294         /* RLC SAVE RESTORE LIST GPM MEM */
1295         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1296         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1297         if (ret)
1298                 return ret;
1299         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1300                    fw_info.feature, fw_info.ver);
1301
1302         /* RLC SAVE RESTORE LIST SRM MEM */
1303         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1304         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1305         if (ret)
1306                 return ret;
1307         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1308                    fw_info.feature, fw_info.ver);
1309
1310         /* MEC */
1311         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1312         query_fw.index = 0;
1313         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1314         if (ret)
1315                 return ret;
1316         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1317                    fw_info.feature, fw_info.ver);
1318
1319         /* MEC2 */
1320         if (adev->asic_type == CHIP_KAVERI ||
1321             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1322                 query_fw.index = 1;
1323                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1324                 if (ret)
1325                         return ret;
1326                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1327                            fw_info.feature, fw_info.ver);
1328         }
1329
1330         /* PSP SOS */
1331         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1332         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1333         if (ret)
1334                 return ret;
1335         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1336                    fw_info.feature, fw_info.ver);
1337
1338
1339         /* PSP ASD */
1340         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1341         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1342         if (ret)
1343                 return ret;
1344         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1345                    fw_info.feature, fw_info.ver);
1346
1347         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1348         for (i = 0; i < 2; i++) {
1349                 query_fw.index = i;
1350                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1351                 if (ret)
1352                         continue;
1353                 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n",
1354                                 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver);
1355         }
1356
1357         /* SMC */
1358         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1359         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1360         if (ret)
1361                 return ret;
1362         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1363                    fw_info.feature, fw_info.ver);
1364
1365         /* SDMA */
1366         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1367         for (i = 0; i < adev->sdma.num_instances; i++) {
1368                 query_fw.index = i;
1369                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1370                 if (ret)
1371                         return ret;
1372                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1373                            i, fw_info.feature, fw_info.ver);
1374         }
1375
1376         /* VCN */
1377         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1378         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1379         if (ret)
1380                 return ret;
1381         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1382                    fw_info.feature, fw_info.ver);
1383
1384         /* DMCU */
1385         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1386         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1387         if (ret)
1388                 return ret;
1389         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1390                    fw_info.feature, fw_info.ver);
1391
1392
1393         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1394
1395         return 0;
1396 }
1397
1398 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1399         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1400 };
1401 #endif
1402
1403 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1404 {
1405 #if defined(CONFIG_DEBUG_FS)
1406         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1407                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1408 #else
1409         return 0;
1410 #endif
1411 }