drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_gpu_instance *gpu_instance;
  49         int i;
  50
  51         mutex_lock(&mgpu_info.mutex);
  52
  53         for (i = 0; i < mgpu_info.num_gpu; i++) {
  54                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  55                 if (gpu_instance->adev == adev) {
  56                         mgpu_info.gpu_ins[i] =
  57                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  58                         mgpu_info.num_gpu--;
  59                         if (adev->flags & AMD_IS_APU)
  60                                 mgpu_info.num_apu--;
  61                         else
  62                                 mgpu_info.num_dgpu--;
  63                         break;
  64                 }
  65         }
  66
  67         mutex_unlock(&mgpu_info.mutex);
  68 }
  69
  70 /**
  71  * amdgpu_driver_unload_kms - Main unload function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  *
  75  * This is the main unload function for KMS (all asics).
  76  * Returns 0 on success.
  77  */
  78 void amdgpu_driver_unload_kms(struct drm_device *dev)
  79 {
  80         struct amdgpu_device *adev = drm_to_adev(dev);
  81
  82         if (adev == NULL)
  83                 return;
  84
  85         amdgpu_unregister_gpu_instance(adev);
  86
  87         if (adev->rmmio == NULL)
  88                 return;
  89
  90         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  91                 DRM_WARN("smart shift update failed\n");
  92
  93         amdgpu_acpi_fini(adev);
  94         amdgpu_device_fini_hw(adev);
  95 }
  96
  97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
  98 {
  99         struct amdgpu_gpu_instance *gpu_instance;
 100
 101         mutex_lock(&mgpu_info.mutex);
 102
 103         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 104                 DRM_ERROR("Cannot register more gpu instance\n");
 105                 mutex_unlock(&mgpu_info.mutex);
 106                 return;
 107         }
 108
 109         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 110         gpu_instance->adev = adev;
 111         gpu_instance->mgpu_fan_enabled = 0;
 112
 113         mgpu_info.num_gpu++;
 114         if (adev->flags & AMD_IS_APU)
 115                 mgpu_info.num_apu++;
 116         else
 117                 mgpu_info.num_dgpu++;
 118
 119         mutex_unlock(&mgpu_info.mutex);
 120 }
 121
 122 /**
 123  * amdgpu_driver_load_kms - Main load function for KMS.
 124  *
 125  * @adev: pointer to struct amdgpu_device
 126  * @flags: device flags
 127  *
 128  * This is the main load function for KMS (all asics).
 129  * Returns 0 on success, error on failure.
 130  */
 131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 132 {
 133         struct drm_device *dev;
 134         int r, acpi_status;
 135
 136         dev = adev_to_drm(adev);
 137
 138         /* amdgpu_device_init should report only fatal error
 139          * like memory allocation failure or iomapping failure,
 140          * or memory manager initialization failure, it must
 141          * properly initialize the GPU MC controller and permit
 142          * VRAM allocation
 143          */
 144         r = amdgpu_device_init(adev, flags);
 145         if (r) {
 146                 dev_err(dev->dev, "Fatal error during GPU init\n");
 147                 goto out;
 148         }
 149
 150         if (amdgpu_device_supports_px(dev) &&
 151             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
 152                 adev->runpm = true;
 153                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 154         } else if (amdgpu_device_supports_boco(dev) &&
 155                    (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 156                 adev->runpm = true;
 157                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 158         } else if (amdgpu_device_supports_baco(dev) &&
 159                    (amdgpu_runtime_pm != 0)) {
 160                 switch (adev->asic_type) {
 161                 case CHIP_VEGA20:
 162                 case CHIP_ARCTURUS:
 163                         /* enable runpm if runpm=1 */
 164                         if (amdgpu_runtime_pm > 0)
 165                                 adev->runpm = true;
 166                         break;
 167                 case CHIP_VEGA10:
 168                         /* turn runpm on if noretry=0 */
 169                         if (!adev->gmc.noretry)
 170                                 adev->runpm = true;
 171                         break;
 172                 default:
 173                         /* enable runpm on CI+ */
 174                         adev->runpm = true;
 175                         break;
 176                 }
 177                 /* XXX: disable runtime pm if we are the primary adapter
 178                  * to avoid displays being re-enabled after DPMS.
 179                  * This needs to be sorted out and fixed properly.
 180                  */
 181                 if (adev->is_fw_fb)
 182                         adev->runpm = false;
 183                 if (adev->runpm)
 184                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 185         }
 186
 187         /* Call ACPI methods: require modeset init
 188          * but failure is not fatal
 189          */
 190
 191         acpi_status = amdgpu_acpi_init(adev);
 192         if (acpi_status)
 193                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 194
 195         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 196                 DRM_WARN("smart shift update failed\n");
 197
 198 out:
 199         if (r)
 200                 amdgpu_driver_unload_kms(dev);
 201
 202         return r;
 203 }
 204
 205 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 206                                 struct drm_amdgpu_query_fw *query_fw,
 207                                 struct amdgpu_device *adev)
 208 {
 209         switch (query_fw->fw_type) {
 210         case AMDGPU_INFO_FW_VCE:
 211                 fw_info->ver = adev->vce.fw_version;
 212                 fw_info->feature = adev->vce.fb_version;
 213                 break;
 214         case AMDGPU_INFO_FW_UVD:
 215                 fw_info->ver = adev->uvd.fw_version;
 216                 fw_info->feature = 0;
 217                 break;
 218         case AMDGPU_INFO_FW_VCN:
 219                 fw_info->ver = adev->vcn.fw_version;
 220                 fw_info->feature = 0;
 221                 break;
 222         case AMDGPU_INFO_FW_GMC:
 223                 fw_info->ver = adev->gmc.fw_version;
 224                 fw_info->feature = 0;
 225                 break;
 226         case AMDGPU_INFO_FW_GFX_ME:
 227                 fw_info->ver = adev->gfx.me_fw_version;
 228                 fw_info->feature = adev->gfx.me_feature_version;
 229                 break;
 230         case AMDGPU_INFO_FW_GFX_PFP:
 231                 fw_info->ver = adev->gfx.pfp_fw_version;
 232                 fw_info->feature = adev->gfx.pfp_feature_version;
 233                 break;
 234         case AMDGPU_INFO_FW_GFX_CE:
 235                 fw_info->ver = adev->gfx.ce_fw_version;
 236                 fw_info->feature = adev->gfx.ce_feature_version;
 237                 break;
 238         case AMDGPU_INFO_FW_GFX_RLC:
 239                 fw_info->ver = adev->gfx.rlc_fw_version;
 240                 fw_info->feature = adev->gfx.rlc_feature_version;
 241                 break;
 242         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 243                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 244                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 245                 break;
 246         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 247                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 248                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 249                 break;
 250         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 251                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 252                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 253                 break;
 254         case AMDGPU_INFO_FW_GFX_MEC:
 255                 if (query_fw->index == 0) {
 256                         fw_info->ver = adev->gfx.mec_fw_version;
 257                         fw_info->feature = adev->gfx.mec_feature_version;
 258                 } else if (query_fw->index == 1) {
 259                         fw_info->ver = adev->gfx.mec2_fw_version;
 260                         fw_info->feature = adev->gfx.mec2_feature_version;
 261                 } else
 262                         return -EINVAL;
 263                 break;
 264         case AMDGPU_INFO_FW_SMC:
 265                 fw_info->ver = adev->pm.fw_version;
 266                 fw_info->feature = 0;
 267                 break;
 268         case AMDGPU_INFO_FW_TA:
 269                 switch (query_fw->index) {
 270                 case TA_FW_TYPE_PSP_XGMI:
 271                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 272                         fw_info->feature = adev->psp.xgmi_context.context
 273                                                    .bin_desc.feature_version;
 274                         break;
 275                 case TA_FW_TYPE_PSP_RAS:
 276                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 277                         fw_info->feature = adev->psp.ras_context.context
 278                                                    .bin_desc.feature_version;
 279                         break;
 280                 case TA_FW_TYPE_PSP_HDCP:
 281                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 282                         fw_info->feature = adev->psp.hdcp_context.context
 283                                                    .bin_desc.feature_version;
 284                         break;
 285                 case TA_FW_TYPE_PSP_DTM:
 286                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 287                         fw_info->feature = adev->psp.dtm_context.context
 288                                                    .bin_desc.feature_version;
 289                         break;
 290                 case TA_FW_TYPE_PSP_RAP:
 291                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 292                         fw_info->feature = adev->psp.rap_context.context
 293                                                    .bin_desc.feature_version;
 294                         break;
 295                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 296                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 297                         fw_info->feature =
 298                                 adev->psp.securedisplay_context.context.bin_desc
 299                                         .feature_version;
 300                         break;
 301                 default:
 302                         return -EINVAL;
 303                 }
 304                 break;
 305         case AMDGPU_INFO_FW_SDMA:
 306                 if (query_fw->index >= adev->sdma.num_instances)
 307                         return -EINVAL;
 308                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 309                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 310                 break;
 311         case AMDGPU_INFO_FW_SOS:
 312                 fw_info->ver = adev->psp.sos.fw_version;
 313                 fw_info->feature = adev->psp.sos.feature_version;
 314                 break;
 315         case AMDGPU_INFO_FW_ASD:
 316                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 317                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 318                 break;
 319         case AMDGPU_INFO_FW_DMCU:
 320                 fw_info->ver = adev->dm.dmcu_fw_version;
 321                 fw_info->feature = 0;
 322                 break;
 323         case AMDGPU_INFO_FW_DMCUB:
 324                 fw_info->ver = adev->dm.dmcub_fw_version;
 325                 fw_info->feature = 0;
 326                 break;
 327         case AMDGPU_INFO_FW_TOC:
 328                 fw_info->ver = adev->psp.toc.fw_version;
 329                 fw_info->feature = adev->psp.toc.feature_version;
 330                 break;
 331         case AMDGPU_INFO_FW_CAP:
 332                 fw_info->ver = adev->psp.cap_fw_version;
 333                 fw_info->feature = adev->psp.cap_feature_version;
 334                 break;
 335         default:
 336                 return -EINVAL;
 337         }
 338         return 0;
 339 }
 340
 341 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 342                              struct drm_amdgpu_info *info,
 343                              struct drm_amdgpu_info_hw_ip *result)
 344 {
 345         uint32_t ib_start_alignment = 0;
 346         uint32_t ib_size_alignment = 0;
 347         enum amd_ip_block_type type;
 348         unsigned int num_rings = 0;
 349         unsigned int i, j;
 350
 351         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 352                 return -EINVAL;
 353
 354         switch (info->query_hw_ip.type) {
 355         case AMDGPU_HW_IP_GFX:
 356                 type = AMD_IP_BLOCK_TYPE_GFX;
 357                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 358                         if (adev->gfx.gfx_ring[i].sched.ready)
 359                                 ++num_rings;
 360                 ib_start_alignment = 32;
 361                 ib_size_alignment = 32;
 362                 break;
 363         case AMDGPU_HW_IP_COMPUTE:
 364                 type = AMD_IP_BLOCK_TYPE_GFX;
 365                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 366                         if (adev->gfx.compute_ring[i].sched.ready)
 367                                 ++num_rings;
 368                 ib_start_alignment = 32;
 369                 ib_size_alignment = 32;
 370                 break;
 371         case AMDGPU_HW_IP_DMA:
 372                 type = AMD_IP_BLOCK_TYPE_SDMA;
 373                 for (i = 0; i < adev->sdma.num_instances; i++)
 374                         if (adev->sdma.instance[i].ring.sched.ready)
 375                                 ++num_rings;
 376                 ib_start_alignment = 256;
 377                 ib_size_alignment = 4;
 378                 break;
 379         case AMDGPU_HW_IP_UVD:
 380                 type = AMD_IP_BLOCK_TYPE_UVD;
 381                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 382                         if (adev->uvd.harvest_config & (1 << i))
 383                                 continue;
 384
 385                         if (adev->uvd.inst[i].ring.sched.ready)
 386                                 ++num_rings;
 387                 }
 388                 ib_start_alignment = 64;
 389                 ib_size_alignment = 64;
 390                 break;
 391         case AMDGPU_HW_IP_VCE:
 392                 type = AMD_IP_BLOCK_TYPE_VCE;
 393                 for (i = 0; i < adev->vce.num_rings; i++)
 394                         if (adev->vce.ring[i].sched.ready)
 395                                 ++num_rings;
 396                 ib_start_alignment = 4;
 397                 ib_size_alignment = 1;
 398                 break;
 399         case AMDGPU_HW_IP_UVD_ENC:
 400                 type = AMD_IP_BLOCK_TYPE_UVD;
 401                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 402                         if (adev->uvd.harvest_config & (1 << i))
 403                                 continue;
 404
 405                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 406                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 407                                         ++num_rings;
 408                 }
 409                 ib_start_alignment = 64;
 410                 ib_size_alignment = 64;
 411                 break;
 412         case AMDGPU_HW_IP_VCN_DEC:
 413                 type = AMD_IP_BLOCK_TYPE_VCN;
 414                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 415                         if (adev->uvd.harvest_config & (1 << i))
 416                                 continue;
 417
 418                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 419                                 ++num_rings;
 420                 }
 421                 ib_start_alignment = 16;
 422                 ib_size_alignment = 16;
 423                 break;
 424         case AMDGPU_HW_IP_VCN_ENC:
 425                 type = AMD_IP_BLOCK_TYPE_VCN;
 426                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 427                         if (adev->uvd.harvest_config & (1 << i))
 428                                 continue;
 429
 430                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 431                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 432                                         ++num_rings;
 433                 }
 434                 ib_start_alignment = 64;
 435                 ib_size_alignment = 1;
 436                 break;
 437         case AMDGPU_HW_IP_VCN_JPEG:
 438                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 439                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 440
 441                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 442                         if (adev->jpeg.harvest_config & (1 << i))
 443                                 continue;
 444
 445                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 446                                 ++num_rings;
 447                 }
 448                 ib_start_alignment = 16;
 449                 ib_size_alignment = 16;
 450                 break;
 451         default:
 452                 return -EINVAL;
 453         }
 454
 455         for (i = 0; i < adev->num_ip_blocks; i++)
 456                 if (adev->ip_blocks[i].version->type == type &&
 457                     adev->ip_blocks[i].status.valid)
 458                         break;
 459
 460         if (i == adev->num_ip_blocks)
 461                 return 0;
 462
 463         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 464                         num_rings);
 465
 466         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 467         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 468         result->capabilities_flags = 0;
 469         result->available_rings = (1 << num_rings) - 1;
 470         result->ib_start_alignment = ib_start_alignment;
 471         result->ib_size_alignment = ib_size_alignment;
 472         return 0;
 473 }
 474
 475 /*
 476  * Userspace get information ioctl
 477  */
 478 /**
 479  * amdgpu_info_ioctl - answer a device specific request.
 480  *
 481  * @dev: drm device pointer
 482  * @data: request object
 483  * @filp: drm filp
 484  *
 485  * This function is used to pass device specific parameters to the userspace
 486  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 487  * etc. (all asics).
 488  * Returns 0 on success, -EINVAL on failure.
 489  */
 490 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 491 {
 492         struct amdgpu_device *adev = drm_to_adev(dev);
 493         struct drm_amdgpu_info *info = data;
 494         struct amdgpu_mode_info *minfo = &adev->mode_info;
 495         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 496         uint32_t size = info->return_size;
 497         struct drm_crtc *crtc;
 498         uint32_t ui32 = 0;
 499         uint64_t ui64 = 0;
 500         int i, found;
 501         int ui32_size = sizeof(ui32);
 502
 503         if (!info->return_size || !info->return_pointer)
 504                 return -EINVAL;
 505
 506         switch (info->query) {
 507         case AMDGPU_INFO_ACCEL_WORKING:
 508                 ui32 = adev->accel_working;
 509                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 510         case AMDGPU_INFO_CRTC_FROM_ID:
 511                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 512                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 513                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 514                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 515                                 ui32 = amdgpu_crtc->crtc_id;
 516                                 found = 1;
 517                                 break;
 518                         }
 519                 }
 520                 if (!found) {
 521                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 522                         return -EINVAL;
 523                 }
 524                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 525         case AMDGPU_INFO_HW_IP_INFO: {
 526                 struct drm_amdgpu_info_hw_ip ip = {};
 527                 int ret;
 528
 529                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 530                 if (ret)
 531                         return ret;
 532
 533                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 534                 return ret ? -EFAULT : 0;
 535         }
 536         case AMDGPU_INFO_HW_IP_COUNT: {
 537                 enum amd_ip_block_type type;
 538                 uint32_t count = 0;
 539
 540                 switch (info->query_hw_ip.type) {
 541                 case AMDGPU_HW_IP_GFX:
 542                         type = AMD_IP_BLOCK_TYPE_GFX;
 543                         break;
 544                 case AMDGPU_HW_IP_COMPUTE:
 545                         type = AMD_IP_BLOCK_TYPE_GFX;
 546                         break;
 547                 case AMDGPU_HW_IP_DMA:
 548                         type = AMD_IP_BLOCK_TYPE_SDMA;
 549                         break;
 550                 case AMDGPU_HW_IP_UVD:
 551                         type = AMD_IP_BLOCK_TYPE_UVD;
 552                         break;
 553                 case AMDGPU_HW_IP_VCE:
 554                         type = AMD_IP_BLOCK_TYPE_VCE;
 555                         break;
 556                 case AMDGPU_HW_IP_UVD_ENC:
 557                         type = AMD_IP_BLOCK_TYPE_UVD;
 558                         break;
 559                 case AMDGPU_HW_IP_VCN_DEC:
 560                 case AMDGPU_HW_IP_VCN_ENC:
 561                         type = AMD_IP_BLOCK_TYPE_VCN;
 562                         break;
 563                 case AMDGPU_HW_IP_VCN_JPEG:
 564                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 565                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 566                         break;
 567                 default:
 568                         return -EINVAL;
 569                 }
 570
 571                 for (i = 0; i < adev->num_ip_blocks; i++)
 572                         if (adev->ip_blocks[i].version->type == type &&
 573                             adev->ip_blocks[i].status.valid &&
 574                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 575                                 count++;
 576
 577                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 578         }
 579         case AMDGPU_INFO_TIMESTAMP:
 580                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 581                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 582         case AMDGPU_INFO_FW_VERSION: {
 583                 struct drm_amdgpu_info_firmware fw_info;
 584                 int ret;
 585
 586                 /* We only support one instance of each IP block right now. */
 587                 if (info->query_fw.ip_instance != 0)
 588                         return -EINVAL;
 589
 590                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 591                 if (ret)
 592                         return ret;
 593
 594                 return copy_to_user(out, &fw_info,
 595                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 596         }
 597         case AMDGPU_INFO_NUM_BYTES_MOVED:
 598                 ui64 = atomic64_read(&adev->num_bytes_moved);
 599                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 600         case AMDGPU_INFO_NUM_EVICTIONS:
 601                 ui64 = atomic64_read(&adev->num_evictions);
 602                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 603         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 604                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 605                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 606         case AMDGPU_INFO_VRAM_USAGE:
 607                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 608                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 609         case AMDGPU_INFO_VIS_VRAM_USAGE:
 610                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 611                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 612         case AMDGPU_INFO_GTT_USAGE:
 613                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 614                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 615         case AMDGPU_INFO_GDS_CONFIG: {
 616                 struct drm_amdgpu_info_gds gds_info;
 617
 618                 memset(&gds_info, 0, sizeof(gds_info));
 619                 gds_info.compute_partition_size = adev->gds.gds_size;
 620                 gds_info.gds_total_size = adev->gds.gds_size;
 621                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 622                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 623                 return copy_to_user(out, &gds_info,
 624                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 625         }
 626         case AMDGPU_INFO_VRAM_GTT: {
 627                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 628
 629                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 630                         atomic64_read(&adev->vram_pin_size) -
 631                         AMDGPU_VM_RESERVED_VRAM;
 632                 vram_gtt.vram_cpu_accessible_size =
 633                         min(adev->gmc.visible_vram_size -
 634                             atomic64_read(&adev->visible_pin_size),
 635                             vram_gtt.vram_size);
 636                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 637                 vram_gtt.gtt_size *= PAGE_SIZE;
 638                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 639                 return copy_to_user(out, &vram_gtt,
 640                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 641         }
 642         case AMDGPU_INFO_MEMORY: {
 643                 struct drm_amdgpu_memory_info mem;
 644                 struct ttm_resource_manager *gtt_man =
 645                         &adev->mman.gtt_mgr.manager;
 646                 struct ttm_resource_manager *vram_man =
 647                         &adev->mman.vram_mgr.manager;
 648
 649                 memset(&mem, 0, sizeof(mem));
 650                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 651                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 652                         atomic64_read(&adev->vram_pin_size) -
 653                         AMDGPU_VM_RESERVED_VRAM;
 654                 mem.vram.heap_usage =
 655                         ttm_resource_manager_usage(vram_man);
 656                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 657
 658                 mem.cpu_accessible_vram.total_heap_size =
 659                         adev->gmc.visible_vram_size;
 660                 mem.cpu_accessible_vram.usable_heap_size =
 661                         min(adev->gmc.visible_vram_size -
 662                             atomic64_read(&adev->visible_pin_size),
 663                             mem.vram.usable_heap_size);
 664                 mem.cpu_accessible_vram.heap_usage =
 665                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 666                 mem.cpu_accessible_vram.max_allocation =
 667                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 668
 669                 mem.gtt.total_heap_size = gtt_man->size;
 670                 mem.gtt.total_heap_size *= PAGE_SIZE;
 671                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 672                         atomic64_read(&adev->gart_pin_size);
 673                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 674                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 675
 676                 return copy_to_user(out, &mem,
 677                                     min((size_t)size, sizeof(mem)))
 678                                     ? -EFAULT : 0;
 679         }
 680         case AMDGPU_INFO_READ_MMR_REG: {
 681                 unsigned n, alloc_size;
 682                 uint32_t *regs;
 683                 unsigned se_num = (info->read_mmr_reg.instance >>
 684                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 685                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 686                 unsigned sh_num = (info->read_mmr_reg.instance >>
 687                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 688                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 689
 690                 /* set full masks if the userspace set all bits
 691                  * in the bitfields */
 692                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 693                         se_num = 0xffffffff;
 694                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 695                         return -EINVAL;
 696                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 697                         sh_num = 0xffffffff;
 698                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 699                         return -EINVAL;
 700
 701                 if (info->read_mmr_reg.count > 128)
 702                         return -EINVAL;
 703
 704                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 705                 if (!regs)
 706                         return -ENOMEM;
 707                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 708
 709                 amdgpu_gfx_off_ctrl(adev, false);
 710                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 711                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 712                                                       info->read_mmr_reg.dword_offset + i,
 713                                                       &regs[i])) {
 714                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 715                                               info->read_mmr_reg.dword_offset + i);
 716                                 kfree(regs);
 717                                 amdgpu_gfx_off_ctrl(adev, true);
 718                                 return -EFAULT;
 719                         }
 720                 }
 721                 amdgpu_gfx_off_ctrl(adev, true);
 722                 n = copy_to_user(out, regs, min(size, alloc_size));
 723                 kfree(regs);
 724                 return n ? -EFAULT : 0;
 725         }
 726         case AMDGPU_INFO_DEV_INFO: {
 727                 struct drm_amdgpu_info_device *dev_info;
 728                 uint64_t vm_size;
 729                 int ret;
 730
 731                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 732                 if (!dev_info)
 733                         return -ENOMEM;
 734
 735                 dev_info->device_id = adev->pdev->device;
 736                 dev_info->chip_rev = adev->rev_id;
 737                 dev_info->external_rev = adev->external_rev_id;
 738                 dev_info->pci_rev = adev->pdev->revision;
 739                 dev_info->family = adev->family;
 740                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 741                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 742                 /* return all clocks in KHz */
 743                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 744                 if (adev->pm.dpm_enabled) {
 745                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 746                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 747                 } else {
 748                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 749                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 750                 }
 751                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 752                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 753                         adev->gfx.config.max_shader_engines;
 754                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 755                 dev_info->_pad = 0;
 756                 dev_info->ids_flags = 0;
 757                 if (adev->flags & AMD_IS_APU)
 758                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 759                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 760                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 761                 if (amdgpu_is_tmz(adev))
 762                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 763
 764                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 765                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 766
 767                 /* Older VCE FW versions are buggy and can handle only 40bits */
 768                 if (adev->vce.fw_version &&
 769                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 770                         vm_size = min(vm_size, 1ULL << 40);
 771
 772                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 773                 dev_info->virtual_address_max =
 774                         min(vm_size, AMDGPU_GMC_HOLE_START);
 775
 776                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 777                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 778                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 779                 }
 780                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 781                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 782                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 783                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 784                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 785                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 786                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 787                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 788                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 789                        sizeof(adev->gfx.cu_info.bitmap));
 790                 dev_info->vram_type = adev->gmc.vram_type;
 791                 dev_info->vram_bit_width = adev->gmc.vram_width;
 792                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 793                 dev_info->gc_double_offchip_lds_buf =
 794                         adev->gfx.config.double_offchip_lds_buf;
 795                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 796                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 797                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 798                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 799                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 800                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 801                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 802
 803                 if (adev->family >= AMDGPU_FAMILY_NV)
 804                         dev_info->pa_sc_tile_steering_override =
 805                                 adev->gfx.config.pa_sc_tile_steering_override;
 806
 807                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 808
 809                 ret = copy_to_user(out, dev_info,
 810                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 811                 kfree(dev_info);
 812                 return ret;
 813         }
 814         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 815                 unsigned i;
 816                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 817                 struct amd_vce_state *vce_state;
 818
 819                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 820                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 821                         if (vce_state) {
 822                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 823                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 824                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 825                                 vce_clk_table.num_valid_entries++;
 826                         }
 827                 }
 828
 829                 return copy_to_user(out, &vce_clk_table,
 830                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 831         }
 832         case AMDGPU_INFO_VBIOS: {
 833                 uint32_t bios_size = adev->bios_size;
 834
 835                 switch (info->vbios_info.type) {
 836                 case AMDGPU_INFO_VBIOS_SIZE:
 837                         return copy_to_user(out, &bios_size,
 838                                         min((size_t)size, sizeof(bios_size)))
 839                                         ? -EFAULT : 0;
 840                 case AMDGPU_INFO_VBIOS_IMAGE: {
 841                         uint8_t *bios;
 842                         uint32_t bios_offset = info->vbios_info.offset;
 843
 844                         if (bios_offset >= bios_size)
 845                                 return -EINVAL;
 846
 847                         bios = adev->bios + bios_offset;
 848                         return copy_to_user(out, bios,
 849                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 850                                         ? -EFAULT : 0;
 851                 }
 852                 case AMDGPU_INFO_VBIOS_INFO: {
 853                         struct drm_amdgpu_info_vbios vbios_info = {};
 854                         struct atom_context *atom_context;
 855
 856                         atom_context = adev->mode_info.atom_context;
 857                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 858                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 859                         vbios_info.version = atom_context->version;
 860                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 861                                                 sizeof(atom_context->vbios_ver_str));
 862                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 863
 864                         return copy_to_user(out, &vbios_info,
 865                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 866                 }
 867                 default:
 868                         DRM_DEBUG_KMS("Invalid request %d\n",
 869                                         info->vbios_info.type);
 870                         return -EINVAL;
 871                 }
 872         }
 873         case AMDGPU_INFO_NUM_HANDLES: {
 874                 struct drm_amdgpu_info_num_handles handle;
 875
 876                 switch (info->query_hw_ip.type) {
 877                 case AMDGPU_HW_IP_UVD:
 878                         /* Starting Polaris, we support unlimited UVD handles */
 879                         if (adev->asic_type < CHIP_POLARIS10) {
 880                                 handle.uvd_max_handles = adev->uvd.max_handles;
 881                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 882
 883                                 return copy_to_user(out, &handle,
 884                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 885                         } else {
 886                                 return -ENODATA;
 887                         }
 888
 889                         break;
 890                 default:
 891                         return -EINVAL;
 892                 }
 893         }
 894         case AMDGPU_INFO_SENSOR: {
 895                 if (!adev->pm.dpm_enabled)
 896                         return -ENOENT;
 897
 898                 switch (info->sensor_info.type) {
 899                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 900                         /* get sclk in Mhz */
 901                         if (amdgpu_dpm_read_sensor(adev,
 902                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 903                                                    (void *)&ui32, &ui32_size)) {
 904                                 return -EINVAL;
 905                         }
 906                         ui32 /= 100;
 907                         break;
 908                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 909                         /* get mclk in Mhz */
 910                         if (amdgpu_dpm_read_sensor(adev,
 911                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 912                                                    (void *)&ui32, &ui32_size)) {
 913                                 return -EINVAL;
 914                         }
 915                         ui32 /= 100;
 916                         break;
 917                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 918                         /* get temperature in millidegrees C */
 919                         if (amdgpu_dpm_read_sensor(adev,
 920                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 921                                                    (void *)&ui32, &ui32_size)) {
 922                                 return -EINVAL;
 923                         }
 924                         break;
 925                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 926                         /* get GPU load */
 927                         if (amdgpu_dpm_read_sensor(adev,
 928                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 929                                                    (void *)&ui32, &ui32_size)) {
 930                                 return -EINVAL;
 931                         }
 932                         break;
 933                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 934                         /* get average GPU power */
 935                         if (amdgpu_dpm_read_sensor(adev,
 936                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 937                                                    (void *)&ui32, &ui32_size)) {
 938                                 return -EINVAL;
 939                         }
 940                         ui32 >>= 8;
 941                         break;
 942                 case AMDGPU_INFO_SENSOR_VDDNB:
 943                         /* get VDDNB in millivolts */
 944                         if (amdgpu_dpm_read_sensor(adev,
 945                                                    AMDGPU_PP_SENSOR_VDDNB,
 946                                                    (void *)&ui32, &ui32_size)) {
 947                                 return -EINVAL;
 948                         }
 949                         break;
 950                 case AMDGPU_INFO_SENSOR_VDDGFX:
 951                         /* get VDDGFX in millivolts */
 952                         if (amdgpu_dpm_read_sensor(adev,
 953                                                    AMDGPU_PP_SENSOR_VDDGFX,
 954                                                    (void *)&ui32, &ui32_size)) {
 955                                 return -EINVAL;
 956                         }
 957                         break;
 958                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 959                         /* get stable pstate sclk in Mhz */
 960                         if (amdgpu_dpm_read_sensor(adev,
 961                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 962                                                    (void *)&ui32, &ui32_size)) {
 963                                 return -EINVAL;
 964                         }
 965                         ui32 /= 100;
 966                         break;
 967                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 968                         /* get stable pstate mclk in Mhz */
 969                         if (amdgpu_dpm_read_sensor(adev,
 970                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 971                                                    (void *)&ui32, &ui32_size)) {
 972                                 return -EINVAL;
 973                         }
 974                         ui32 /= 100;
 975                         break;
 976                 default:
 977                         DRM_DEBUG_KMS("Invalid request %d\n",
 978                                       info->sensor_info.type);
 979                         return -EINVAL;
 980                 }
 981                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 982         }
 983         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 984                 ui32 = atomic_read(&adev->vram_lost_counter);
 985                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 986         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 987                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 988                 uint64_t ras_mask;
 989
 990                 if (!ras)
 991                         return -EINVAL;
 992                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
 993
 994                 return copy_to_user(out, &ras_mask,
 995                                 min_t(u64, size, sizeof(ras_mask))) ?
 996                         -EFAULT : 0;
 997         }
 998         case AMDGPU_INFO_VIDEO_CAPS: {
 999                 const struct amdgpu_video_codecs *codecs;
1000                 struct drm_amdgpu_info_video_caps *caps;
1001                 int r;
1002
1003                 switch (info->video_cap.type) {
1004                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1005                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1006                         if (r)
1007                                 return -EINVAL;
1008                         break;
1009                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1010                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1011                         if (r)
1012                                 return -EINVAL;
1013                         break;
1014                 default:
1015                         DRM_DEBUG_KMS("Invalid request %d\n",
1016                                       info->video_cap.type);
1017                         return -EINVAL;
1018                 }
1019
1020                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1021                 if (!caps)
1022                         return -ENOMEM;
1023
1024                 for (i = 0; i < codecs->codec_count; i++) {
1025                         int idx = codecs->codec_array[i].codec_type;
1026
1027                         switch (idx) {
1028                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1029                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1030                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1031                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1032                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1033                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1034                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1035                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1036                                 caps->codec_info[idx].valid = 1;
1037                                 caps->codec_info[idx].max_width =
1038                                         codecs->codec_array[i].max_width;
1039                                 caps->codec_info[idx].max_height =
1040                                         codecs->codec_array[i].max_height;
1041                                 caps->codec_info[idx].max_pixels_per_frame =
1042                                         codecs->codec_array[i].max_pixels_per_frame;
1043                                 caps->codec_info[idx].max_level =
1044                                         codecs->codec_array[i].max_level;
1045                                 break;
1046                         default:
1047                                 break;
1048                         }
1049                 }
1050                 r = copy_to_user(out, caps,
1051                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1052                 kfree(caps);
1053                 return r;
1054         }
1055         default:
1056                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1057                 return -EINVAL;
1058         }
1059         return 0;
1060 }
1061
1062
1063 /*
1064  * Outdated mess for old drm with Xorg being in charge (void function now).
1065  */
1066 /**
1067  * amdgpu_driver_lastclose_kms - drm callback for last close
1068  *
1069  * @dev: drm dev pointer
1070  *
1071  * Switch vga_switcheroo state after last close (all asics).
1072  */
1073 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1074 {
1075         drm_fb_helper_lastclose(dev);
1076         vga_switcheroo_process_delayed_switch();
1077 }
1078
1079 /**
1080  * amdgpu_driver_open_kms - drm callback for open
1081  *
1082  * @dev: drm dev pointer
1083  * @file_priv: drm file
1084  *
1085  * On device open, init vm on cayman+ (all asics).
1086  * Returns 0 on success, error on failure.
1087  */
1088 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1089 {
1090         struct amdgpu_device *adev = drm_to_adev(dev);
1091         struct amdgpu_fpriv *fpriv;
1092         int r, pasid;
1093
1094         /* Ensure IB tests are run on ring */
1095         flush_delayed_work(&adev->delayed_init_work);
1096
1097
1098         if (amdgpu_ras_intr_triggered()) {
1099                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1100                 return -EHWPOISON;
1101         }
1102
1103         file_priv->driver_priv = NULL;
1104
1105         r = pm_runtime_get_sync(dev->dev);
1106         if (r < 0)
1107                 goto pm_put;
1108
1109         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1110         if (unlikely(!fpriv)) {
1111                 r = -ENOMEM;
1112                 goto out_suspend;
1113         }
1114
1115         pasid = amdgpu_pasid_alloc(16);
1116         if (pasid < 0) {
1117                 dev_warn(adev->dev, "No more PASIDs available!");
1118                 pasid = 0;
1119         }
1120
1121         r = amdgpu_vm_init(adev, &fpriv->vm);
1122         if (r)
1123                 goto error_pasid;
1124
1125         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1126         if (r)
1127                 goto error_vm;
1128
1129         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1130         if (!fpriv->prt_va) {
1131                 r = -ENOMEM;
1132                 goto error_vm;
1133         }
1134
1135         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1136                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1137
1138                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1139                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1140                 if (r)
1141                         goto error_vm;
1142         }
1143
1144         mutex_init(&fpriv->bo_list_lock);
1145         idr_init(&fpriv->bo_list_handles);
1146
1147         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1148
1149         file_priv->driver_priv = fpriv;
1150         goto out_suspend;
1151
1152 error_vm:
1153         amdgpu_vm_fini(adev, &fpriv->vm);
1154
1155 error_pasid:
1156         if (pasid) {
1157                 amdgpu_pasid_free(pasid);
1158                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1159         }
1160
1161         kfree(fpriv);
1162
1163 out_suspend:
1164         pm_runtime_mark_last_busy(dev->dev);
1165 pm_put:
1166         pm_runtime_put_autosuspend(dev->dev);
1167
1168         return r;
1169 }
1170
1171 /**
1172  * amdgpu_driver_postclose_kms - drm callback for post close
1173  *
1174  * @dev: drm dev pointer
1175  * @file_priv: drm file
1176  *
1177  * On device post close, tear down vm on cayman+ (all asics).
1178  */
1179 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1180                                  struct drm_file *file_priv)
1181 {
1182         struct amdgpu_device *adev = drm_to_adev(dev);
1183         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1184         struct amdgpu_bo_list *list;
1185         struct amdgpu_bo *pd;
1186         u32 pasid;
1187         int handle;
1188
1189         if (!fpriv)
1190                 return;
1191
1192         pm_runtime_get_sync(dev->dev);
1193
1194         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1195                 amdgpu_uvd_free_handles(adev, file_priv);
1196         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1197                 amdgpu_vce_free_handles(adev, file_priv);
1198
1199         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1200                 /* TODO: how to handle reserve failure */
1201                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1202                 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1203                 fpriv->csa_va = NULL;
1204                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1205         }
1206
1207         pasid = fpriv->vm.pasid;
1208         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1209         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1210                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1211                 amdgpu_bo_unreserve(pd);
1212         }
1213
1214         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1215         amdgpu_vm_fini(adev, &fpriv->vm);
1216
1217         if (pasid)
1218                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1219         amdgpu_bo_unref(&pd);
1220
1221         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1222                 amdgpu_bo_list_put(list);
1223
1224         idr_destroy(&fpriv->bo_list_handles);
1225         mutex_destroy(&fpriv->bo_list_lock);
1226
1227         kfree(fpriv);
1228         file_priv->driver_priv = NULL;
1229
1230         pm_runtime_mark_last_busy(dev->dev);
1231         pm_runtime_put_autosuspend(dev->dev);
1232 }
1233
1234
1235 void amdgpu_driver_release_kms(struct drm_device *dev)
1236 {
1237         struct amdgpu_device *adev = drm_to_adev(dev);
1238
1239         amdgpu_device_fini_sw(adev);
1240         pci_set_drvdata(adev->pdev, NULL);
1241 }
1242
1243 /*
1244  * VBlank related functions.
1245  */
1246 /**
1247  * amdgpu_get_vblank_counter_kms - get frame count
1248  *
1249  * @crtc: crtc to get the frame count from
1250  *
1251  * Gets the frame count on the requested crtc (all asics).
1252  * Returns frame count on success, -EINVAL on failure.
1253  */
1254 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1255 {
1256         struct drm_device *dev = crtc->dev;
1257         unsigned int pipe = crtc->index;
1258         struct amdgpu_device *adev = drm_to_adev(dev);
1259         int vpos, hpos, stat;
1260         u32 count;
1261
1262         if (pipe >= adev->mode_info.num_crtc) {
1263                 DRM_ERROR("Invalid crtc %u\n", pipe);
1264                 return -EINVAL;
1265         }
1266
1267         /* The hw increments its frame counter at start of vsync, not at start
1268          * of vblank, as is required by DRM core vblank counter handling.
1269          * Cook the hw count here to make it appear to the caller as if it
1270          * incremented at start of vblank. We measure distance to start of
1271          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1272          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1273          * result by 1 to give the proper appearance to caller.
1274          */
1275         if (adev->mode_info.crtcs[pipe]) {
1276                 /* Repeat readout if needed to provide stable result if
1277                  * we cross start of vsync during the queries.
1278                  */
1279                 do {
1280                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1281                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1282                          * vpos as distance to start of vblank, instead of
1283                          * regular vertical scanout pos.
1284                          */
1285                         stat = amdgpu_display_get_crtc_scanoutpos(
1286                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1287                                 &vpos, &hpos, NULL, NULL,
1288                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1289                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1290
1291                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1292                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1293                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1294                 } else {
1295                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1296                                       pipe, vpos);
1297
1298                         /* Bump counter if we are at >= leading edge of vblank,
1299                          * but before vsync where vpos would turn negative and
1300                          * the hw counter really increments.
1301                          */
1302                         if (vpos >= 0)
1303                                 count++;
1304                 }
1305         } else {
1306                 /* Fallback to use value as is. */
1307                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1308                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1309         }
1310
1311         return count;
1312 }
1313
1314 /**
1315  * amdgpu_enable_vblank_kms - enable vblank interrupt
1316  *
1317  * @crtc: crtc to enable vblank interrupt for
1318  *
1319  * Enable the interrupt on the requested crtc (all asics).
1320  * Returns 0 on success, -EINVAL on failure.
1321  */
1322 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1323 {
1324         struct drm_device *dev = crtc->dev;
1325         unsigned int pipe = crtc->index;
1326         struct amdgpu_device *adev = drm_to_adev(dev);
1327         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1328
1329         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1330 }
1331
1332 /**
1333  * amdgpu_disable_vblank_kms - disable vblank interrupt
1334  *
1335  * @crtc: crtc to disable vblank interrupt for
1336  *
1337  * Disable the interrupt on the requested crtc (all asics).
1338  */
1339 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1340 {
1341         struct drm_device *dev = crtc->dev;
1342         unsigned int pipe = crtc->index;
1343         struct amdgpu_device *adev = drm_to_adev(dev);
1344         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1345
1346         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1347 }
1348
1349 /*
1350  * Debugfs info
1351  */
1352 #if defined(CONFIG_DEBUG_FS)
1353
1354 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1355 {
1356         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1357         struct drm_amdgpu_info_firmware fw_info;
1358         struct drm_amdgpu_query_fw query_fw;
1359         struct atom_context *ctx = adev->mode_info.atom_context;
1360         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1361         int ret, i;
1362
1363         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1364 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1365                 TA_FW_NAME(XGMI),
1366                 TA_FW_NAME(RAS),
1367                 TA_FW_NAME(HDCP),
1368                 TA_FW_NAME(DTM),
1369                 TA_FW_NAME(RAP),
1370                 TA_FW_NAME(SECUREDISPLAY),
1371 #undef TA_FW_NAME
1372         };
1373
1374         /* VCE */
1375         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1376         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1377         if (ret)
1378                 return ret;
1379         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1380                    fw_info.feature, fw_info.ver);
1381
1382         /* UVD */
1383         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1384         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1385         if (ret)
1386                 return ret;
1387         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1388                    fw_info.feature, fw_info.ver);
1389
1390         /* GMC */
1391         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1392         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1393         if (ret)
1394                 return ret;
1395         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1396                    fw_info.feature, fw_info.ver);
1397
1398         /* ME */
1399         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1400         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1401         if (ret)
1402                 return ret;
1403         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1404                    fw_info.feature, fw_info.ver);
1405
1406         /* PFP */
1407         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1408         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1409         if (ret)
1410                 return ret;
1411         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1412                    fw_info.feature, fw_info.ver);
1413
1414         /* CE */
1415         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1416         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1417         if (ret)
1418                 return ret;
1419         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1420                    fw_info.feature, fw_info.ver);
1421
1422         /* RLC */
1423         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1424         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1425         if (ret)
1426                 return ret;
1427         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1428                    fw_info.feature, fw_info.ver);
1429
1430         /* RLC SAVE RESTORE LIST CNTL */
1431         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1432         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1433         if (ret)
1434                 return ret;
1435         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1436                    fw_info.feature, fw_info.ver);
1437
1438         /* RLC SAVE RESTORE LIST GPM MEM */
1439         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1440         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1441         if (ret)
1442                 return ret;
1443         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1444                    fw_info.feature, fw_info.ver);
1445
1446         /* RLC SAVE RESTORE LIST SRM MEM */
1447         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1448         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1449         if (ret)
1450                 return ret;
1451         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1452                    fw_info.feature, fw_info.ver);
1453
1454         /* MEC */
1455         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1456         query_fw.index = 0;
1457         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1458         if (ret)
1459                 return ret;
1460         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1461                    fw_info.feature, fw_info.ver);
1462
1463         /* MEC2 */
1464         if (adev->gfx.mec2_fw) {
1465                 query_fw.index = 1;
1466                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1467                 if (ret)
1468                         return ret;
1469                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1470                            fw_info.feature, fw_info.ver);
1471         }
1472
1473         /* PSP SOS */
1474         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1475         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1476         if (ret)
1477                 return ret;
1478         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1479                    fw_info.feature, fw_info.ver);
1480
1481
1482         /* PSP ASD */
1483         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1484         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1485         if (ret)
1486                 return ret;
1487         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1488                    fw_info.feature, fw_info.ver);
1489
1490         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1491         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1492                 query_fw.index = i;
1493                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1494                 if (ret)
1495                         continue;
1496
1497                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1498                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1499         }
1500
1501         /* SMC */
1502         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1503         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1504         if (ret)
1505                 return ret;
1506         smu_program = (fw_info.ver >> 24) & 0xff;
1507         smu_major = (fw_info.ver >> 16) & 0xff;
1508         smu_minor = (fw_info.ver >> 8) & 0xff;
1509         smu_debug = (fw_info.ver >> 0) & 0xff;
1510         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1511                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1512
1513         /* SDMA */
1514         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1515         for (i = 0; i < adev->sdma.num_instances; i++) {
1516                 query_fw.index = i;
1517                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1518                 if (ret)
1519                         return ret;
1520                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1521                            i, fw_info.feature, fw_info.ver);
1522         }
1523
1524         /* VCN */
1525         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1526         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1527         if (ret)
1528                 return ret;
1529         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1530                    fw_info.feature, fw_info.ver);
1531
1532         /* DMCU */
1533         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1534         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1535         if (ret)
1536                 return ret;
1537         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1538                    fw_info.feature, fw_info.ver);
1539
1540         /* DMCUB */
1541         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1542         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1543         if (ret)
1544                 return ret;
1545         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1546                    fw_info.feature, fw_info.ver);
1547
1548         /* TOC */
1549         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1550         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1551         if (ret)
1552                 return ret;
1553         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1554                    fw_info.feature, fw_info.ver);
1555
1556         /* CAP */
1557         if (adev->psp.cap_fw) {
1558                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1559                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1560                 if (ret)
1561                         return ret;
1562                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1563                                 fw_info.feature, fw_info.ver);
1564         }
1565
1566         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1567
1568         return 0;
1569 }
1570
1571 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1572
1573 #endif
1574
1575 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1576 {
1577 #if defined(CONFIG_DEBUG_FS)
1578         struct drm_minor *minor = adev_to_drm(adev)->primary;
1579         struct dentry *root = minor->debugfs_root;
1580
1581         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1582                             adev, &amdgpu_debugfs_firmware_info_fops);
1583
1584 #endif
1585 }