drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_sched.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46
  47 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  48 {
  49         struct amdgpu_gpu_instance *gpu_instance;
  50         int i;
  51
  52         mutex_lock(&mgpu_info.mutex);
  53
  54         for (i = 0; i < mgpu_info.num_gpu; i++) {
  55                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  56                 if (gpu_instance->adev == adev) {
  57                         mgpu_info.gpu_ins[i] =
  58                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  59                         mgpu_info.num_gpu--;
  60                         if (adev->flags & AMD_IS_APU)
  61                                 mgpu_info.num_apu--;
  62                         else
  63                                 mgpu_info.num_dgpu--;
  64                         break;
  65                 }
  66         }
  67
  68         mutex_unlock(&mgpu_info.mutex);
  69 }
  70
  71 /**
  72  * amdgpu_driver_unload_kms - Main unload function for KMS.
  73  *
  74  * @dev: drm dev pointer
  75  *
  76  * This is the main unload function for KMS (all asics).
  77  * Returns 0 on success.
  78  */
  79 void amdgpu_driver_unload_kms(struct drm_device *dev)
  80 {
  81         struct amdgpu_device *adev = dev->dev_private;
  82
  83         if (adev == NULL)
  84                 return;
  85
  86         amdgpu_unregister_gpu_instance(adev);
  87
  88         if (adev->rmmio == NULL)
  89                 goto done_free;
  90
  91         if (adev->runpm) {
  92                 pm_runtime_get_sync(dev->dev);
  93                 pm_runtime_forbid(dev->dev);
  94         }
  95
  96         amdgpu_acpi_fini(adev);
  97
  98         amdgpu_device_fini(adev);
  99
 100 done_free:
 101         kfree(adev);
 102         dev->dev_private = NULL;
 103 }
 104
 105 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 106 {
 107         struct amdgpu_gpu_instance *gpu_instance;
 108
 109         mutex_lock(&mgpu_info.mutex);
 110
 111         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 112                 DRM_ERROR("Cannot register more gpu instance\n");
 113                 mutex_unlock(&mgpu_info.mutex);
 114                 return;
 115         }
 116
 117         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 118         gpu_instance->adev = adev;
 119         gpu_instance->mgpu_fan_enabled = 0;
 120
 121         mgpu_info.num_gpu++;
 122         if (adev->flags & AMD_IS_APU)
 123                 mgpu_info.num_apu++;
 124         else
 125                 mgpu_info.num_dgpu++;
 126
 127         mutex_unlock(&mgpu_info.mutex);
 128 }
 129
 130 /**
 131  * amdgpu_driver_load_kms - Main load function for KMS.
 132  *
 133  * @dev: drm dev pointer
 134  * @flags: device flags
 135  *
 136  * This is the main load function for KMS (all asics).
 137  * Returns 0 on success, error on failure.
 138  */
 139 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
 140 {
 141         struct amdgpu_device *adev;
 142         int r, acpi_status;
 143
 144         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 145         if (adev == NULL) {
 146                 return -ENOMEM;
 147         }
 148         dev->dev_private = (void *)adev;
 149
 150         if (amdgpu_has_atpx() &&
 151             (amdgpu_is_atpx_hybrid() ||
 152              amdgpu_has_atpx_dgpu_power_cntl()) &&
 153             ((flags & AMD_IS_APU) == 0) &&
 154             !pci_is_thunderbolt_attached(dev->pdev))
 155                 flags |= AMD_IS_PX;
 156
 157         /* amdgpu_device_init should report only fatal error
 158          * like memory allocation failure or iomapping failure,
 159          * or memory manager initialization failure, it must
 160          * properly initialize the GPU MC controller and permit
 161          * VRAM allocation
 162          */
 163         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 164         if (r) {
 165                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 166                 goto out;
 167         }
 168
 169         if (amdgpu_device_supports_boco(dev) &&
 170             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 171                 adev->runpm = true;
 172         } else if (amdgpu_device_supports_baco(dev) &&
 173                    (amdgpu_runtime_pm != 0)) {
 174                 switch (adev->asic_type) {
 175 #ifdef CONFIG_DRM_AMDGPU_CIK
 176                 case CHIP_BONAIRE:
 177                 case CHIP_HAWAII:
 178 #endif
 179                 case CHIP_VEGA20:
 180                 case CHIP_ARCTURUS:
 181                 case CHIP_SIENNA_CICHLID:
 182                         /* enable runpm if runpm=1 */
 183                         if (amdgpu_runtime_pm > 0)
 184                                 adev->runpm = true;
 185                         break;
 186                 case CHIP_VEGA10:
 187                         /* turn runpm on if noretry=0 */
 188                         if (!amdgpu_noretry)
 189                                 adev->runpm = true;
 190                         break;
 191                 default:
 192                         /* enable runpm on VI+ */
 193                         adev->runpm = true;
 194                         break;
 195                 }
 196         }
 197
 198         /* Call ACPI methods: require modeset init
 199          * but failure is not fatal
 200          */
 201
 202         acpi_status = amdgpu_acpi_init(adev);
 203         if (acpi_status)
 204                 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
 205
 206         if (adev->runpm) {
 207                 /* only need to skip on ATPX */
 208                 if (amdgpu_device_supports_boco(dev) &&
 209                     !amdgpu_is_atpx_hybrid())
 210                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 211                 pm_runtime_use_autosuspend(dev->dev);
 212                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 213                 pm_runtime_allow(dev->dev);
 214                 pm_runtime_mark_last_busy(dev->dev);
 215                 pm_runtime_put_autosuspend(dev->dev);
 216         }
 217
 218 out:
 219         if (r) {
 220                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 221                 if (adev->rmmio && adev->runpm)
 222                         pm_runtime_put_noidle(dev->dev);
 223                 amdgpu_driver_unload_kms(dev);
 224         }
 225
 226         return r;
 227 }
 228
 229 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 230                                 struct drm_amdgpu_query_fw *query_fw,
 231                                 struct amdgpu_device *adev)
 232 {
 233         switch (query_fw->fw_type) {
 234         case AMDGPU_INFO_FW_VCE:
 235                 fw_info->ver = adev->vce.fw_version;
 236                 fw_info->feature = adev->vce.fb_version;
 237                 break;
 238         case AMDGPU_INFO_FW_UVD:
 239                 fw_info->ver = adev->uvd.fw_version;
 240                 fw_info->feature = 0;
 241                 break;
 242         case AMDGPU_INFO_FW_VCN:
 243                 fw_info->ver = adev->vcn.fw_version;
 244                 fw_info->feature = 0;
 245                 break;
 246         case AMDGPU_INFO_FW_GMC:
 247                 fw_info->ver = adev->gmc.fw_version;
 248                 fw_info->feature = 0;
 249                 break;
 250         case AMDGPU_INFO_FW_GFX_ME:
 251                 fw_info->ver = adev->gfx.me_fw_version;
 252                 fw_info->feature = adev->gfx.me_feature_version;
 253                 break;
 254         case AMDGPU_INFO_FW_GFX_PFP:
 255                 fw_info->ver = adev->gfx.pfp_fw_version;
 256                 fw_info->feature = adev->gfx.pfp_feature_version;
 257                 break;
 258         case AMDGPU_INFO_FW_GFX_CE:
 259                 fw_info->ver = adev->gfx.ce_fw_version;
 260                 fw_info->feature = adev->gfx.ce_feature_version;
 261                 break;
 262         case AMDGPU_INFO_FW_GFX_RLC:
 263                 fw_info->ver = adev->gfx.rlc_fw_version;
 264                 fw_info->feature = adev->gfx.rlc_feature_version;
 265                 break;
 266         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 267                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 268                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 269                 break;
 270         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 271                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 272                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 273                 break;
 274         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 275                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 276                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 277                 break;
 278         case AMDGPU_INFO_FW_GFX_MEC:
 279                 if (query_fw->index == 0) {
 280                         fw_info->ver = adev->gfx.mec_fw_version;
 281                         fw_info->feature = adev->gfx.mec_feature_version;
 282                 } else if (query_fw->index == 1) {
 283                         fw_info->ver = adev->gfx.mec2_fw_version;
 284                         fw_info->feature = adev->gfx.mec2_feature_version;
 285                 } else
 286                         return -EINVAL;
 287                 break;
 288         case AMDGPU_INFO_FW_SMC:
 289                 fw_info->ver = adev->pm.fw_version;
 290                 fw_info->feature = 0;
 291                 break;
 292         case AMDGPU_INFO_FW_TA:
 293                 if (query_fw->index > 1)
 294                         return -EINVAL;
 295                 if (query_fw->index == 0) {
 296                         fw_info->ver = adev->psp.ta_fw_version;
 297                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 298                 } else {
 299                         fw_info->ver = adev->psp.ta_fw_version;
 300                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 301                 }
 302                 break;
 303         case AMDGPU_INFO_FW_SDMA:
 304                 if (query_fw->index >= adev->sdma.num_instances)
 305                         return -EINVAL;
 306                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 307                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 308                 break;
 309         case AMDGPU_INFO_FW_SOS:
 310                 fw_info->ver = adev->psp.sos_fw_version;
 311                 fw_info->feature = adev->psp.sos_feature_version;
 312                 break;
 313         case AMDGPU_INFO_FW_ASD:
 314                 fw_info->ver = adev->psp.asd_fw_version;
 315                 fw_info->feature = adev->psp.asd_feature_version;
 316                 break;
 317         case AMDGPU_INFO_FW_DMCU:
 318                 fw_info->ver = adev->dm.dmcu_fw_version;
 319                 fw_info->feature = 0;
 320                 break;
 321         case AMDGPU_INFO_FW_DMCUB:
 322                 fw_info->ver = adev->dm.dmcub_fw_version;
 323                 fw_info->feature = 0;
 324                 break;
 325         default:
 326                 return -EINVAL;
 327         }
 328         return 0;
 329 }
 330
 331 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 332                              struct drm_amdgpu_info *info,
 333                              struct drm_amdgpu_info_hw_ip *result)
 334 {
 335         uint32_t ib_start_alignment = 0;
 336         uint32_t ib_size_alignment = 0;
 337         enum amd_ip_block_type type;
 338         unsigned int num_rings = 0;
 339         unsigned int i, j;
 340
 341         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 342                 return -EINVAL;
 343
 344         switch (info->query_hw_ip.type) {
 345         case AMDGPU_HW_IP_GFX:
 346                 type = AMD_IP_BLOCK_TYPE_GFX;
 347                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 348                         if (adev->gfx.gfx_ring[i].sched.ready)
 349                                 ++num_rings;
 350                 ib_start_alignment = 32;
 351                 ib_size_alignment = 32;
 352                 break;
 353         case AMDGPU_HW_IP_COMPUTE:
 354                 type = AMD_IP_BLOCK_TYPE_GFX;
 355                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 356                         if (adev->gfx.compute_ring[i].sched.ready)
 357                                 ++num_rings;
 358                 ib_start_alignment = 32;
 359                 ib_size_alignment = 32;
 360                 break;
 361         case AMDGPU_HW_IP_DMA:
 362                 type = AMD_IP_BLOCK_TYPE_SDMA;
 363                 for (i = 0; i < adev->sdma.num_instances; i++)
 364                         if (adev->sdma.instance[i].ring.sched.ready)
 365                                 ++num_rings;
 366                 ib_start_alignment = 256;
 367                 ib_size_alignment = 4;
 368                 break;
 369         case AMDGPU_HW_IP_UVD:
 370                 type = AMD_IP_BLOCK_TYPE_UVD;
 371                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 372                         if (adev->uvd.harvest_config & (1 << i))
 373                                 continue;
 374
 375                         if (adev->uvd.inst[i].ring.sched.ready)
 376                                 ++num_rings;
 377                 }
 378                 ib_start_alignment = 64;
 379                 ib_size_alignment = 64;
 380                 break;
 381         case AMDGPU_HW_IP_VCE:
 382                 type = AMD_IP_BLOCK_TYPE_VCE;
 383                 for (i = 0; i < adev->vce.num_rings; i++)
 384                         if (adev->vce.ring[i].sched.ready)
 385                                 ++num_rings;
 386                 ib_start_alignment = 4;
 387                 ib_size_alignment = 1;
 388                 break;
 389         case AMDGPU_HW_IP_UVD_ENC:
 390                 type = AMD_IP_BLOCK_TYPE_UVD;
 391                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 392                         if (adev->uvd.harvest_config & (1 << i))
 393                                 continue;
 394
 395                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 396                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 397                                         ++num_rings;
 398                 }
 399                 ib_start_alignment = 64;
 400                 ib_size_alignment = 64;
 401                 break;
 402         case AMDGPU_HW_IP_VCN_DEC:
 403                 type = AMD_IP_BLOCK_TYPE_VCN;
 404                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 405                         if (adev->uvd.harvest_config & (1 << i))
 406                                 continue;
 407
 408                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 409                                 ++num_rings;
 410                 }
 411                 ib_start_alignment = 16;
 412                 ib_size_alignment = 16;
 413                 break;
 414         case AMDGPU_HW_IP_VCN_ENC:
 415                 type = AMD_IP_BLOCK_TYPE_VCN;
 416                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 417                         if (adev->uvd.harvest_config & (1 << i))
 418                                 continue;
 419
 420                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 421                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 422                                         ++num_rings;
 423                 }
 424                 ib_start_alignment = 64;
 425                 ib_size_alignment = 1;
 426                 break;
 427         case AMDGPU_HW_IP_VCN_JPEG:
 428                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 429                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 430
 431                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 432                         if (adev->jpeg.harvest_config & (1 << i))
 433                                 continue;
 434
 435                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 436                                 ++num_rings;
 437                 }
 438                 ib_start_alignment = 16;
 439                 ib_size_alignment = 16;
 440                 break;
 441         default:
 442                 return -EINVAL;
 443         }
 444
 445         for (i = 0; i < adev->num_ip_blocks; i++)
 446                 if (adev->ip_blocks[i].version->type == type &&
 447                     adev->ip_blocks[i].status.valid)
 448                         break;
 449
 450         if (i == adev->num_ip_blocks)
 451                 return 0;
 452
 453         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 454                         num_rings);
 455
 456         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 457         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 458         result->capabilities_flags = 0;
 459         result->available_rings = (1 << num_rings) - 1;
 460         result->ib_start_alignment = ib_start_alignment;
 461         result->ib_size_alignment = ib_size_alignment;
 462         return 0;
 463 }
 464
 465 /*
 466  * Userspace get information ioctl
 467  */
 468 /**
 469  * amdgpu_info_ioctl - answer a device specific request.
 470  *
 471  * @adev: amdgpu device pointer
 472  * @data: request object
 473  * @filp: drm filp
 474  *
 475  * This function is used to pass device specific parameters to the userspace
 476  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 477  * etc. (all asics).
 478  * Returns 0 on success, -EINVAL on failure.
 479  */
 480 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 481 {
 482         struct amdgpu_device *adev = dev->dev_private;
 483         struct drm_amdgpu_info *info = data;
 484         struct amdgpu_mode_info *minfo = &adev->mode_info;
 485         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 486         uint32_t size = info->return_size;
 487         struct drm_crtc *crtc;
 488         uint32_t ui32 = 0;
 489         uint64_t ui64 = 0;
 490         int i, found;
 491         int ui32_size = sizeof(ui32);
 492
 493         if (!info->return_size || !info->return_pointer)
 494                 return -EINVAL;
 495
 496         switch (info->query) {
 497         case AMDGPU_INFO_ACCEL_WORKING:
 498                 ui32 = adev->accel_working;
 499                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 500         case AMDGPU_INFO_CRTC_FROM_ID:
 501                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 502                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 503                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 504                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 505                                 ui32 = amdgpu_crtc->crtc_id;
 506                                 found = 1;
 507                                 break;
 508                         }
 509                 }
 510                 if (!found) {
 511                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 512                         return -EINVAL;
 513                 }
 514                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 515         case AMDGPU_INFO_HW_IP_INFO: {
 516                 struct drm_amdgpu_info_hw_ip ip = {};
 517                 int ret;
 518
 519                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 520                 if (ret)
 521                         return ret;
 522
 523                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 524                 return ret ? -EFAULT : 0;
 525         }
 526         case AMDGPU_INFO_HW_IP_COUNT: {
 527                 enum amd_ip_block_type type;
 528                 uint32_t count = 0;
 529
 530                 switch (info->query_hw_ip.type) {
 531                 case AMDGPU_HW_IP_GFX:
 532                         type = AMD_IP_BLOCK_TYPE_GFX;
 533                         break;
 534                 case AMDGPU_HW_IP_COMPUTE:
 535                         type = AMD_IP_BLOCK_TYPE_GFX;
 536                         break;
 537                 case AMDGPU_HW_IP_DMA:
 538                         type = AMD_IP_BLOCK_TYPE_SDMA;
 539                         break;
 540                 case AMDGPU_HW_IP_UVD:
 541                         type = AMD_IP_BLOCK_TYPE_UVD;
 542                         break;
 543                 case AMDGPU_HW_IP_VCE:
 544                         type = AMD_IP_BLOCK_TYPE_VCE;
 545                         break;
 546                 case AMDGPU_HW_IP_UVD_ENC:
 547                         type = AMD_IP_BLOCK_TYPE_UVD;
 548                         break;
 549                 case AMDGPU_HW_IP_VCN_DEC:
 550                 case AMDGPU_HW_IP_VCN_ENC:
 551                         type = AMD_IP_BLOCK_TYPE_VCN;
 552                         break;
 553                 case AMDGPU_HW_IP_VCN_JPEG:
 554                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 555                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 556                         break;
 557                 default:
 558                         return -EINVAL;
 559                 }
 560
 561                 for (i = 0; i < adev->num_ip_blocks; i++)
 562                         if (adev->ip_blocks[i].version->type == type &&
 563                             adev->ip_blocks[i].status.valid &&
 564                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 565                                 count++;
 566
 567                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 568         }
 569         case AMDGPU_INFO_TIMESTAMP:
 570                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 571                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 572         case AMDGPU_INFO_FW_VERSION: {
 573                 struct drm_amdgpu_info_firmware fw_info;
 574                 int ret;
 575
 576                 /* We only support one instance of each IP block right now. */
 577                 if (info->query_fw.ip_instance != 0)
 578                         return -EINVAL;
 579
 580                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 581                 if (ret)
 582                         return ret;
 583
 584                 return copy_to_user(out, &fw_info,
 585                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 586         }
 587         case AMDGPU_INFO_NUM_BYTES_MOVED:
 588                 ui64 = atomic64_read(&adev->num_bytes_moved);
 589                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 590         case AMDGPU_INFO_NUM_EVICTIONS:
 591                 ui64 = atomic64_read(&adev->num_evictions);
 592                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 593         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 594                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 595                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 596         case AMDGPU_INFO_VRAM_USAGE:
 597                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 598                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 599         case AMDGPU_INFO_VIS_VRAM_USAGE:
 600                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 601                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 602         case AMDGPU_INFO_GTT_USAGE:
 603                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 604                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 605         case AMDGPU_INFO_GDS_CONFIG: {
 606                 struct drm_amdgpu_info_gds gds_info;
 607
 608                 memset(&gds_info, 0, sizeof(gds_info));
 609                 gds_info.compute_partition_size = adev->gds.gds_size;
 610                 gds_info.gds_total_size = adev->gds.gds_size;
 611                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 612                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 613                 return copy_to_user(out, &gds_info,
 614                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 615         }
 616         case AMDGPU_INFO_VRAM_GTT: {
 617                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 618
 619                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 620                         atomic64_read(&adev->vram_pin_size) -
 621                         AMDGPU_VM_RESERVED_VRAM;
 622                 vram_gtt.vram_cpu_accessible_size =
 623                         min(adev->gmc.visible_vram_size -
 624                             atomic64_read(&adev->visible_pin_size),
 625                             vram_gtt.vram_size);
 626                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 627                 vram_gtt.gtt_size *= PAGE_SIZE;
 628                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 629                 return copy_to_user(out, &vram_gtt,
 630                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 631         }
 632         case AMDGPU_INFO_MEMORY: {
 633                 struct drm_amdgpu_memory_info mem;
 634                 struct ttm_resource_manager *vram_man =
 635                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 636                 struct ttm_resource_manager *gtt_man =
 637                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 638                 memset(&mem, 0, sizeof(mem));
 639                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 640                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 641                         atomic64_read(&adev->vram_pin_size) -
 642                         AMDGPU_VM_RESERVED_VRAM;
 643                 mem.vram.heap_usage =
 644                         amdgpu_vram_mgr_usage(vram_man);
 645                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 646
 647                 mem.cpu_accessible_vram.total_heap_size =
 648                         adev->gmc.visible_vram_size;
 649                 mem.cpu_accessible_vram.usable_heap_size =
 650                         min(adev->gmc.visible_vram_size -
 651                             atomic64_read(&adev->visible_pin_size),
 652                             mem.vram.usable_heap_size);
 653                 mem.cpu_accessible_vram.heap_usage =
 654                         amdgpu_vram_mgr_vis_usage(vram_man);
 655                 mem.cpu_accessible_vram.max_allocation =
 656                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 657
 658                 mem.gtt.total_heap_size = gtt_man->size;
 659                 mem.gtt.total_heap_size *= PAGE_SIZE;
 660                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 661                         atomic64_read(&adev->gart_pin_size);
 662                 mem.gtt.heap_usage =
 663                         amdgpu_gtt_mgr_usage(gtt_man);
 664                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 665
 666                 return copy_to_user(out, &mem,
 667                                     min((size_t)size, sizeof(mem)))
 668                                     ? -EFAULT : 0;
 669         }
 670         case AMDGPU_INFO_READ_MMR_REG: {
 671                 unsigned n, alloc_size;
 672                 uint32_t *regs;
 673                 unsigned se_num = (info->read_mmr_reg.instance >>
 674                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 675                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 676                 unsigned sh_num = (info->read_mmr_reg.instance >>
 677                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 678                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 679
 680                 /* set full masks if the userspace set all bits
 681                  * in the bitfields */
 682                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 683                         se_num = 0xffffffff;
 684                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 685                         sh_num = 0xffffffff;
 686
 687                 if (info->read_mmr_reg.count > 128)
 688                         return -EINVAL;
 689
 690                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 691                 if (!regs)
 692                         return -ENOMEM;
 693                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 694
 695                 amdgpu_gfx_off_ctrl(adev, false);
 696                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 697                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 698                                                       info->read_mmr_reg.dword_offset + i,
 699                                                       &regs[i])) {
 700                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 701                                               info->read_mmr_reg.dword_offset + i);
 702                                 kfree(regs);
 703                                 amdgpu_gfx_off_ctrl(adev, true);
 704                                 return -EFAULT;
 705                         }
 706                 }
 707                 amdgpu_gfx_off_ctrl(adev, true);
 708                 n = copy_to_user(out, regs, min(size, alloc_size));
 709                 kfree(regs);
 710                 return n ? -EFAULT : 0;
 711         }
 712         case AMDGPU_INFO_DEV_INFO: {
 713                 struct drm_amdgpu_info_device dev_info;
 714                 uint64_t vm_size;
 715
 716                 memset(&dev_info, 0, sizeof(dev_info));
 717                 dev_info.device_id = dev->pdev->device;
 718                 dev_info.chip_rev = adev->rev_id;
 719                 dev_info.external_rev = adev->external_rev_id;
 720                 dev_info.pci_rev = dev->pdev->revision;
 721                 dev_info.family = adev->family;
 722                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 723                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 724                 /* return all clocks in KHz */
 725                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 726                 if (adev->pm.dpm_enabled) {
 727                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 728                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 729                 } else {
 730                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 731                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 732                 }
 733                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 734                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 735                         adev->gfx.config.max_shader_engines;
 736                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 737                 dev_info._pad = 0;
 738                 dev_info.ids_flags = 0;
 739                 if (adev->flags & AMD_IS_APU)
 740                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 741                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 742                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 743
 744                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 745                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 746
 747                 /* Older VCE FW versions are buggy and can handle only 40bits */
 748                 if (adev->vce.fw_version &&
 749                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 750                         vm_size = min(vm_size, 1ULL << 40);
 751
 752                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 753                 dev_info.virtual_address_max =
 754                         min(vm_size, AMDGPU_GMC_HOLE_START);
 755
 756                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 757                         dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
 758                         dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 759                 }
 760                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 761                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 762                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 763                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 764                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 765                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 766                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 767                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 768                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 769                        sizeof(adev->gfx.cu_info.bitmap));
 770                 dev_info.vram_type = adev->gmc.vram_type;
 771                 dev_info.vram_bit_width = adev->gmc.vram_width;
 772                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 773                 dev_info.gc_double_offchip_lds_buf =
 774                         adev->gfx.config.double_offchip_lds_buf;
 775                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 776                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 777                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 778                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 779                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 780                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 781                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 782
 783                 if (adev->family >= AMDGPU_FAMILY_NV)
 784                         dev_info.pa_sc_tile_steering_override =
 785                                 adev->gfx.config.pa_sc_tile_steering_override;
 786
 787                 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 788
 789                 return copy_to_user(out, &dev_info,
 790                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 791         }
 792         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 793                 unsigned i;
 794                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 795                 struct amd_vce_state *vce_state;
 796
 797                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 798                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 799                         if (vce_state) {
 800                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 801                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 802                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 803                                 vce_clk_table.num_valid_entries++;
 804                         }
 805                 }
 806
 807                 return copy_to_user(out, &vce_clk_table,
 808                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 809         }
 810         case AMDGPU_INFO_VBIOS: {
 811                 uint32_t bios_size = adev->bios_size;
 812
 813                 switch (info->vbios_info.type) {
 814                 case AMDGPU_INFO_VBIOS_SIZE:
 815                         return copy_to_user(out, &bios_size,
 816                                         min((size_t)size, sizeof(bios_size)))
 817                                         ? -EFAULT : 0;
 818                 case AMDGPU_INFO_VBIOS_IMAGE: {
 819                         uint8_t *bios;
 820                         uint32_t bios_offset = info->vbios_info.offset;
 821
 822                         if (bios_offset >= bios_size)
 823                                 return -EINVAL;
 824
 825                         bios = adev->bios + bios_offset;
 826                         return copy_to_user(out, bios,
 827                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 828                                         ? -EFAULT : 0;
 829                 }
 830                 default:
 831                         DRM_DEBUG_KMS("Invalid request %d\n",
 832                                         info->vbios_info.type);
 833                         return -EINVAL;
 834                 }
 835         }
 836         case AMDGPU_INFO_NUM_HANDLES: {
 837                 struct drm_amdgpu_info_num_handles handle;
 838
 839                 switch (info->query_hw_ip.type) {
 840                 case AMDGPU_HW_IP_UVD:
 841                         /* Starting Polaris, we support unlimited UVD handles */
 842                         if (adev->asic_type < CHIP_POLARIS10) {
 843                                 handle.uvd_max_handles = adev->uvd.max_handles;
 844                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 845
 846                                 return copy_to_user(out, &handle,
 847                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 848                         } else {
 849                                 return -ENODATA;
 850                         }
 851
 852                         break;
 853                 default:
 854                         return -EINVAL;
 855                 }
 856         }
 857         case AMDGPU_INFO_SENSOR: {
 858                 if (!adev->pm.dpm_enabled)
 859                         return -ENOENT;
 860
 861                 switch (info->sensor_info.type) {
 862                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 863                         /* get sclk in Mhz */
 864                         if (amdgpu_dpm_read_sensor(adev,
 865                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 866                                                    (void *)&ui32, &ui32_size)) {
 867                                 return -EINVAL;
 868                         }
 869                         ui32 /= 100;
 870                         break;
 871                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 872                         /* get mclk in Mhz */
 873                         if (amdgpu_dpm_read_sensor(adev,
 874                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 875                                                    (void *)&ui32, &ui32_size)) {
 876                                 return -EINVAL;
 877                         }
 878                         ui32 /= 100;
 879                         break;
 880                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 881                         /* get temperature in millidegrees C */
 882                         if (amdgpu_dpm_read_sensor(adev,
 883                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 884                                                    (void *)&ui32, &ui32_size)) {
 885                                 return -EINVAL;
 886                         }
 887                         break;
 888                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 889                         /* get GPU load */
 890                         if (amdgpu_dpm_read_sensor(adev,
 891                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 892                                                    (void *)&ui32, &ui32_size)) {
 893                                 return -EINVAL;
 894                         }
 895                         break;
 896                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 897                         /* get average GPU power */
 898                         if (amdgpu_dpm_read_sensor(adev,
 899                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 900                                                    (void *)&ui32, &ui32_size)) {
 901                                 return -EINVAL;
 902                         }
 903                         ui32 >>= 8;
 904                         break;
 905                 case AMDGPU_INFO_SENSOR_VDDNB:
 906                         /* get VDDNB in millivolts */
 907                         if (amdgpu_dpm_read_sensor(adev,
 908                                                    AMDGPU_PP_SENSOR_VDDNB,
 909                                                    (void *)&ui32, &ui32_size)) {
 910                                 return -EINVAL;
 911                         }
 912                         break;
 913                 case AMDGPU_INFO_SENSOR_VDDGFX:
 914                         /* get VDDGFX in millivolts */
 915                         if (amdgpu_dpm_read_sensor(adev,
 916                                                    AMDGPU_PP_SENSOR_VDDGFX,
 917                                                    (void *)&ui32, &ui32_size)) {
 918                                 return -EINVAL;
 919                         }
 920                         break;
 921                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 922                         /* get stable pstate sclk in Mhz */
 923                         if (amdgpu_dpm_read_sensor(adev,
 924                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 925                                                    (void *)&ui32, &ui32_size)) {
 926                                 return -EINVAL;
 927                         }
 928                         ui32 /= 100;
 929                         break;
 930                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 931                         /* get stable pstate mclk in Mhz */
 932                         if (amdgpu_dpm_read_sensor(adev,
 933                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 934                                                    (void *)&ui32, &ui32_size)) {
 935                                 return -EINVAL;
 936                         }
 937                         ui32 /= 100;
 938                         break;
 939                 default:
 940                         DRM_DEBUG_KMS("Invalid request %d\n",
 941                                       info->sensor_info.type);
 942                         return -EINVAL;
 943                 }
 944                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 945         }
 946         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 947                 ui32 = atomic_read(&adev->vram_lost_counter);
 948                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 949         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 950                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 951                 uint64_t ras_mask;
 952
 953                 if (!ras)
 954                         return -EINVAL;
 955                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 956
 957                 return copy_to_user(out, &ras_mask,
 958                                 min_t(u64, size, sizeof(ras_mask))) ?
 959                         -EFAULT : 0;
 960         }
 961         default:
 962                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 963                 return -EINVAL;
 964         }
 965         return 0;
 966 }
 967
 968
 969 /*
 970  * Outdated mess for old drm with Xorg being in charge (void function now).
 971  */
 972 /**
 973  * amdgpu_driver_lastclose_kms - drm callback for last close
 974  *
 975  * @dev: drm dev pointer
 976  *
 977  * Switch vga_switcheroo state after last close (all asics).
 978  */
 979 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 980 {
 981         drm_fb_helper_lastclose(dev);
 982         vga_switcheroo_process_delayed_switch();
 983 }
 984
 985 /**
 986  * amdgpu_driver_open_kms - drm callback for open
 987  *
 988  * @dev: drm dev pointer
 989  * @file_priv: drm file
 990  *
 991  * On device open, init vm on cayman+ (all asics).
 992  * Returns 0 on success, error on failure.
 993  */
 994 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 995 {
 996         struct amdgpu_device *adev = dev->dev_private;
 997         struct amdgpu_fpriv *fpriv;
 998         int r, pasid;
 999
1000         /* Ensure IB tests are run on ring */
1001         flush_delayed_work(&adev->delayed_init_work);
1002
1003
1004         if (amdgpu_ras_intr_triggered()) {
1005                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1006                 return -EHWPOISON;
1007         }
1008
1009         file_priv->driver_priv = NULL;
1010
1011         r = pm_runtime_get_sync(dev->dev);
1012         if (r < 0)
1013                 goto pm_put;
1014
1015         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1016         if (unlikely(!fpriv)) {
1017                 r = -ENOMEM;
1018                 goto out_suspend;
1019         }
1020
1021         pasid = amdgpu_pasid_alloc(16);
1022         if (pasid < 0) {
1023                 dev_warn(adev->dev, "No more PASIDs available!");
1024                 pasid = 0;
1025         }
1026         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1027         if (r)
1028                 goto error_pasid;
1029
1030         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1031         if (!fpriv->prt_va) {
1032                 r = -ENOMEM;
1033                 goto error_vm;
1034         }
1035
1036         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1037                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1038
1039                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1040                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1041                 if (r)
1042                         goto error_vm;
1043         }
1044
1045         mutex_init(&fpriv->bo_list_lock);
1046         idr_init(&fpriv->bo_list_handles);
1047
1048         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1049
1050         file_priv->driver_priv = fpriv;
1051         goto out_suspend;
1052
1053 error_vm:
1054         amdgpu_vm_fini(adev, &fpriv->vm);
1055
1056 error_pasid:
1057         if (pasid)
1058                 amdgpu_pasid_free(pasid);
1059
1060         kfree(fpriv);
1061
1062 out_suspend:
1063         pm_runtime_mark_last_busy(dev->dev);
1064 pm_put:
1065         pm_runtime_put_autosuspend(dev->dev);
1066
1067         return r;
1068 }
1069
1070 /**
1071  * amdgpu_driver_postclose_kms - drm callback for post close
1072  *
1073  * @dev: drm dev pointer
1074  * @file_priv: drm file
1075  *
1076  * On device post close, tear down vm on cayman+ (all asics).
1077  */
1078 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1079                                  struct drm_file *file_priv)
1080 {
1081         struct amdgpu_device *adev = dev->dev_private;
1082         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1083         struct amdgpu_bo_list *list;
1084         struct amdgpu_bo *pd;
1085         unsigned int pasid;
1086         int handle;
1087
1088         if (!fpriv)
1089                 return;
1090
1091         pm_runtime_get_sync(dev->dev);
1092
1093         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1094                 amdgpu_uvd_free_handles(adev, file_priv);
1095         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1096                 amdgpu_vce_free_handles(adev, file_priv);
1097
1098         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1099
1100         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1101                 /* TODO: how to handle reserve failure */
1102                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1103                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1104                 fpriv->csa_va = NULL;
1105                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1106         }
1107
1108         pasid = fpriv->vm.pasid;
1109         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1110
1111         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1112         amdgpu_vm_fini(adev, &fpriv->vm);
1113
1114         if (pasid)
1115                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1116         amdgpu_bo_unref(&pd);
1117
1118         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1119                 amdgpu_bo_list_put(list);
1120
1121         idr_destroy(&fpriv->bo_list_handles);
1122         mutex_destroy(&fpriv->bo_list_lock);
1123
1124         kfree(fpriv);
1125         file_priv->driver_priv = NULL;
1126
1127         pm_runtime_mark_last_busy(dev->dev);
1128         pm_runtime_put_autosuspend(dev->dev);
1129 }
1130
1131 /*
1132  * VBlank related functions.
1133  */
1134 /**
1135  * amdgpu_get_vblank_counter_kms - get frame count
1136  *
1137  * @crtc: crtc to get the frame count from
1138  *
1139  * Gets the frame count on the requested crtc (all asics).
1140  * Returns frame count on success, -EINVAL on failure.
1141  */
1142 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1143 {
1144         struct drm_device *dev = crtc->dev;
1145         unsigned int pipe = crtc->index;
1146         struct amdgpu_device *adev = dev->dev_private;
1147         int vpos, hpos, stat;
1148         u32 count;
1149
1150         if (pipe >= adev->mode_info.num_crtc) {
1151                 DRM_ERROR("Invalid crtc %u\n", pipe);
1152                 return -EINVAL;
1153         }
1154
1155         /* The hw increments its frame counter at start of vsync, not at start
1156          * of vblank, as is required by DRM core vblank counter handling.
1157          * Cook the hw count here to make it appear to the caller as if it
1158          * incremented at start of vblank. We measure distance to start of
1159          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1160          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1161          * result by 1 to give the proper appearance to caller.
1162          */
1163         if (adev->mode_info.crtcs[pipe]) {
1164                 /* Repeat readout if needed to provide stable result if
1165                  * we cross start of vsync during the queries.
1166                  */
1167                 do {
1168                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1169                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1170                          * vpos as distance to start of vblank, instead of
1171                          * regular vertical scanout pos.
1172                          */
1173                         stat = amdgpu_display_get_crtc_scanoutpos(
1174                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1175                                 &vpos, &hpos, NULL, NULL,
1176                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1177                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1178
1179                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1180                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1181                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1182                 } else {
1183                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1184                                       pipe, vpos);
1185
1186                         /* Bump counter if we are at >= leading edge of vblank,
1187                          * but before vsync where vpos would turn negative and
1188                          * the hw counter really increments.
1189                          */
1190                         if (vpos >= 0)
1191                                 count++;
1192                 }
1193         } else {
1194                 /* Fallback to use value as is. */
1195                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1196                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1197         }
1198
1199         return count;
1200 }
1201
1202 /**
1203  * amdgpu_enable_vblank_kms - enable vblank interrupt
1204  *
1205  * @crtc: crtc to enable vblank interrupt for
1206  *
1207  * Enable the interrupt on the requested crtc (all asics).
1208  * Returns 0 on success, -EINVAL on failure.
1209  */
1210 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1211 {
1212         struct drm_device *dev = crtc->dev;
1213         unsigned int pipe = crtc->index;
1214         struct amdgpu_device *adev = dev->dev_private;
1215         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1216
1217         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1218 }
1219
1220 /**
1221  * amdgpu_disable_vblank_kms - disable vblank interrupt
1222  *
1223  * @crtc: crtc to disable vblank interrupt for
1224  *
1225  * Disable the interrupt on the requested crtc (all asics).
1226  */
1227 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1228 {
1229         struct drm_device *dev = crtc->dev;
1230         unsigned int pipe = crtc->index;
1231         struct amdgpu_device *adev = dev->dev_private;
1232         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1233
1234         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1235 }
1236
1237 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1238         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1239         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1240         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1241         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1242         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1243         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1244         /* KMS */
1245         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1246         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1247         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1248         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1249         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1250         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1251         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1252         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1253         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1254         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1255 };
1256 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1257
1258 /*
1259  * Debugfs info
1260  */
1261 #if defined(CONFIG_DEBUG_FS)
1262
1263 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1264 {
1265         struct drm_info_node *node = (struct drm_info_node *) m->private;
1266         struct drm_device *dev = node->minor->dev;
1267         struct amdgpu_device *adev = dev->dev_private;
1268         struct drm_amdgpu_info_firmware fw_info;
1269         struct drm_amdgpu_query_fw query_fw;
1270         struct atom_context *ctx = adev->mode_info.atom_context;
1271         int ret, i;
1272
1273         /* VCE */
1274         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1275         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1276         if (ret)
1277                 return ret;
1278         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1279                    fw_info.feature, fw_info.ver);
1280
1281         /* UVD */
1282         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1283         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1284         if (ret)
1285                 return ret;
1286         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1287                    fw_info.feature, fw_info.ver);
1288
1289         /* GMC */
1290         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1291         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1292         if (ret)
1293                 return ret;
1294         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1295                    fw_info.feature, fw_info.ver);
1296
1297         /* ME */
1298         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1299         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1300         if (ret)
1301                 return ret;
1302         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1303                    fw_info.feature, fw_info.ver);
1304
1305         /* PFP */
1306         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1307         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1308         if (ret)
1309                 return ret;
1310         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1311                    fw_info.feature, fw_info.ver);
1312
1313         /* CE */
1314         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1315         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1316         if (ret)
1317                 return ret;
1318         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1319                    fw_info.feature, fw_info.ver);
1320
1321         /* RLC */
1322         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1323         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1324         if (ret)
1325                 return ret;
1326         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1327                    fw_info.feature, fw_info.ver);
1328
1329         /* RLC SAVE RESTORE LIST CNTL */
1330         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1331         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1332         if (ret)
1333                 return ret;
1334         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1335                    fw_info.feature, fw_info.ver);
1336
1337         /* RLC SAVE RESTORE LIST GPM MEM */
1338         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1339         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1340         if (ret)
1341                 return ret;
1342         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1343                    fw_info.feature, fw_info.ver);
1344
1345         /* RLC SAVE RESTORE LIST SRM MEM */
1346         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1347         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1348         if (ret)
1349                 return ret;
1350         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1351                    fw_info.feature, fw_info.ver);
1352
1353         /* MEC */
1354         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1355         query_fw.index = 0;
1356         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1357         if (ret)
1358                 return ret;
1359         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1360                    fw_info.feature, fw_info.ver);
1361
1362         /* MEC2 */
1363         if (adev->gfx.mec2_fw) {
1364                 query_fw.index = 1;
1365                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1366                 if (ret)
1367                         return ret;
1368                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1369                            fw_info.feature, fw_info.ver);
1370         }
1371
1372         /* PSP SOS */
1373         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1374         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1375         if (ret)
1376                 return ret;
1377         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1378                    fw_info.feature, fw_info.ver);
1379
1380
1381         /* PSP ASD */
1382         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1383         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1384         if (ret)
1385                 return ret;
1386         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1387                    fw_info.feature, fw_info.ver);
1388
1389         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1390         for (i = 0; i < 2; i++) {
1391                 query_fw.index = i;
1392                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1393                 if (ret)
1394                         continue;
1395                 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n",
1396                                 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver);
1397         }
1398
1399         /* SMC */
1400         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1401         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1402         if (ret)
1403                 return ret;
1404         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1405                    fw_info.feature, fw_info.ver);
1406
1407         /* SDMA */
1408         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1409         for (i = 0; i < adev->sdma.num_instances; i++) {
1410                 query_fw.index = i;
1411                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1412                 if (ret)
1413                         return ret;
1414                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1415                            i, fw_info.feature, fw_info.ver);
1416         }
1417
1418         /* VCN */
1419         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1420         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1421         if (ret)
1422                 return ret;
1423         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1424                    fw_info.feature, fw_info.ver);
1425
1426         /* DMCU */
1427         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1428         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1429         if (ret)
1430                 return ret;
1431         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1432                    fw_info.feature, fw_info.ver);
1433
1434         /* DMCUB */
1435         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1436         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1437         if (ret)
1438                 return ret;
1439         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1440                    fw_info.feature, fw_info.ver);
1441
1442
1443         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1444
1445         return 0;
1446 }
1447
1448 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1449         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1450 };
1451 #endif
1452
1453 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1454 {
1455 #if defined(CONFIG_DEBUG_FS)
1456         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1457                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1458 #else
1459         return 0;
1460 #endif
1461 }