drivers/gpu/drm/stm/ltdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2017
   4  *
   5  * Authors: Philippe Cornu <[email protected]>
   6  *          Yannick Fertre <[email protected]>
   7  *          Fabien Dessenne <[email protected]>
   8  *          Mickael Reulier <[email protected]>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/media-bus-format.h>
  16 #include <linux/module.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset.h>
  23
  24 #include <drm/drm_atomic.h>
  25 #include <drm/drm_atomic_helper.h>
  26 #include <drm/drm_blend.h>
  27 #include <drm/drm_bridge.h>
  28 #include <drm/drm_device.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_fb_dma_helper.h>
  31 #include <drm/drm_fourcc.h>
  32 #include <drm/drm_framebuffer.h>
  33 #include <drm/drm_gem_atomic_helper.h>
  34 #include <drm/drm_gem_dma_helper.h>
  35 #include <drm/drm_of.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_vblank.h>
  39
  40 #include <video/videomode.h>
  41
  42 #include "ltdc.h"
  43
  44 #define NB_CRTC 1
  45 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
  46
  47 #define MAX_IRQ 4
  48
  49 #define HWVER_10200 0x010200
  50 #define HWVER_10300 0x010300
  51 #define HWVER_20101 0x020101
  52 #define HWVER_40100 0x040100
  53
  54 /*
  55  * The address of some registers depends on the HW version: such registers have
  56  * an extra offset specified with layer_ofs.
  57  */
  58 #define LAY_OFS_0       0x80
  59 #define LAY_OFS_1       0x100
  60 #define LAY_OFS (ldev->caps.layer_ofs)
  61
  62 /* Global register offsets */
  63 #define LTDC_IDR        0x0000          /* IDentification */
  64 #define LTDC_LCR        0x0004          /* Layer Count */
  65 #define LTDC_SSCR       0x0008          /* Synchronization Size Configuration */
  66 #define LTDC_BPCR       0x000C          /* Back Porch Configuration */
  67 #define LTDC_AWCR       0x0010          /* Active Width Configuration */
  68 #define LTDC_TWCR       0x0014          /* Total Width Configuration */
  69 #define LTDC_GCR        0x0018          /* Global Control */
  70 #define LTDC_GC1R       0x001C          /* Global Configuration 1 */
  71 #define LTDC_GC2R       0x0020          /* Global Configuration 2 */
  72 #define LTDC_SRCR       0x0024          /* Shadow Reload Configuration */
  73 #define LTDC_GACR       0x0028          /* GAmma Correction */
  74 #define LTDC_BCCR       0x002C          /* Background Color Configuration */
  75 #define LTDC_IER        0x0034          /* Interrupt Enable */
  76 #define LTDC_ISR        0x0038          /* Interrupt Status */
  77 #define LTDC_ICR        0x003C          /* Interrupt Clear */
  78 #define LTDC_LIPCR      0x0040          /* Line Interrupt Position Conf. */
  79 #define LTDC_CPSR       0x0044          /* Current Position Status */
  80 #define LTDC_CDSR       0x0048          /* Current Display Status */
  81 #define LTDC_EDCR       0x0060          /* External Display Control */
  82 #define LTDC_CCRCR      0x007C          /* Computed CRC value */
  83 #define LTDC_FUT        0x0090          /* Fifo underrun Threshold */
  84
  85 /* Layer register offsets */
  86 #define LTDC_L1C0R      (ldev->caps.layer_regs[0])      /* L1 configuration 0 */
  87 #define LTDC_L1C1R      (ldev->caps.layer_regs[1])      /* L1 configuration 1 */
  88 #define LTDC_L1RCR      (ldev->caps.layer_regs[2])      /* L1 reload control */
  89 #define LTDC_L1CR       (ldev->caps.layer_regs[3])      /* L1 control register */
  90 #define LTDC_L1WHPCR    (ldev->caps.layer_regs[4])      /* L1 window horizontal position configuration */
  91 #define LTDC_L1WVPCR    (ldev->caps.layer_regs[5])      /* L1 window vertical position configuration */
  92 #define LTDC_L1CKCR     (ldev->caps.layer_regs[6])      /* L1 color keying configuration */
  93 #define LTDC_L1PFCR     (ldev->caps.layer_regs[7])      /* L1 pixel format configuration */
  94 #define LTDC_L1CACR     (ldev->caps.layer_regs[8])      /* L1 constant alpha configuration */
  95 #define LTDC_L1DCCR     (ldev->caps.layer_regs[9])      /* L1 default color configuration */
  96 #define LTDC_L1BFCR     (ldev->caps.layer_regs[10])     /* L1 blending factors configuration */
  97 #define LTDC_L1BLCR     (ldev->caps.layer_regs[11])     /* L1 burst length configuration */
  98 #define LTDC_L1PCR      (ldev->caps.layer_regs[12])     /* L1 planar configuration */
  99 #define LTDC_L1CFBAR    (ldev->caps.layer_regs[13])     /* L1 color frame buffer address */
 100 #define LTDC_L1CFBLR    (ldev->caps.layer_regs[14])     /* L1 color frame buffer length */
 101 #define LTDC_L1CFBLNR   (ldev->caps.layer_regs[15])     /* L1 color frame buffer line number */
 102 #define LTDC_L1AFBA0R   (ldev->caps.layer_regs[16])     /* L1 auxiliary frame buffer address 0 */
 103 #define LTDC_L1AFBA1R   (ldev->caps.layer_regs[17])     /* L1 auxiliary frame buffer address 1 */
 104 #define LTDC_L1AFBLR    (ldev->caps.layer_regs[18])     /* L1 auxiliary frame buffer length */
 105 #define LTDC_L1AFBLNR   (ldev->caps.layer_regs[19])     /* L1 auxiliary frame buffer line number */
 106 #define LTDC_L1CLUTWR   (ldev->caps.layer_regs[20])     /* L1 CLUT write */
 107 #define LTDC_L1CYR0R    (ldev->caps.layer_regs[21])     /* L1 Conversion YCbCr RGB 0 */
 108 #define LTDC_L1CYR1R    (ldev->caps.layer_regs[22])     /* L1 Conversion YCbCr RGB 1 */
 109 #define LTDC_L1FPF0R    (ldev->caps.layer_regs[23])     /* L1 Flexible Pixel Format 0 */
 110 #define LTDC_L1FPF1R    (ldev->caps.layer_regs[24])     /* L1 Flexible Pixel Format 1 */
 111
 112 /* Bit definitions */
 113 #define SSCR_VSH        GENMASK(10, 0)  /* Vertical Synchronization Height */
 114 #define SSCR_HSW        GENMASK(27, 16) /* Horizontal Synchronization Width */
 115
 116 #define BPCR_AVBP       GENMASK(10, 0)  /* Accumulated Vertical Back Porch */
 117 #define BPCR_AHBP       GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
 118
 119 #define AWCR_AAH        GENMASK(10, 0)  /* Accumulated Active Height */
 120 #define AWCR_AAW        GENMASK(27, 16) /* Accumulated Active Width */
 121
 122 #define TWCR_TOTALH     GENMASK(10, 0)  /* TOTAL Height */
 123 #define TWCR_TOTALW     GENMASK(27, 16) /* TOTAL Width */
 124
 125 #define GCR_LTDCEN      BIT(0)          /* LTDC ENable */
 126 #define GCR_DEN         BIT(16)         /* Dither ENable */
 127 #define GCR_CRCEN       BIT(19)         /* CRC ENable */
 128 #define GCR_PCPOL       BIT(28)         /* Pixel Clock POLarity-Inverted */
 129 #define GCR_DEPOL       BIT(29)         /* Data Enable POLarity-High */
 130 #define GCR_VSPOL       BIT(30)         /* Vertical Synchro POLarity-High */
 131 #define GCR_HSPOL       BIT(31)         /* Horizontal Synchro POLarity-High */
 132
 133 #define GC1R_WBCH       GENMASK(3, 0)   /* Width of Blue CHannel output */
 134 #define GC1R_WGCH       GENMASK(7, 4)   /* Width of Green Channel output */
 135 #define GC1R_WRCH       GENMASK(11, 8)  /* Width of Red Channel output */
 136 #define GC1R_PBEN       BIT(12)         /* Precise Blending ENable */
 137 #define GC1R_DT         GENMASK(15, 14) /* Dithering Technique */
 138 #define GC1R_GCT        GENMASK(19, 17) /* Gamma Correction Technique */
 139 #define GC1R_SHREN      BIT(21)         /* SHadow Registers ENabled */
 140 #define GC1R_BCP        BIT(22)         /* Background Colour Programmable */
 141 #define GC1R_BBEN       BIT(23)         /* Background Blending ENabled */
 142 #define GC1R_LNIP       BIT(24)         /* Line Number IRQ Position */
 143 #define GC1R_TP         BIT(25)         /* Timing Programmable */
 144 #define GC1R_IPP        BIT(26)         /* IRQ Polarity Programmable */
 145 #define GC1R_SPP        BIT(27)         /* Sync Polarity Programmable */
 146 #define GC1R_DWP        BIT(28)         /* Dither Width Programmable */
 147 #define GC1R_STREN      BIT(29)         /* STatus Registers ENabled */
 148 #define GC1R_BMEN       BIT(31)         /* Blind Mode ENabled */
 149
 150 #define GC2R_EDCA       BIT(0)          /* External Display Control Ability  */
 151 #define GC2R_STSAEN     BIT(1)          /* Slave Timing Sync Ability ENabled */
 152 #define GC2R_DVAEN      BIT(2)          /* Dual-View Ability ENabled */
 153 #define GC2R_DPAEN      BIT(3)          /* Dual-Port Ability ENabled */
 154 #define GC2R_BW         GENMASK(6, 4)   /* Bus Width (log2 of nb of bytes) */
 155 #define GC2R_EDCEN      BIT(7)          /* External Display Control ENabled */
 156
 157 #define SRCR_IMR        BIT(0)          /* IMmediate Reload */
 158 #define SRCR_VBR        BIT(1)          /* Vertical Blanking Reload */
 159
 160 #define BCCR_BCBLACK    0x00            /* Background Color BLACK */
 161 #define BCCR_BCBLUE     GENMASK(7, 0)   /* Background Color BLUE */
 162 #define BCCR_BCGREEN    GENMASK(15, 8)  /* Background Color GREEN */
 163 #define BCCR_BCRED      GENMASK(23, 16) /* Background Color RED */
 164 #define BCCR_BCWHITE    GENMASK(23, 0)  /* Background Color WHITE */
 165
 166 #define IER_LIE         BIT(0)          /* Line Interrupt Enable */
 167 #define IER_FUWIE       BIT(1)          /* Fifo Underrun Warning Interrupt Enable */
 168 #define IER_TERRIE      BIT(2)          /* Transfer ERRor Interrupt Enable */
 169 #define IER_RRIE        BIT(3)          /* Register Reload Interrupt Enable */
 170 #define IER_FUEIE       BIT(6)          /* Fifo Underrun Error Interrupt Enable */
 171 #define IER_CRCIE       BIT(7)          /* CRC Error Interrupt Enable */
 172
 173 #define CPSR_CYPOS      GENMASK(15, 0)  /* Current Y position */
 174
 175 #define ISR_LIF         BIT(0)          /* Line Interrupt Flag */
 176 #define ISR_FUWIF       BIT(1)          /* Fifo Underrun Warning Interrupt Flag */
 177 #define ISR_TERRIF      BIT(2)          /* Transfer ERRor Interrupt Flag */
 178 #define ISR_RRIF        BIT(3)          /* Register Reload Interrupt Flag */
 179 #define ISR_FUEIF       BIT(6)          /* Fifo Underrun Error Interrupt Flag */
 180 #define ISR_CRCIF       BIT(7)          /* CRC Error Interrupt Flag */
 181
 182 #define EDCR_OCYEN      BIT(25)         /* Output Conversion to YCbCr 422: ENable */
 183 #define EDCR_OCYSEL     BIT(26)         /* Output Conversion to YCbCr 422: SELection of the CCIR */
 184 #define EDCR_OCYCO      BIT(27)         /* Output Conversion to YCbCr 422: Chrominance Order */
 185
 186 #define LXCR_LEN        BIT(0)          /* Layer ENable */
 187 #define LXCR_COLKEN     BIT(1)          /* Color Keying Enable */
 188 #define LXCR_CLUTEN     BIT(4)          /* Color Look-Up Table ENable */
 189 #define LXCR_HMEN       BIT(8)          /* Horizontal Mirroring ENable */
 190
 191 #define LXWHPCR_WHSTPOS GENMASK(11, 0)  /* Window Horizontal StarT POSition */
 192 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
 193
 194 #define LXWVPCR_WVSTPOS GENMASK(10, 0)  /* Window Vertical StarT POSition */
 195 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
 196
 197 #define LXPFCR_PF       GENMASK(2, 0)   /* Pixel Format */
 198 #define PF_FLEXIBLE     0x7             /* Flexible Pixel Format selected */
 199
 200 #define LXCACR_CONSTA   GENMASK(7, 0)   /* CONSTant Alpha */
 201
 202 #define LXBFCR_BF2      GENMASK(2, 0)   /* Blending Factor 2 */
 203 #define LXBFCR_BF1      GENMASK(10, 8)  /* Blending Factor 1 */
 204 #define LXBFCR_BOR      GENMASK(18, 16) /* Blending ORder */
 205
 206 #define LXCFBLR_CFBLL   GENMASK(12, 0)  /* Color Frame Buffer Line Length */
 207 #define LXCFBLR_CFBP    GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */
 208
 209 #define LXCFBLNR_CFBLN  GENMASK(10, 0)  /* Color Frame Buffer Line Number */
 210
 211 #define LXCR_C1R_YIA    BIT(0)          /* Ycbcr 422 Interleaved Ability */
 212 #define LXCR_C1R_YSPA   BIT(1)          /* Ycbcr 420 Semi-Planar Ability */
 213 #define LXCR_C1R_YFPA   BIT(2)          /* Ycbcr 420 Full-Planar Ability */
 214 #define LXCR_C1R_SCA    BIT(31)         /* SCaling Ability*/
 215
 216 #define LxPCR_YREN      BIT(9)          /* Y Rescale Enable for the color dynamic range */
 217 #define LxPCR_OF        BIT(8)          /* Odd pixel First */
 218 #define LxPCR_CBF       BIT(7)          /* CB component First */
 219 #define LxPCR_YF        BIT(6)          /* Y component First */
 220 #define LxPCR_YCM       GENMASK(5, 4)   /* Ycbcr Conversion Mode */
 221 #define YCM_I           0x0             /* Interleaved 422 */
 222 #define YCM_SP          0x1             /* Semi-Planar 420 */
 223 #define YCM_FP          0x2             /* Full-Planar 420 */
 224 #define LxPCR_YCEN      BIT(3)          /* YCbCr-to-RGB Conversion Enable */
 225
 226 #define LXRCR_IMR       BIT(0)          /* IMmediate Reload */
 227 #define LXRCR_VBR       BIT(1)          /* Vertical Blanking Reload */
 228 #define LXRCR_GRMSK     BIT(2)          /* Global (centralized) Reload MaSKed */
 229
 230 #define CLUT_SIZE       256
 231
 232 #define CONSTA_MAX      0xFF            /* CONSTant Alpha MAX= 1.0 */
 233 #define BF1_PAXCA       0x600           /* Pixel Alpha x Constant Alpha */
 234 #define BF1_CA          0x400           /* Constant Alpha */
 235 #define BF2_1PAXCA      0x007           /* 1 - (Pixel Alpha x Constant Alpha) */
 236 #define BF2_1CA         0x005           /* 1 - Constant Alpha */
 237
 238 #define NB_PF           8               /* Max nb of HW pixel format */
 239
 240 #define FUT_DFT         128             /* Default value of fifo underrun threshold */
 241
 242 /*
 243  * Skip the first value and the second in case CRC was enabled during
 244  * the thread irq. This is to be sure CRC value is relevant for the
 245  * frame.
 246  */
 247 #define CRC_SKIP_FRAMES 2
 248
 249 enum ltdc_pix_fmt {
 250         PF_NONE,
 251         /* RGB formats */
 252         PF_ARGB8888,            /* ARGB [32 bits] */
 253         PF_RGBA8888,            /* RGBA [32 bits] */
 254         PF_ABGR8888,            /* ABGR [32 bits] */
 255         PF_BGRA8888,            /* BGRA [32 bits] */
 256         PF_RGB888,              /* RGB [24 bits] */
 257         PF_BGR888,              /* BGR [24 bits] */
 258         PF_RGB565,              /* RGB [16 bits] */
 259         PF_BGR565,              /* BGR [16 bits] */
 260         PF_ARGB1555,            /* ARGB A:1 bit RGB:15 bits [16 bits] */
 261         PF_ARGB4444,            /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
 262         /* Indexed formats */
 263         PF_L8,                  /* Indexed 8 bits [8 bits] */
 264         PF_AL44,                /* Alpha:4 bits + indexed 4 bits [8 bits] */
 265         PF_AL88                 /* Alpha:8 bits + indexed 8 bits [16 bits] */
 266 };
 267
 268 /* The index gives the encoding of the pixel format for an HW version */
 269 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
 270         PF_ARGB8888,            /* 0x00 */
 271         PF_RGB888,              /* 0x01 */
 272         PF_RGB565,              /* 0x02 */
 273         PF_ARGB1555,            /* 0x03 */
 274         PF_ARGB4444,            /* 0x04 */
 275         PF_L8,                  /* 0x05 */
 276         PF_AL44,                /* 0x06 */
 277         PF_AL88                 /* 0x07 */
 278 };
 279
 280 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
 281         PF_ARGB8888,            /* 0x00 */
 282         PF_RGB888,              /* 0x01 */
 283         PF_RGB565,              /* 0x02 */
 284         PF_RGBA8888,            /* 0x03 */
 285         PF_AL44,                /* 0x04 */
 286         PF_L8,                  /* 0x05 */
 287         PF_ARGB1555,            /* 0x06 */
 288         PF_ARGB4444             /* 0x07 */
 289 };
 290
 291 static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = {
 292         PF_ARGB8888,            /* 0x00 */
 293         PF_ABGR8888,            /* 0x01 */
 294         PF_RGBA8888,            /* 0x02 */
 295         PF_BGRA8888,            /* 0x03 */
 296         PF_RGB565,              /* 0x04 */
 297         PF_BGR565,              /* 0x05 */
 298         PF_RGB888,              /* 0x06 */
 299         PF_NONE                 /* 0x07 */
 300 };
 301
 302 static const u32 ltdc_drm_fmt_a0[] = {
 303         DRM_FORMAT_ARGB8888,
 304         DRM_FORMAT_XRGB8888,
 305         DRM_FORMAT_RGB888,
 306         DRM_FORMAT_RGB565,
 307         DRM_FORMAT_ARGB1555,
 308         DRM_FORMAT_XRGB1555,
 309         DRM_FORMAT_ARGB4444,
 310         DRM_FORMAT_XRGB4444,
 311         DRM_FORMAT_C8
 312 };
 313
 314 static const u32 ltdc_drm_fmt_a1[] = {
 315         DRM_FORMAT_ARGB8888,
 316         DRM_FORMAT_XRGB8888,
 317         DRM_FORMAT_RGB888,
 318         DRM_FORMAT_RGB565,
 319         DRM_FORMAT_RGBA8888,
 320         DRM_FORMAT_RGBX8888,
 321         DRM_FORMAT_ARGB1555,
 322         DRM_FORMAT_XRGB1555,
 323         DRM_FORMAT_ARGB4444,
 324         DRM_FORMAT_XRGB4444,
 325         DRM_FORMAT_C8
 326 };
 327
 328 static const u32 ltdc_drm_fmt_a2[] = {
 329         DRM_FORMAT_ARGB8888,
 330         DRM_FORMAT_XRGB8888,
 331         DRM_FORMAT_ABGR8888,
 332         DRM_FORMAT_XBGR8888,
 333         DRM_FORMAT_RGBA8888,
 334         DRM_FORMAT_RGBX8888,
 335         DRM_FORMAT_BGRA8888,
 336         DRM_FORMAT_BGRX8888,
 337         DRM_FORMAT_RGB565,
 338         DRM_FORMAT_BGR565,
 339         DRM_FORMAT_RGB888,
 340         DRM_FORMAT_BGR888,
 341         DRM_FORMAT_ARGB1555,
 342         DRM_FORMAT_XRGB1555,
 343         DRM_FORMAT_ARGB4444,
 344         DRM_FORMAT_XRGB4444,
 345         DRM_FORMAT_C8
 346 };
 347
 348 static const u32 ltdc_drm_fmt_ycbcr_cp[] = {
 349         DRM_FORMAT_YUYV,
 350         DRM_FORMAT_YVYU,
 351         DRM_FORMAT_UYVY,
 352         DRM_FORMAT_VYUY
 353 };
 354
 355 static const u32 ltdc_drm_fmt_ycbcr_sp[] = {
 356         DRM_FORMAT_NV12,
 357         DRM_FORMAT_NV21
 358 };
 359
 360 static const u32 ltdc_drm_fmt_ycbcr_fp[] = {
 361         DRM_FORMAT_YUV420,
 362         DRM_FORMAT_YVU420
 363 };
 364
 365 /* Layer register offsets */
 366 static const u32 ltdc_layer_regs_a0[] = {
 367         0x80,   /* L1 configuration 0 */
 368         0x00,   /* not available */
 369         0x00,   /* not available */
 370         0x84,   /* L1 control register */
 371         0x88,   /* L1 window horizontal position configuration */
 372         0x8c,   /* L1 window vertical position configuration */
 373         0x90,   /* L1 color keying configuration */
 374         0x94,   /* L1 pixel format configuration */
 375         0x98,   /* L1 constant alpha configuration */
 376         0x9c,   /* L1 default color configuration */
 377         0xa0,   /* L1 blending factors configuration */
 378         0x00,   /* not available */
 379         0x00,   /* not available */
 380         0xac,   /* L1 color frame buffer address */
 381         0xb0,   /* L1 color frame buffer length */
 382         0xb4,   /* L1 color frame buffer line number */
 383         0x00,   /* not available */
 384         0x00,   /* not available */
 385         0x00,   /* not available */
 386         0x00,   /* not available */
 387         0xc4,   /* L1 CLUT write */
 388         0x00,   /* not available */
 389         0x00,   /* not available */
 390         0x00,   /* not available */
 391         0x00    /* not available */
 392 };
 393
 394 static const u32 ltdc_layer_regs_a1[] = {
 395         0x80,   /* L1 configuration 0 */
 396         0x84,   /* L1 configuration 1 */
 397         0x00,   /* L1 reload control */
 398         0x88,   /* L1 control register */
 399         0x8c,   /* L1 window horizontal position configuration */
 400         0x90,   /* L1 window vertical position configuration */
 401         0x94,   /* L1 color keying configuration */
 402         0x98,   /* L1 pixel format configuration */
 403         0x9c,   /* L1 constant alpha configuration */
 404         0xa0,   /* L1 default color configuration */
 405         0xa4,   /* L1 blending factors configuration */
 406         0xa8,   /* L1 burst length configuration */
 407         0x00,   /* not available */
 408         0xac,   /* L1 color frame buffer address */
 409         0xb0,   /* L1 color frame buffer length */
 410         0xb4,   /* L1 color frame buffer line number */
 411         0xb8,   /* L1 auxiliary frame buffer address 0 */
 412         0xbc,   /* L1 auxiliary frame buffer address 1 */
 413         0xc0,   /* L1 auxiliary frame buffer length */
 414         0xc4,   /* L1 auxiliary frame buffer line number */
 415         0xc8,   /* L1 CLUT write */
 416         0x00,   /* not available */
 417         0x00,   /* not available */
 418         0x00,   /* not available */
 419         0x00    /* not available */
 420 };
 421
 422 static const u32 ltdc_layer_regs_a2[] = {
 423         0x100,  /* L1 configuration 0 */
 424         0x104,  /* L1 configuration 1 */
 425         0x108,  /* L1 reload control */
 426         0x10c,  /* L1 control register */
 427         0x110,  /* L1 window horizontal position configuration */
 428         0x114,  /* L1 window vertical position configuration */
 429         0x118,  /* L1 color keying configuration */
 430         0x11c,  /* L1 pixel format configuration */
 431         0x120,  /* L1 constant alpha configuration */
 432         0x124,  /* L1 default color configuration */
 433         0x128,  /* L1 blending factors configuration */
 434         0x12c,  /* L1 burst length configuration */
 435         0x130,  /* L1 planar configuration */
 436         0x134,  /* L1 color frame buffer address */
 437         0x138,  /* L1 color frame buffer length */
 438         0x13c,  /* L1 color frame buffer line number */
 439         0x140,  /* L1 auxiliary frame buffer address 0 */
 440         0x144,  /* L1 auxiliary frame buffer address 1 */
 441         0x148,  /* L1 auxiliary frame buffer length */
 442         0x14c,  /* L1 auxiliary frame buffer line number */
 443         0x150,  /* L1 CLUT write */
 444         0x16c,  /* L1 Conversion YCbCr RGB 0 */
 445         0x170,  /* L1 Conversion YCbCr RGB 1 */
 446         0x174,  /* L1 Flexible Pixel Format 0 */
 447         0x178   /* L1 Flexible Pixel Format 1 */
 448 };
 449
 450 static const u64 ltdc_format_modifiers[] = {
 451         DRM_FORMAT_MOD_LINEAR,
 452         DRM_FORMAT_MOD_INVALID
 453 };
 454
 455 static const struct regmap_config stm32_ltdc_regmap_cfg = {
 456         .reg_bits = 32,
 457         .val_bits = 32,
 458         .reg_stride = sizeof(u32),
 459         .max_register = 0x400,
 460         .use_relaxed_mmio = true,
 461         .cache_type = REGCACHE_NONE,
 462 };
 463
 464 static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = {
 465         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 466                 0x02040199,     /* (b_cb = 516 / r_cr = 409) */
 467                 0x006400D0      /* (g_cb = 100 / g_cr = 208) */
 468         },
 469         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
 470                 0x01C60167,     /* (b_cb = 454 / r_cr = 359) */
 471                 0x005800B7      /* (g_cb = 88 / g_cr = 183) */
 472         },
 473         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 474                 0x021D01CB,     /* (b_cb = 541 / r_cr = 459) */
 475                 0x00370089      /* (g_cb = 55 / g_cr = 137) */
 476         },
 477         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
 478                 0x01DB0193,     /* (b_cb = 475 / r_cr = 403) */
 479                 0x00300078      /* (g_cb = 48 / g_cr = 120) */
 480         }
 481         /* BT2020 not supported */
 482 };
 483
 484 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
 485 {
 486         return (struct ltdc_device *)crtc->dev->dev_private;
 487 }
 488
 489 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
 490 {
 491         return (struct ltdc_device *)plane->dev->dev_private;
 492 }
 493
 494 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
 495 {
 496         return (struct ltdc_device *)enc->dev->dev_private;
 497 }
 498
 499 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
 500 {
 501         enum ltdc_pix_fmt pf;
 502
 503         switch (drm_fmt) {
 504         case DRM_FORMAT_ARGB8888:
 505         case DRM_FORMAT_XRGB8888:
 506                 pf = PF_ARGB8888;
 507                 break;
 508         case DRM_FORMAT_ABGR8888:
 509         case DRM_FORMAT_XBGR8888:
 510                 pf = PF_ABGR8888;
 511                 break;
 512         case DRM_FORMAT_RGBA8888:
 513         case DRM_FORMAT_RGBX8888:
 514                 pf = PF_RGBA8888;
 515                 break;
 516         case DRM_FORMAT_BGRA8888:
 517         case DRM_FORMAT_BGRX8888:
 518                 pf = PF_BGRA8888;
 519                 break;
 520         case DRM_FORMAT_RGB888:
 521                 pf = PF_RGB888;
 522                 break;
 523         case DRM_FORMAT_BGR888:
 524                 pf = PF_BGR888;
 525                 break;
 526         case DRM_FORMAT_RGB565:
 527                 pf = PF_RGB565;
 528                 break;
 529         case DRM_FORMAT_BGR565:
 530                 pf = PF_BGR565;
 531                 break;
 532         case DRM_FORMAT_ARGB1555:
 533         case DRM_FORMAT_XRGB1555:
 534                 pf = PF_ARGB1555;
 535                 break;
 536         case DRM_FORMAT_ARGB4444:
 537         case DRM_FORMAT_XRGB4444:
 538                 pf = PF_ARGB4444;
 539                 break;
 540         case DRM_FORMAT_C8:
 541                 pf = PF_L8;
 542                 break;
 543         default:
 544                 pf = PF_NONE;
 545                 break;
 546                 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
 547         }
 548
 549         return pf;
 550 }
 551
 552 static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt)
 553 {
 554         struct ltdc_device *ldev = plane_to_ltdc(plane);
 555         u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE;
 556         int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos;
 557
 558         switch (pix_fmt) {
 559         case PF_BGR888:
 560                 psize = 3;
 561                 alen = 0; apos = 0; rlen = 8; rpos = 0;
 562                 glen = 8; gpos = 8; blen = 8; bpos = 16;
 563         break;
 564         case PF_ARGB1555:
 565                 psize = 2;
 566                 alen = 1; apos = 15; rlen = 5; rpos = 10;
 567                 glen = 5; gpos = 5;  blen = 5; bpos = 0;
 568         break;
 569         case PF_ARGB4444:
 570                 psize = 2;
 571                 alen = 4; apos = 12; rlen = 4; rpos = 8;
 572                 glen = 4; gpos = 4; blen = 4; bpos = 0;
 573         break;
 574         case PF_L8:
 575                 psize = 1;
 576                 alen = 0; apos = 0; rlen = 8; rpos = 0;
 577                 glen = 8; gpos = 0; blen = 8; bpos = 0;
 578         break;
 579         case PF_AL44:
 580                 psize = 1;
 581                 alen = 4; apos = 4; rlen = 4; rpos = 0;
 582                 glen = 4; gpos = 0; blen = 4; bpos = 0;
 583         break;
 584         case PF_AL88:
 585                 psize = 2;
 586                 alen = 8; apos = 8; rlen = 8; rpos = 0;
 587                 glen = 8; gpos = 0; blen = 8; bpos = 0;
 588         break;
 589         default:
 590                 ret = NB_PF; /* error case, trace msg is handled by the caller */
 591         break;
 592         }
 593
 594         if (ret == PF_FLEXIBLE) {
 595                 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs,
 596                              (rlen << 14)  + (rpos << 9) + (alen << 5) + apos);
 597
 598                 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs,
 599                              (psize << 18) + (blen << 14)  + (bpos << 9) + (glen << 5) + gpos);
 600         }
 601
 602         return ret;
 603 }
 604
 605 /*
 606  * All non-alpha color formats derived from native alpha color formats are
 607  * either characterized by a FourCC format code
 608  */
 609 static inline u32 is_xrgb(u32 drm)
 610 {
 611         return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X');
 612 }
 613
 614 static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt)
 615 {
 616         struct ltdc_device *ldev = plane_to_ltdc(plane);
 617         struct drm_plane_state *state = plane->state;
 618         u32 lofs = plane->index * LAY_OFS;
 619         u32 val;
 620
 621         switch (drm_pix_fmt) {
 622         case DRM_FORMAT_YUYV:
 623                 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF;
 624                 break;
 625         case DRM_FORMAT_YVYU:
 626                 val = (YCM_I << 4) | LxPCR_YF;
 627                 break;
 628         case DRM_FORMAT_UYVY:
 629                 val = (YCM_I << 4) | LxPCR_CBF;
 630                 break;
 631         case DRM_FORMAT_VYUY:
 632                 val = (YCM_I << 4);
 633                 break;
 634         case DRM_FORMAT_NV12:
 635                 val = (YCM_SP << 4) | LxPCR_CBF;
 636                 break;
 637         case DRM_FORMAT_NV21:
 638                 val = (YCM_SP << 4);
 639                 break;
 640         case DRM_FORMAT_YUV420:
 641         case DRM_FORMAT_YVU420:
 642                 val = (YCM_FP << 4);
 643                 break;
 644         default:
 645                 /* RGB or not a YCbCr supported format */
 646                 DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt);
 647                 return;
 648         }
 649
 650         /* Enable limited range */
 651         if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE)
 652                 val |= LxPCR_YREN;
 653
 654         /* enable ycbcr conversion */
 655         val |= LxPCR_YCEN;
 656
 657         regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val);
 658 }
 659
 660 static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane)
 661 {
 662         struct ltdc_device *ldev = plane_to_ltdc(plane);
 663         struct drm_plane_state *state = plane->state;
 664         enum drm_color_encoding enc = state->color_encoding;
 665         enum drm_color_range ran = state->color_range;
 666         u32 lofs = plane->index * LAY_OFS;
 667
 668         if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) {
 669                 DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc);
 670                 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */
 671                 enc = DRM_COLOR_YCBCR_BT601;
 672         }
 673
 674         if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) {
 675                 DRM_ERROR("color range %d not supported, use limited range by default\n", ran);
 676                 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */
 677                 ran = DRM_COLOR_YCBCR_LIMITED_RANGE;
 678         }
 679
 680         DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran);
 681         regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs,
 682                      ltdc_ycbcr2rgb_coeffs[enc][ran][0]);
 683         regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs,
 684                      ltdc_ycbcr2rgb_coeffs[enc][ran][1]);
 685 }
 686
 687 static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev,
 688                                        struct drm_crtc *crtc)
 689 {
 690         u32 crc;
 691         int ret;
 692
 693         if (ldev->crc_skip_count < CRC_SKIP_FRAMES) {
 694                 ldev->crc_skip_count++;
 695                 return;
 696         }
 697
 698         /* Get the CRC of the frame */
 699         ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc);
 700         if (ret)
 701                 return;
 702
 703         /* Report to DRM the CRC (hw dependent feature) */
 704         drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc);
 705 }
 706
 707 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
 708 {
 709         struct drm_device *ddev = arg;
 710         struct ltdc_device *ldev = ddev->dev_private;
 711         struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
 712
 713         /* Line IRQ : trigger the vblank event */
 714         if (ldev->irq_status & ISR_LIF) {
 715                 drm_crtc_handle_vblank(crtc);
 716
 717                 /* Early return if CRC is not active */
 718                 if (ldev->crc_active)
 719                         ltdc_irq_crc_handle(ldev, crtc);
 720         }
 721
 722         mutex_lock(&ldev->err_lock);
 723         if (ldev->irq_status & ISR_TERRIF)
 724                 ldev->transfer_err++;
 725         if (ldev->irq_status & ISR_FUEIF)
 726                 ldev->fifo_err++;
 727         if (ldev->irq_status & ISR_FUWIF)
 728                 ldev->fifo_warn++;
 729         mutex_unlock(&ldev->err_lock);
 730
 731         return IRQ_HANDLED;
 732 }
 733
 734 static irqreturn_t ltdc_irq(int irq, void *arg)
 735 {
 736         struct drm_device *ddev = arg;
 737         struct ltdc_device *ldev = ddev->dev_private;
 738
 739         /*
 740          *  Read & Clear the interrupt status
 741          *  In order to write / read registers in this critical section
 742          *  very quickly, the regmap functions are not used.
 743          */
 744         ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR);
 745         writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR);
 746
 747         return IRQ_WAKE_THREAD;
 748 }
 749
 750 /*
 751  * DRM_CRTC
 752  */
 753
 754 static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
 755 {
 756         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 757         struct drm_color_lut *lut;
 758         u32 val;
 759         int i;
 760
 761         if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
 762                 return;
 763
 764         lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
 765
 766         for (i = 0; i < CLUT_SIZE; i++, lut++) {
 767                 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
 768                         (lut->blue >> 8) | (i << 24);
 769                 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val);
 770         }
 771 }
 772
 773 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
 774                                     struct drm_atomic_state *state)
 775 {
 776         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 777         struct drm_device *ddev = crtc->dev;
 778
 779         DRM_DEBUG_DRIVER("\n");
 780
 781         pm_runtime_get_sync(ddev->dev);
 782
 783         /* Sets the background color value */
 784         regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK);
 785
 786         /* Enable IRQ */
 787         regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE);
 788
 789         /* Commit shadow registers = update planes at next vblank */
 790         if (!ldev->caps.plane_reg_shadow)
 791                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
 792
 793         drm_crtc_vblank_on(crtc);
 794 }
 795
 796 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
 797                                      struct drm_atomic_state *state)
 798 {
 799         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 800         struct drm_device *ddev = crtc->dev;
 801         int layer_index = 0;
 802
 803         DRM_DEBUG_DRIVER("\n");
 804
 805         drm_crtc_vblank_off(crtc);
 806
 807         /* Disable all layers */
 808         for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++)
 809                 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS,
 810                                   LXCR_CLUTEN | LXCR_LEN, 0);
 811
 812         /* disable IRQ */
 813         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE);
 814
 815         /* immediately commit disable of layers before switching off LTDC */
 816         if (!ldev->caps.plane_reg_shadow)
 817                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
 818
 819         pm_runtime_put_sync(ddev->dev);
 820
 821         /*  clear interrupt error counters */
 822         mutex_lock(&ldev->err_lock);
 823         ldev->transfer_err = 0;
 824         ldev->fifo_err = 0;
 825         ldev->fifo_warn = 0;
 826         mutex_unlock(&ldev->err_lock);
 827 }
 828
 829 #define CLK_TOLERANCE_HZ 50
 830
 831 static enum drm_mode_status
 832 ltdc_crtc_mode_valid(struct drm_crtc *crtc,
 833                      const struct drm_display_mode *mode)
 834 {
 835         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 836         int target = mode->clock * 1000;
 837         int target_min = target - CLK_TOLERANCE_HZ;
 838         int target_max = target + CLK_TOLERANCE_HZ;
 839         int result;
 840
 841         result = clk_round_rate(ldev->pixel_clk, target);
 842
 843         DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
 844
 845         /* Filter modes according to the max frequency supported by the pads */
 846         if (result > ldev->caps.pad_max_freq_hz)
 847                 return MODE_CLOCK_HIGH;
 848
 849         /*
 850          * Accept all "preferred" modes:
 851          * - this is important for panels because panel clock tolerances are
 852          *   bigger than hdmi ones and there is no reason to not accept them
 853          *   (the fps may vary a little but it is not a problem).
 854          * - the hdmi preferred mode will be accepted too, but userland will
 855          *   be able to use others hdmi "valid" modes if necessary.
 856          */
 857         if (mode->type & DRM_MODE_TYPE_PREFERRED)
 858                 return MODE_OK;
 859
 860         /*
 861          * Filter modes according to the clock value, particularly useful for
 862          * hdmi modes that require precise pixel clocks.
 863          */
 864         if (result < target_min || result > target_max)
 865                 return MODE_CLOCK_RANGE;
 866
 867         return MODE_OK;
 868 }
 869
 870 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
 871                                  const struct drm_display_mode *mode,
 872                                  struct drm_display_mode *adjusted_mode)
 873 {
 874         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 875         int rate = mode->clock * 1000;
 876
 877         if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
 878                 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
 879                 return false;
 880         }
 881
 882         adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
 883
 884         DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
 885                          mode->clock, adjusted_mode->clock);
 886
 887         return true;
 888 }
 889
 890 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 891 {
 892         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 893         struct drm_device *ddev = crtc->dev;
 894         struct drm_connector_list_iter iter;
 895         struct drm_connector *connector = NULL;
 896         struct drm_encoder *encoder = NULL, *en_iter;
 897         struct drm_bridge *bridge = NULL, *br_iter;
 898         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 899         u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
 900         u32 total_width, total_height;
 901         u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24;
 902         u32 bus_flags = 0;
 903         u32 val;
 904         int ret;
 905
 906         /* get encoder from crtc */
 907         drm_for_each_encoder(en_iter, ddev)
 908                 if (en_iter->crtc == crtc) {
 909                         encoder = en_iter;
 910                         break;
 911                 }
 912
 913         if (encoder) {
 914                 /* get bridge from encoder */
 915                 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node)
 916                         if (br_iter->encoder == encoder) {
 917                                 bridge = br_iter;
 918                                 break;
 919                         }
 920
 921                 /* Get the connector from encoder */
 922                 drm_connector_list_iter_begin(ddev, &iter);
 923                 drm_for_each_connector_iter(connector, &iter)
 924                         if (connector->encoder == encoder)
 925                                 break;
 926                 drm_connector_list_iter_end(&iter);
 927         }
 928
 929         if (bridge && bridge->timings) {
 930                 bus_flags = bridge->timings->input_bus_flags;
 931         } else if (connector) {
 932                 bus_flags = connector->display_info.bus_flags;
 933                 if (connector->display_info.num_bus_formats)
 934                         bus_formats = connector->display_info.bus_formats[0];
 935         }
 936
 937         if (!pm_runtime_active(ddev->dev)) {
 938                 ret = pm_runtime_get_sync(ddev->dev);
 939                 if (ret) {
 940                         DRM_ERROR("Failed to set mode, cannot get sync\n");
 941                         return;
 942                 }
 943         }
 944
 945         DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
 946         DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay);
 947         DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
 948                          mode->hsync_start - mode->hdisplay,
 949                          mode->htotal - mode->hsync_end,
 950                          mode->hsync_end - mode->hsync_start,
 951                          mode->vsync_start - mode->vdisplay,
 952                          mode->vtotal - mode->vsync_end,
 953                          mode->vsync_end - mode->vsync_start);
 954
 955         /* Convert video timings to ltdc timings */
 956         hsync = mode->hsync_end - mode->hsync_start - 1;
 957         vsync = mode->vsync_end - mode->vsync_start - 1;
 958         accum_hbp = mode->htotal - mode->hsync_start - 1;
 959         accum_vbp = mode->vtotal - mode->vsync_start - 1;
 960         accum_act_w = accum_hbp + mode->hdisplay;
 961         accum_act_h = accum_vbp + mode->vdisplay;
 962         total_width = mode->htotal - 1;
 963         total_height = mode->vtotal - 1;
 964
 965         /* Configures the HS, VS, DE and PC polarities. Default Active Low */
 966         val = 0;
 967
 968         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 969                 val |= GCR_HSPOL;
 970
 971         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 972                 val |= GCR_VSPOL;
 973
 974         if (bus_flags & DRM_BUS_FLAG_DE_LOW)
 975                 val |= GCR_DEPOL;
 976
 977         if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 978                 val |= GCR_PCPOL;
 979
 980         regmap_update_bits(ldev->regmap, LTDC_GCR,
 981                            GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
 982
 983         /* Set Synchronization size */
 984         val = (hsync << 16) | vsync;
 985         regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
 986
 987         /* Set Accumulated Back porch */
 988         val = (accum_hbp << 16) | accum_vbp;
 989         regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
 990
 991         /* Set Accumulated Active Width */
 992         val = (accum_act_w << 16) | accum_act_h;
 993         regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
 994
 995         /* Set total width & height */
 996         val = (total_width << 16) | total_height;
 997         regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 998
 999         regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1));
1000
1001         /* Configure the output format (hw version dependent) */
1002         if (ldev->caps.ycbcr_output) {
1003                 /* Input video dynamic_range & colorimetry */
1004                 int vic = drm_match_cea_mode(mode);
1005                 u32 val;
1006
1007                 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 ||
1008                     vic == 2 || vic == 3 || vic == 17 || vic == 18)
1009                         /* ITU-R BT.601 */
1010                         val = 0;
1011                 else
1012                         /* ITU-R BT.709 */
1013                         val = EDCR_OCYSEL;
1014
1015                 switch (bus_formats) {
1016                 case MEDIA_BUS_FMT_YUYV8_1X16:
1017                         /* enable ycbcr output converter */
1018                         regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val);
1019                         break;
1020                 case MEDIA_BUS_FMT_YVYU8_1X16:
1021                         /* enable ycbcr output converter & invert chrominance order */
1022                         regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val);
1023                         break;
1024                 default:
1025                         /* disable ycbcr output converter */
1026                         regmap_write(ldev->regmap, LTDC_EDCR, 0);
1027                         break;
1028                 }
1029         }
1030 }
1031
1032 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
1033                                    struct drm_atomic_state *state)
1034 {
1035         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1036         struct drm_device *ddev = crtc->dev;
1037         struct drm_pending_vblank_event *event = crtc->state->event;
1038
1039         DRM_DEBUG_ATOMIC("\n");
1040
1041         ltdc_crtc_update_clut(crtc);
1042
1043         /* Commit shadow registers = update planes at next vblank */
1044         if (!ldev->caps.plane_reg_shadow)
1045                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
1046
1047         if (event) {
1048                 crtc->state->event = NULL;
1049
1050                 spin_lock_irq(&ddev->event_lock);
1051                 if (drm_crtc_vblank_get(crtc) == 0)
1052                         drm_crtc_arm_vblank_event(crtc, event);
1053                 else
1054                         drm_crtc_send_vblank_event(crtc, event);
1055                 spin_unlock_irq(&ddev->event_lock);
1056         }
1057 }
1058
1059 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
1060                                            bool in_vblank_irq,
1061                                            int *vpos, int *hpos,
1062                                            ktime_t *stime, ktime_t *etime,
1063                                            const struct drm_display_mode *mode)
1064 {
1065         struct drm_device *ddev = crtc->dev;
1066         struct ltdc_device *ldev = ddev->dev_private;
1067         int line, vactive_start, vactive_end, vtotal;
1068
1069         if (stime)
1070                 *stime = ktime_get();
1071
1072         /* The active area starts after vsync + front porch and ends
1073          * at vsync + front porc + display size.
1074          * The total height also include back porch.
1075          * We have 3 possible cases to handle:
1076          * - line < vactive_start: vpos = line - vactive_start and will be
1077          * negative
1078          * - vactive_start < line < vactive_end: vpos = line - vactive_start
1079          * and will be positive
1080          * - line > vactive_end: vpos = line - vtotal - vactive_start
1081          * and will negative
1082          *
1083          * Computation for the two first cases are identical so we can
1084          * simplify the code and only test if line > vactive_end
1085          */
1086         if (pm_runtime_active(ddev->dev)) {
1087                 regmap_read(ldev->regmap, LTDC_CPSR, &line);
1088                 line &= CPSR_CYPOS;
1089                 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start);
1090                 vactive_start &= BPCR_AVBP;
1091                 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end);
1092                 vactive_end &= AWCR_AAH;
1093                 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal);
1094                 vtotal &= TWCR_TOTALH;
1095
1096                 if (line > vactive_end)
1097                         *vpos = line - vtotal - vactive_start;
1098                 else
1099                         *vpos = line - vactive_start;
1100         } else {
1101                 *vpos = 0;
1102         }
1103
1104         *hpos = 0;
1105
1106         if (etime)
1107                 *etime = ktime_get();
1108
1109         return true;
1110 }
1111
1112 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
1113         .mode_valid = ltdc_crtc_mode_valid,
1114         .mode_fixup = ltdc_crtc_mode_fixup,
1115         .mode_set_nofb = ltdc_crtc_mode_set_nofb,
1116         .atomic_flush = ltdc_crtc_atomic_flush,
1117         .atomic_enable = ltdc_crtc_atomic_enable,
1118         .atomic_disable = ltdc_crtc_atomic_disable,
1119         .get_scanout_position = ltdc_crtc_get_scanout_position,
1120 };
1121
1122 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
1123 {
1124         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1125         struct drm_crtc_state *state = crtc->state;
1126
1127         DRM_DEBUG_DRIVER("\n");
1128
1129         if (state->enable)
1130                 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE);
1131         else
1132                 return -EPERM;
1133
1134         return 0;
1135 }
1136
1137 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
1138 {
1139         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1140
1141         DRM_DEBUG_DRIVER("\n");
1142         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE);
1143 }
1144
1145 static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source)
1146 {
1147         struct ltdc_device *ldev;
1148         int ret;
1149
1150         DRM_DEBUG_DRIVER("\n");
1151
1152         if (!crtc)
1153                 return -ENODEV;
1154
1155         ldev = crtc_to_ltdc(crtc);
1156
1157         if (source && strcmp(source, "auto") == 0) {
1158                 ldev->crc_active = true;
1159                 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1160         } else if (!source) {
1161                 ldev->crc_active = false;
1162                 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1163         } else {
1164                 ret = -EINVAL;
1165         }
1166
1167         ldev->crc_skip_count = 0;
1168         return ret;
1169 }
1170
1171 static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc,
1172                                        const char *source, size_t *values_cnt)
1173 {
1174         DRM_DEBUG_DRIVER("\n");
1175
1176         if (!crtc)
1177                 return -ENODEV;
1178
1179         if (source && strcmp(source, "auto") != 0) {
1180                 DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n",
1181                                  source, crtc->name);
1182                 return -EINVAL;
1183         }
1184
1185         *values_cnt = 1;
1186         return 0;
1187 }
1188
1189 static void ltdc_crtc_atomic_print_state(struct drm_printer *p,
1190                                          const struct drm_crtc_state *state)
1191 {
1192         struct drm_crtc *crtc = state->crtc;
1193         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1194
1195         drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err);
1196         drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err);
1197         drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn);
1198         drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold);
1199 }
1200
1201 static const struct drm_crtc_funcs ltdc_crtc_funcs = {
1202         .destroy = drm_crtc_cleanup,
1203         .set_config = drm_atomic_helper_set_config,
1204         .page_flip = drm_atomic_helper_page_flip,
1205         .reset = drm_atomic_helper_crtc_reset,
1206         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1207         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1208         .enable_vblank = ltdc_crtc_enable_vblank,
1209         .disable_vblank = ltdc_crtc_disable_vblank,
1210         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1211         .atomic_print_state = ltdc_crtc_atomic_print_state,
1212 };
1213
1214 static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = {
1215         .destroy = drm_crtc_cleanup,
1216         .set_config = drm_atomic_helper_set_config,
1217         .page_flip = drm_atomic_helper_page_flip,
1218         .reset = drm_atomic_helper_crtc_reset,
1219         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1220         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1221         .enable_vblank = ltdc_crtc_enable_vblank,
1222         .disable_vblank = ltdc_crtc_disable_vblank,
1223         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1224         .set_crc_source = ltdc_crtc_set_crc_source,
1225         .verify_crc_source = ltdc_crtc_verify_crc_source,
1226         .atomic_print_state = ltdc_crtc_atomic_print_state,
1227 };
1228
1229 /*
1230  * DRM_PLANE
1231  */
1232
1233 static int ltdc_plane_atomic_check(struct drm_plane *plane,
1234                                    struct drm_atomic_state *state)
1235 {
1236         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1237                                                                                  plane);
1238         struct drm_framebuffer *fb = new_plane_state->fb;
1239         u32 src_w, src_h;
1240
1241         DRM_DEBUG_DRIVER("\n");
1242
1243         if (!fb)
1244                 return 0;
1245
1246         /* convert src_ from 16:16 format */
1247         src_w = new_plane_state->src_w >> 16;
1248         src_h = new_plane_state->src_h >> 16;
1249
1250         /* Reject scaling */
1251         if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) {
1252                 DRM_DEBUG_DRIVER("Scaling is not supported");
1253
1254                 return -EINVAL;
1255         }
1256
1257         return 0;
1258 }
1259
1260 static void ltdc_plane_atomic_update(struct drm_plane *plane,
1261                                      struct drm_atomic_state *state)
1262 {
1263         struct ltdc_device *ldev = plane_to_ltdc(plane);
1264         struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
1265                                                                           plane);
1266         struct drm_framebuffer *fb = newstate->fb;
1267         u32 lofs = plane->index * LAY_OFS;
1268         u32 x0 = newstate->crtc_x;
1269         u32 x1 = newstate->crtc_x + newstate->crtc_w - 1;
1270         u32 y0 = newstate->crtc_y;
1271         u32 y1 = newstate->crtc_y + newstate->crtc_h - 1;
1272         u32 src_x, src_y, src_w, src_h;
1273         u32 val, pitch_in_bytes, line_length, line_number, ahbp, avbp, bpcr;
1274         u32 paddr, paddr1, paddr2;
1275         enum ltdc_pix_fmt pf;
1276
1277         if (!newstate->crtc || !fb) {
1278                 DRM_DEBUG_DRIVER("fb or crtc NULL");
1279                 return;
1280         }
1281
1282         /* convert src_ from 16:16 format */
1283         src_x = newstate->src_x >> 16;
1284         src_y = newstate->src_y >> 16;
1285         src_w = newstate->src_w >> 16;
1286         src_h = newstate->src_h >> 16;
1287
1288         DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
1289                          plane->base.id, fb->base.id,
1290                          src_w, src_h, src_x, src_y,
1291                          newstate->crtc_w, newstate->crtc_h,
1292                          newstate->crtc_x, newstate->crtc_y);
1293
1294         regmap_read(ldev->regmap, LTDC_BPCR, &bpcr);
1295
1296         ahbp = (bpcr & BPCR_AHBP) >> 16;
1297         avbp = bpcr & BPCR_AVBP;
1298
1299         /* Configures the horizontal start and stop position */
1300         val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
1301         regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs,
1302                           LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
1303
1304         /* Configures the vertical start and stop position */
1305         val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
1306         regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs,
1307                           LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
1308
1309         /* Specifies the pixel format */
1310         pf = to_ltdc_pixelformat(fb->format->format);
1311         for (val = 0; val < NB_PF; val++)
1312                 if (ldev->caps.pix_fmt_hw[val] == pf)
1313                         break;
1314
1315         /* Use the flexible color format feature if necessary and available */
1316         if (ldev->caps.pix_fmt_flex && val == NB_PF)
1317                 val = ltdc_set_flexible_pixel_format(plane, pf);
1318
1319         if (val == NB_PF) {
1320                 DRM_ERROR("Pixel format %.4s not supported\n",
1321                           (char *)&fb->format->format);
1322                 val = 0;        /* set by default ARGB 32 bits */
1323         }
1324         regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
1325
1326         /* Specifies the constant alpha value */
1327         val = newstate->alpha >> 8;
1328         regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
1329
1330         /* Specifies the blending factors */
1331         val = BF1_PAXCA | BF2_1PAXCA;
1332         if (!fb->format->has_alpha)
1333                 val = BF1_CA | BF2_1CA;
1334
1335         /* Manage hw-specific capabilities */
1336         if (ldev->caps.non_alpha_only_l1 &&
1337             plane->type != DRM_PLANE_TYPE_PRIMARY)
1338                 val = BF1_PAXCA | BF2_1PAXCA;
1339
1340         if (ldev->caps.dynamic_zorder) {
1341                 val |= (newstate->normalized_zpos << 16);
1342                 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs,
1343                                   LXBFCR_BF2 | LXBFCR_BF1 | LXBFCR_BOR, val);
1344         } else {
1345                 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs,
1346                                   LXBFCR_BF2 | LXBFCR_BF1, val);
1347         }
1348
1349         /* Sets the FB address */
1350         paddr = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 0);
1351
1352         if (newstate->rotation & DRM_MODE_REFLECT_X)
1353                 paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1;
1354
1355         if (newstate->rotation & DRM_MODE_REFLECT_Y)
1356                 paddr += (fb->pitches[0] * (y1 - y0));
1357
1358         DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
1359         regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr);
1360
1361         /* Configures the color frame buffer pitch in bytes & line length */
1362         line_length = fb->format->cpp[0] *
1363                       (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
1364
1365         if (newstate->rotation & DRM_MODE_REFLECT_Y)
1366                 /* Compute negative value (signed on 16 bits) for the picth */
1367                 pitch_in_bytes = 0x10000 - fb->pitches[0];
1368         else
1369                 pitch_in_bytes = fb->pitches[0];
1370
1371         val = (pitch_in_bytes << 16) | line_length;
1372         regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
1373
1374         /* Configures the frame buffer line number */
1375         line_number = y1 - y0 + 1;
1376         regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number);
1377
1378         if (ldev->caps.ycbcr_input) {
1379                 if (fb->format->is_yuv) {
1380                         switch (fb->format->format) {
1381                         case DRM_FORMAT_NV12:
1382                         case DRM_FORMAT_NV21:
1383                         /* Configure the auxiliary frame buffer address 0 */
1384                         paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1);
1385
1386                         if (newstate->rotation & DRM_MODE_REFLECT_X)
1387                                 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
1388
1389                         if (newstate->rotation & DRM_MODE_REFLECT_Y)
1390                                 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
1391
1392                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1393                         break;
1394                         case DRM_FORMAT_YUV420:
1395                         /* Configure the auxiliary frame buffer address 0 & 1 */
1396                         paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1);
1397                         paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2);
1398
1399                         if (newstate->rotation & DRM_MODE_REFLECT_X) {
1400                                 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
1401                                 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1;
1402                         }
1403
1404                         if (newstate->rotation & DRM_MODE_REFLECT_Y) {
1405                                 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
1406                                 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1;
1407                         }
1408
1409                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1410                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2);
1411                         break;
1412                         case DRM_FORMAT_YVU420:
1413                         /* Configure the auxiliary frame buffer address 0 & 1 */
1414                         paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2);
1415                         paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1);
1416
1417                         if (newstate->rotation & DRM_MODE_REFLECT_X) {
1418                                 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
1419                                 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1;
1420                         }
1421
1422                         if (newstate->rotation & DRM_MODE_REFLECT_Y) {
1423                                 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
1424                                 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1;
1425                         }
1426
1427                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1428                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2);
1429                         break;
1430                         }
1431
1432                         /*
1433                          * Set the length and the number of lines of the auxiliary
1434                          * buffers if the framebuffer contains more than one plane.
1435                          */
1436                         if (fb->format->num_planes > 1) {
1437                                 if (newstate->rotation & DRM_MODE_REFLECT_Y)
1438                                         /*
1439                                          * Compute negative value (signed on 16 bits)
1440                                          * for the picth
1441                                          */
1442                                         pitch_in_bytes = 0x10000 - fb->pitches[1];
1443                                 else
1444                                         pitch_in_bytes = fb->pitches[1];
1445
1446                                 line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) +
1447                                               (ldev->caps.bus_width >> 3) - 1;
1448
1449                                 /* Configure the auxiliary buffer length */
1450                                 val = (pitch_in_bytes << 16) | line_length;
1451                                 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1452
1453                                 /* Configure the auxiliary frame buffer line number */
1454                                 val = line_number >> 1;
1455                                 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1456                         }
1457
1458                         /* Configure YCbC conversion coefficient */
1459                         ltdc_set_ycbcr_coeffs(plane);
1460
1461                         /* Configure YCbCr format and enable/disable conversion */
1462                         ltdc_set_ycbcr_config(plane, fb->format->format);
1463                 } else {
1464                         /* disable ycbcr conversion */
1465                         regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0);
1466                 }
1467         }
1468
1469         /* Enable layer and CLUT if needed */
1470         val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
1471         val |= LXCR_LEN;
1472
1473         /* Enable horizontal mirroring if requested */
1474         if (newstate->rotation & DRM_MODE_REFLECT_X)
1475                 val |= LXCR_HMEN;
1476
1477         regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, val);
1478
1479         /* Commit shadow registers = update plane at next vblank */
1480         if (ldev->caps.plane_reg_shadow)
1481                 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1482                                   LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1483
1484         ldev->plane_fpsi[plane->index].counter++;
1485
1486         mutex_lock(&ldev->err_lock);
1487         if (ldev->transfer_err) {
1488                 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err);
1489                 ldev->transfer_err = 0;
1490         }
1491
1492         if (ldev->caps.fifo_threshold) {
1493                 if (ldev->fifo_err) {
1494                         DRM_WARN("ltdc fifo underrun: please verify display mode\n");
1495                         ldev->fifo_err = 0;
1496                 }
1497         } else {
1498                 if (ldev->fifo_warn >= ldev->fifo_threshold) {
1499                         DRM_WARN("ltdc fifo underrun: please verify display mode\n");
1500                         ldev->fifo_warn = 0;
1501                 }
1502         }
1503         mutex_unlock(&ldev->err_lock);
1504 }
1505
1506 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
1507                                       struct drm_atomic_state *state)
1508 {
1509         struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
1510                                                                           plane);
1511         struct ltdc_device *ldev = plane_to_ltdc(plane);
1512         u32 lofs = plane->index * LAY_OFS;
1513
1514         /* Disable layer */
1515         regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN |  LXCR_HMEN, 0);
1516
1517         /* Commit shadow registers = update plane at next vblank */
1518         if (ldev->caps.plane_reg_shadow)
1519                 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1520                                   LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1521
1522         DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
1523                          oldstate->crtc->base.id, plane->base.id);
1524 }
1525
1526 static void ltdc_plane_atomic_print_state(struct drm_printer *p,
1527                                           const struct drm_plane_state *state)
1528 {
1529         struct drm_plane *plane = state->plane;
1530         struct ltdc_device *ldev = plane_to_ltdc(plane);
1531         struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
1532         int ms_since_last;
1533         ktime_t now;
1534
1535         now = ktime_get();
1536         ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
1537
1538         drm_printf(p, "\tuser_updates=%dfps\n",
1539                    DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
1540
1541         fpsi->last_timestamp = now;
1542         fpsi->counter = 0;
1543 }
1544
1545 static const struct drm_plane_funcs ltdc_plane_funcs = {
1546         .update_plane = drm_atomic_helper_update_plane,
1547         .disable_plane = drm_atomic_helper_disable_plane,
1548         .destroy = drm_plane_cleanup,
1549         .reset = drm_atomic_helper_plane_reset,
1550         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1551         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1552         .atomic_print_state = ltdc_plane_atomic_print_state,
1553 };
1554
1555 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
1556         .atomic_check = ltdc_plane_atomic_check,
1557         .atomic_update = ltdc_plane_atomic_update,
1558         .atomic_disable = ltdc_plane_atomic_disable,
1559 };
1560
1561 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
1562                                            enum drm_plane_type type,
1563                                            int index)
1564 {
1565         unsigned long possible_crtcs = CRTC_MASK;
1566         struct ltdc_device *ldev = ddev->dev_private;
1567         struct device *dev = ddev->dev;
1568         struct drm_plane *plane;
1569         unsigned int i, nb_fmt = 0;
1570         u32 *formats;
1571         u32 drm_fmt;
1572         const u64 *modifiers = ltdc_format_modifiers;
1573         u32 lofs = index * LAY_OFS;
1574         u32 val;
1575         int ret;
1576
1577         /* Allocate the biggest size according to supported color formats */
1578         formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb +
1579                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) +
1580                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) +
1581                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) *
1582                                sizeof(*formats), GFP_KERNEL);
1583
1584         for (i = 0; i < ldev->caps.pix_fmt_nb; i++) {
1585                 drm_fmt = ldev->caps.pix_fmt_drm[i];
1586
1587                 /* Manage hw-specific capabilities */
1588                 if (ldev->caps.non_alpha_only_l1)
1589                         /* XR24 & RX24 like formats supported only on primary layer */
1590                         if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt))
1591                                 continue;
1592
1593                 formats[nb_fmt++] = drm_fmt;
1594         }
1595
1596         /* Add YCbCr supported pixel formats */
1597         if (ldev->caps.ycbcr_input) {
1598                 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val);
1599                 if (val & LXCR_C1R_YIA) {
1600                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp,
1601                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats));
1602                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp);
1603                 }
1604                 if (val & LXCR_C1R_YSPA) {
1605                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp,
1606                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats));
1607                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp);
1608                 }
1609                 if (val & LXCR_C1R_YFPA) {
1610                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp,
1611                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats));
1612                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp);
1613                 }
1614         }
1615
1616         plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
1617         if (!plane)
1618                 return NULL;
1619
1620         ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
1621                                        &ltdc_plane_funcs, formats, nb_fmt,
1622                                        modifiers, type, NULL);
1623         if (ret < 0)
1624                 return NULL;
1625
1626         if (ldev->caps.ycbcr_input) {
1627                 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA))
1628                         drm_plane_create_color_properties(plane,
1629                                                           BIT(DRM_COLOR_YCBCR_BT601) |
1630                                                           BIT(DRM_COLOR_YCBCR_BT709),
1631                                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1632                                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1633                                                           DRM_COLOR_YCBCR_BT601,
1634                                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1635         }
1636
1637         drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
1638
1639         drm_plane_create_alpha_property(plane);
1640
1641         DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
1642
1643         return plane;
1644 }
1645
1646 static void ltdc_plane_destroy_all(struct drm_device *ddev)
1647 {
1648         struct drm_plane *plane, *plane_temp;
1649
1650         list_for_each_entry_safe(plane, plane_temp,
1651                                  &ddev->mode_config.plane_list, head)
1652                 drm_plane_cleanup(plane);
1653 }
1654
1655 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
1656 {
1657         struct ltdc_device *ldev = ddev->dev_private;
1658         struct drm_plane *primary, *overlay;
1659         int supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
1660         unsigned int i;
1661         int ret;
1662
1663         primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0);
1664         if (!primary) {
1665                 DRM_ERROR("Can not create primary plane\n");
1666                 return -EINVAL;
1667         }
1668
1669         if (ldev->caps.dynamic_zorder)
1670                 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1);
1671         else
1672                 drm_plane_create_zpos_immutable_property(primary, 0);
1673
1674         if (ldev->caps.plane_rotation)
1675                 drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0,
1676                                                    supported_rotations);
1677
1678         /* Init CRTC according to its hardware features */
1679         if (ldev->caps.crc)
1680                 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1681                                                 &ltdc_crtc_with_crc_support_funcs, NULL);
1682         else
1683                 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1684                                                 &ltdc_crtc_funcs, NULL);
1685         if (ret) {
1686                 DRM_ERROR("Can not initialize CRTC\n");
1687                 goto cleanup;
1688         }
1689
1690         drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
1691
1692         drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
1693         drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
1694
1695         DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
1696
1697         /* Add planes. Note : the first layer is used by primary plane */
1698         for (i = 1; i < ldev->caps.nb_layers; i++) {
1699                 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i);
1700                 if (!overlay) {
1701                         ret = -ENOMEM;
1702                         DRM_ERROR("Can not create overlay plane %d\n", i);
1703                         goto cleanup;
1704                 }
1705                 if (ldev->caps.dynamic_zorder)
1706                         drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1);
1707                 else
1708                         drm_plane_create_zpos_immutable_property(overlay, i);
1709
1710                 if (ldev->caps.plane_rotation)
1711                         drm_plane_create_rotation_property(overlay, DRM_MODE_ROTATE_0,
1712                                                            supported_rotations);
1713         }
1714
1715         return 0;
1716
1717 cleanup:
1718         ltdc_plane_destroy_all(ddev);
1719         return ret;
1720 }
1721
1722 static void ltdc_encoder_disable(struct drm_encoder *encoder)
1723 {
1724         struct drm_device *ddev = encoder->dev;
1725         struct ltdc_device *ldev = ddev->dev_private;
1726
1727         DRM_DEBUG_DRIVER("\n");
1728
1729         /* Disable LTDC */
1730         regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1731
1732         /* Set to sleep state the pinctrl whatever type of encoder */
1733         pinctrl_pm_select_sleep_state(ddev->dev);
1734 }
1735
1736 static void ltdc_encoder_enable(struct drm_encoder *encoder)
1737 {
1738         struct drm_device *ddev = encoder->dev;
1739         struct ltdc_device *ldev = ddev->dev_private;
1740
1741         DRM_DEBUG_DRIVER("\n");
1742
1743         /* set fifo underrun threshold register */
1744         if (ldev->caps.fifo_threshold)
1745                 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold);
1746
1747         /* Enable LTDC */
1748         regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1749 }
1750
1751 static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
1752                                   struct drm_display_mode *mode,
1753                                   struct drm_display_mode *adjusted_mode)
1754 {
1755         struct drm_device *ddev = encoder->dev;
1756
1757         DRM_DEBUG_DRIVER("\n");
1758
1759         /*
1760          * Set to default state the pinctrl only with DPI type.
1761          * Others types like DSI, don't need pinctrl due to
1762          * internal bridge (the signals do not come out of the chipset).
1763          */
1764         if (encoder->encoder_type == DRM_MODE_ENCODER_DPI)
1765                 pinctrl_pm_select_default_state(ddev->dev);
1766 }
1767
1768 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = {
1769         .disable = ltdc_encoder_disable,
1770         .enable = ltdc_encoder_enable,
1771         .mode_set = ltdc_encoder_mode_set,
1772 };
1773
1774 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
1775 {
1776         struct drm_encoder *encoder;
1777         int ret;
1778
1779         encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
1780         if (!encoder)
1781                 return -ENOMEM;
1782
1783         encoder->possible_crtcs = CRTC_MASK;
1784         encoder->possible_clones = 0;   /* No cloning support */
1785
1786         drm_simple_encoder_init(ddev, encoder, DRM_MODE_ENCODER_DPI);
1787
1788         drm_encoder_helper_add(encoder, &ltdc_encoder_helper_funcs);
1789
1790         ret = drm_bridge_attach(encoder, bridge, NULL, 0);
1791         if (ret) {
1792                 if (ret != -EPROBE_DEFER)
1793                         drm_encoder_cleanup(encoder);
1794                 return ret;
1795         }
1796
1797         DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
1798
1799         return 0;
1800 }
1801
1802 static int ltdc_get_caps(struct drm_device *ddev)
1803 {
1804         struct ltdc_device *ldev = ddev->dev_private;
1805         u32 bus_width_log2, lcr, gc2r;
1806
1807         /*
1808          * at least 1 layer must be managed & the number of layers
1809          * must not exceed LTDC_MAX_LAYER
1810          */
1811         regmap_read(ldev->regmap, LTDC_LCR, &lcr);
1812
1813         ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
1814
1815         /* set data bus width */
1816         regmap_read(ldev->regmap, LTDC_GC2R, &gc2r);
1817         bus_width_log2 = (gc2r & GC2R_BW) >> 4;
1818         ldev->caps.bus_width = 8 << bus_width_log2;
1819         regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
1820
1821         switch (ldev->caps.hw_version) {
1822         case HWVER_10200:
1823         case HWVER_10300:
1824                 ldev->caps.layer_ofs = LAY_OFS_0;
1825                 ldev->caps.layer_regs = ltdc_layer_regs_a0;
1826                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
1827                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0;
1828                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0);
1829                 ldev->caps.pix_fmt_flex = false;
1830                 /*
1831                  * Hw older versions support non-alpha color formats derived
1832                  * from native alpha color formats only on the primary layer.
1833                  * For instance, RG16 native format without alpha works fine
1834                  * on 2nd layer but XR24 (derived color format from AR24)
1835                  * does not work on 2nd layer.
1836                  */
1837                 ldev->caps.non_alpha_only_l1 = true;
1838                 ldev->caps.pad_max_freq_hz = 90000000;
1839                 if (ldev->caps.hw_version == HWVER_10200)
1840                         ldev->caps.pad_max_freq_hz = 65000000;
1841                 ldev->caps.nb_irq = 2;
1842                 ldev->caps.ycbcr_input = false;
1843                 ldev->caps.ycbcr_output = false;
1844                 ldev->caps.plane_reg_shadow = false;
1845                 ldev->caps.crc = false;
1846                 ldev->caps.dynamic_zorder = false;
1847                 ldev->caps.plane_rotation = false;
1848                 ldev->caps.fifo_threshold = false;
1849                 break;
1850         case HWVER_20101:
1851                 ldev->caps.layer_ofs = LAY_OFS_0;
1852                 ldev->caps.layer_regs = ltdc_layer_regs_a1;
1853                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1854                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1;
1855                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1);
1856                 ldev->caps.pix_fmt_flex = false;
1857                 ldev->caps.non_alpha_only_l1 = false;
1858                 ldev->caps.pad_max_freq_hz = 150000000;
1859                 ldev->caps.nb_irq = 4;
1860                 ldev->caps.ycbcr_input = false;
1861                 ldev->caps.ycbcr_output = false;
1862                 ldev->caps.plane_reg_shadow = false;
1863                 ldev->caps.crc = false;
1864                 ldev->caps.dynamic_zorder = false;
1865                 ldev->caps.plane_rotation = false;
1866                 ldev->caps.fifo_threshold = false;
1867                 break;
1868         case HWVER_40100:
1869                 ldev->caps.layer_ofs = LAY_OFS_1;
1870                 ldev->caps.layer_regs = ltdc_layer_regs_a2;
1871                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
1872                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2;
1873                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
1874                 ldev->caps.pix_fmt_flex = true;
1875                 ldev->caps.non_alpha_only_l1 = false;
1876                 ldev->caps.pad_max_freq_hz = 90000000;
1877                 ldev->caps.nb_irq = 2;
1878                 ldev->caps.ycbcr_input = true;
1879                 ldev->caps.ycbcr_output = true;
1880                 ldev->caps.plane_reg_shadow = true;
1881                 ldev->caps.crc = true;
1882                 ldev->caps.dynamic_zorder = true;
1883                 ldev->caps.plane_rotation = true;
1884                 ldev->caps.fifo_threshold = true;
1885                 break;
1886         default:
1887                 return -ENODEV;
1888         }
1889
1890         return 0;
1891 }
1892
1893 void ltdc_suspend(struct drm_device *ddev)
1894 {
1895         struct ltdc_device *ldev = ddev->dev_private;
1896
1897         DRM_DEBUG_DRIVER("\n");
1898         clk_disable_unprepare(ldev->pixel_clk);
1899 }
1900
1901 int ltdc_resume(struct drm_device *ddev)
1902 {
1903         struct ltdc_device *ldev = ddev->dev_private;
1904         int ret;
1905
1906         DRM_DEBUG_DRIVER("\n");
1907
1908         ret = clk_prepare_enable(ldev->pixel_clk);
1909         if (ret) {
1910                 DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
1911                 return ret;
1912         }
1913
1914         return 0;
1915 }
1916
1917 int ltdc_load(struct drm_device *ddev)
1918 {
1919         struct platform_device *pdev = to_platform_device(ddev->dev);
1920         struct ltdc_device *ldev = ddev->dev_private;
1921         struct device *dev = ddev->dev;
1922         struct device_node *np = dev->of_node;
1923         struct drm_bridge *bridge;
1924         struct drm_panel *panel;
1925         struct drm_crtc *crtc;
1926         struct reset_control *rstc;
1927         struct resource *res;
1928         int irq, i, nb_endpoints;
1929         int ret = -ENODEV;
1930
1931         DRM_DEBUG_DRIVER("\n");
1932
1933         /* Get number of endpoints */
1934         nb_endpoints = of_graph_get_endpoint_count(np);
1935         if (!nb_endpoints)
1936                 return -ENODEV;
1937
1938         ldev->pixel_clk = devm_clk_get(dev, "lcd");
1939         if (IS_ERR(ldev->pixel_clk)) {
1940                 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1941                         DRM_ERROR("Unable to get lcd clock\n");
1942                 return PTR_ERR(ldev->pixel_clk);
1943         }
1944
1945         if (clk_prepare_enable(ldev->pixel_clk)) {
1946                 DRM_ERROR("Unable to prepare pixel clock\n");
1947                 return -ENODEV;
1948         }
1949
1950         /* Get endpoints if any */
1951         for (i = 0; i < nb_endpoints; i++) {
1952                 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
1953
1954                 /*
1955                  * If at least one endpoint is -ENODEV, continue probing,
1956                  * else if at least one endpoint returned an error
1957                  * (ie -EPROBE_DEFER) then stop probing.
1958                  */
1959                 if (ret == -ENODEV)
1960                         continue;
1961                 else if (ret)
1962                         goto err;
1963
1964                 if (panel) {
1965                         bridge = drm_panel_bridge_add_typed(panel,
1966                                                             DRM_MODE_CONNECTOR_DPI);
1967                         if (IS_ERR(bridge)) {
1968                                 DRM_ERROR("panel-bridge endpoint %d\n", i);
1969                                 ret = PTR_ERR(bridge);
1970                                 goto err;
1971                         }
1972                 }
1973
1974                 if (bridge) {
1975                         ret = ltdc_encoder_init(ddev, bridge);
1976                         if (ret) {
1977                                 if (ret != -EPROBE_DEFER)
1978                                         DRM_ERROR("init encoder endpoint %d\n", i);
1979                                 goto err;
1980                         }
1981                 }
1982         }
1983
1984         rstc = devm_reset_control_get_exclusive(dev, NULL);
1985
1986         mutex_init(&ldev->err_lock);
1987
1988         if (!IS_ERR(rstc)) {
1989                 reset_control_assert(rstc);
1990                 usleep_range(10, 20);
1991                 reset_control_deassert(rstc);
1992         }
1993
1994         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1995         ldev->regs = devm_ioremap_resource(dev, res);
1996         if (IS_ERR(ldev->regs)) {
1997                 DRM_ERROR("Unable to get ltdc registers\n");
1998                 ret = PTR_ERR(ldev->regs);
1999                 goto err;
2000         }
2001
2002         ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg);
2003         if (IS_ERR(ldev->regmap)) {
2004                 DRM_ERROR("Unable to regmap ltdc registers\n");
2005                 ret = PTR_ERR(ldev->regmap);
2006                 goto err;
2007         }
2008
2009         ret = ltdc_get_caps(ddev);
2010         if (ret) {
2011                 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
2012                           ldev->caps.hw_version);
2013                 goto err;
2014         }
2015
2016         /* Disable interrupts */
2017         if (ldev->caps.fifo_threshold)
2018                 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE |
2019                                   IER_TERRIE);
2020         else
2021                 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE |
2022                                   IER_TERRIE | IER_FUEIE);
2023
2024         DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
2025
2026         /* initialize default value for fifo underrun threshold & clear interrupt error counters */
2027         ldev->transfer_err = 0;
2028         ldev->fifo_err = 0;
2029         ldev->fifo_warn = 0;
2030         ldev->fifo_threshold = FUT_DFT;
2031
2032         for (i = 0; i < ldev->caps.nb_irq; i++) {
2033                 irq = platform_get_irq(pdev, i);
2034                 if (irq < 0) {
2035                         ret = irq;
2036                         goto err;
2037                 }
2038
2039                 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
2040                                                 ltdc_irq_thread, IRQF_ONESHOT,
2041                                                 dev_name(dev), ddev);
2042                 if (ret) {
2043                         DRM_ERROR("Failed to register LTDC interrupt\n");
2044                         goto err;
2045                 }
2046         }
2047
2048         crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
2049         if (!crtc) {
2050                 DRM_ERROR("Failed to allocate crtc\n");
2051                 ret = -ENOMEM;
2052                 goto err;
2053         }
2054
2055         ret = ltdc_crtc_init(ddev, crtc);
2056         if (ret) {
2057                 DRM_ERROR("Failed to init crtc\n");
2058                 goto err;
2059         }
2060
2061         ret = drm_vblank_init(ddev, NB_CRTC);
2062         if (ret) {
2063                 DRM_ERROR("Failed calling drm_vblank_init()\n");
2064                 goto err;
2065         }
2066
2067         clk_disable_unprepare(ldev->pixel_clk);
2068
2069         pinctrl_pm_select_sleep_state(ddev->dev);
2070
2071         pm_runtime_enable(ddev->dev);
2072
2073         return 0;
2074 err:
2075         for (i = 0; i < nb_endpoints; i++)
2076                 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
2077
2078         clk_disable_unprepare(ldev->pixel_clk);
2079
2080         return ret;
2081 }
2082
2083 void ltdc_unload(struct drm_device *ddev)
2084 {
2085         struct device *dev = ddev->dev;
2086         int nb_endpoints, i;
2087
2088         DRM_DEBUG_DRIVER("\n");
2089
2090         nb_endpoints = of_graph_get_endpoint_count(dev->of_node);
2091
2092         for (i = 0; i < nb_endpoints; i++)
2093                 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
2094
2095         pm_runtime_disable(ddev->dev);
2096 }
2097
2098 MODULE_AUTHOR("Philippe Cornu <[email protected]>");
2099 MODULE_AUTHOR("Yannick Fertre <[email protected]>");
2100 MODULE_AUTHOR("Fabien Dessenne <[email protected]>");
2101 MODULE_AUTHOR("Mickael Reulier <[email protected]>");
2102 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
2103 MODULE_LICENSE("GPL v2");